Parsing VHDL file "/home/lusius/Devel/STM32_Devel/FPGA/Test/Test1sym.vhd" into library work "/home/lusius/Devel/STM32_Devel/FPGA/Test/Test1sym.vhd" Line 50. Syntax error near "if". "/home/lusius/Devel/STM32_Devel/FPGA/Test/Test1sym.vhd" Line 55. Syntax error near "<=". "/home/lusius/Devel/STM32_Devel/FPGA/Test/Test1sym.vhd" Line 58. Syntax error near "process". "/home/lusius/Devel/STM32_Devel/FPGA/Test/Test1sym.vhd" Line 60. Syntax error near "Behavioral".