build/main.elf: file format elf32-littlearm Disassembly of section .text: 0800010c : * interrupt, or negative to specify an internal (core) interrupt. * * Note: The priority cannot be set for every core interrupt. */ static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 800010c: b480 push {r7} 800010e: b083 sub sp, #12 8000110: af00 add r7, sp, #0 8000112: 4603 mov r3, r0 8000114: 6039 str r1, [r7, #0] 8000116: 71fb strb r3, [r7, #7] if(IRQn < 0) { 8000118: f997 3007 ldrsb.w r3, [r7, #7] 800011c: 2b00 cmp r3, #0 800011e: da0b bge.n 8000138 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ 8000120: 490d ldr r1, [pc, #52] ; (8000158 ) 8000122: 79fb ldrb r3, [r7, #7] 8000124: f003 030f and.w r3, r3, #15 8000128: 3b04 subs r3, #4 800012a: 683a ldr r2, [r7, #0] 800012c: b2d2 uxtb r2, r2 800012e: 0112 lsls r2, r2, #4 8000130: b2d2 uxtb r2, r2 8000132: 440b add r3, r1 8000134: 761a strb r2, [r3, #24] else { NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ } 8000136: e009 b.n 800014c static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if(IRQn < 0) { SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ else { NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ 8000138: 4908 ldr r1, [pc, #32] ; (800015c ) 800013a: f997 3007 ldrsb.w r3, [r7, #7] 800013e: 683a ldr r2, [r7, #0] 8000140: b2d2 uxtb r2, r2 8000142: 0112 lsls r2, r2, #4 8000144: b2d2 uxtb r2, r2 8000146: 440b add r3, r1 8000148: f883 2300 strb.w r2, [r3, #768] ; 0x300 } 800014c: bf00 nop 800014e: 370c adds r7, #12 8000150: 46bd mov sp, r7 8000152: bc80 pop {r7} 8000154: 4770 bx lr 8000156: bf00 nop 8000158: e000ed00 .word 0xe000ed00 800015c: e000e100 .word 0xe000e100 08000160 : * Initialise the system tick timer and its interrupt and start the * system tick timer / counter in free running mode to generate * periodical interrupts. */ static __INLINE uint32_t SysTick_Config(uint32_t ticks) { 8000160: b580 push {r7, lr} 8000162: b082 sub sp, #8 8000164: af00 add r7, sp, #0 8000166: 6078 str r0, [r7, #4] if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ 8000168: 687b ldr r3, [r7, #4] 800016a: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 800016e: d301 bcc.n 8000174 8000170: 2301 movs r3, #1 8000172: e011 b.n 8000198 SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ 8000174: 4a0a ldr r2, [pc, #40] ; (80001a0 ) 8000176: 687b ldr r3, [r7, #4] 8000178: f023 437f bic.w r3, r3, #4278190080 ; 0xff000000 800017c: 3b01 subs r3, #1 800017e: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ 8000180: 210f movs r1, #15 8000182: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8000186: f7ff ffc1 bl 800010c SysTick->VAL = 0; /* Load the SysTick Counter Value */ 800018a: 4b05 ldr r3, [pc, #20] ; (80001a0 ) 800018c: 2200 movs r2, #0 800018e: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8000190: 4b03 ldr r3, [pc, #12] ; (80001a0 ) 8000192: 2207 movs r2, #7 8000194: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0); /* Function successful */ 8000196: 2300 movs r3, #0 } 8000198: 4618 mov r0, r3 800019a: 3708 adds r7, #8 800019c: 46bd mov sp, r7 800019e: bd80 pop {r7, pc} 80001a0: e000e010 .word 0xe000e010 080001a4 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 80001a4: b580 push {r7, lr} 80001a6: af00 add r7, sp, #0 /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ /* Set HSION bit */ RCC->CR |= (uint32_t)0x00000001; 80001a8: 4a15 ldr r2, [pc, #84] ; (8000200 ) 80001aa: 4b15 ldr r3, [pc, #84] ; (8000200 ) 80001ac: 681b ldr r3, [r3, #0] 80001ae: f043 0301 orr.w r3, r3, #1 80001b2: 6013 str r3, [r2, #0] /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ #ifndef STM32F10X_CL RCC->CFGR &= (uint32_t)0xF8FF0000; 80001b4: 4912 ldr r1, [pc, #72] ; (8000200 ) 80001b6: 4b12 ldr r3, [pc, #72] ; (8000200 ) 80001b8: 685a ldr r2, [r3, #4] 80001ba: 4b12 ldr r3, [pc, #72] ; (8000204 ) 80001bc: 4013 ands r3, r2 80001be: 604b str r3, [r1, #4] #else RCC->CFGR &= (uint32_t)0xF0FF0000; #endif /* STM32F10X_CL */ /* Reset HSEON, CSSON and PLLON bits */ RCC->CR &= (uint32_t)0xFEF6FFFF; 80001c0: 4a0f ldr r2, [pc, #60] ; (8000200 ) 80001c2: 4b0f ldr r3, [pc, #60] ; (8000200 ) 80001c4: 681b ldr r3, [r3, #0] 80001c6: f023 7384 bic.w r3, r3, #17301504 ; 0x1080000 80001ca: f423 3380 bic.w r3, r3, #65536 ; 0x10000 80001ce: 6013 str r3, [r2, #0] /* Reset HSEBYP bit */ RCC->CR &= (uint32_t)0xFFFBFFFF; 80001d0: 4a0b ldr r2, [pc, #44] ; (8000200 ) 80001d2: 4b0b ldr r3, [pc, #44] ; (8000200 ) 80001d4: 681b ldr r3, [r3, #0] 80001d6: f423 2380 bic.w r3, r3, #262144 ; 0x40000 80001da: 6013 str r3, [r2, #0] /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ RCC->CFGR &= (uint32_t)0xFF80FFFF; 80001dc: 4a08 ldr r2, [pc, #32] ; (8000200 ) 80001de: 4b08 ldr r3, [pc, #32] ; (8000200 ) 80001e0: 685b ldr r3, [r3, #4] 80001e2: f423 03fe bic.w r3, r3, #8323072 ; 0x7f0000 80001e6: 6053 str r3, [r2, #4] /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000; #else /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x009F0000; 80001e8: 4b05 ldr r3, [pc, #20] ; (8000200 ) 80001ea: f44f 021f mov.w r2, #10420224 ; 0x9f0000 80001ee: 609a str r2, [r3, #8] #endif /* DATA_IN_ExtSRAM */ #endif /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ /* Configure the Flash Latency cycles and enable prefetch buffer */ SetSysClock(); 80001f0: f000 f878 bl 80002e4 #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ 80001f4: 4b04 ldr r3, [pc, #16] ; (8000208 ) 80001f6: f04f 6200 mov.w r2, #134217728 ; 0x8000000 80001fa: 609a str r2, [r3, #8] #endif } 80001fc: bf00 nop 80001fe: bd80 pop {r7, pc} 8000200: 40021000 .word 0x40021000 8000204: f8ff0000 .word 0xf8ff0000 8000208: e000ed00 .word 0xe000ed00 0800020c : * value for HSE crystal. * @param None * @retval None */ void SystemCoreClockUpdate (void) { 800020c: b480 push {r7} 800020e: b085 sub sp, #20 8000210: af00 add r7, sp, #0 uint32_t tmp = 0, pllmull = 0, pllsource = 0; 8000212: 2300 movs r3, #0 8000214: 60fb str r3, [r7, #12] 8000216: 2300 movs r3, #0 8000218: 60bb str r3, [r7, #8] 800021a: 2300 movs r3, #0 800021c: 607b str r3, [r7, #4] #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) uint32_t prediv1factor = 0; #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; 800021e: 4b2c ldr r3, [pc, #176] ; (80002d0 ) 8000220: 685b ldr r3, [r3, #4] 8000222: f003 030c and.w r3, r3, #12 8000226: 60fb str r3, [r7, #12] switch (tmp) 8000228: 68fb ldr r3, [r7, #12] 800022a: 2b04 cmp r3, #4 800022c: d007 beq.n 800023e 800022e: 2b08 cmp r3, #8 8000230: d009 beq.n 8000246 8000232: 2b00 cmp r3, #0 8000234: d133 bne.n 800029e { case 0x00: /* HSI used as system clock */ SystemCoreClock = HSI_VALUE; 8000236: 4b27 ldr r3, [pc, #156] ; (80002d4 ) 8000238: 4a27 ldr r2, [pc, #156] ; (80002d8 ) 800023a: 601a str r2, [r3, #0] break; 800023c: e033 b.n 80002a6 case 0x04: /* HSE used as system clock */ SystemCoreClock = HSE_VALUE; 800023e: 4b25 ldr r3, [pc, #148] ; (80002d4 ) 8000240: 4a25 ldr r2, [pc, #148] ; (80002d8 ) 8000242: 601a str r2, [r3, #0] break; 8000244: e02f b.n 80002a6 case 0x08: /* PLL used as system clock */ /* Get PLL clock source and multiplication factor ----------------------*/ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; 8000246: 4b22 ldr r3, [pc, #136] ; (80002d0 ) 8000248: 685b ldr r3, [r3, #4] 800024a: f403 1370 and.w r3, r3, #3932160 ; 0x3c0000 800024e: 60bb str r3, [r7, #8] pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; 8000250: 4b1f ldr r3, [pc, #124] ; (80002d0 ) 8000252: 685b ldr r3, [r3, #4] 8000254: f403 3380 and.w r3, r3, #65536 ; 0x10000 8000258: 607b str r3, [r7, #4] #ifndef STM32F10X_CL pllmull = ( pllmull >> 18) + 2; 800025a: 68bb ldr r3, [r7, #8] 800025c: 0c9b lsrs r3, r3, #18 800025e: 3302 adds r3, #2 8000260: 60bb str r3, [r7, #8] if (pllsource == 0x00) 8000262: 687b ldr r3, [r7, #4] 8000264: 2b00 cmp r3, #0 8000266: d106 bne.n 8000276 { /* HSI oscillator clock divided by 2 selected as PLL clock entry */ SystemCoreClock = (HSI_VALUE >> 1) * pllmull; 8000268: 68bb ldr r3, [r7, #8] 800026a: 4a1c ldr r2, [pc, #112] ; (80002dc ) 800026c: fb02 f303 mul.w r3, r2, r3 8000270: 4a18 ldr r2, [pc, #96] ; (80002d4 ) 8000272: 6013 str r3, [r2, #0] pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; } } #endif /* STM32F10X_CL */ break; 8000274: e017 b.n 80002a6 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; /* HSE oscillator clock selected as PREDIV1 clock entry */ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; #else /* HSE selected as PLL clock entry */ if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) 8000276: 4b16 ldr r3, [pc, #88] ; (80002d0 ) 8000278: 685b ldr r3, [r3, #4] 800027a: f403 3300 and.w r3, r3, #131072 ; 0x20000 800027e: 2b00 cmp r3, #0 8000280: d006 beq.n 8000290 {/* HSE oscillator clock divided by 2 */ SystemCoreClock = (HSE_VALUE >> 1) * pllmull; 8000282: 68bb ldr r3, [r7, #8] 8000284: 4a15 ldr r2, [pc, #84] ; (80002dc ) 8000286: fb02 f303 mul.w r3, r2, r3 800028a: 4a12 ldr r2, [pc, #72] ; (80002d4 ) 800028c: 6013 str r3, [r2, #0] pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; } } #endif /* STM32F10X_CL */ break; 800028e: e00a b.n 80002a6 {/* HSE oscillator clock divided by 2 */ SystemCoreClock = (HSE_VALUE >> 1) * pllmull; } else { SystemCoreClock = HSE_VALUE * pllmull; 8000290: 68bb ldr r3, [r7, #8] 8000292: 4a11 ldr r2, [pc, #68] ; (80002d8 ) 8000294: fb02 f303 mul.w r3, r2, r3 8000298: 4a0e ldr r2, [pc, #56] ; (80002d4 ) 800029a: 6013 str r3, [r2, #0] pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; } } #endif /* STM32F10X_CL */ break; 800029c: e003 b.n 80002a6 default: SystemCoreClock = HSI_VALUE; 800029e: 4b0d ldr r3, [pc, #52] ; (80002d4 ) 80002a0: 4a0d ldr r2, [pc, #52] ; (80002d8 ) 80002a2: 601a str r2, [r3, #0] break; 80002a4: bf00 nop } /* Compute HCLK clock frequency ----------------*/ /* Get HCLK prescaler */ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; 80002a6: 4b0a ldr r3, [pc, #40] ; (80002d0 ) 80002a8: 685b ldr r3, [r3, #4] 80002aa: f003 03f0 and.w r3, r3, #240 ; 0xf0 80002ae: 091b lsrs r3, r3, #4 80002b0: 4a0b ldr r2, [pc, #44] ; (80002e0 ) 80002b2: 5cd3 ldrb r3, [r2, r3] 80002b4: b2db uxtb r3, r3 80002b6: 60fb str r3, [r7, #12] /* HCLK clock frequency */ SystemCoreClock >>= tmp; 80002b8: 4b06 ldr r3, [pc, #24] ; (80002d4 ) 80002ba: 681a ldr r2, [r3, #0] 80002bc: 68fb ldr r3, [r7, #12] 80002be: fa22 f303 lsr.w r3, r2, r3 80002c2: 4a04 ldr r2, [pc, #16] ; (80002d4 ) 80002c4: 6013 str r3, [r2, #0] } 80002c6: bf00 nop 80002c8: 3714 adds r7, #20 80002ca: 46bd mov sp, r7 80002cc: bc80 pop {r7} 80002ce: 4770 bx lr 80002d0: 40021000 .word 0x40021000 80002d4: 20000000 .word 0x20000000 80002d8: 007a1200 .word 0x007a1200 80002dc: 003d0900 .word 0x003d0900 80002e0: 20000004 .word 0x20000004 080002e4 : * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. * @param None * @retval None */ static void SetSysClock(void) { 80002e4: b580 push {r7, lr} 80002e6: af00 add r7, sp, #0 #elif defined SYSCLK_FREQ_48MHz SetSysClockTo48(); #elif defined SYSCLK_FREQ_56MHz SetSysClockTo56(); #elif defined SYSCLK_FREQ_72MHz SetSysClockTo72(); 80002e8: f000 f802 bl 80002f0 #endif /* If none of the define above is enabled, the HSI is used as System clock source (default after reset) */ } 80002ec: bf00 nop 80002ee: bd80 pop {r7, pc} 080002f0 : * @note This function should be used only after reset. * @param None * @retval None */ static void SetSysClockTo72(void) { 80002f0: b480 push {r7} 80002f2: b083 sub sp, #12 80002f4: af00 add r7, sp, #0 __IO uint32_t StartUpCounter = 0, HSEStatus = 0; 80002f6: 2300 movs r3, #0 80002f8: 607b str r3, [r7, #4] 80002fa: 2300 movs r3, #0 80002fc: 603b str r3, [r7, #0] /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ /* Enable HSE */ RCC->CR |= ((uint32_t)RCC_CR_HSEON); 80002fe: 4a3a ldr r2, [pc, #232] ; (80003e8 ) 8000300: 4b39 ldr r3, [pc, #228] ; (80003e8 ) 8000302: 681b ldr r3, [r3, #0] 8000304: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8000308: 6013 str r3, [r2, #0] /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CR & RCC_CR_HSERDY; 800030a: 4b37 ldr r3, [pc, #220] ; (80003e8 ) 800030c: 681b ldr r3, [r3, #0] 800030e: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000312: 603b str r3, [r7, #0] StartUpCounter++; 8000314: 687b ldr r3, [r7, #4] 8000316: 3301 adds r3, #1 8000318: 607b str r3, [r7, #4] } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); 800031a: 683b ldr r3, [r7, #0] 800031c: 2b00 cmp r3, #0 800031e: d103 bne.n 8000328 8000320: 687b ldr r3, [r7, #4] 8000322: f5b3 6fa0 cmp.w r3, #1280 ; 0x500 8000326: d1f0 bne.n 800030a if ((RCC->CR & RCC_CR_HSERDY) != RESET) 8000328: 4b2f ldr r3, [pc, #188] ; (80003e8 ) 800032a: 681b ldr r3, [r3, #0] 800032c: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000330: 2b00 cmp r3, #0 8000332: d002 beq.n 800033a { HSEStatus = (uint32_t)0x01; 8000334: 2301 movs r3, #1 8000336: 603b str r3, [r7, #0] 8000338: e001 b.n 800033e } else { HSEStatus = (uint32_t)0x00; 800033a: 2300 movs r3, #0 800033c: 603b str r3, [r7, #0] } if (HSEStatus == (uint32_t)0x01) 800033e: 683b ldr r3, [r7, #0] 8000340: 2b01 cmp r3, #1 8000342: d14b bne.n 80003dc { /* Enable Prefetch Buffer */ FLASH->ACR |= FLASH_ACR_PRFTBE; 8000344: 4a29 ldr r2, [pc, #164] ; (80003ec ) 8000346: 4b29 ldr r3, [pc, #164] ; (80003ec ) 8000348: 681b ldr r3, [r3, #0] 800034a: f043 0310 orr.w r3, r3, #16 800034e: 6013 str r3, [r2, #0] /* Flash 2 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); 8000350: 4a26 ldr r2, [pc, #152] ; (80003ec ) 8000352: 4b26 ldr r3, [pc, #152] ; (80003ec ) 8000354: 681b ldr r3, [r3, #0] 8000356: f023 0303 bic.w r3, r3, #3 800035a: 6013 str r3, [r2, #0] FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; 800035c: 4a23 ldr r2, [pc, #140] ; (80003ec ) 800035e: 4b23 ldr r3, [pc, #140] ; (80003ec ) 8000360: 681b ldr r3, [r3, #0] 8000362: f043 0302 orr.w r3, r3, #2 8000366: 6013 str r3, [r2, #0] /* HCLK = SYSCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; 8000368: 4a1f ldr r2, [pc, #124] ; (80003e8 ) 800036a: 4b1f ldr r3, [pc, #124] ; (80003e8 ) 800036c: 685b ldr r3, [r3, #4] 800036e: 6053 str r3, [r2, #4] /* PCLK2 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; 8000370: 4a1d ldr r2, [pc, #116] ; (80003e8 ) 8000372: 4b1d ldr r3, [pc, #116] ; (80003e8 ) 8000374: 685b ldr r3, [r3, #4] 8000376: 6053 str r3, [r2, #4] /* PCLK1 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; 8000378: 4a1b ldr r2, [pc, #108] ; (80003e8 ) 800037a: 4b1b ldr r3, [pc, #108] ; (80003e8 ) 800037c: 685b ldr r3, [r3, #4] 800037e: f443 6380 orr.w r3, r3, #1024 ; 0x400 8000382: 6053 str r3, [r2, #4] RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLMULL9); #else /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | 8000384: 4a18 ldr r2, [pc, #96] ; (80003e8 ) 8000386: 4b18 ldr r3, [pc, #96] ; (80003e8 ) 8000388: 685b ldr r3, [r3, #4] 800038a: f423 137c bic.w r3, r3, #4128768 ; 0x3f0000 800038e: 6053 str r3, [r2, #4] RCC_CFGR_PLLMULL)); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); 8000390: 4a15 ldr r2, [pc, #84] ; (80003e8 ) 8000392: 4b15 ldr r3, [pc, #84] ; (80003e8 ) 8000394: 685b ldr r3, [r3, #4] 8000396: f443 13e8 orr.w r3, r3, #1900544 ; 0x1d0000 800039a: 6053 str r3, [r2, #4] #endif /* STM32F10X_CL */ /* Enable PLL */ RCC->CR |= RCC_CR_PLLON; 800039c: 4a12 ldr r2, [pc, #72] ; (80003e8 ) 800039e: 4b12 ldr r3, [pc, #72] ; (80003e8 ) 80003a0: 681b ldr r3, [r3, #0] 80003a2: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 80003a6: 6013 str r3, [r2, #0] /* Wait till PLL is ready */ while((RCC->CR & RCC_CR_PLLRDY) == 0) 80003a8: bf00 nop 80003aa: 4b0f ldr r3, [pc, #60] ; (80003e8 ) 80003ac: 681b ldr r3, [r3, #0] 80003ae: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80003b2: 2b00 cmp r3, #0 80003b4: d0f9 beq.n 80003aa { } /* Select PLL as system clock source */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); 80003b6: 4a0c ldr r2, [pc, #48] ; (80003e8 ) 80003b8: 4b0b ldr r3, [pc, #44] ; (80003e8 ) 80003ba: 685b ldr r3, [r3, #4] 80003bc: f023 0303 bic.w r3, r3, #3 80003c0: 6053 str r3, [r2, #4] RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; 80003c2: 4a09 ldr r2, [pc, #36] ; (80003e8 ) 80003c4: 4b08 ldr r3, [pc, #32] ; (80003e8 ) 80003c6: 685b ldr r3, [r3, #4] 80003c8: f043 0302 orr.w r3, r3, #2 80003cc: 6053 str r3, [r2, #4] /* Wait till PLL is used as system clock source */ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) 80003ce: bf00 nop 80003d0: 4b05 ldr r3, [pc, #20] ; (80003e8 ) 80003d2: 685b ldr r3, [r3, #4] 80003d4: f003 030c and.w r3, r3, #12 80003d8: 2b08 cmp r3, #8 80003da: d1f9 bne.n 80003d0 } else { /* If HSE fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */ } } 80003dc: bf00 nop 80003de: 370c adds r7, #12 80003e0: 46bd mov sp, r7 80003e2: bc80 pop {r7} 80003e4: 4770 bx lr 80003e6: bf00 nop 80003e8: 40021000 .word 0x40021000 80003ec: 40022000 .word 0x40022000 080003f0 : volatile long int aa=0,bb=0; void SysTick_Handler(void) { 80003f0: b480 push {r7} 80003f2: af00 add r7, sp, #0 aa++; 80003f4: 4b04 ldr r3, [pc, #16] ; (8000408 ) 80003f6: 681b ldr r3, [r3, #0] 80003f8: 3301 adds r3, #1 80003fa: 4a03 ldr r2, [pc, #12] ; (8000408 ) 80003fc: 6013 str r3, [r2, #0] } 80003fe: bf00 nop 8000400: 46bd mov sp, r7 8000402: bc80 pop {r7} 8000404: 4770 bx lr 8000406: bf00 nop 8000408: 20000014 .word 0x20000014 0800040c
: int main(void) { 800040c: b580 push {r7, lr} 800040e: af00 add r7, sp, #0 SystemCoreClockUpdate(); 8000410: f7ff fefc bl 800020c SysTick_Config(SystemCoreClock/10000); 8000414: 4b07 ldr r3, [pc, #28] ; (8000434 ) 8000416: 681b ldr r3, [r3, #0] 8000418: 4a07 ldr r2, [pc, #28] ; (8000438 ) 800041a: fba2 2303 umull r2, r3, r2, r3 800041e: 0b5b lsrs r3, r3, #13 8000420: 4618 mov r0, r3 8000422: f7ff fe9d bl 8000160 while (1) { bb=SystemCoreClock; 8000426: 4b03 ldr r3, [pc, #12] ; (8000434 ) 8000428: 681b ldr r3, [r3, #0] 800042a: 461a mov r2, r3 800042c: 4b03 ldr r3, [pc, #12] ; (800043c ) 800042e: 601a str r2, [r3, #0] } 8000430: e7f9 b.n 8000426 8000432: bf00 nop 8000434: 20000000 .word 0x20000000 8000438: d1b71759 .word 0xd1b71759 800043c: 20000018 .word 0x20000018 8000440: 0800049c .word 0x0800049c 8000444: 20000000 .word 0x20000000 8000448: 20000014 .word 0x20000014 800044c: 20000014 .word 0x20000014 8000450: 2000001c .word 0x2000001c 08000454 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 8000454: 2100 movs r1, #0 b LoopCopyDataInit 8000456: e003 b.n 8000460 08000458 : CopyDataInit: ldr r3, =_sidata 8000458: 4b0a ldr r3, [pc, #40] ; (8000484 ) ldr r3, [r3, r1] 800045a: 585b ldr r3, [r3, r1] str r3, [r0, r1] 800045c: 5043 str r3, [r0, r1] adds r1, r1, #4 800045e: 3104 adds r1, #4 08000460 : LoopCopyDataInit: ldr r0, =_sdata 8000460: 4809 ldr r0, [pc, #36] ; (8000488 ) ldr r3, =_edata 8000462: 4b0a ldr r3, [pc, #40] ; (800048c ) adds r2, r0, r1 8000464: 1842 adds r2, r0, r1 cmp r2, r3 8000466: 429a cmp r2, r3 bcc CopyDataInit 8000468: d3f6 bcc.n 8000458 ldr r2, =_sbss 800046a: 4a09 ldr r2, [pc, #36] ; (8000490 ) b LoopFillZerobss 800046c: e002 b.n 8000474 0800046e : /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 800046e: 2300 movs r3, #0 str r3, [r2], #4 8000470: f842 3b04 str.w r3, [r2], #4 08000474 : LoopFillZerobss: ldr r3, = _ebss 8000474: 4b07 ldr r3, [pc, #28] ; (8000494 ) cmp r2, r3 8000476: 429a cmp r2, r3 bcc FillZerobss 8000478: d3f9 bcc.n 800046e /* Call the clock system intitialization function.*/ bl SystemInit 800047a: f7ff fe93 bl 80001a4 /* Call the application's entry point.*/ bl main 800047e: f7ff ffc5 bl 800040c
bx lr 8000482: 4770 bx lr /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 b LoopCopyDataInit CopyDataInit: ldr r3, =_sidata 8000484: 0800049c .word 0x0800049c ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: ldr r0, =_sdata 8000488: 20000000 .word 0x20000000 ldr r3, =_edata 800048c: 20000014 .word 0x20000014 adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit ldr r2, =_sbss 8000490: 20000014 .word 0x20000014 FillZerobss: movs r3, #0 str r3, [r2], #4 LoopFillZerobss: ldr r3, = _ebss 8000494: 2000001c .word 0x2000001c 08000498 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8000498: e7fe b.n 8000498 ...