build/main.elf: file format elf32-littlearm Disassembly of section .text: 0800010c : * interrupt, or negative to specify an internal (core) interrupt. * * Note: The priority cannot be set for every core interrupt. */ static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 800010c: b480 push {r7} 800010e: b083 sub sp, #12 8000110: af00 add r7, sp, #0 8000112: 4603 mov r3, r0 8000114: 6039 str r1, [r7, #0] 8000116: 71fb strb r3, [r7, #7] if(IRQn < 0) { 8000118: f997 3007 ldrsb.w r3, [r7, #7] 800011c: 2b00 cmp r3, #0 800011e: da0b bge.n 8000138 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ 8000120: 490d ldr r1, [pc, #52] ; (8000158 ) 8000122: 79fb ldrb r3, [r7, #7] 8000124: f003 030f and.w r3, r3, #15 8000128: 3b04 subs r3, #4 800012a: 683a ldr r2, [r7, #0] 800012c: b2d2 uxtb r2, r2 800012e: 0112 lsls r2, r2, #4 8000130: b2d2 uxtb r2, r2 8000132: 440b add r3, r1 8000134: 761a strb r2, [r3, #24] else { NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ } 8000136: e009 b.n 800014c static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if(IRQn < 0) { SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ else { NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ 8000138: 4908 ldr r1, [pc, #32] ; (800015c ) 800013a: f997 3007 ldrsb.w r3, [r7, #7] 800013e: 683a ldr r2, [r7, #0] 8000140: b2d2 uxtb r2, r2 8000142: 0112 lsls r2, r2, #4 8000144: b2d2 uxtb r2, r2 8000146: 440b add r3, r1 8000148: f883 2300 strb.w r2, [r3, #768] ; 0x300 } 800014c: bf00 nop 800014e: 370c adds r7, #12 8000150: 46bd mov sp, r7 8000152: bc80 pop {r7} 8000154: 4770 bx lr 8000156: bf00 nop 8000158: e000ed00 .word 0xe000ed00 800015c: e000e100 .word 0xe000e100 08000160 : * Initialise the system tick timer and its interrupt and start the * system tick timer / counter in free running mode to generate * periodical interrupts. */ static __INLINE uint32_t SysTick_Config(uint32_t ticks) { 8000160: b580 push {r7, lr} 8000162: b082 sub sp, #8 8000164: af00 add r7, sp, #0 8000166: 6078 str r0, [r7, #4] if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ 8000168: 687b ldr r3, [r7, #4] 800016a: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 800016e: d301 bcc.n 8000174 8000170: 2301 movs r3, #1 8000172: e011 b.n 8000198 SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ 8000174: 4a0a ldr r2, [pc, #40] ; (80001a0 ) 8000176: 687b ldr r3, [r7, #4] 8000178: f023 437f bic.w r3, r3, #4278190080 ; 0xff000000 800017c: 3b01 subs r3, #1 800017e: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ 8000180: 210f movs r1, #15 8000182: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8000186: f7ff ffc1 bl 800010c SysTick->VAL = 0; /* Load the SysTick Counter Value */ 800018a: 4b05 ldr r3, [pc, #20] ; (80001a0 ) 800018c: 2200 movs r2, #0 800018e: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8000190: 4b03 ldr r3, [pc, #12] ; (80001a0 ) 8000192: 2207 movs r2, #7 8000194: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0); /* Function successful */ 8000196: 2300 movs r3, #0 } 8000198: 4618 mov r0, r3 800019a: 3708 adds r7, #8 800019c: 46bd mov sp, r7 800019e: bd80 pop {r7, pc} 80001a0: e000e010 .word 0xe000e010 080001a4 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 80001a4: b580 push {r7, lr} 80001a6: af00 add r7, sp, #0 /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ /* Set HSION bit */ RCC->CR |= (uint32_t)0x00000001; 80001a8: 4a15 ldr r2, [pc, #84] ; (8000200 ) 80001aa: 4b15 ldr r3, [pc, #84] ; (8000200 ) 80001ac: 681b ldr r3, [r3, #0] 80001ae: f043 0301 orr.w r3, r3, #1 80001b2: 6013 str r3, [r2, #0] /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ #ifndef STM32F10X_CL RCC->CFGR &= (uint32_t)0xF8FF0000; 80001b4: 4912 ldr r1, [pc, #72] ; (8000200 ) 80001b6: 4b12 ldr r3, [pc, #72] ; (8000200 ) 80001b8: 685a ldr r2, [r3, #4] 80001ba: 4b12 ldr r3, [pc, #72] ; (8000204 ) 80001bc: 4013 ands r3, r2 80001be: 604b str r3, [r1, #4] #else RCC->CFGR &= (uint32_t)0xF0FF0000; #endif /* STM32F10X_CL */ /* Reset HSEON, CSSON and PLLON bits */ RCC->CR &= (uint32_t)0xFEF6FFFF; 80001c0: 4a0f ldr r2, [pc, #60] ; (8000200 ) 80001c2: 4b0f ldr r3, [pc, #60] ; (8000200 ) 80001c4: 681b ldr r3, [r3, #0] 80001c6: f023 7384 bic.w r3, r3, #17301504 ; 0x1080000 80001ca: f423 3380 bic.w r3, r3, #65536 ; 0x10000 80001ce: 6013 str r3, [r2, #0] /* Reset HSEBYP bit */ RCC->CR &= (uint32_t)0xFFFBFFFF; 80001d0: 4a0b ldr r2, [pc, #44] ; (8000200 ) 80001d2: 4b0b ldr r3, [pc, #44] ; (8000200 ) 80001d4: 681b ldr r3, [r3, #0] 80001d6: f423 2380 bic.w r3, r3, #262144 ; 0x40000 80001da: 6013 str r3, [r2, #0] /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ RCC->CFGR &= (uint32_t)0xFF80FFFF; 80001dc: 4a08 ldr r2, [pc, #32] ; (8000200 ) 80001de: 4b08 ldr r3, [pc, #32] ; (8000200 ) 80001e0: 685b ldr r3, [r3, #4] 80001e2: f423 03fe bic.w r3, r3, #8323072 ; 0x7f0000 80001e6: 6053 str r3, [r2, #4] /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000; #else /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x009F0000; 80001e8: 4b05 ldr r3, [pc, #20] ; (8000200 ) 80001ea: f44f 021f mov.w r2, #10420224 ; 0x9f0000 80001ee: 609a str r2, [r3, #8] #endif /* DATA_IN_ExtSRAM */ #endif /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ /* Configure the Flash Latency cycles and enable prefetch buffer */ SetSysClock(); 80001f0: f000 f878 bl 80002e4 #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ 80001f4: 4b04 ldr r3, [pc, #16] ; (8000208 ) 80001f6: f04f 6200 mov.w r2, #134217728 ; 0x8000000 80001fa: 609a str r2, [r3, #8] #endif } 80001fc: bf00 nop 80001fe: bd80 pop {r7, pc} 8000200: 40021000 .word 0x40021000 8000204: f8ff0000 .word 0xf8ff0000 8000208: e000ed00 .word 0xe000ed00 0800020c : * value for HSE crystal. * @param None * @retval None */ void SystemCoreClockUpdate (void) { 800020c: b480 push {r7} 800020e: b085 sub sp, #20 8000210: af00 add r7, sp, #0 uint32_t tmp = 0, pllmull = 0, pllsource = 0; 8000212: 2300 movs r3, #0 8000214: 60fb str r3, [r7, #12] 8000216: 2300 movs r3, #0 8000218: 60bb str r3, [r7, #8] 800021a: 2300 movs r3, #0 800021c: 607b str r3, [r7, #4] #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) uint32_t prediv1factor = 0; #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; 800021e: 4b2c ldr r3, [pc, #176] ; (80002d0 ) 8000220: 685b ldr r3, [r3, #4] 8000222: f003 030c and.w r3, r3, #12 8000226: 60fb str r3, [r7, #12] switch (tmp) 8000228: 68fb ldr r3, [r7, #12] 800022a: 2b04 cmp r3, #4 800022c: d007 beq.n 800023e 800022e: 2b08 cmp r3, #8 8000230: d009 beq.n 8000246 8000232: 2b00 cmp r3, #0 8000234: d133 bne.n 800029e { case 0x00: /* HSI used as system clock */ SystemCoreClock = HSI_VALUE; 8000236: 4b27 ldr r3, [pc, #156] ; (80002d4 ) 8000238: 4a27 ldr r2, [pc, #156] ; (80002d8 ) 800023a: 601a str r2, [r3, #0] break; 800023c: e033 b.n 80002a6 case 0x04: /* HSE used as system clock */ SystemCoreClock = HSE_VALUE; 800023e: 4b25 ldr r3, [pc, #148] ; (80002d4 ) 8000240: 4a25 ldr r2, [pc, #148] ; (80002d8 ) 8000242: 601a str r2, [r3, #0] break; 8000244: e02f b.n 80002a6 case 0x08: /* PLL used as system clock */ /* Get PLL clock source and multiplication factor ----------------------*/ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; 8000246: 4b22 ldr r3, [pc, #136] ; (80002d0 ) 8000248: 685b ldr r3, [r3, #4] 800024a: f403 1370 and.w r3, r3, #3932160 ; 0x3c0000 800024e: 60bb str r3, [r7, #8] pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; 8000250: 4b1f ldr r3, [pc, #124] ; (80002d0 ) 8000252: 685b ldr r3, [r3, #4] 8000254: f403 3380 and.w r3, r3, #65536 ; 0x10000 8000258: 607b str r3, [r7, #4] #ifndef STM32F10X_CL pllmull = ( pllmull >> 18) + 2; 800025a: 68bb ldr r3, [r7, #8] 800025c: 0c9b lsrs r3, r3, #18 800025e: 3302 adds r3, #2 8000260: 60bb str r3, [r7, #8] if (pllsource == 0x00) 8000262: 687b ldr r3, [r7, #4] 8000264: 2b00 cmp r3, #0 8000266: d106 bne.n 8000276 { /* HSI oscillator clock divided by 2 selected as PLL clock entry */ SystemCoreClock = (HSI_VALUE >> 1) * pllmull; 8000268: 68bb ldr r3, [r7, #8] 800026a: 4a1c ldr r2, [pc, #112] ; (80002dc ) 800026c: fb02 f303 mul.w r3, r2, r3 8000270: 4a18 ldr r2, [pc, #96] ; (80002d4 ) 8000272: 6013 str r3, [r2, #0] pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; } } #endif /* STM32F10X_CL */ break; 8000274: e017 b.n 80002a6 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; /* HSE oscillator clock selected as PREDIV1 clock entry */ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; #else /* HSE selected as PLL clock entry */ if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) 8000276: 4b16 ldr r3, [pc, #88] ; (80002d0 ) 8000278: 685b ldr r3, [r3, #4] 800027a: f403 3300 and.w r3, r3, #131072 ; 0x20000 800027e: 2b00 cmp r3, #0 8000280: d006 beq.n 8000290 {/* HSE oscillator clock divided by 2 */ SystemCoreClock = (HSE_VALUE >> 1) * pllmull; 8000282: 68bb ldr r3, [r7, #8] 8000284: 4a15 ldr r2, [pc, #84] ; (80002dc ) 8000286: fb02 f303 mul.w r3, r2, r3 800028a: 4a12 ldr r2, [pc, #72] ; (80002d4 ) 800028c: 6013 str r3, [r2, #0] pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; } } #endif /* STM32F10X_CL */ break; 800028e: e00a b.n 80002a6 {/* HSE oscillator clock divided by 2 */ SystemCoreClock = (HSE_VALUE >> 1) * pllmull; } else { SystemCoreClock = HSE_VALUE * pllmull; 8000290: 68bb ldr r3, [r7, #8] 8000292: 4a11 ldr r2, [pc, #68] ; (80002d8 ) 8000294: fb02 f303 mul.w r3, r2, r3 8000298: 4a0e ldr r2, [pc, #56] ; (80002d4 ) 800029a: 6013 str r3, [r2, #0] pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; } } #endif /* STM32F10X_CL */ break; 800029c: e003 b.n 80002a6 default: SystemCoreClock = HSI_VALUE; 800029e: 4b0d ldr r3, [pc, #52] ; (80002d4 ) 80002a0: 4a0d ldr r2, [pc, #52] ; (80002d8 ) 80002a2: 601a str r2, [r3, #0] break; 80002a4: bf00 nop } /* Compute HCLK clock frequency ----------------*/ /* Get HCLK prescaler */ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; 80002a6: 4b0a ldr r3, [pc, #40] ; (80002d0 ) 80002a8: 685b ldr r3, [r3, #4] 80002aa: f003 03f0 and.w r3, r3, #240 ; 0xf0 80002ae: 091b lsrs r3, r3, #4 80002b0: 4a0b ldr r2, [pc, #44] ; (80002e0 ) 80002b2: 5cd3 ldrb r3, [r2, r3] 80002b4: b2db uxtb r3, r3 80002b6: 60fb str r3, [r7, #12] /* HCLK clock frequency */ SystemCoreClock >>= tmp; 80002b8: 4b06 ldr r3, [pc, #24] ; (80002d4 ) 80002ba: 681a ldr r2, [r3, #0] 80002bc: 68fb ldr r3, [r7, #12] 80002be: fa22 f303 lsr.w r3, r2, r3 80002c2: 4a04 ldr r2, [pc, #16] ; (80002d4 ) 80002c4: 6013 str r3, [r2, #0] } 80002c6: bf00 nop 80002c8: 3714 adds r7, #20 80002ca: 46bd mov sp, r7 80002cc: bc80 pop {r7} 80002ce: 4770 bx lr 80002d0: 40021000 .word 0x40021000 80002d4: 20000000 .word 0x20000000 80002d8: 007a1200 .word 0x007a1200 80002dc: 003d0900 .word 0x003d0900 80002e0: 20000004 .word 0x20000004 080002e4 : * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. * @param None * @retval None */ static void SetSysClock(void) { 80002e4: b580 push {r7, lr} 80002e6: af00 add r7, sp, #0 #elif defined SYSCLK_FREQ_48MHz SetSysClockTo48(); #elif defined SYSCLK_FREQ_56MHz SetSysClockTo56(); #elif defined SYSCLK_FREQ_72MHz SetSysClockTo72(); 80002e8: f000 f802 bl 80002f0 #endif /* If none of the define above is enabled, the HSI is used as System clock source (default after reset) */ } 80002ec: bf00 nop 80002ee: bd80 pop {r7, pc} 080002f0 : * @note This function should be used only after reset. * @param None * @retval None */ static void SetSysClockTo72(void) { 80002f0: b480 push {r7} 80002f2: b083 sub sp, #12 80002f4: af00 add r7, sp, #0 __IO uint32_t StartUpCounter = 0, HSEStatus = 0; 80002f6: 2300 movs r3, #0 80002f8: 607b str r3, [r7, #4] 80002fa: 2300 movs r3, #0 80002fc: 603b str r3, [r7, #0] /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ /* Enable HSE */ RCC->CR |= ((uint32_t)RCC_CR_HSEON); 80002fe: 4a3a ldr r2, [pc, #232] ; (80003e8 ) 8000300: 4b39 ldr r3, [pc, #228] ; (80003e8 ) 8000302: 681b ldr r3, [r3, #0] 8000304: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8000308: 6013 str r3, [r2, #0] /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CR & RCC_CR_HSERDY; 800030a: 4b37 ldr r3, [pc, #220] ; (80003e8 ) 800030c: 681b ldr r3, [r3, #0] 800030e: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000312: 603b str r3, [r7, #0] StartUpCounter++; 8000314: 687b ldr r3, [r7, #4] 8000316: 3301 adds r3, #1 8000318: 607b str r3, [r7, #4] } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); 800031a: 683b ldr r3, [r7, #0] 800031c: 2b00 cmp r3, #0 800031e: d103 bne.n 8000328 8000320: 687b ldr r3, [r7, #4] 8000322: f5b3 6fa0 cmp.w r3, #1280 ; 0x500 8000326: d1f0 bne.n 800030a if ((RCC->CR & RCC_CR_HSERDY) != RESET) 8000328: 4b2f ldr r3, [pc, #188] ; (80003e8 ) 800032a: 681b ldr r3, [r3, #0] 800032c: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000330: 2b00 cmp r3, #0 8000332: d002 beq.n 800033a { HSEStatus = (uint32_t)0x01; 8000334: 2301 movs r3, #1 8000336: 603b str r3, [r7, #0] 8000338: e001 b.n 800033e } else { HSEStatus = (uint32_t)0x00; 800033a: 2300 movs r3, #0 800033c: 603b str r3, [r7, #0] } if (HSEStatus == (uint32_t)0x01) 800033e: 683b ldr r3, [r7, #0] 8000340: 2b01 cmp r3, #1 8000342: d14b bne.n 80003dc { /* Enable Prefetch Buffer */ FLASH->ACR |= FLASH_ACR_PRFTBE; 8000344: 4a29 ldr r2, [pc, #164] ; (80003ec ) 8000346: 4b29 ldr r3, [pc, #164] ; (80003ec ) 8000348: 681b ldr r3, [r3, #0] 800034a: f043 0310 orr.w r3, r3, #16 800034e: 6013 str r3, [r2, #0] /* Flash 2 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); 8000350: 4a26 ldr r2, [pc, #152] ; (80003ec ) 8000352: 4b26 ldr r3, [pc, #152] ; (80003ec ) 8000354: 681b ldr r3, [r3, #0] 8000356: f023 0303 bic.w r3, r3, #3 800035a: 6013 str r3, [r2, #0] FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; 800035c: 4a23 ldr r2, [pc, #140] ; (80003ec ) 800035e: 4b23 ldr r3, [pc, #140] ; (80003ec ) 8000360: 681b ldr r3, [r3, #0] 8000362: f043 0302 orr.w r3, r3, #2 8000366: 6013 str r3, [r2, #0] /* HCLK = SYSCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; 8000368: 4a1f ldr r2, [pc, #124] ; (80003e8 ) 800036a: 4b1f ldr r3, [pc, #124] ; (80003e8 ) 800036c: 685b ldr r3, [r3, #4] 800036e: 6053 str r3, [r2, #4] /* PCLK2 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; 8000370: 4a1d ldr r2, [pc, #116] ; (80003e8 ) 8000372: 4b1d ldr r3, [pc, #116] ; (80003e8 ) 8000374: 685b ldr r3, [r3, #4] 8000376: 6053 str r3, [r2, #4] /* PCLK1 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; 8000378: 4a1b ldr r2, [pc, #108] ; (80003e8 ) 800037a: 4b1b ldr r3, [pc, #108] ; (80003e8 ) 800037c: 685b ldr r3, [r3, #4] 800037e: f443 6380 orr.w r3, r3, #1024 ; 0x400 8000382: 6053 str r3, [r2, #4] RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLMULL9); #else /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | 8000384: 4a18 ldr r2, [pc, #96] ; (80003e8 ) 8000386: 4b18 ldr r3, [pc, #96] ; (80003e8 ) 8000388: 685b ldr r3, [r3, #4] 800038a: f423 137c bic.w r3, r3, #4128768 ; 0x3f0000 800038e: 6053 str r3, [r2, #4] RCC_CFGR_PLLMULL)); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); 8000390: 4a15 ldr r2, [pc, #84] ; (80003e8 ) 8000392: 4b15 ldr r3, [pc, #84] ; (80003e8 ) 8000394: 685b ldr r3, [r3, #4] 8000396: f443 13e8 orr.w r3, r3, #1900544 ; 0x1d0000 800039a: 6053 str r3, [r2, #4] #endif /* STM32F10X_CL */ /* Enable PLL */ RCC->CR |= RCC_CR_PLLON; 800039c: 4a12 ldr r2, [pc, #72] ; (80003e8 ) 800039e: 4b12 ldr r3, [pc, #72] ; (80003e8 ) 80003a0: 681b ldr r3, [r3, #0] 80003a2: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 80003a6: 6013 str r3, [r2, #0] /* Wait till PLL is ready */ while((RCC->CR & RCC_CR_PLLRDY) == 0) 80003a8: bf00 nop 80003aa: 4b0f ldr r3, [pc, #60] ; (80003e8 ) 80003ac: 681b ldr r3, [r3, #0] 80003ae: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80003b2: 2b00 cmp r3, #0 80003b4: d0f9 beq.n 80003aa { } /* Select PLL as system clock source */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); 80003b6: 4a0c ldr r2, [pc, #48] ; (80003e8 ) 80003b8: 4b0b ldr r3, [pc, #44] ; (80003e8 ) 80003ba: 685b ldr r3, [r3, #4] 80003bc: f023 0303 bic.w r3, r3, #3 80003c0: 6053 str r3, [r2, #4] RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; 80003c2: 4a09 ldr r2, [pc, #36] ; (80003e8 ) 80003c4: 4b08 ldr r3, [pc, #32] ; (80003e8 ) 80003c6: 685b ldr r3, [r3, #4] 80003c8: f043 0302 orr.w r3, r3, #2 80003cc: 6053 str r3, [r2, #4] /* Wait till PLL is used as system clock source */ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) 80003ce: bf00 nop 80003d0: 4b05 ldr r3, [pc, #20] ; (80003e8 ) 80003d2: 685b ldr r3, [r3, #4] 80003d4: f003 030c and.w r3, r3, #12 80003d8: 2b08 cmp r3, #8 80003da: d1f9 bne.n 80003d0 } else { /* If HSE fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */ } } 80003dc: bf00 nop 80003de: 370c adds r7, #12 80003e0: 46bd mov sp, r7 80003e2: bc80 pop {r7} 80003e4: 4770 bx lr 80003e6: bf00 nop 80003e8: 40021000 .word 0x40021000 80003ec: 40022000 .word 0x40022000 080003f0 : void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) { 80003f0: b480 push {r7} 80003f2: b089 sub sp, #36 ; 0x24 80003f4: af00 add r7, sp, #0 80003f6: 6078 str r0, [r7, #4] 80003f8: 6039 str r1, [r7, #0] uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; 80003fa: 2300 movs r3, #0 80003fc: 61fb str r3, [r7, #28] 80003fe: 2300 movs r3, #0 8000400: 613b str r3, [r7, #16] 8000402: 2300 movs r3, #0 8000404: 61bb str r3, [r7, #24] 8000406: 2300 movs r3, #0 8000408: 60fb str r3, [r7, #12] uint32_t tmpreg = 0x00, pinmask = 0x00; 800040a: 2300 movs r3, #0 800040c: 617b str r3, [r7, #20] 800040e: 2300 movs r3, #0 8000410: 60bb str r3, [r7, #8] assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); /*---------------------------- GPIO Mode Configuration -----------------------*/ currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); 8000412: 683b ldr r3, [r7, #0] 8000414: 78db ldrb r3, [r3, #3] 8000416: f003 030f and.w r3, r3, #15 800041a: 61fb str r3, [r7, #28] if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) 800041c: 683b ldr r3, [r7, #0] 800041e: 78db ldrb r3, [r3, #3] 8000420: f003 0310 and.w r3, r3, #16 8000424: 2b00 cmp r3, #0 8000426: d005 beq.n 8000434 { /* Check the parameters */ assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); /* Output mode */ currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; 8000428: 683b ldr r3, [r7, #0] 800042a: 789b ldrb r3, [r3, #2] 800042c: 461a mov r2, r3 800042e: 69fb ldr r3, [r7, #28] 8000430: 4313 orrs r3, r2 8000432: 61fb str r3, [r7, #28] } /*---------------------------- GPIO CRL Configuration ------------------------*/ /* Configure the eight low port pins */ if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) 8000434: 683b ldr r3, [r7, #0] 8000436: 881b ldrh r3, [r3, #0] 8000438: b2db uxtb r3, r3 800043a: 2b00 cmp r3, #0 800043c: d044 beq.n 80004c8 { tmpreg = GPIOx->CRL; 800043e: 687b ldr r3, [r7, #4] 8000440: 681b ldr r3, [r3, #0] 8000442: 617b str r3, [r7, #20] for (pinpos = 0x00; pinpos < 0x08; pinpos++) 8000444: 2300 movs r3, #0 8000446: 61bb str r3, [r7, #24] 8000448: e038 b.n 80004bc { pos = ((uint32_t)0x01) << pinpos; 800044a: 2201 movs r2, #1 800044c: 69bb ldr r3, [r7, #24] 800044e: fa02 f303 lsl.w r3, r2, r3 8000452: 60fb str r3, [r7, #12] /* Get the port pins position */ currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; 8000454: 683b ldr r3, [r7, #0] 8000456: 881b ldrh r3, [r3, #0] 8000458: 461a mov r2, r3 800045a: 68fb ldr r3, [r7, #12] 800045c: 4013 ands r3, r2 800045e: 613b str r3, [r7, #16] if (currentpin == pos) 8000460: 693a ldr r2, [r7, #16] 8000462: 68fb ldr r3, [r7, #12] 8000464: 429a cmp r2, r3 8000466: d126 bne.n 80004b6 { pos = pinpos << 2; 8000468: 69bb ldr r3, [r7, #24] 800046a: 009b lsls r3, r3, #2 800046c: 60fb str r3, [r7, #12] /* Clear the corresponding low control register bits */ pinmask = ((uint32_t)0x0F) << pos; 800046e: 220f movs r2, #15 8000470: 68fb ldr r3, [r7, #12] 8000472: fa02 f303 lsl.w r3, r2, r3 8000476: 60bb str r3, [r7, #8] tmpreg &= ~pinmask; 8000478: 68bb ldr r3, [r7, #8] 800047a: 43db mvns r3, r3 800047c: 697a ldr r2, [r7, #20] 800047e: 4013 ands r3, r2 8000480: 617b str r3, [r7, #20] /* Write the mode configuration in the corresponding bits */ tmpreg |= (currentmode << pos); 8000482: 69fa ldr r2, [r7, #28] 8000484: 68fb ldr r3, [r7, #12] 8000486: fa02 f303 lsl.w r3, r2, r3 800048a: 697a ldr r2, [r7, #20] 800048c: 4313 orrs r3, r2 800048e: 617b str r3, [r7, #20] /* Reset the corresponding ODR bit */ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) 8000490: 683b ldr r3, [r7, #0] 8000492: 78db ldrb r3, [r3, #3] 8000494: 2b28 cmp r3, #40 ; 0x28 8000496: d105 bne.n 80004a4 { GPIOx->BRR = (((uint32_t)0x01) << pinpos); 8000498: 2201 movs r2, #1 800049a: 69bb ldr r3, [r7, #24] 800049c: 409a lsls r2, r3 800049e: 687b ldr r3, [r7, #4] 80004a0: 615a str r2, [r3, #20] 80004a2: e008 b.n 80004b6 } else { /* Set the corresponding ODR bit */ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) 80004a4: 683b ldr r3, [r7, #0] 80004a6: 78db ldrb r3, [r3, #3] 80004a8: 2b48 cmp r3, #72 ; 0x48 80004aa: d104 bne.n 80004b6 { GPIOx->BSRR = (((uint32_t)0x01) << pinpos); 80004ac: 2201 movs r2, #1 80004ae: 69bb ldr r3, [r7, #24] 80004b0: 409a lsls r2, r3 80004b2: 687b ldr r3, [r7, #4] 80004b4: 611a str r2, [r3, #16] /*---------------------------- GPIO CRL Configuration ------------------------*/ /* Configure the eight low port pins */ if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) { tmpreg = GPIOx->CRL; for (pinpos = 0x00; pinpos < 0x08; pinpos++) 80004b6: 69bb ldr r3, [r7, #24] 80004b8: 3301 adds r3, #1 80004ba: 61bb str r3, [r7, #24] 80004bc: 69bb ldr r3, [r7, #24] 80004be: 2b07 cmp r3, #7 80004c0: d9c3 bls.n 800044a GPIOx->BSRR = (((uint32_t)0x01) << pinpos); } } } } GPIOx->CRL = tmpreg; 80004c2: 687b ldr r3, [r7, #4] 80004c4: 697a ldr r2, [r7, #20] 80004c6: 601a str r2, [r3, #0] } /*---------------------------- GPIO CRH Configuration ------------------------*/ /* Configure the eight high port pins */ if (GPIO_InitStruct->GPIO_Pin > 0x00FF) 80004c8: 683b ldr r3, [r7, #0] 80004ca: 881b ldrh r3, [r3, #0] 80004cc: 2bff cmp r3, #255 ; 0xff 80004ce: d946 bls.n 800055e { tmpreg = GPIOx->CRH; 80004d0: 687b ldr r3, [r7, #4] 80004d2: 685b ldr r3, [r3, #4] 80004d4: 617b str r3, [r7, #20] for (pinpos = 0x00; pinpos < 0x08; pinpos++) 80004d6: 2300 movs r3, #0 80004d8: 61bb str r3, [r7, #24] 80004da: e03a b.n 8000552 { pos = (((uint32_t)0x01) << (pinpos + 0x08)); 80004dc: 69bb ldr r3, [r7, #24] 80004de: 3308 adds r3, #8 80004e0: 2201 movs r2, #1 80004e2: fa02 f303 lsl.w r3, r2, r3 80004e6: 60fb str r3, [r7, #12] /* Get the port pins position */ currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); 80004e8: 683b ldr r3, [r7, #0] 80004ea: 881b ldrh r3, [r3, #0] 80004ec: 461a mov r2, r3 80004ee: 68fb ldr r3, [r7, #12] 80004f0: 4013 ands r3, r2 80004f2: 613b str r3, [r7, #16] if (currentpin == pos) 80004f4: 693a ldr r2, [r7, #16] 80004f6: 68fb ldr r3, [r7, #12] 80004f8: 429a cmp r2, r3 80004fa: d127 bne.n 800054c { pos = pinpos << 2; 80004fc: 69bb ldr r3, [r7, #24] 80004fe: 009b lsls r3, r3, #2 8000500: 60fb str r3, [r7, #12] /* Clear the corresponding high control register bits */ pinmask = ((uint32_t)0x0F) << pos; 8000502: 220f movs r2, #15 8000504: 68fb ldr r3, [r7, #12] 8000506: fa02 f303 lsl.w r3, r2, r3 800050a: 60bb str r3, [r7, #8] tmpreg &= ~pinmask; 800050c: 68bb ldr r3, [r7, #8] 800050e: 43db mvns r3, r3 8000510: 697a ldr r2, [r7, #20] 8000512: 4013 ands r3, r2 8000514: 617b str r3, [r7, #20] /* Write the mode configuration in the corresponding bits */ tmpreg |= (currentmode << pos); 8000516: 69fa ldr r2, [r7, #28] 8000518: 68fb ldr r3, [r7, #12] 800051a: fa02 f303 lsl.w r3, r2, r3 800051e: 697a ldr r2, [r7, #20] 8000520: 4313 orrs r3, r2 8000522: 617b str r3, [r7, #20] /* Reset the corresponding ODR bit */ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) 8000524: 683b ldr r3, [r7, #0] 8000526: 78db ldrb r3, [r3, #3] 8000528: 2b28 cmp r3, #40 ; 0x28 800052a: d105 bne.n 8000538 { GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08)); 800052c: 69bb ldr r3, [r7, #24] 800052e: 3308 adds r3, #8 8000530: 2201 movs r2, #1 8000532: 409a lsls r2, r3 8000534: 687b ldr r3, [r7, #4] 8000536: 615a str r2, [r3, #20] } /* Set the corresponding ODR bit */ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) 8000538: 683b ldr r3, [r7, #0] 800053a: 78db ldrb r3, [r3, #3] 800053c: 2b48 cmp r3, #72 ; 0x48 800053e: d105 bne.n 800054c { GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08)); 8000540: 69bb ldr r3, [r7, #24] 8000542: 3308 adds r3, #8 8000544: 2201 movs r2, #1 8000546: 409a lsls r2, r3 8000548: 687b ldr r3, [r7, #4] 800054a: 611a str r2, [r3, #16] /*---------------------------- GPIO CRH Configuration ------------------------*/ /* Configure the eight high port pins */ if (GPIO_InitStruct->GPIO_Pin > 0x00FF) { tmpreg = GPIOx->CRH; for (pinpos = 0x00; pinpos < 0x08; pinpos++) 800054c: 69bb ldr r3, [r7, #24] 800054e: 3301 adds r3, #1 8000550: 61bb str r3, [r7, #24] 8000552: 69bb ldr r3, [r7, #24] 8000554: 2b07 cmp r3, #7 8000556: d9c1 bls.n 80004dc { GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08)); } } } GPIOx->CRH = tmpreg; 8000558: 687b ldr r3, [r7, #4] 800055a: 697a ldr r2, [r7, #20] 800055c: 605a str r2, [r3, #4] } } 800055e: bf00 nop 8000560: 3724 adds r7, #36 ; 0x24 8000562: 46bd mov sp, r7 8000564: bc80 pop {r7} 8000566: 4770 bx lr 08000568 : void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 8000568: b480 push {r7} 800056a: b083 sub sp, #12 800056c: af00 add r7, sp, #0 800056e: 6078 str r0, [r7, #4] 8000570: 460b mov r3, r1 8000572: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); GPIOx->BSRR = GPIO_Pin; 8000574: 887a ldrh r2, [r7, #2] 8000576: 687b ldr r3, [r7, #4] 8000578: 611a str r2, [r3, #16] } 800057a: bf00 nop 800057c: 370c adds r7, #12 800057e: 46bd mov sp, r7 8000580: bc80 pop {r7} 8000582: 4770 bx lr 08000584 : void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 8000584: b480 push {r7} 8000586: b083 sub sp, #12 8000588: af00 add r7, sp, #0 800058a: 6078 str r0, [r7, #4] 800058c: 460b mov r3, r1 800058e: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); GPIOx->BRR = GPIO_Pin; 8000590: 887a ldrh r2, [r7, #2] 8000592: 687b ldr r3, [r7, #4] 8000594: 615a str r2, [r3, #20] } 8000596: bf00 nop 8000598: 370c adds r7, #12 800059a: 46bd mov sp, r7 800059c: bc80 pop {r7} 800059e: 4770 bx lr 080005a0 : void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) { 80005a0: b480 push {r7} 80005a2: b083 sub sp, #12 80005a4: af00 add r7, sp, #0 80005a6: 6078 str r0, [r7, #4] 80005a8: 460b mov r3, r1 80005aa: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 80005ac: 78fb ldrb r3, [r7, #3] 80005ae: 2b00 cmp r3, #0 80005b0: d006 beq.n 80005c0 { RCC->APB2ENR |= RCC_APB2Periph; 80005b2: 4909 ldr r1, [pc, #36] ; (80005d8 ) 80005b4: 4b08 ldr r3, [pc, #32] ; (80005d8 ) 80005b6: 699a ldr r2, [r3, #24] 80005b8: 687b ldr r3, [r7, #4] 80005ba: 4313 orrs r3, r2 80005bc: 618b str r3, [r1, #24] } else { RCC->APB2ENR &= ~RCC_APB2Periph; } } 80005be: e006 b.n 80005ce { RCC->APB2ENR |= RCC_APB2Periph; } else { RCC->APB2ENR &= ~RCC_APB2Periph; 80005c0: 4905 ldr r1, [pc, #20] ; (80005d8 ) 80005c2: 4b05 ldr r3, [pc, #20] ; (80005d8 ) 80005c4: 699a ldr r2, [r3, #24] 80005c6: 687b ldr r3, [r7, #4] 80005c8: 43db mvns r3, r3 80005ca: 4013 ands r3, r2 80005cc: 618b str r3, [r1, #24] } } 80005ce: bf00 nop 80005d0: 370c adds r7, #12 80005d2: 46bd mov sp, r7 80005d4: bc80 pop {r7} 80005d6: 4770 bx lr 80005d8: 40021000 .word 0x40021000 080005dc : FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) { 80005dc: b480 push {r7} 80005de: b085 sub sp, #20 80005e0: af00 add r7, sp, #0 80005e2: 6078 str r0, [r7, #4] 80005e4: 460b mov r3, r1 80005e6: 807b strh r3, [r7, #2] FlagStatus bitstatus = RESET; 80005e8: 2300 movs r3, #0 80005ea: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); /* Check the status of the specified SPI/I2S flag */ if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) 80005ec: 687b ldr r3, [r7, #4] 80005ee: 891b ldrh r3, [r3, #8] 80005f0: b29a uxth r2, r3 80005f2: 887b ldrh r3, [r7, #2] 80005f4: 4013 ands r3, r2 80005f6: b29b uxth r3, r3 80005f8: 2b00 cmp r3, #0 80005fa: d002 beq.n 8000602 { /* SPI_I2S_FLAG is set */ bitstatus = SET; 80005fc: 2301 movs r3, #1 80005fe: 73fb strb r3, [r7, #15] 8000600: e001 b.n 8000606 } else { /* SPI_I2S_FLAG is reset */ bitstatus = RESET; 8000602: 2300 movs r3, #0 8000604: 73fb strb r3, [r7, #15] } /* Return the SPI_I2S_FLAG status */ return bitstatus; 8000606: 7bfb ldrb r3, [r7, #15] } 8000608: 4618 mov r0, r3 800060a: 3714 adds r7, #20 800060c: 46bd mov sp, r7 800060e: bc80 pop {r7} 8000610: 4770 bx lr 8000612: bf00 nop 08000614 : void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) { 8000614: b480 push {r7} 8000616: b083 sub sp, #12 8000618: af00 add r7, sp, #0 800061a: 6078 str r0, [r7, #4] 800061c: 460b mov r3, r1 800061e: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); /* Write in the DR register the data to be sent */ SPIx->DR = Data; 8000620: 687b ldr r3, [r7, #4] 8000622: 887a ldrh r2, [r7, #2] 8000624: 819a strh r2, [r3, #12] } 8000626: bf00 nop 8000628: 370c adds r7, #12 800062a: 46bd mov sp, r7 800062c: bc80 pop {r7} 800062e: 4770 bx lr 08000630 : uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) { 8000630: b480 push {r7} 8000632: b083 sub sp, #12 8000634: af00 add r7, sp, #0 8000636: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); /* Return the data in the DR register */ return SPIx->DR; 8000638: 687b ldr r3, [r7, #4] 800063a: 899b ldrh r3, [r3, #12] 800063c: b29b uxth r3, r3 } 800063e: 4618 mov r0, r3 8000640: 370c adds r7, #12 8000642: 46bd mov sp, r7 8000644: bc80 pop {r7} 8000646: 4770 bx lr 08000648 : void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) { 8000648: b480 push {r7} 800064a: b085 sub sp, #20 800064c: af00 add r7, sp, #0 800064e: 6078 str r0, [r7, #4] 8000650: 6039 str r1, [r7, #0] uint16_t tmpreg = 0; 8000652: 2300 movs r3, #0 8000654: 81fb strh r3, [r7, #14] assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); /*---------------------------- SPIx CR1 Configuration ------------------------*/ /* Get the SPIx CR1 value */ tmpreg = SPIx->CR1; 8000656: 687b ldr r3, [r7, #4] 8000658: 881b ldrh r3, [r3, #0] 800065a: 81fb strh r3, [r7, #14] /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ tmpreg &= CR1_CLEAR_Mask; 800065c: 89fb ldrh r3, [r7, #14] 800065e: f403 5341 and.w r3, r3, #12352 ; 0x3040 8000662: 81fb strh r3, [r7, #14] /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ /* Set LSBFirst bit according to SPI_FirstBit value */ /* Set BR bits according to SPI_BaudRatePrescaler value */ /* Set CPOL bit according to SPI_CPOL value */ /* Set CPHA bit according to SPI_CPHA value */ tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | 8000664: 683b ldr r3, [r7, #0] 8000666: 881a ldrh r2, [r3, #0] 8000668: 683b ldr r3, [r7, #0] 800066a: 885b ldrh r3, [r3, #2] 800066c: 4313 orrs r3, r2 800066e: b29a uxth r2, r3 SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | 8000670: 683b ldr r3, [r7, #0] 8000672: 889b ldrh r3, [r3, #4] /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ /* Set LSBFirst bit according to SPI_FirstBit value */ /* Set BR bits according to SPI_BaudRatePrescaler value */ /* Set CPOL bit according to SPI_CPOL value */ /* Set CPHA bit according to SPI_CPHA value */ tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | 8000674: 4313 orrs r3, r2 8000676: b29a uxth r2, r3 SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | 8000678: 683b ldr r3, [r7, #0] 800067a: 88db ldrh r3, [r3, #6] /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ /* Set LSBFirst bit according to SPI_FirstBit value */ /* Set BR bits according to SPI_BaudRatePrescaler value */ /* Set CPOL bit according to SPI_CPOL value */ /* Set CPHA bit according to SPI_CPHA value */ tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | 800067c: 4313 orrs r3, r2 800067e: b29a uxth r2, r3 SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | 8000680: 683b ldr r3, [r7, #0] 8000682: 891b ldrh r3, [r3, #8] /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ /* Set LSBFirst bit according to SPI_FirstBit value */ /* Set BR bits according to SPI_BaudRatePrescaler value */ /* Set CPOL bit according to SPI_CPOL value */ /* Set CPHA bit according to SPI_CPHA value */ tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | 8000684: 4313 orrs r3, r2 8000686: b29a uxth r2, r3 SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | 8000688: 683b ldr r3, [r7, #0] 800068a: 895b ldrh r3, [r3, #10] /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ /* Set LSBFirst bit according to SPI_FirstBit value */ /* Set BR bits according to SPI_BaudRatePrescaler value */ /* Set CPOL bit according to SPI_CPOL value */ /* Set CPHA bit according to SPI_CPHA value */ tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | 800068c: 4313 orrs r3, r2 800068e: b29a uxth r2, r3 SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); 8000690: 683b ldr r3, [r7, #0] 8000692: 899b ldrh r3, [r3, #12] /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ /* Set LSBFirst bit according to SPI_FirstBit value */ /* Set BR bits according to SPI_BaudRatePrescaler value */ /* Set CPOL bit according to SPI_CPOL value */ /* Set CPHA bit according to SPI_CPHA value */ tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | 8000694: 4313 orrs r3, r2 8000696: b29a uxth r2, r3 SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); 8000698: 683b ldr r3, [r7, #0] 800069a: 89db ldrh r3, [r3, #14] /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ /* Set LSBFirst bit according to SPI_FirstBit value */ /* Set BR bits according to SPI_BaudRatePrescaler value */ /* Set CPOL bit according to SPI_CPOL value */ /* Set CPHA bit according to SPI_CPHA value */ tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | 800069c: 4313 orrs r3, r2 800069e: b29a uxth r2, r3 80006a0: 89fb ldrh r3, [r7, #14] 80006a2: 4313 orrs r3, r2 80006a4: 81fb strh r3, [r7, #14] SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); /* Write to SPIx CR1 */ SPIx->CR1 = tmpreg; 80006a6: 687b ldr r3, [r7, #4] 80006a8: 89fa ldrh r2, [r7, #14] 80006aa: 801a strh r2, [r3, #0] /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ SPIx->I2SCFGR &= SPI_Mode_Select; 80006ac: 687b ldr r3, [r7, #4] 80006ae: 8b9b ldrh r3, [r3, #28] 80006b0: b29b uxth r3, r3 80006b2: f423 6300 bic.w r3, r3, #2048 ; 0x800 80006b6: b29a uxth r2, r3 80006b8: 687b ldr r3, [r7, #4] 80006ba: 839a strh r2, [r3, #28] /*---------------------------- SPIx CRCPOLY Configuration --------------------*/ /* Write to SPIx CRCPOLY */ SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; 80006bc: 683b ldr r3, [r7, #0] 80006be: 8a1a ldrh r2, [r3, #16] 80006c0: 687b ldr r3, [r7, #4] 80006c2: 821a strh r2, [r3, #16] } 80006c4: bf00 nop 80006c6: 3714 adds r7, #20 80006c8: 46bd mov sp, r7 80006ca: bc80 pop {r7} 80006cc: 4770 bx lr 80006ce: bf00 nop 080006d0 : void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) { 80006d0: b480 push {r7} 80006d2: b083 sub sp, #12 80006d4: af00 add r7, sp, #0 80006d6: 6078 str r0, [r7, #4] 80006d8: 460b mov r3, r1 80006da: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 80006dc: 78fb ldrb r3, [r7, #3] 80006de: 2b00 cmp r3, #0 80006e0: d008 beq.n 80006f4 { /* Enable the selected SPI peripheral */ SPIx->CR1 |= CR1_SPE_Set; 80006e2: 687b ldr r3, [r7, #4] 80006e4: 881b ldrh r3, [r3, #0] 80006e6: b29b uxth r3, r3 80006e8: f043 0340 orr.w r3, r3, #64 ; 0x40 80006ec: b29a uxth r2, r3 80006ee: 687b ldr r3, [r7, #4] 80006f0: 801a strh r2, [r3, #0] else { /* Disable the selected SPI peripheral */ SPIx->CR1 &= CR1_SPE_Reset; } } 80006f2: e007 b.n 8000704 SPIx->CR1 |= CR1_SPE_Set; } else { /* Disable the selected SPI peripheral */ SPIx->CR1 &= CR1_SPE_Reset; 80006f4: 687b ldr r3, [r7, #4] 80006f6: 881b ldrh r3, [r3, #0] 80006f8: b29b uxth r3, r3 80006fa: f023 0340 bic.w r3, r3, #64 ; 0x40 80006fe: b29a uxth r2, r3 8000700: 687b ldr r3, [r7, #4] 8000702: 801a strh r2, [r3, #0] } } 8000704: bf00 nop 8000706: 370c adds r7, #12 8000708: 46bd mov sp, r7 800070a: bc80 pop {r7} 800070c: 4770 bx lr 800070e: bf00 nop 08000710 : void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) { 8000710: b480 push {r7} 8000712: b083 sub sp, #12 8000714: af00 add r7, sp, #0 8000716: 6078 str r0, [r7, #4] 8000718: 460b mov r3, r1 800071a: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 800071c: 78fb ldrb r3, [r7, #3] 800071e: 2b00 cmp r3, #0 8000720: d006 beq.n 8000730 { /* Set the ADON bit to wake up the ADC from power down mode */ ADCx->CR2 |= CR2_ADON_Set; 8000722: 687b ldr r3, [r7, #4] 8000724: 689b ldr r3, [r3, #8] 8000726: f043 0201 orr.w r2, r3, #1 800072a: 687b ldr r3, [r7, #4] 800072c: 609a str r2, [r3, #8] else { /* Disable the selected ADC peripheral */ ADCx->CR2 &= CR2_ADON_Reset; } } 800072e: e005 b.n 800073c ADCx->CR2 |= CR2_ADON_Set; } else { /* Disable the selected ADC peripheral */ ADCx->CR2 &= CR2_ADON_Reset; 8000730: 687b ldr r3, [r7, #4] 8000732: 689b ldr r3, [r3, #8] 8000734: f023 0201 bic.w r2, r3, #1 8000738: 687b ldr r3, [r7, #4] 800073a: 609a str r2, [r3, #8] } } 800073c: bf00 nop 800073e: 370c adds r7, #12 8000740: 46bd mov sp, r7 8000742: bc80 pop {r7} 8000744: 4770 bx lr 8000746: bf00 nop 08000748 : void ADC_ResetCalibration(ADC_TypeDef* ADCx) { 8000748: b480 push {r7} 800074a: b083 sub sp, #12 800074c: af00 add r7, sp, #0 800074e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Resets the selected ADC calibration registers */ ADCx->CR2 |= CR2_RSTCAL_Set; 8000750: 687b ldr r3, [r7, #4] 8000752: 689b ldr r3, [r3, #8] 8000754: f043 0208 orr.w r2, r3, #8 8000758: 687b ldr r3, [r7, #4] 800075a: 609a str r2, [r3, #8] } 800075c: bf00 nop 800075e: 370c adds r7, #12 8000760: 46bd mov sp, r7 8000762: bc80 pop {r7} 8000764: 4770 bx lr 8000766: bf00 nop 08000768 : FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx) { 8000768: b480 push {r7} 800076a: b085 sub sp, #20 800076c: af00 add r7, sp, #0 800076e: 6078 str r0, [r7, #4] FlagStatus bitstatus = RESET; 8000770: 2300 movs r3, #0 8000772: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Check the status of RSTCAL bit */ if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET) 8000774: 687b ldr r3, [r7, #4] 8000776: 689b ldr r3, [r3, #8] 8000778: f003 0308 and.w r3, r3, #8 800077c: 2b00 cmp r3, #0 800077e: d002 beq.n 8000786 { /* RSTCAL bit is set */ bitstatus = SET; 8000780: 2301 movs r3, #1 8000782: 73fb strb r3, [r7, #15] 8000784: e001 b.n 800078a } else { /* RSTCAL bit is reset */ bitstatus = RESET; 8000786: 2300 movs r3, #0 8000788: 73fb strb r3, [r7, #15] } /* Return the RSTCAL bit status */ return bitstatus; 800078a: 7bfb ldrb r3, [r7, #15] } 800078c: 4618 mov r0, r3 800078e: 3714 adds r7, #20 8000790: 46bd mov sp, r7 8000792: bc80 pop {r7} 8000794: 4770 bx lr 8000796: bf00 nop 08000798 : void ADC_StartCalibration(ADC_TypeDef* ADCx) { 8000798: b480 push {r7} 800079a: b083 sub sp, #12 800079c: af00 add r7, sp, #0 800079e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Enable the selected ADC calibration process */ ADCx->CR2 |= CR2_CAL_Set; 80007a0: 687b ldr r3, [r7, #4] 80007a2: 689b ldr r3, [r3, #8] 80007a4: f043 0204 orr.w r2, r3, #4 80007a8: 687b ldr r3, [r7, #4] 80007aa: 609a str r2, [r3, #8] } 80007ac: bf00 nop 80007ae: 370c adds r7, #12 80007b0: 46bd mov sp, r7 80007b2: bc80 pop {r7} 80007b4: 4770 bx lr 80007b6: bf00 nop 080007b8 : FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx) { 80007b8: b480 push {r7} 80007ba: b085 sub sp, #20 80007bc: af00 add r7, sp, #0 80007be: 6078 str r0, [r7, #4] FlagStatus bitstatus = RESET; 80007c0: 2300 movs r3, #0 80007c2: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Check the status of CAL bit */ if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET) 80007c4: 687b ldr r3, [r7, #4] 80007c6: 689b ldr r3, [r3, #8] 80007c8: f003 0304 and.w r3, r3, #4 80007cc: 2b00 cmp r3, #0 80007ce: d002 beq.n 80007d6 { /* CAL bit is set: calibration on going */ bitstatus = SET; 80007d0: 2301 movs r3, #1 80007d2: 73fb strb r3, [r7, #15] 80007d4: e001 b.n 80007da } else { /* CAL bit is reset: end of calibration */ bitstatus = RESET; 80007d6: 2300 movs r3, #0 80007d8: 73fb strb r3, [r7, #15] } /* Return the CAL bit status */ return bitstatus; 80007da: 7bfb ldrb r3, [r7, #15] } 80007dc: 4618 mov r0, r3 80007de: 3714 adds r7, #20 80007e0: 46bd mov sp, r7 80007e2: bc80 pop {r7} 80007e4: 4770 bx lr 80007e6: bf00 nop 080007e8 : void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) { 80007e8: b480 push {r7} 80007ea: b083 sub sp, #12 80007ec: af00 add r7, sp, #0 80007ee: 6078 str r0, [r7, #4] 80007f0: 460b mov r3, r1 80007f2: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 80007f4: 78fb ldrb r3, [r7, #3] 80007f6: 2b00 cmp r3, #0 80007f8: d006 beq.n 8000808 { /* Enable the selected ADC conversion on external event and start the selected ADC conversion */ ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set; 80007fa: 687b ldr r3, [r7, #4] 80007fc: 689b ldr r3, [r3, #8] 80007fe: f443 02a0 orr.w r2, r3, #5242880 ; 0x500000 8000802: 687b ldr r3, [r7, #4] 8000804: 609a str r2, [r3, #8] { /* Disable the selected ADC conversion on external event and stop the selected ADC conversion */ ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset; } } 8000806: e005 b.n 8000814 } else { /* Disable the selected ADC conversion on external event and stop the selected ADC conversion */ ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset; 8000808: 687b ldr r3, [r7, #4] 800080a: 689b ldr r3, [r3, #8] 800080c: f423 02a0 bic.w r2, r3, #5242880 ; 0x500000 8000810: 687b ldr r3, [r7, #4] 8000812: 609a str r2, [r3, #8] } } 8000814: bf00 nop 8000816: 370c adds r7, #12 8000818: 46bd mov sp, r7 800081a: bc80 pop {r7} 800081c: 4770 bx lr 800081e: bf00 nop 08000820 : void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) { 8000820: b480 push {r7} 8000822: b085 sub sp, #20 8000824: af00 add r7, sp, #0 8000826: 6078 str r0, [r7, #4] 8000828: 6039 str r1, [r7, #0] uint32_t tmpreg1 = 0; 800082a: 2300 movs r3, #0 800082c: 60fb str r3, [r7, #12] uint8_t tmpreg2 = 0; 800082e: 2300 movs r3, #0 8000830: 72fb strb r3, [r7, #11] assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel)); /*---------------------------- ADCx CR1 Configuration -----------------*/ /* Get the ADCx CR1 value */ tmpreg1 = ADCx->CR1; 8000832: 687b ldr r3, [r7, #4] 8000834: 685b ldr r3, [r3, #4] 8000836: 60fb str r3, [r7, #12] /* Clear DUALMOD and SCAN bits */ tmpreg1 &= CR1_CLEAR_Mask; 8000838: 68fb ldr r3, [r7, #12] 800083a: f403 5341 and.w r3, r3, #12352 ; 0x3040 800083e: 60fb str r3, [r7, #12] /* Configure ADCx: Dual mode and scan conversion mode */ /* Set DUALMOD bits according to ADC_Mode value */ /* Set SCAN bit according to ADC_ScanConvMode value */ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); 8000840: 683b ldr r3, [r7, #0] 8000842: 681a ldr r2, [r3, #0] 8000844: 683b ldr r3, [r7, #0] 8000846: 791b ldrb r3, [r3, #4] 8000848: 021b lsls r3, r3, #8 800084a: 4313 orrs r3, r2 800084c: 68fa ldr r2, [r7, #12] 800084e: 4313 orrs r3, r2 8000850: 60fb str r3, [r7, #12] /* Write to ADCx CR1 */ ADCx->CR1 = tmpreg1; 8000852: 687b ldr r3, [r7, #4] 8000854: 68fa ldr r2, [r7, #12] 8000856: 605a str r2, [r3, #4] /*---------------------------- ADCx CR2 Configuration -----------------*/ /* Get the ADCx CR2 value */ tmpreg1 = ADCx->CR2; 8000858: 687b ldr r3, [r7, #4] 800085a: 689b ldr r3, [r3, #8] 800085c: 60fb str r3, [r7, #12] /* Clear CONT, ALIGN and EXTSEL bits */ tmpreg1 &= CR2_CLEAR_Mask; 800085e: 68fa ldr r2, [r7, #12] 8000860: 4b16 ldr r3, [pc, #88] ; (80008bc ) 8000862: 4013 ands r3, r2 8000864: 60fb str r3, [r7, #12] /* Configure ADCx: external trigger event and continuous conversion mode */ /* Set ALIGN bit according to ADC_DataAlign value */ /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ /* Set CONT bit according to ADC_ContinuousConvMode value */ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | 8000866: 683b ldr r3, [r7, #0] 8000868: 68da ldr r2, [r3, #12] 800086a: 683b ldr r3, [r7, #0] 800086c: 689b ldr r3, [r3, #8] 800086e: 431a orrs r2, r3 ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); 8000870: 683b ldr r3, [r7, #0] 8000872: 795b ldrb r3, [r3, #5] 8000874: 005b lsls r3, r3, #1 tmpreg1 &= CR2_CLEAR_Mask; /* Configure ADCx: external trigger event and continuous conversion mode */ /* Set ALIGN bit according to ADC_DataAlign value */ /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ /* Set CONT bit according to ADC_ContinuousConvMode value */ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | 8000876: 4313 orrs r3, r2 8000878: 68fa ldr r2, [r7, #12] 800087a: 4313 orrs r3, r2 800087c: 60fb str r3, [r7, #12] ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); /* Write to ADCx CR2 */ ADCx->CR2 = tmpreg1; 800087e: 687b ldr r3, [r7, #4] 8000880: 68fa ldr r2, [r7, #12] 8000882: 609a str r2, [r3, #8] /*---------------------------- ADCx SQR1 Configuration -----------------*/ /* Get the ADCx SQR1 value */ tmpreg1 = ADCx->SQR1; 8000884: 687b ldr r3, [r7, #4] 8000886: 6adb ldr r3, [r3, #44] ; 0x2c 8000888: 60fb str r3, [r7, #12] /* Clear L bits */ tmpreg1 &= SQR1_CLEAR_Mask; 800088a: 68fb ldr r3, [r7, #12] 800088c: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000 8000890: 60fb str r3, [r7, #12] /* Configure ADCx: regular channel sequence length */ /* Set L bits according to ADC_NbrOfChannel value */ tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); 8000892: 683b ldr r3, [r7, #0] 8000894: 7c1b ldrb r3, [r3, #16] 8000896: 3b01 subs r3, #1 8000898: b2da uxtb r2, r3 800089a: 7afb ldrb r3, [r7, #11] 800089c: 4313 orrs r3, r2 800089e: 72fb strb r3, [r7, #11] tmpreg1 |= (uint32_t)tmpreg2 << 20; 80008a0: 7afb ldrb r3, [r7, #11] 80008a2: 051b lsls r3, r3, #20 80008a4: 68fa ldr r2, [r7, #12] 80008a6: 4313 orrs r3, r2 80008a8: 60fb str r3, [r7, #12] /* Write to ADCx SQR1 */ ADCx->SQR1 = tmpreg1; 80008aa: 687b ldr r3, [r7, #4] 80008ac: 68fa ldr r2, [r7, #12] 80008ae: 62da str r2, [r3, #44] ; 0x2c } 80008b0: bf00 nop 80008b2: 3714 adds r7, #20 80008b4: 46bd mov sp, r7 80008b6: bc80 pop {r7} 80008b8: 4770 bx lr 80008ba: bf00 nop 80008bc: fff1f7fd .word 0xfff1f7fd 080008c0 : uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) { 80008c0: b480 push {r7} 80008c2: b083 sub sp, #12 80008c4: af00 add r7, sp, #0 80008c6: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Return the selected ADC conversion value */ return (uint16_t) ADCx->DR; 80008c8: 687b ldr r3, [r7, #4] 80008ca: 6cdb ldr r3, [r3, #76] ; 0x4c 80008cc: b29b uxth r3, r3 } 80008ce: 4618 mov r0, r3 80008d0: 370c adds r7, #12 80008d2: 46bd mov sp, r7 80008d4: bc80 pop {r7} 80008d6: 4770 bx lr 080008d8 : uint8_t SD_WriteByte(uint8_t Data) { 80008d8: b580 push {r7, lr} 80008da: b082 sub sp, #8 80008dc: af00 add r7, sp, #0 80008de: 4603 mov r3, r0 80008e0: 71fb strb r3, [r7, #7] /*!< Wait until the transmit buffer is empty */ while(SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_TXE) == RESET) 80008e2: bf00 nop 80008e4: 2102 movs r1, #2 80008e6: 480e ldr r0, [pc, #56] ; (8000920 ) 80008e8: f7ff fe78 bl 80005dc 80008ec: 4603 mov r3, r0 80008ee: 2b00 cmp r3, #0 80008f0: d0f8 beq.n 80008e4 { } /*!< Send the byte */ SPI_I2S_SendData(SD_SPI, Data); 80008f2: 79fb ldrb r3, [r7, #7] 80008f4: b29b uxth r3, r3 80008f6: 4619 mov r1, r3 80008f8: 4809 ldr r0, [pc, #36] ; (8000920 ) 80008fa: f7ff fe8b bl 8000614 /*!< Wait to receive a byte*/ while(SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_RXNE) == RESET) 80008fe: bf00 nop 8000900: 2101 movs r1, #1 8000902: 4807 ldr r0, [pc, #28] ; (8000920 ) 8000904: f7ff fe6a bl 80005dc 8000908: 4603 mov r3, r0 800090a: 2b00 cmp r3, #0 800090c: d0f8 beq.n 8000900 { } /*!< Return the byte read from the SPI bus */ return SPI_I2S_ReceiveData(SD_SPI); 800090e: 4804 ldr r0, [pc, #16] ; (8000920 ) 8000910: f7ff fe8e bl 8000630 8000914: 4603 mov r3, r0 8000916: b2db uxtb r3, r3 } 8000918: 4618 mov r0, r3 800091a: 3708 adds r7, #8 800091c: 46bd mov sp, r7 800091e: bd80 pop {r7, pc} 8000920: 40003800 .word 0x40003800 08000924 : void SD_LowLevel_Init(void) { 8000924: b580 push {r7, lr} 8000926: b086 sub sp, #24 8000928: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStructure; SPI_InitTypeDef SPI_InitStructure; /*!< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); 800092a: 2101 movs r1, #1 800092c: 2004 movs r0, #4 800092e: f7ff fe37 bl 80005a0 /*!< SD_SPI Periph clock enable */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE); 8000932: 2101 movs r1, #1 8000934: f44f 5080 mov.w r0, #4096 ; 0x1000 8000938: f7ff fe32 bl 80005a0 /*!< Configure SD_SPI pins: SCK */ GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN | SD_SPI_MOSI_PIN | SD_SPI_MISO_PIN; 800093c: f44f 4360 mov.w r3, #57344 ; 0xe000 8000940: 82bb strh r3, [r7, #20] GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 8000942: 2303 movs r3, #3 8000944: 75bb strb r3, [r7, #22] GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; 8000946: 2318 movs r3, #24 8000948: 75fb strb r3, [r7, #23] GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); 800094a: f107 0314 add.w r3, r7, #20 800094e: 4619 mov r1, r3 8000950: 4817 ldr r0, [pc, #92] ; (80009b0 ) 8000952: f7ff fd4d bl 80003f0 /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */ GPIO_InitStructure.GPIO_Pin = SD_CS_PIN; 8000956: f44f 5380 mov.w r3, #4096 ; 0x1000 800095a: 82bb strh r3, [r7, #20] GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; 800095c: 2310 movs r3, #16 800095e: 75fb strb r3, [r7, #23] GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure); 8000960: f107 0314 add.w r3, r7, #20 8000964: 4619 mov r1, r3 8000966: 4812 ldr r0, [pc, #72] ; (80009b0 ) 8000968: f7ff fd42 bl 80003f0 /*!< SD_SPI Config */ SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; 800096c: 2300 movs r3, #0 800096e: 803b strh r3, [r7, #0] SPI_InitStructure.SPI_Mode = SPI_Mode_Master; 8000970: f44f 7382 mov.w r3, #260 ; 0x104 8000974: 807b strh r3, [r7, #2] SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; 8000976: 2300 movs r3, #0 8000978: 80bb strh r3, [r7, #4] SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; 800097a: 2302 movs r3, #2 800097c: 80fb strh r3, [r7, #6] SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; 800097e: 2301 movs r3, #1 8000980: 813b strh r3, [r7, #8] SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; 8000982: f44f 7300 mov.w r3, #512 ; 0x200 8000986: 817b strh r3, [r7, #10] SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; 8000988: 2300 movs r3, #0 800098a: 81bb strh r3, [r7, #12] SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; 800098c: 2300 movs r3, #0 800098e: 81fb strh r3, [r7, #14] SPI_InitStructure.SPI_CRCPolynomial = 7; 8000990: 2307 movs r3, #7 8000992: 823b strh r3, [r7, #16] SPI_Init(SD_SPI, &SPI_InitStructure); 8000994: 463b mov r3, r7 8000996: 4619 mov r1, r3 8000998: 4806 ldr r0, [pc, #24] ; (80009b4 ) 800099a: f7ff fe55 bl 8000648 SPI_Cmd(SD_SPI, ENABLE); /*!< SD_SPI enable */ 800099e: 2101 movs r1, #1 80009a0: 4804 ldr r0, [pc, #16] ; (80009b4 ) 80009a2: f7ff fe95 bl 80006d0 } 80009a6: bf00 nop 80009a8: 3718 adds r7, #24 80009aa: 46bd mov sp, r7 80009ac: bd80 pop {r7, pc} 80009ae: bf00 nop 80009b0: 40010c00 .word 0x40010c00 80009b4: 40003800 .word 0x40003800 080009b8 : SD_Error SD_GoIdleState(void) { 80009b8: b580 push {r7, lr} 80009ba: af00 add r7, sp, #0 /*!< SD chip select low */ SD_CS_LOW(); 80009bc: f44f 5180 mov.w r1, #4096 ; 0x1000 80009c0: 4819 ldr r0, [pc, #100] ; (8000a28 ) 80009c2: f7ff fddf bl 8000584 /*!< Send CMD0 (SD_CMD_GO_IDLE_STATE) to put SD in SPI mode */ SD_SendCmd(SD_CMD_GO_IDLE_STATE, 0, 0x95); 80009c6: 2295 movs r2, #149 ; 0x95 80009c8: 2100 movs r1, #0 80009ca: 2000 movs r0, #0 80009cc: f000 f82e bl 8000a2c /*!< Wait for In Idle State Response (R1 Format) equal to 0x01 */ if (SD_GetResponse(SD_IN_IDLE_STATE)) 80009d0: 2001 movs r0, #1 80009d2: f000 f861 bl 8000a98 80009d6: 4603 mov r3, r0 80009d8: 2b00 cmp r3, #0 80009da: d001 beq.n 80009e0 { /*!< No Idle State Response: return response failue */ return SD_RESPONSE_FAILURE; 80009dc: 23ff movs r3, #255 ; 0xff 80009de: e020 b.n 8000a22 } /*----------Activates the card initialization process-----------*/ do { /*!< SD chip select high */ SD_CS_HIGH(); 80009e0: f44f 5180 mov.w r1, #4096 ; 0x1000 80009e4: 4810 ldr r0, [pc, #64] ; (8000a28 ) 80009e6: f7ff fdbf bl 8000568 /*!< Send Dummy byte 0xFF */ SD_WriteByte(SD_DUMMY_BYTE); 80009ea: 20ff movs r0, #255 ; 0xff 80009ec: f7ff ff74 bl 80008d8 /*!< SD chip select low */ SD_CS_LOW(); 80009f0: f44f 5180 mov.w r1, #4096 ; 0x1000 80009f4: 480c ldr r0, [pc, #48] ; (8000a28 ) 80009f6: f7ff fdc5 bl 8000584 /*!< Send CMD1 (Activates the card process) until response equal to 0x0 */ SD_SendCmd(SD_CMD_SEND_OP_COND, 0, 0xFF); 80009fa: 22ff movs r2, #255 ; 0xff 80009fc: 2100 movs r1, #0 80009fe: 2001 movs r0, #1 8000a00: f000 f814 bl 8000a2c /*!< Wait for no error Response (R1 Format) equal to 0x00 */ } while (SD_GetResponse(SD_RESPONSE_NO_ERROR)); 8000a04: 2000 movs r0, #0 8000a06: f000 f847 bl 8000a98 8000a0a: 4603 mov r3, r0 8000a0c: 2b00 cmp r3, #0 8000a0e: d1e7 bne.n 80009e0 /*!< SD chip select high */ SD_CS_HIGH(); 8000a10: f44f 5180 mov.w r1, #4096 ; 0x1000 8000a14: 4804 ldr r0, [pc, #16] ; (8000a28 ) 8000a16: f7ff fda7 bl 8000568 /*!< Send dummy byte 0xFF */ SD_WriteByte(SD_DUMMY_BYTE); 8000a1a: 20ff movs r0, #255 ; 0xff 8000a1c: f7ff ff5c bl 80008d8 return SD_RESPONSE_NO_ERROR; 8000a20: 2300 movs r3, #0 } 8000a22: 4618 mov r0, r3 8000a24: bd80 pop {r7, pc} 8000a26: bf00 nop 8000a28: 40010c00 .word 0x40010c00 08000a2c : void SD_SendCmd(uint8_t Cmd, uint32_t Arg, uint8_t Crc) { 8000a2c: b580 push {r7, lr} 8000a2e: b086 sub sp, #24 8000a30: af00 add r7, sp, #0 8000a32: 4603 mov r3, r0 8000a34: 6039 str r1, [r7, #0] 8000a36: 71fb strb r3, [r7, #7] 8000a38: 4613 mov r3, r2 8000a3a: 71bb strb r3, [r7, #6] uint32_t i = 0x00; 8000a3c: 2300 movs r3, #0 8000a3e: 617b str r3, [r7, #20] uint8_t Frame[6]; Frame[0] = (Cmd | 0x40); /*!< Construct byte 1 */ 8000a40: 79fb ldrb r3, [r7, #7] 8000a42: f043 0340 orr.w r3, r3, #64 ; 0x40 8000a46: b2db uxtb r3, r3 8000a48: 733b strb r3, [r7, #12] Frame[1] = (uint8_t)(Arg >> 24); /*!< Construct byte 2 */ 8000a4a: 683b ldr r3, [r7, #0] 8000a4c: 0e1b lsrs r3, r3, #24 8000a4e: b2db uxtb r3, r3 8000a50: 737b strb r3, [r7, #13] Frame[2] = (uint8_t)(Arg >> 16); /*!< Construct byte 3 */ 8000a52: 683b ldr r3, [r7, #0] 8000a54: 0c1b lsrs r3, r3, #16 8000a56: b2db uxtb r3, r3 8000a58: 73bb strb r3, [r7, #14] Frame[3] = (uint8_t)(Arg >> 8); /*!< Construct byte 4 */ 8000a5a: 683b ldr r3, [r7, #0] 8000a5c: 0a1b lsrs r3, r3, #8 8000a5e: b2db uxtb r3, r3 8000a60: 73fb strb r3, [r7, #15] Frame[4] = (uint8_t)(Arg); /*!< Construct byte 5 */ 8000a62: 683b ldr r3, [r7, #0] 8000a64: b2db uxtb r3, r3 8000a66: 743b strb r3, [r7, #16] Frame[5] = (Crc); /*!< Construct CRC: byte 6 */ 8000a68: 79bb ldrb r3, [r7, #6] 8000a6a: 747b strb r3, [r7, #17] for (i = 0; i < 6; i++) 8000a6c: 2300 movs r3, #0 8000a6e: 617b str r3, [r7, #20] 8000a70: e00a b.n 8000a88 { SD_WriteByte(Frame[i]); /*!< Send the Cmd bytes */ 8000a72: f107 020c add.w r2, r7, #12 8000a76: 697b ldr r3, [r7, #20] 8000a78: 4413 add r3, r2 8000a7a: 781b ldrb r3, [r3, #0] 8000a7c: 4618 mov r0, r3 8000a7e: f7ff ff2b bl 80008d8 Frame[4] = (uint8_t)(Arg); /*!< Construct byte 5 */ Frame[5] = (Crc); /*!< Construct CRC: byte 6 */ for (i = 0; i < 6; i++) 8000a82: 697b ldr r3, [r7, #20] 8000a84: 3301 adds r3, #1 8000a86: 617b str r3, [r7, #20] 8000a88: 697b ldr r3, [r7, #20] 8000a8a: 2b05 cmp r3, #5 8000a8c: d9f1 bls.n 8000a72 { SD_WriteByte(Frame[i]); /*!< Send the Cmd bytes */ } } 8000a8e: bf00 nop 8000a90: 3718 adds r7, #24 8000a92: 46bd mov sp, r7 8000a94: bd80 pop {r7, pc} 8000a96: bf00 nop 08000a98 : SD_Error SD_GetResponse(uint8_t Response) { 8000a98: b580 push {r7, lr} 8000a9a: b084 sub sp, #16 8000a9c: af00 add r7, sp, #0 8000a9e: 4603 mov r3, r0 8000aa0: 71fb strb r3, [r7, #7] uint32_t Count = 0xFFF; 8000aa2: f640 73ff movw r3, #4095 ; 0xfff 8000aa6: 60fb str r3, [r7, #12] /*!< Check if response is got or a timeout is happen */ while ((SD_ReadByte() != Response) && Count) 8000aa8: e002 b.n 8000ab0 { Count--; 8000aaa: 68fb ldr r3, [r7, #12] 8000aac: 3b01 subs r3, #1 8000aae: 60fb str r3, [r7, #12] SD_Error SD_GetResponse(uint8_t Response) { uint32_t Count = 0xFFF; /*!< Check if response is got or a timeout is happen */ while ((SD_ReadByte() != Response) && Count) 8000ab0: f000 f812 bl 8000ad8 8000ab4: 4603 mov r3, r0 8000ab6: 461a mov r2, r3 8000ab8: 79fb ldrb r3, [r7, #7] 8000aba: 4293 cmp r3, r2 8000abc: d002 beq.n 8000ac4 8000abe: 68fb ldr r3, [r7, #12] 8000ac0: 2b00 cmp r3, #0 8000ac2: d1f2 bne.n 8000aaa { Count--; } if (Count == 0) 8000ac4: 68fb ldr r3, [r7, #12] 8000ac6: 2b00 cmp r3, #0 8000ac8: d101 bne.n 8000ace { /*!< After time out */ return SD_RESPONSE_FAILURE; 8000aca: 23ff movs r3, #255 ; 0xff 8000acc: e000 b.n 8000ad0 } else { /*!< Right response got */ return SD_RESPONSE_NO_ERROR; 8000ace: 2300 movs r3, #0 } } 8000ad0: 4618 mov r0, r3 8000ad2: 3710 adds r7, #16 8000ad4: 46bd mov sp, r7 8000ad6: bd80 pop {r7, pc} 08000ad8 : uint8_t SD_ReadByte(void) { 8000ad8: b580 push {r7, lr} 8000ada: b082 sub sp, #8 8000adc: af00 add r7, sp, #0 uint8_t Data = 0; 8000ade: 2300 movs r3, #0 8000ae0: 71fb strb r3, [r7, #7] /*!< Wait until the transmit buffer is empty */ while (SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_TXE) == RESET) 8000ae2: bf00 nop 8000ae4: 2102 movs r1, #2 8000ae6: 480e ldr r0, [pc, #56] ; (8000b20 ) 8000ae8: f7ff fd78 bl 80005dc 8000aec: 4603 mov r3, r0 8000aee: 2b00 cmp r3, #0 8000af0: d0f8 beq.n 8000ae4 { } /*!< Send the byte */ SPI_I2S_SendData(SD_SPI, SD_DUMMY_BYTE); 8000af2: 21ff movs r1, #255 ; 0xff 8000af4: 480a ldr r0, [pc, #40] ; (8000b20 ) 8000af6: f7ff fd8d bl 8000614 /*!< Wait until a data is received */ while (SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_RXNE) == RESET) 8000afa: bf00 nop 8000afc: 2101 movs r1, #1 8000afe: 4808 ldr r0, [pc, #32] ; (8000b20 ) 8000b00: f7ff fd6c bl 80005dc 8000b04: 4603 mov r3, r0 8000b06: 2b00 cmp r3, #0 8000b08: d0f8 beq.n 8000afc { } /*!< Get the received data */ Data = SPI_I2S_ReceiveData(SD_SPI); 8000b0a: 4805 ldr r0, [pc, #20] ; (8000b20 ) 8000b0c: f7ff fd90 bl 8000630 8000b10: 4603 mov r3, r0 8000b12: 71fb strb r3, [r7, #7] /*!< Return the shifted data */ return Data; 8000b14: 79fb ldrb r3, [r7, #7] } 8000b16: 4618 mov r0, r3 8000b18: 3708 adds r7, #8 8000b1a: 46bd mov sp, r7 8000b1c: bd80 pop {r7, pc} 8000b1e: bf00 nop 8000b20: 40003800 .word 0x40003800 08000b24 : uint8_t SD_GetDataResponse(void) { 8000b24: b580 push {r7, lr} 8000b26: b082 sub sp, #8 8000b28: af00 add r7, sp, #0 uint32_t i = 0; 8000b2a: 2300 movs r3, #0 8000b2c: 607b str r3, [r7, #4] uint8_t response, rvalue; while (i <= 64) 8000b2e: e01e b.n 8000b6e { /*!< Read resonse */ response = SD_ReadByte(); 8000b30: f7ff ffd2 bl 8000ad8 8000b34: 4603 mov r3, r0 8000b36: 70fb strb r3, [r7, #3] /*!< Mask unused bits */ response &= 0x1F; 8000b38: 78fb ldrb r3, [r7, #3] 8000b3a: f003 031f and.w r3, r3, #31 8000b3e: 70fb strb r3, [r7, #3] switch (response) 8000b40: 78fb ldrb r3, [r7, #3] 8000b42: 2b0b cmp r3, #11 8000b44: d006 beq.n 8000b54 8000b46: 2b0d cmp r3, #13 8000b48: d006 beq.n 8000b58 8000b4a: 2b05 cmp r3, #5 8000b4c: d106 bne.n 8000b5c { case SD_DATA_OK: { rvalue = SD_DATA_OK; 8000b4e: 2305 movs r3, #5 8000b50: 70bb strb r3, [r7, #2] break; 8000b52: e006 b.n 8000b62 } case SD_DATA_CRC_ERROR: return SD_DATA_CRC_ERROR; 8000b54: 230b movs r3, #11 8000b56: e016 b.n 8000b86 case SD_DATA_WRITE_ERROR: return SD_DATA_WRITE_ERROR; 8000b58: 230d movs r3, #13 8000b5a: e014 b.n 8000b86 default: { rvalue = SD_DATA_OTHER_ERROR; 8000b5c: 23ff movs r3, #255 ; 0xff 8000b5e: 70bb strb r3, [r7, #2] break; 8000b60: bf00 nop } } /*!< Exit loop in case of data ok */ if (rvalue == SD_DATA_OK) 8000b62: 78bb ldrb r3, [r7, #2] 8000b64: 2b05 cmp r3, #5 8000b66: d006 beq.n 8000b76 break; /*!< Increment loop counter */ i++; 8000b68: 687b ldr r3, [r7, #4] 8000b6a: 3301 adds r3, #1 8000b6c: 607b str r3, [r7, #4] uint8_t SD_GetDataResponse(void) { uint32_t i = 0; uint8_t response, rvalue; while (i <= 64) 8000b6e: 687b ldr r3, [r7, #4] 8000b70: 2b40 cmp r3, #64 ; 0x40 8000b72: d9dd bls.n 8000b30 8000b74: e000 b.n 8000b78 break; } } /*!< Exit loop in case of data ok */ if (rvalue == SD_DATA_OK) break; 8000b76: bf00 nop /*!< Increment loop counter */ i++; } /*!< Wait null data */ while (SD_ReadByte() == 0); 8000b78: bf00 nop 8000b7a: f7ff ffad bl 8000ad8 8000b7e: 4603 mov r3, r0 8000b80: 2b00 cmp r3, #0 8000b82: d0fa beq.n 8000b7a /*!< Return response */ return response; 8000b84: 78fb ldrb r3, [r7, #3] } 8000b86: 4618 mov r0, r3 8000b88: 3708 adds r7, #8 8000b8a: 46bd mov sp, r7 8000b8c: bd80 pop {r7, pc} 8000b8e: bf00 nop 08000b90 : SD_Error SD_Init(void) { 8000b90: b580 push {r7, lr} 8000b92: b082 sub sp, #8 8000b94: af00 add r7, sp, #0 uint32_t i = 0; 8000b96: 2300 movs r3, #0 8000b98: 607b str r3, [r7, #4] /*!< Initialize SD_SPI */ SD_LowLevel_Init(); 8000b9a: f7ff fec3 bl 8000924 /*!< SD chip select high */ SD_CS_HIGH(); 8000b9e: f44f 5180 mov.w r1, #4096 ; 0x1000 8000ba2: 480b ldr r0, [pc, #44] ; (8000bd0 ) 8000ba4: f7ff fce0 bl 8000568 /*!< Send dummy byte 0xFF, 10 times with CS high */ /*!< Rise CS and MOSI for 80 clocks cycles */ for (i = 0; i <= 9; i++) 8000ba8: 2300 movs r3, #0 8000baa: 607b str r3, [r7, #4] 8000bac: e005 b.n 8000bba { /*!< Send dummy byte 0xFF */ SD_WriteByte(SD_DUMMY_BYTE); 8000bae: 20ff movs r0, #255 ; 0xff 8000bb0: f7ff fe92 bl 80008d8 /*!< SD chip select high */ SD_CS_HIGH(); /*!< Send dummy byte 0xFF, 10 times with CS high */ /*!< Rise CS and MOSI for 80 clocks cycles */ for (i = 0; i <= 9; i++) 8000bb4: 687b ldr r3, [r7, #4] 8000bb6: 3301 adds r3, #1 8000bb8: 607b str r3, [r7, #4] 8000bba: 687b ldr r3, [r7, #4] 8000bbc: 2b09 cmp r3, #9 8000bbe: d9f6 bls.n 8000bae /*!< Send dummy byte 0xFF */ SD_WriteByte(SD_DUMMY_BYTE); } /*------------Put SD in SPI mode--------------*/ /*!< SD initialized and set to SPI mode properly */ return (SD_GoIdleState()); 8000bc0: f7ff fefa bl 80009b8 8000bc4: 4603 mov r3, r0 } 8000bc6: 4618 mov r0, r3 8000bc8: 3708 adds r7, #8 8000bca: 46bd mov sp, r7 8000bcc: bd80 pop {r7, pc} 8000bce: bf00 nop 8000bd0: 40010c00 .word 0x40010c00 08000bd4 <_checkSDStatus>: uint8_t _checkSDStatus() { 8000bd4: b580 push {r7, lr} 8000bd6: af00 add r7, sp, #0 if (SD_Status == SD_RESPONSE_NO_ERROR) 8000bd8: 4b09 ldr r3, [pc, #36] ; (8000c00 <_checkSDStatus+0x2c>) 8000bda: 881b ldrh r3, [r3, #0] 8000bdc: 2b00 cmp r3, #0 8000bde: d101 bne.n 8000be4 <_checkSDStatus+0x10> return 0; 8000be0: 2300 movs r3, #0 8000be2: e00a b.n 8000bfa <_checkSDStatus+0x26> do SD_Status = SD_Init(); 8000be4: f7ff ffd4 bl 8000b90 8000be8: 4603 mov r3, r0 8000bea: b29a uxth r2, r3 8000bec: 4b04 ldr r3, [pc, #16] ; (8000c00 <_checkSDStatus+0x2c>) 8000bee: 801a strh r2, [r3, #0] while (SD_Status != SD_RESPONSE_NO_ERROR); 8000bf0: 4b03 ldr r3, [pc, #12] ; (8000c00 <_checkSDStatus+0x2c>) 8000bf2: 881b ldrh r3, [r3, #0] 8000bf4: 2b00 cmp r3, #0 8000bf6: d1f5 bne.n 8000be4 <_checkSDStatus+0x10> return 1; 8000bf8: 2301 movs r3, #1 } 8000bfa: 4618 mov r0, r3 8000bfc: bd80 pop {r7, pc} 8000bfe: bf00 nop 8000c00: 20000018 .word 0x20000018 08000c04 : void checkSDStatus() { 8000c04: b580 push {r7, lr} 8000c06: af00 add r7, sp, #0 while (_checkSDStatus()) { 8000c08: bf00 nop 8000c0a: f7ff ffe3 bl 8000bd4 <_checkSDStatus> 8000c0e: 4603 mov r3, r0 8000c10: 2b00 cmp r3, #0 8000c12: d1fa bne.n 8000c0a //<----><------>writeBufFilled = 0; //<----><------>SDWriteOffset = SD_WriteHeaders(); } } 8000c14: bf00 nop 8000c16: bd80 pop {r7, pc} 08000c18 : SD_Error SD_WriteBlock(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t BlockSize) { 8000c18: b580 push {r7, lr} 8000c1a: b086 sub sp, #24 8000c1c: af00 add r7, sp, #0 8000c1e: 60f8 str r0, [r7, #12] 8000c20: 60b9 str r1, [r7, #8] 8000c22: 4613 mov r3, r2 8000c24: 80fb strh r3, [r7, #6] uint32_t i = 0; 8000c26: 2300 movs r3, #0 8000c28: 617b str r3, [r7, #20] SD_Error rvalue = SD_RESPONSE_FAILURE; 8000c2a: 23ff movs r3, #255 ; 0xff 8000c2c: 74fb strb r3, [r7, #19] /*!< SD chip select low */ SD_CS_LOW(); 8000c2e: f44f 5180 mov.w r1, #4096 ; 0x1000 8000c32: 481f ldr r0, [pc, #124] ; (8000cb0 ) 8000c34: f7ff fca6 bl 8000584 /*!< Send CMD24 (SD_CMD_WRITE_SINGLE_BLOCK) to write multiple block */ SD_SendCmd(SD_CMD_WRITE_SINGLE_BLOCK, WriteAddr, 0xFF); 8000c38: 22ff movs r2, #255 ; 0xff 8000c3a: 68b9 ldr r1, [r7, #8] 8000c3c: 2018 movs r0, #24 8000c3e: f7ff fef5 bl 8000a2c /*!< Check if the SD acknowledged the write block command: R1 response (0x00: no errors) */ if (!SD_GetResponse(SD_RESPONSE_NO_ERROR)) 8000c42: 2000 movs r0, #0 8000c44: f7ff ff28 bl 8000a98 8000c48: 4603 mov r3, r0 8000c4a: 2b00 cmp r3, #0 8000c4c: d122 bne.n 8000c94 { /*!< Send a dummy byte */ SD_WriteByte(SD_DUMMY_BYTE); 8000c4e: 20ff movs r0, #255 ; 0xff 8000c50: f7ff fe42 bl 80008d8 /*!< Send the data token to signify the start of the data */ SD_WriteByte(0xFE); 8000c54: 20fe movs r0, #254 ; 0xfe 8000c56: f7ff fe3f bl 80008d8 /*!< Write the block data to SD : write count data by block */ for (i = 0; i < BlockSize; i++) 8000c5a: 2300 movs r3, #0 8000c5c: 617b str r3, [r7, #20] 8000c5e: e00a b.n 8000c76 { /*!< Send the pointed byte */ SD_WriteByte(*pBuffer); 8000c60: 68fb ldr r3, [r7, #12] 8000c62: 781b ldrb r3, [r3, #0] 8000c64: 4618 mov r0, r3 8000c66: f7ff fe37 bl 80008d8 /*!< Point to the next location where the byte read will be saved */ pBuffer++; 8000c6a: 68fb ldr r3, [r7, #12] 8000c6c: 3301 adds r3, #1 8000c6e: 60fb str r3, [r7, #12] /*!< Send the data token to signify the start of the data */ SD_WriteByte(0xFE); /*!< Write the block data to SD : write count data by block */ for (i = 0; i < BlockSize; i++) 8000c70: 697b ldr r3, [r7, #20] 8000c72: 3301 adds r3, #1 8000c74: 617b str r3, [r7, #20] 8000c76: 88fa ldrh r2, [r7, #6] 8000c78: 697b ldr r3, [r7, #20] 8000c7a: 429a cmp r2, r3 8000c7c: d8f0 bhi.n 8000c60 SD_WriteByte(*pBuffer); /*!< Point to the next location where the byte read will be saved */ pBuffer++; } /*!< Put CRC bytes (not really needed by us, but required by SD) */ SD_ReadByte(); 8000c7e: f7ff ff2b bl 8000ad8 SD_ReadByte(); 8000c82: f7ff ff29 bl 8000ad8 /*!< Read data response */ if (SD_GetDataResponse() == SD_DATA_OK) 8000c86: f7ff ff4d bl 8000b24 8000c8a: 4603 mov r3, r0 8000c8c: 2b05 cmp r3, #5 8000c8e: d101 bne.n 8000c94 { rvalue = SD_RESPONSE_NO_ERROR; 8000c90: 2300 movs r3, #0 8000c92: 74fb strb r3, [r7, #19] } } /*!< SD chip select high */ SD_CS_HIGH(); 8000c94: f44f 5180 mov.w r1, #4096 ; 0x1000 8000c98: 4805 ldr r0, [pc, #20] ; (8000cb0 ) 8000c9a: f7ff fc65 bl 8000568 /*!< Send dummy byte: 8 Clock pulses of delay */ SD_WriteByte(SD_DUMMY_BYTE); 8000c9e: 20ff movs r0, #255 ; 0xff 8000ca0: f7ff fe1a bl 80008d8 /*!< Returns the reponse */ return rvalue; 8000ca4: 7cfb ldrb r3, [r7, #19] } 8000ca6: 4618 mov r0, r3 8000ca8: 3718 adds r7, #24 8000caa: 46bd mov sp, r7 8000cac: bd80 pop {r7, pc} 8000cae: bf00 nop 8000cb0: 40010c00 .word 0x40010c00 08000cb4 : #define SD_HEADERS "\000voltlogger\000\001\001\000\000Voltlogger0000\0000\0000" SD_Error SD_WriteBlock_1(uint32_t WriteAddr) { 8000cb4: b580 push {r7, lr} 8000cb6: b084 sub sp, #16 8000cb8: af00 add r7, sp, #0 8000cba: 6078 str r0, [r7, #4] Wstatus = BuffReady; 8000cbc: 4b3c ldr r3, [pc, #240] ; (8000db0 ) 8000cbe: 781a ldrb r2, [r3, #0] 8000cc0: 4b3c ldr r3, [pc, #240] ; (8000db4 ) 8000cc2: 701a strb r2, [r3, #0] BuffReady = 0; 8000cc4: 4b3a ldr r3, [pc, #232] ; (8000db0 ) 8000cc6: 2200 movs r2, #0 8000cc8: 701a strb r2, [r3, #0] uint32_t i = 0; 8000cca: 2300 movs r3, #0 8000ccc: 60fb str r3, [r7, #12] SD_Error rvalue = SD_RESPONSE_FAILURE; 8000cce: 23ff movs r3, #255 ; 0xff 8000cd0: 72fb strb r3, [r7, #11] SD_CS_LOW(); 8000cd2: f44f 5180 mov.w r1, #4096 ; 0x1000 8000cd6: 4838 ldr r0, [pc, #224] ; (8000db8 ) 8000cd8: f7ff fc54 bl 8000584 SD_SendCmd(SD_CMD_WRITE_SINGLE_BLOCK, WriteAddr, 0xFF); 8000cdc: 22ff movs r2, #255 ; 0xff 8000cde: 6879 ldr r1, [r7, #4] 8000ce0: 2018 movs r0, #24 8000ce2: f7ff fea3 bl 8000a2c if (!SD_GetResponse(SD_RESPONSE_NO_ERROR)) 8000ce6: 2000 movs r0, #0 8000ce8: f7ff fed6 bl 8000a98 8000cec: 4603 mov r3, r0 8000cee: 2b00 cmp r3, #0 8000cf0: d14e bne.n 8000d90 { SD_WriteByte(SD_DUMMY_BYTE); 8000cf2: 20ff movs r0, #255 ; 0xff 8000cf4: f7ff fdf0 bl 80008d8 SD_WriteByte(0xFE); 8000cf8: 20fe movs r0, #254 ; 0xfe 8000cfa: f7ff fded bl 80008d8 if (Wstatus == 1){ 8000cfe: 4b2d ldr r3, [pc, #180] ; (8000db4 ) 8000d00: 781b ldrb r3, [r3, #0] 8000d02: 2b01 cmp r3, #1 8000d04: d11a bne.n 8000d3c for (i = 0; i < SD_BUFSIZE/2; i += 1) 8000d06: 2300 movs r3, #0 8000d08: 60fb str r3, [r7, #12] 8000d0a: e014 b.n 8000d36 { SD_WriteByte(Buffer1[i]); 8000d0c: 4a2b ldr r2, [pc, #172] ; (8000dbc ) 8000d0e: 68fb ldr r3, [r7, #12] 8000d10: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8000d14: b2db uxtb r3, r3 8000d16: 4618 mov r0, r3 8000d18: f7ff fdde bl 80008d8 SD_WriteByte(Buffer1[i] >> 8); 8000d1c: 4a27 ldr r2, [pc, #156] ; (8000dbc ) 8000d1e: 68fb ldr r3, [r7, #12] 8000d20: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8000d24: 0a1b lsrs r3, r3, #8 8000d26: b29b uxth r3, r3 8000d28: b2db uxtb r3, r3 8000d2a: 4618 mov r0, r3 8000d2c: f7ff fdd4 bl 80008d8 if (!SD_GetResponse(SD_RESPONSE_NO_ERROR)) { SD_WriteByte(SD_DUMMY_BYTE); SD_WriteByte(0xFE); if (Wstatus == 1){ for (i = 0; i < SD_BUFSIZE/2; i += 1) 8000d30: 68fb ldr r3, [r7, #12] 8000d32: 3301 adds r3, #1 8000d34: 60fb str r3, [r7, #12] 8000d36: 68fb ldr r3, [r7, #12] 8000d38: 2bff cmp r3, #255 ; 0xff 8000d3a: d9e7 bls.n 8000d0c SD_WriteByte(Buffer1[i]); SD_WriteByte(Buffer1[i] >> 8); } } if (Wstatus == 2){ 8000d3c: 4b1d ldr r3, [pc, #116] ; (8000db4 ) 8000d3e: 781b ldrb r3, [r3, #0] 8000d40: 2b02 cmp r3, #2 8000d42: d11a bne.n 8000d7a for (i = 0; i < SD_BUFSIZE/2; i += 1) 8000d44: 2300 movs r3, #0 8000d46: 60fb str r3, [r7, #12] 8000d48: e014 b.n 8000d74 { SD_WriteByte(Buffer2[i]); 8000d4a: 4a1d ldr r2, [pc, #116] ; (8000dc0 ) 8000d4c: 68fb ldr r3, [r7, #12] 8000d4e: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8000d52: b2db uxtb r3, r3 8000d54: 4618 mov r0, r3 8000d56: f7ff fdbf bl 80008d8 SD_WriteByte(Buffer2[i] >> 8); 8000d5a: 4a19 ldr r2, [pc, #100] ; (8000dc0 ) 8000d5c: 68fb ldr r3, [r7, #12] 8000d5e: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8000d62: 0a1b lsrs r3, r3, #8 8000d64: b29b uxth r3, r3 8000d66: b2db uxtb r3, r3 8000d68: 4618 mov r0, r3 8000d6a: f7ff fdb5 bl 80008d8 SD_WriteByte(Buffer1[i] >> 8); } } if (Wstatus == 2){ for (i = 0; i < SD_BUFSIZE/2; i += 1) 8000d6e: 68fb ldr r3, [r7, #12] 8000d70: 3301 adds r3, #1 8000d72: 60fb str r3, [r7, #12] 8000d74: 68fb ldr r3, [r7, #12] 8000d76: 2bff cmp r3, #255 ; 0xff 8000d78: d9e7 bls.n 8000d4a SD_WriteByte(Buffer2[i]); SD_WriteByte(Buffer2[i] >> 8); } } SD_ReadByte(); 8000d7a: f7ff fead bl 8000ad8 SD_ReadByte(); 8000d7e: f7ff feab bl 8000ad8 if (SD_GetDataResponse() == SD_DATA_OK) 8000d82: f7ff fecf bl 8000b24 8000d86: 4603 mov r3, r0 8000d88: 2b05 cmp r3, #5 8000d8a: d101 bne.n 8000d90 { rvalue = SD_RESPONSE_NO_ERROR; 8000d8c: 2300 movs r3, #0 8000d8e: 72fb strb r3, [r7, #11] } } SD_CS_HIGH(); 8000d90: f44f 5180 mov.w r1, #4096 ; 0x1000 8000d94: 4808 ldr r0, [pc, #32] ; (8000db8 ) 8000d96: f7ff fbe7 bl 8000568 SD_WriteByte(SD_DUMMY_BYTE); 8000d9a: 20ff movs r0, #255 ; 0xff 8000d9c: f7ff fd9c bl 80008d8 Wstatus = 0; 8000da0: 4b04 ldr r3, [pc, #16] ; (8000db4 ) 8000da2: 2200 movs r2, #0 8000da4: 701a strb r2, [r3, #0] return rvalue; 8000da6: 7afb ldrb r3, [r7, #11] } 8000da8: 4618 mov r0, r3 8000daa: 3710 adds r7, #16 8000dac: 46bd mov sp, r7 8000dae: bd80 pop {r7, pc} 8000db0: 20000630 .word 0x20000630 8000db4: 2000001b .word 0x2000001b 8000db8: 40010c00 .word 0x40010c00 8000dbc: 20000230 .word 0x20000230 8000dc0: 20000430 .word 0x20000430 08000dc4 : void ADC_Start (void){ 8000dc4: b580 push {r7, lr} 8000dc6: b086 sub sp, #24 8000dc8: af00 add r7, sp, #0 ADC_InitTypeDef ADC_InitStructure; GPIO_InitTypeDef GPIO_InitStructure; RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE); 8000dca: 2101 movs r1, #1 8000dcc: f44f 7000 mov.w r0, #512 ; 0x200 8000dd0: f7ff fbe6 bl 80005a0 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 ; 8000dd4: 2301 movs r3, #1 8000dd6: 803b strh r3, [r7, #0] GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN; 8000dd8: 2300 movs r3, #0 8000dda: 70fb strb r3, [r7, #3] GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz ; 8000ddc: 2302 movs r3, #2 8000dde: 70bb strb r3, [r7, #2] GPIO_Init(GPIOA, &GPIO_InitStructure); 8000de0: 463b mov r3, r7 8000de2: 4619 mov r1, r3 8000de4: 481a ldr r0, [pc, #104] ; (8000e50 ) 8000de6: f7ff fb03 bl 80003f0 ADC_InitStructure.ADC_Mode = ADC_Mode_Independent; 8000dea: 2300 movs r3, #0 8000dec: 607b str r3, [r7, #4] ADC_InitStructure.ADC_ScanConvMode = ENABLE; 8000dee: 2301 movs r3, #1 8000df0: 723b strb r3, [r7, #8] ADC_InitStructure.ADC_ContinuousConvMode = ENABLE; 8000df2: 2301 movs r3, #1 8000df4: 727b strb r3, [r7, #9] ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None; 8000df6: f44f 2360 mov.w r3, #917504 ; 0xe0000 8000dfa: 60fb str r3, [r7, #12] ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; 8000dfc: 2300 movs r3, #0 8000dfe: 613b str r3, [r7, #16] ADC_InitStructure.ADC_NbrOfChannel = 0; 8000e00: 2300 movs r3, #0 8000e02: 753b strb r3, [r7, #20] ADC_Init(ADC1, &ADC_InitStructure); 8000e04: 1d3b adds r3, r7, #4 8000e06: 4619 mov r1, r3 8000e08: 4812 ldr r0, [pc, #72] ; (8000e54 ) 8000e0a: f7ff fd09 bl 8000820 ADC_Cmd(ADC1, ENABLE); 8000e0e: 2101 movs r1, #1 8000e10: 4810 ldr r0, [pc, #64] ; (8000e54 ) 8000e12: f7ff fc7d bl 8000710 ADC_ResetCalibration(ADC1); 8000e16: 480f ldr r0, [pc, #60] ; (8000e54 ) 8000e18: f7ff fc96 bl 8000748 while(ADC_GetResetCalibrationStatus(ADC1)); 8000e1c: bf00 nop 8000e1e: 480d ldr r0, [pc, #52] ; (8000e54 ) 8000e20: f7ff fca2 bl 8000768 8000e24: 4603 mov r3, r0 8000e26: 2b00 cmp r3, #0 8000e28: d1f9 bne.n 8000e1e ADC_StartCalibration(ADC1); 8000e2a: 480a ldr r0, [pc, #40] ; (8000e54 ) 8000e2c: f7ff fcb4 bl 8000798 while(ADC_GetCalibrationStatus(ADC1)); 8000e30: bf00 nop 8000e32: 4808 ldr r0, [pc, #32] ; (8000e54 ) 8000e34: f7ff fcc0 bl 80007b8 8000e38: 4603 mov r3, r0 8000e3a: 2b00 cmp r3, #0 8000e3c: d1f9 bne.n 8000e32 ADC_SoftwareStartConvCmd(ADC1, ENABLE); 8000e3e: 2101 movs r1, #1 8000e40: 4804 ldr r0, [pc, #16] ; (8000e54 ) 8000e42: f7ff fcd1 bl 80007e8 } 8000e46: bf00 nop 8000e48: 3718 adds r7, #24 8000e4a: 46bd mov sp, r7 8000e4c: bd80 pop {r7, pc} 8000e4e: bf00 nop 8000e50: 40010800 .word 0x40010800 8000e54: 40012400 .word 0x40012400 08000e58 : uint32_t SD_WriteHeaders() { 8000e58: b580 push {r7, lr} 8000e5a: af00 add r7, sp, #0 //uint8_t header[SD_BUFSIZE]; memset(Buffer1, 0, SD_BUFSIZE); 8000e5c: f44f 7200 mov.w r2, #512 ; 0x200 8000e60: 2100 movs r1, #0 8000e62: 4809 ldr r0, [pc, #36] ; (8000e88 ) 8000e64: f000 f980 bl 8001168 memcpy(Buffer1, SD_HEADERS, sizeof(SD_HEADERS)); 8000e68: 2223 movs r2, #35 ; 0x23 8000e6a: 4908 ldr r1, [pc, #32] ; (8000e8c ) 8000e6c: 4806 ldr r0, [pc, #24] ; (8000e88 ) 8000e6e: f000 f903 bl 8001078 SD_Status = SD_WriteBlock_1(0); 8000e72: 2000 movs r0, #0 8000e74: f7ff ff1e bl 8000cb4 8000e78: 4603 mov r3, r0 8000e7a: b29a uxth r2, r3 8000e7c: 4b04 ldr r3, [pc, #16] ; (8000e90 ) 8000e7e: 801a strh r2, [r3, #0] return 1; // SD_BUFSIZE; 8000e80: 2301 movs r3, #1 } 8000e82: 4618 mov r0, r3 8000e84: bd80 pop {r7, pc} 8000e86: bf00 nop 8000e88: 20000230 .word 0x20000230 8000e8c: 0800125c .word 0x0800125c 8000e90: 20000018 .word 0x20000018 08000e94
: int main(void) { 8000e94: b580 push {r7, lr} 8000e96: af00 add r7, sp, #0 status = SD_Init(); 8000e98: f7ff fe7a bl 8000b90 8000e9c: 4603 mov r3, r0 8000e9e: 461a mov r2, r3 8000ea0: 4b15 ldr r3, [pc, #84] ; (8000ef8 ) 8000ea2: 601a str r2, [r3, #0] checkSDStatus(); 8000ea4: f7ff feae bl 8000c04 writeBufFilled = 0; 8000ea8: 4b14 ldr r3, [pc, #80] ; (8000efc ) 8000eaa: 2200 movs r2, #0 8000eac: 801a strh r2, [r3, #0] // SD_WriteHeaders(); SDWriteOffset = SD_BUFSIZE; 8000eae: 4b14 ldr r3, [pc, #80] ; (8000f00 ) 8000eb0: f44f 7200 mov.w r2, #512 ; 0x200 8000eb4: 601a str r2, [r3, #0] SystemCoreClockUpdate(); 8000eb6: f7ff f9a9 bl 800020c SysTick_Config(SystemCoreClock/5000); 8000eba: 4b12 ldr r3, [pc, #72] ; (8000f04 ) 8000ebc: 681b ldr r3, [r3, #0] 8000ebe: 4a12 ldr r2, [pc, #72] ; (8000f08 ) 8000ec0: fba2 2303 umull r2, r3, r2, r3 8000ec4: 0b1b lsrs r3, r3, #12 8000ec6: 4618 mov r0, r3 8000ec8: f7ff f94a bl 8000160 ADC_Start(); 8000ecc: f7ff ff7a bl 8000dc4 while (1) { if (BuffReady != 0){ 8000ed0: 4b0e ldr r3, [pc, #56] ; (8000f0c ) 8000ed2: 781b ldrb r3, [r3, #0] 8000ed4: 2b00 cmp r3, #0 8000ed6: d0fb beq.n 8000ed0 check=1; 8000ed8: 4b0d ldr r3, [pc, #52] ; (8000f10 ) 8000eda: 2201 movs r2, #1 8000edc: 701a strb r2, [r3, #0] SD_WriteBlock_1(SDWriteOffset); 8000ede: 4b08 ldr r3, [pc, #32] ; (8000f00 ) 8000ee0: 681b ldr r3, [r3, #0] 8000ee2: 4618 mov r0, r3 8000ee4: f7ff fee6 bl 8000cb4 SDWriteOffset = SDWriteOffset + SD_BUFSIZE; 8000ee8: 4b05 ldr r3, [pc, #20] ; (8000f00 ) 8000eea: 681b ldr r3, [r3, #0] 8000eec: f503 7300 add.w r3, r3, #512 ; 0x200 8000ef0: 4a03 ldr r2, [pc, #12] ; (8000f00 ) 8000ef2: 6013 str r3, [r2, #0] } } 8000ef4: e7ec b.n 8000ed0 8000ef6: bf00 nop 8000ef8: 20000014 .word 0x20000014 8000efc: 20000226 .word 0x20000226 8000f00: 20000228 .word 0x20000228 8000f04: 20000000 .word 0x20000000 8000f08: d1b71759 .word 0xd1b71759 8000f0c: 20000630 .word 0x20000630 8000f10: 20000632 .word 0x20000632 08000f14 : } void SysTick_Handler(void) { 8000f14: b480 push {r7} 8000f16: af00 add r7, sp, #0 //ADC1ConvertedValue = ADC_GetConversionValue(ADC1); ADC1ConvertedValue = 0xAA; 8000f18: 4b38 ldr r3, [pc, #224] ; (8000ffc ) 8000f1a: 22aa movs r2, #170 ; 0xaa 8000f1c: 801a strh r2, [r3, #0] if (Rstatus == 1 && Wstatus != 1){ 8000f1e: 4b38 ldr r3, [pc, #224] ; (8001000 ) 8000f20: 781b ldrb r3, [r3, #0] 8000f22: 2b01 cmp r3, #1 8000f24: d130 bne.n 8000f88 8000f26: 4b37 ldr r3, [pc, #220] ; (8001004 ) 8000f28: 781b ldrb r3, [r3, #0] 8000f2a: 2b01 cmp r3, #1 8000f2c: d02c beq.n 8000f88 Buffer1[BuffCount] = TMSTP; 8000f2e: 4b36 ldr r3, [pc, #216] ; (8001008 ) 8000f30: 781b ldrb r3, [r3, #0] 8000f32: 461a mov r2, r3 8000f34: 4b35 ldr r3, [pc, #212] ; (800100c ) 8000f36: 8819 ldrh r1, [r3, #0] 8000f38: 4b35 ldr r3, [pc, #212] ; (8001010 ) 8000f3a: f823 1012 strh.w r1, [r3, r2, lsl #1] BuffCount++; 8000f3e: 4b32 ldr r3, [pc, #200] ; (8001008 ) 8000f40: 781b ldrb r3, [r3, #0] 8000f42: 3301 adds r3, #1 8000f44: b2da uxtb r2, r3 8000f46: 4b30 ldr r3, [pc, #192] ; (8001008 ) 8000f48: 701a strb r2, [r3, #0] Buffer1[BuffCount] = ADC1ConvertedValue; 8000f4a: 4b2f ldr r3, [pc, #188] ; (8001008 ) 8000f4c: 781b ldrb r3, [r3, #0] 8000f4e: 461a mov r2, r3 8000f50: 4b2a ldr r3, [pc, #168] ; (8000ffc ) 8000f52: 881b ldrh r3, [r3, #0] 8000f54: b299 uxth r1, r3 8000f56: 4b2e ldr r3, [pc, #184] ; (8001010 ) 8000f58: f823 1012 strh.w r1, [r3, r2, lsl #1] BuffCount++; 8000f5c: 4b2a ldr r3, [pc, #168] ; (8001008 ) 8000f5e: 781b ldrb r3, [r3, #0] 8000f60: 3301 adds r3, #1 8000f62: b2da uxtb r2, r3 8000f64: 4b28 ldr r3, [pc, #160] ; (8001008 ) 8000f66: 701a strb r2, [r3, #0] TMSTP++; 8000f68: 4b28 ldr r3, [pc, #160] ; (800100c ) 8000f6a: 881b ldrh r3, [r3, #0] 8000f6c: 3301 adds r3, #1 8000f6e: b29a uxth r2, r3 8000f70: 4b26 ldr r3, [pc, #152] ; (800100c ) 8000f72: 801a strh r2, [r3, #0] if ( BuffCount == 0){ 8000f74: 4b24 ldr r3, [pc, #144] ; (8001008 ) 8000f76: 781b ldrb r3, [r3, #0] 8000f78: 2b00 cmp r3, #0 8000f7a: d105 bne.n 8000f88 Rstatus = 2; 8000f7c: 4b20 ldr r3, [pc, #128] ; (8001000 ) 8000f7e: 2202 movs r2, #2 8000f80: 701a strb r2, [r3, #0] BuffReady = 1; 8000f82: 4b24 ldr r3, [pc, #144] ; (8001014 ) 8000f84: 2201 movs r2, #1 8000f86: 701a strb r2, [r3, #0] } } if (Rstatus == 2 && Wstatus != 2){ 8000f88: 4b1d ldr r3, [pc, #116] ; (8001000 ) 8000f8a: 781b ldrb r3, [r3, #0] 8000f8c: 2b02 cmp r3, #2 8000f8e: d130 bne.n 8000ff2 8000f90: 4b1c ldr r3, [pc, #112] ; (8001004 ) 8000f92: 781b ldrb r3, [r3, #0] 8000f94: 2b02 cmp r3, #2 8000f96: d02c beq.n 8000ff2 Buffer2[BuffCount] = TMSTP; 8000f98: 4b1b ldr r3, [pc, #108] ; (8001008 ) 8000f9a: 781b ldrb r3, [r3, #0] 8000f9c: 461a mov r2, r3 8000f9e: 4b1b ldr r3, [pc, #108] ; (800100c ) 8000fa0: 8819 ldrh r1, [r3, #0] 8000fa2: 4b1d ldr r3, [pc, #116] ; (8001018 ) 8000fa4: f823 1012 strh.w r1, [r3, r2, lsl #1] BuffCount++; 8000fa8: 4b17 ldr r3, [pc, #92] ; (8001008 ) 8000faa: 781b ldrb r3, [r3, #0] 8000fac: 3301 adds r3, #1 8000fae: b2da uxtb r2, r3 8000fb0: 4b15 ldr r3, [pc, #84] ; (8001008 ) 8000fb2: 701a strb r2, [r3, #0] Buffer2[BuffCount] = ADC1ConvertedValue; 8000fb4: 4b14 ldr r3, [pc, #80] ; (8001008 ) 8000fb6: 781b ldrb r3, [r3, #0] 8000fb8: 461a mov r2, r3 8000fba: 4b10 ldr r3, [pc, #64] ; (8000ffc ) 8000fbc: 881b ldrh r3, [r3, #0] 8000fbe: b299 uxth r1, r3 8000fc0: 4b15 ldr r3, [pc, #84] ; (8001018 ) 8000fc2: f823 1012 strh.w r1, [r3, r2, lsl #1] BuffCount++; 8000fc6: 4b10 ldr r3, [pc, #64] ; (8001008 ) 8000fc8: 781b ldrb r3, [r3, #0] 8000fca: 3301 adds r3, #1 8000fcc: b2da uxtb r2, r3 8000fce: 4b0e ldr r3, [pc, #56] ; (8001008 ) 8000fd0: 701a strb r2, [r3, #0] TMSTP++; 8000fd2: 4b0e ldr r3, [pc, #56] ; (800100c ) 8000fd4: 881b ldrh r3, [r3, #0] 8000fd6: 3301 adds r3, #1 8000fd8: b29a uxth r2, r3 8000fda: 4b0c ldr r3, [pc, #48] ; (800100c ) 8000fdc: 801a strh r2, [r3, #0] if (BuffCount == 0){ 8000fde: 4b0a ldr r3, [pc, #40] ; (8001008 ) 8000fe0: 781b ldrb r3, [r3, #0] 8000fe2: 2b00 cmp r3, #0 8000fe4: d105 bne.n 8000ff2 Rstatus = 1; 8000fe6: 4b06 ldr r3, [pc, #24] ; (8001000 ) 8000fe8: 2201 movs r2, #1 8000fea: 701a strb r2, [r3, #0] BuffReady = 2; 8000fec: 4b09 ldr r3, [pc, #36] ; (8001014 ) 8000fee: 2202 movs r2, #2 8000ff0: 701a strb r2, [r3, #0] BuffReady = 2; // BuffCount = 0; } */ } 8000ff2: bf00 nop 8000ff4: 46bd mov sp, r7 8000ff6: bc80 pop {r7} 8000ff8: 4770 bx lr 8000ffa: bf00 nop 8000ffc: 2000022c .word 0x2000022c 8001000: 2000001a .word 0x2000001a 8001004: 2000001b .word 0x2000001b 8001008: 20000631 .word 0x20000631 800100c: 20000634 .word 0x20000634 8001010: 20000230 .word 0x20000230 8001014: 20000630 .word 0x20000630 8001018: 20000430 .word 0x20000430 800101c: 08001280 .word 0x08001280 8001020: 20000000 .word 0x20000000 8001024: 2000001c .word 0x2000001c 8001028: 2000001c .word 0x2000001c 800102c: 20000638 .word 0x20000638 08001030 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 8001030: 2100 movs r1, #0 b LoopCopyDataInit 8001032: e003 b.n 800103c 08001034 : CopyDataInit: ldr r3, =_sidata 8001034: 4b0a ldr r3, [pc, #40] ; (8001060 ) ldr r3, [r3, r1] 8001036: 585b ldr r3, [r3, r1] str r3, [r0, r1] 8001038: 5043 str r3, [r0, r1] adds r1, r1, #4 800103a: 3104 adds r1, #4 0800103c : LoopCopyDataInit: ldr r0, =_sdata 800103c: 4809 ldr r0, [pc, #36] ; (8001064 ) ldr r3, =_edata 800103e: 4b0a ldr r3, [pc, #40] ; (8001068 ) adds r2, r0, r1 8001040: 1842 adds r2, r0, r1 cmp r2, r3 8001042: 429a cmp r2, r3 bcc CopyDataInit 8001044: d3f6 bcc.n 8001034 ldr r2, =_sbss 8001046: 4a09 ldr r2, [pc, #36] ; (800106c ) b LoopFillZerobss 8001048: e002 b.n 8001050 0800104a : /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 800104a: 2300 movs r3, #0 str r3, [r2], #4 800104c: f842 3b04 str.w r3, [r2], #4 08001050 : LoopFillZerobss: ldr r3, = _ebss 8001050: 4b07 ldr r3, [pc, #28] ; (8001070 ) cmp r2, r3 8001052: 429a cmp r2, r3 bcc FillZerobss 8001054: d3f9 bcc.n 800104a /* Call the clock system intitialization function.*/ bl SystemInit 8001056: f7ff f8a5 bl 80001a4 /* Call the application's entry point.*/ bl main 800105a: f7ff ff1b bl 8000e94
bx lr 800105e: 4770 bx lr /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 b LoopCopyDataInit CopyDataInit: ldr r3, =_sidata 8001060: 08001280 .word 0x08001280 ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: ldr r0, =_sdata 8001064: 20000000 .word 0x20000000 ldr r3, =_edata 8001068: 2000001c .word 0x2000001c adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit ldr r2, =_sbss 800106c: 2000001c .word 0x2000001c FillZerobss: movs r3, #0 str r3, [r2], #4 LoopFillZerobss: ldr r3, = _ebss 8001070: 20000638 .word 0x20000638 08001074 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8001074: e7fe b.n 8001074 ... 08001078 : 8001078: e352000f cmp r2, #15 800107c: e92d40f0 push {r4, r5, r6, r7, lr} 8001080: 9a000029 bls 800112c 8001084: e1813000 orr r3, r1, r0 8001088: e3130003 tst r3, #3 800108c: 1a000031 bne 8001158 8001090: e1a0e002 mov lr, r2 8001094: e280c010 add ip, r0, #16 8001098: e2813010 add r3, r1, #16 800109c: e5137010 ldr r7, [r3, #-16] 80010a0: e513600c ldr r6, [r3, #-12] 80010a4: e5135008 ldr r5, [r3, #-8] 80010a8: e5134004 ldr r4, [r3, #-4] 80010ac: e24ee010 sub lr, lr, #16 80010b0: e35e000f cmp lr, #15 80010b4: e50c7010 str r7, [ip, #-16] 80010b8: e50c600c str r6, [ip, #-12] 80010bc: e50c5008 str r5, [ip, #-8] 80010c0: e50c4004 str r4, [ip, #-4] 80010c4: e2833010 add r3, r3, #16 80010c8: e28cc010 add ip, ip, #16 80010cc: 8afffff2 bhi 800109c 80010d0: e2423010 sub r3, r2, #16 80010d4: e3c3300f bic r3, r3, #15 80010d8: e202600f and r6, r2, #15 80010dc: e2833010 add r3, r3, #16 80010e0: e3560003 cmp r6, #3 80010e4: e0811003 add r1, r1, r3 80010e8: e0803003 add r3, r0, r3 80010ec: 9a00001b bls 8001160 80010f0: e1a04001 mov r4, r1 80010f4: e1a0c006 mov ip, r6 80010f8: e243e004 sub lr, r3, #4 80010fc: e24cc004 sub ip, ip, #4 8001100: e4945004 ldr r5, [r4], #4 8001104: e35c0003 cmp ip, #3 8001108: e5ae5004 str r5, [lr, #4]! 800110c: 8afffffa bhi 80010fc 8001110: e246c004 sub ip, r6, #4 8001114: e3ccc003 bic ip, ip, #3 8001118: e28cc004 add ip, ip, #4 800111c: e083300c add r3, r3, ip 8001120: e081100c add r1, r1, ip 8001124: e2022003 and r2, r2, #3 8001128: ea000000 b 8001130 800112c: e1a03000 mov r3, r0 8001130: e3520000 cmp r2, #0 8001134: 0a000005 beq 8001150 8001138: e2433001 sub r3, r3, #1 800113c: e0812002 add r2, r1, r2 8001140: e4d1c001 ldrb ip, [r1], #1 8001144: e1510002 cmp r1, r2 8001148: e5e3c001 strb ip, [r3, #1]! 800114c: 1afffffb bne 8001140 8001150: e8bd40f0 pop {r4, r5, r6, r7, lr} 8001154: e12fff1e bx lr 8001158: e1a03000 mov r3, r0 800115c: eafffff5 b 8001138 8001160: e1a02006 mov r2, r6 8001164: eafffff1 b 8001130 08001168 : 8001168: e3100003 tst r0, #3 800116c: e92d4010 push {r4, lr} 8001170: 0a000037 beq 8001254 8001174: e3520000 cmp r2, #0 8001178: e2422001 sub r2, r2, #1 800117c: 0a000032 beq 800124c 8001180: e201c0ff and ip, r1, #255 ; 0xff 8001184: e1a03000 mov r3, r0 8001188: ea000002 b 8001198 800118c: e3520000 cmp r2, #0 8001190: e2422001 sub r2, r2, #1 8001194: 0a00002c beq 800124c 8001198: e4c3c001 strb ip, [r3], #1 800119c: e3130003 tst r3, #3 80011a0: 1afffff9 bne 800118c 80011a4: e3520003 cmp r2, #3 80011a8: 9a000020 bls 8001230 80011ac: e201e0ff and lr, r1, #255 ; 0xff 80011b0: e18ee40e orr lr, lr, lr, lsl #8 80011b4: e352000f cmp r2, #15 80011b8: e18ee80e orr lr, lr, lr, lsl #16 80011bc: 9a000010 bls 8001204 80011c0: e1a04002 mov r4, r2 80011c4: e283c010 add ip, r3, #16 80011c8: e2444010 sub r4, r4, #16 80011cc: e354000f cmp r4, #15 80011d0: e50ce010 str lr, [ip, #-16] 80011d4: e50ce00c str lr, [ip, #-12] 80011d8: e50ce008 str lr, [ip, #-8] 80011dc: e50ce004 str lr, [ip, #-4] 80011e0: e28cc010 add ip, ip, #16 80011e4: 8afffff7 bhi 80011c8 80011e8: e242c010 sub ip, r2, #16 80011ec: e3ccc00f bic ip, ip, #15 80011f0: e202200f and r2, r2, #15 80011f4: e28cc010 add ip, ip, #16 80011f8: e3520003 cmp r2, #3 80011fc: e083300c add r3, r3, ip 8001200: 9a00000a bls 8001230 8001204: e1a04003 mov r4, r3 8001208: e1a0c002 mov ip, r2 800120c: e24cc004 sub ip, ip, #4 8001210: e35c0003 cmp ip, #3 8001214: e484e004 str lr, [r4], #4 8001218: 8afffffb bhi 800120c 800121c: e242c004 sub ip, r2, #4 8001220: e3ccc003 bic ip, ip, #3 8001224: e28cc004 add ip, ip, #4 8001228: e083300c add r3, r3, ip 800122c: e2022003 and r2, r2, #3 8001230: e3520000 cmp r2, #0 8001234: 120110ff andne r1, r1, #255 ; 0xff 8001238: 10832002 addne r2, r3, r2 800123c: 0a000002 beq 800124c 8001240: e4c31001 strb r1, [r3], #1 8001244: e1530002 cmp r3, r2 8001248: 1afffffc bne 8001240 800124c: e8bd4010 pop {r4, lr} 8001250: e12fff1e bx lr 8001254: e1a03000 mov r3, r0 8001258: eaffffd1 b 80011a4 800125c: 6c6f7600 .word 0x6c6f7600 8001260: 676f6c74 .word 0x676f6c74 8001264: 00726567 .word 0x00726567 8001268: 00000101 .word 0x00000101 800126c: 746c6f56 .word 0x746c6f56 8001270: 67676f6c .word 0x67676f6c 8001274: 30307265 .word 0x30307265 8001278: 30003030 .word 0x30003030 800127c: 00003000 .word 0x00003000