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- Release 14.7 Map P.20131013 (lin64)
- Xilinx Mapping Report File for Design 'input_schheme'
- Design Information
- ------------------
- Command Line : map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol
- high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
- -pr off -lc off -power off -o input_schheme_map.ncd input_schheme.ngd
- input_schheme.pcf
- Target Device : xc6slx9
- Target Package : tqg144
- Target Speed : -3
- Mapper Version : spartan6 -- $Revision: 1.55 $
- Mapped Date : Thu Jul 19 14:07:40 2018
- Design Summary
- --------------
- Number of errors: 0
- Number of warnings: 0
- Slice Logic Utilization:
- Number of Slice Registers: 4 out of 11,440 1%
- Number used as Flip Flops: 4
- Number used as Latches: 0
- Number used as Latch-thrus: 0
- Number used as AND/OR logics: 0
- Number of Slice LUTs: 2 out of 5,720 1%
- Number used as logic: 0 out of 5,720 0%
- Number used as Memory: 0 out of 1,440 0%
- Number used exclusively as route-thrus: 2
- Number with same-slice register load: 2
- Number with same-slice carry load: 0
- Number with other load: 0
- Slice Logic Distribution:
- Number of occupied Slices: 1 out of 1,430 1%
- Number of MUXCYs used: 0 out of 2,860 0%
- Number of LUT Flip Flop pairs used: 2
- Number with an unused Flip Flop: 0 out of 2 0%
- Number with an unused LUT: 0 out of 2 0%
- Number of fully used LUT-FF pairs: 2 out of 2 100%
- Number of unique control sets: 1
- Number of slice register sites lost
- to control set restrictions: 4 out of 11,440 1%
- A LUT Flip Flop pair for this architecture represents one LUT paired with
- one Flip Flop within a slice. A control set is a unique combination of
- clock, reset, set, and enable signals for a registered element.
- The Slice Logic Distribution report is not meaningful if the design is
- over-mapped for a non-slice resource or if Placement fails.
- IO Utilization:
- Number of bonded IOBs: 8 out of 102 7%
- Specific Feature Utilization:
- Number of RAMB16BWERs: 0 out of 32 0%
- Number of RAMB8BWERs: 0 out of 64 0%
- Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
- Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
- Number of BUFG/BUFGMUXs: 1 out of 16 6%
- Number used as BUFGs: 1
- Number used as BUFGMUX: 0
- Number of DCM/DCM_CLKGENs: 0 out of 4 0%
- Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
- Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
- Number of OLOGIC2/OSERDES2s: 0 out of 200 0%
- Number of BSCANs: 0 out of 4 0%
- Number of BUFHs: 0 out of 128 0%
- Number of BUFPLLs: 0 out of 8 0%
- Number of BUFPLL_MCBs: 0 out of 4 0%
- Number of DSP48A1s: 0 out of 16 0%
- Number of ICAPs: 0 out of 1 0%
- Number of MCBs: 0 out of 2 0%
- Number of PCILOGICSEs: 0 out of 2 0%
- Number of PLL_ADVs: 0 out of 2 0%
- Number of PMVs: 0 out of 1 0%
- Number of STARTUPs: 0 out of 1 0%
- Number of SUSPEND_SYNCs: 0 out of 1 0%
- Average Fanout of Non-Clock Nets: 2.12
- Peak Memory Usage: 698 MB
- Total REAL time to MAP completion: 4 secs
- Total CPU time to MAP completion: 4 secs
- Table of Contents
- -----------------
- Section 1 - Errors
- Section 2 - Warnings
- Section 3 - Informational
- Section 4 - Removed Logic Summary
- Section 5 - Removed Logic
- Section 6 - IOB Properties
- Section 7 - RPMs
- Section 8 - Guide Report
- Section 9 - Area Group and Partition Summary
- Section 10 - Timing Report
- Section 11 - Configuration String Information
- Section 12 - Control Set Information
- Section 13 - Utilization by Hierarchy
- Section 1 - Errors
- ------------------
- Section 2 - Warnings
- --------------------
- Section 3 - Informational
- -------------------------
- INFO:MapLib:562 - No environment variables are currently set.
- INFO:LIT:244 - All of the single ended outputs in this design are using slew
- rate limited output drivers. The delay on speed critical single ended outputs
- can be dramatically reduced by designating them as fast outputs.
- INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
- 0.000 to 85.000 Celsius)
- INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
- 1.260 Volts)
- INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
- (.mrp).
- INFO:Pack:1650 - Map created a placed design.
- Section 4 - Removed Logic Summary
- ---------------------------------
- Section 5 - Removed Logic
- -------------------------
- Section 6 - IOB Properties
- --------------------------
- +---------------------------------------------------------------------------------------------------------------------------------------------------------+
- | IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
- | | | | | Term | Strength | Rate | | | Delay |
- +---------------------------------------------------------------------------------------------------------------------------------------------------------+
- | XLXN_1 | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
- | XLXN_2 | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
- | XLXN_3 | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
- | XLXN_4 | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
- | clk | IOB | INPUT | LVCMOS25 | | | | | | |
- | data | IOB | INPUT | LVCMOS25 | | | | | | |
- | enbl | IOB | INPUT | LVCMOS25 | | | | | | |
- | rst | IOB | INPUT | LVCMOS25 | | | | | | |
- +---------------------------------------------------------------------------------------------------------------------------------------------------------+
- Section 7 - RPMs
- ----------------
- Section 8 - Guide Report
- ------------------------
- Guide not run on this design.
- Section 9 - Area Group and Partition Summary
- --------------------------------------------
- Partition Implementation Status
- -------------------------------
- No Partitions were found in this design.
- -------------------------------
- Area Group Information
- ----------------------
- No area groups were found in this design.
- ----------------------
- Section 10 - Timing Report
- --------------------------
- A logic-level (pre-route) timing report can be generated by using Xilinx static
- timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
- mapped NCD and PCF files. Please note that this timing report will be generated
- using estimated delay information. For accurate numbers, please generate a
- timing report with the post Place and Route NCD file.
- For more information about the Timing Analyzer, consult the Xilinx Timing
- Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
- Command Line Tools User Guide "TRACE" chapter.
- Section 11 - Configuration String Details
- -----------------------------------------
- Use the "-detail" map option to print out Configuration Strings
- Section 12 - Control Set Information
- ------------------------------------
- Use the "-detail" map option to print out Control Set Information.
- Section 13 - Utilization by Hierarchy
- -------------------------------------
- Use the "-detail" map option to print out the Utilization by Hierarchy section.
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