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- --------------------------------------------------------------------------------
- Release 14.7 Trace (lin64)
- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
- /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -v 3 -s 3 -n
- 3 -fastpaths -xml sdc.twx sdc.ncd -o sdc.twr sdc.pcf -ucf sdc.ucf
- Design file: sdc.ncd
- Physical constraint file: sdc.pcf
- Device,package,speed: xc6slx9,tqg144,C,-3 (PRODUCTION 1.23 2013-10-13)
- Report level: verbose report
- Environment Variable Effect
- -------------------- ------
- NONE No environment variables were set
- --------------------------------------------------------------------------------
- INFO:Timing:2698 - No timing constraints found, doing default enumeration.
- INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
- INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
- option. All paths that are not constrained will be reported in the
- unconstrained paths section(s) of the report.
- INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
- a 50 Ohm transmission line loading model. For the details of this model,
- and for more information on accounting for different loading conditions,
- please see the device datasheet.
- Data Sheet report:
- -----------------
- All values displayed in nanoseconds (ns)
- Setup/Hold to clock clock
- ------------+------------+------------+------------+------------+------------------+--------+
- |Max Setup to| Process |Max Hold to | Process | | Clock |
- Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
- ------------+------------+------------+------------+------------+------------------+--------+
- L_INIT | 2.322(R)| SLOW | -0.359(R)| SLOW |clock_BUFGP | 0.000|
- clear | 1.760(R)| SLOW | -0.675(R)| FAST |clock_BUFGP | 0.000|
- enbl | 3.096(R)| SLOW | -0.984(R)| FAST |clock_BUFGP | 0.000|
- up | 2.520(R)| SLOW | -0.841(R)| FAST |clock_BUFGP | 0.000|
- ------------+------------+------------+------------+------------+------------------+--------+
- Clock clock to Pad
- ------------+-----------------+------------+-----------------+------------+------------------+--------+
- |Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
- Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
- ------------+-----------------+------------+-----------------+------------+------------------+--------+
- A1 | 10.218(R)| SLOW | 4.998(R)| FAST |clock_BUFGP | 0.000|
- A2 | 9.422(R)| SLOW | 4.956(R)| FAST |clock_BUFGP | 0.000|
- B1 | 9.547(R)| SLOW | 4.969(R)| FAST |clock_BUFGP | 0.000|
- B2 | 8.979(R)| SLOW | 4.436(R)| FAST |clock_BUFGP | 0.000|
- ------------+-----------------+------------+-----------------+------------+------------------+--------+
- Clock to Setup on destination clock clock
- ---------------+---------+---------+---------+---------+
- | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
- Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
- ---------------+---------+---------+---------+---------+
- clock | 1.902| | | |
- ---------------+---------+---------+---------+---------+
- Analysis completed Wed Jul 18 18:56:43 2018
- --------------------------------------------------------------------------------
- Trace Settings:
- -------------------------
- Trace Settings
- Peak Memory Usage: 383 MB
|
