STM32_Devel/FPGA/CNC/step_driver_control/sdc_divider.syr

Release 14.7 - xst P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
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Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.04 secs
 
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Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.04 secs
 
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Reading design: sdc_divider.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "sdc_divider.prj"
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "sdc_divider"
Output Format                      : NGC
Target Device                      : xc6slx9-3-tqg144

---- Source Options
Top Module Name                    : sdc_divider
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Shift Register Extraction          : YES
ROM Style                          : Auto
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : Auto
Reduce Control Sets                : Auto
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file "/home/trurl/STM32_Devel/FPGA/CNC/step_driver_control/sdc_divider.vf" into library work
Parsing module <FTC_HXILINX_sdc_divider>.
Parsing module <COMP8_HXILINX_sdc_divider>.
Parsing module <SR8CE_HXILINX_sdc_divider>.
Parsing module <CB8CE_HXILINX_sdc_divider>.
Parsing module <sdc_divider>.
Analyzing Verilog file "/home/trurl/STM32_Devel/FPGA/CNC/step_driver_control/input_schheme.vf" into library work
Parsing module <SR8CE_HXILINX_input_schheme>.
Parsing module <input_schheme>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating module <sdc_divider>.

Elaborating module <SR8CE_HXILINX_sdc_divider>.

Elaborating module <CB8CE_HXILINX_sdc_divider>.
WARNING:HDLCompiler:413 - "/home/trurl/STM32_Devel/FPGA/CNC/step_driver_control/sdc_divider.vf" Line 103: Result of 9-bit expression is truncated to fit in 8-bit target.

Elaborating module <COMP8_HXILINX_sdc_divider>.

Elaborating module <FTC_HXILINX_sdc_divider>.

Elaborating module <OR2>.

Elaborating module <AND2>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <sdc_divider>.
    Related source file is "/home/trurl/STM32_Devel/FPGA/CNC/step_driver_control/sdc_divider.vf".
    Set property "HU_SET = XLXI_2_0" for instance <XLXI_2>.
    Set property "HU_SET = XLXI_3_3" for instance <XLXI_3>.
    Set property "HU_SET = XLXI_4_1" for instance <XLXI_4>.
    Set property "HU_SET = XLXI_7_2" for instance <XLXI_7>.
INFO:Xst:3210 - "/home/trurl/STM32_Devel/FPGA/CNC/step_driver_control/sdc_divider.vf" line 143: Output port <CEO> of the instance <XLXI_3> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/trurl/STM32_Devel/FPGA/CNC/step_driver_control/sdc_divider.vf" line 143: Output port <TC> of the instance <XLXI_3> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <sdc_divider> synthesized.

Synthesizing Unit <SR8CE_HXILINX_sdc_divider>.
    Related source file is "/home/trurl/STM32_Devel/FPGA/CNC/step_driver_control/sdc_divider.vf".
    Found 8-bit register for signal <Q>.
    Summary:
	inferred   8 D-type flip-flop(s).
Unit <SR8CE_HXILINX_sdc_divider> synthesized.

Synthesizing Unit <CB8CE_HXILINX_sdc_divider>.
    Related source file is "/home/trurl/STM32_Devel/FPGA/CNC/step_driver_control/sdc_divider.vf".
    Found 8-bit register for signal <Q>.
    Found 8-bit adder for signal <Q[7]_GND_3_o_add_0_OUT> created at line 103.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   8 D-type flip-flop(s).
Unit <CB8CE_HXILINX_sdc_divider> synthesized.

Synthesizing Unit <COMP8_HXILINX_sdc_divider>.
    Related source file is "/home/trurl/STM32_Devel/FPGA/CNC/step_driver_control/sdc_divider.vf".
    Found 8-bit comparator equal for signal <EQ> created at line 55
    Summary:
	inferred   1 Comparator(s).
Unit <COMP8_HXILINX_sdc_divider> synthesized.

Synthesizing Unit <FTC_HXILINX_sdc_divider>.
    Related source file is "/home/trurl/STM32_Devel/FPGA/CNC/step_driver_control/sdc_divider.vf".
        INIT = 1'b0
    Found 1-bit register for signal <Q>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <FTC_HXILINX_sdc_divider> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 1
 8-bit adder                                           : 1
# Registers                                            : 3
 1-bit register                                        : 1
 8-bit register                                        : 2
# Comparators                                          : 1
 8-bit comparator equal                                : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


Synthesizing (advanced) Unit <CB8CE_HXILINX_sdc_divider>.
The following registers are absorbed into counter <Q>: 1 register on signal <Q>.
Unit <CB8CE_HXILINX_sdc_divider> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Counters                                             : 1
 8-bit up counter                                      : 1
# Registers                                            : 9
 Flip-Flops                                            : 9
# Comparators                                          : 1
 8-bit comparator equal                                : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <sdc_divider> ...

Optimizing unit <SR8CE_HXILINX_sdc_divider> ...

Optimizing unit <CB8CE_HXILINX_sdc_divider> ...

Optimizing unit <FTC_HXILINX_sdc_divider> ...

Optimizing unit <COMP8_HXILINX_sdc_divider> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block sdc_divider, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 17
 Flip-Flops                                            : 17

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : sdc_divider.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 30
#      AND2                        : 1
#      GND                         : 1
#      INV                         : 2
#      LUT1                        : 6
#      LUT6                        : 3
#      MUXCY                       : 7
#      OR2                         : 1
#      VCC                         : 1
#      XORCY                       : 8
# FlipFlops/Latches                : 17
#      FDC                         : 1
#      FDCE                        : 16
# Clock Buffers                    : 2
#      BUFG                        : 1
#      BUFGP                       : 1
# IO Buffers                       : 6
#      IBUF                        : 5
#      OBUF                        : 1

Device utilization summary:
---------------------------

Selected Device : 6slx9tqg144-3 


Slice Logic Utilization: 
 Number of Slice Registers:              17  out of  11440     0%  
 Number of Slice LUTs:                   11  out of   5720     0%  
    Number used as Logic:                11  out of   5720     0%  

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:     28
   Number with an unused Flip Flop:      11  out of     28    39%  
   Number with an unused LUT:            17  out of     28    60%  
   Number of fully used LUT-FF pairs:     0  out of     28     0%  
   Number of unique control sets:         3

IO Utilization: 
 Number of IOs:                           7
 Number of bonded IOBs:                   7  out of    102     6%  

Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                2  out of     16    12%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
SYS_CLK                            | IBUF+BUFG              | 8     |
SET_DIV_CLK                        | BUFGP                  | 8     |
XLXI_4/EQ(XLXI_4/EQ83:O)           | NONE(*)(XLXI_7/Q)      | 1     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: 5.947ns (Maximum Frequency: 168.159MHz)
   Minimum input arrival time before clock: 4.747ns
   Maximum output required time after clock: 3.634ns
   Maximum combinational path delay: No path found

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'SYS_CLK'
  Clock period: 5.947ns (frequency: 168.159MHz)
  Total number of paths / destination ports: 100 / 16
-------------------------------------------------------------------------
Delay:               5.947ns (Levels of Logic = 6)
  Source:            XLXI_3/Q_2 (FF)
  Destination:       XLXI_3/Q_0 (FF)
  Source Clock:      SYS_CLK rising
  Destination Clock: SYS_CLK rising

  Data Path: XLXI_3/Q_2 to XLXI_3/Q_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             2   0.447   0.845  Q_2 (Q_2)
     end scope: 'XLXI_3:Q<2>'
     begin scope: 'XLXI_4:B<2>'
     LUT6:I3->O            1   0.205   0.684  EQ82 (EQ81)
     LUT6:I4->O            2   0.203   0.981  EQ83 (EQ)
     end scope: 'XLXI_4:EQ'
     AND2:I0->O            1   0.203   0.944  XLXI_17 (XLXN_12)
     OR2:I0->O             8   0.203   0.802  XLXI_16 (XLXN_8)
     begin scope: 'XLXI_3:CLR'
     FDCE:CLR                  0.430          Q_0
    ----------------------------------------
    Total                      5.947ns (1.691ns logic, 4.256ns route)
                                       (28.4% logic, 71.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'SET_DIV_CLK'
  Clock period: 1.165ns (frequency: 858.185MHz)
  Total number of paths / destination ports: 7 / 7
-------------------------------------------------------------------------
Delay:               1.165ns (Levels of Logic = 0)
  Source:            XLXI_2/Q_0 (FF)
  Destination:       XLXI_2/Q_1 (FF)
  Source Clock:      SET_DIV_CLK rising
  Destination Clock: SET_DIV_CLK rising

  Data Path: XLXI_2/Q_0 to XLXI_2/Q_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             2   0.447   0.616  Q_0 (Q_0)
     FDCE:D                    0.102          Q_1
    ----------------------------------------
    Total                      1.165ns (0.549ns logic, 0.616ns route)
                                       (47.1% logic, 52.9% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'XLXI_4/EQ'
  Clock period: 1.950ns (frequency: 512.794MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               1.950ns (Levels of Logic = 1)
  Source:            XLXI_7/Q (FF)
  Destination:       XLXI_7/Q (FF)
  Source Clock:      XLXI_4/EQ rising
  Destination Clock: XLXI_4/EQ rising

  Data Path: XLXI_7/Q to XLXI_7/Q
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   0.447   0.616  Q (Q)
     INV:I->O              1   0.206   0.579  Q_Q_MUX_9_o1_INV_0 (Q_Q_MUX_9_o)
     FDC:D                     0.102          Q
    ----------------------------------------
    Total                      1.950ns (0.755ns logic, 1.195ns route)
                                       (38.7% logic, 61.3% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'SYS_CLK'
  Total number of paths / destination ports: 24 / 16
-------------------------------------------------------------------------
Offset:              4.747ns (Levels of Logic = 4)
  Source:            SYS_CLK (PAD)
  Destination:       XLXI_3/Q_0 (FF)
  Destination Clock: SYS_CLK rising

  Data Path: SYS_CLK to XLXI_3/Q_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.222   0.924  SYS_CLK_IBUF (SYS_CLK_IBUF)
     AND2:I1->O            1   0.223   0.944  XLXI_17 (XLXN_12)
     OR2:I0->O             8   0.203   0.802  XLXI_16 (XLXN_8)
     begin scope: 'XLXI_3:CLR'
     FDCE:CLR                  0.430          Q_0
    ----------------------------------------
    Total                      4.747ns (2.078ns logic, 2.669ns route)
                                       (43.8% logic, 56.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'SET_DIV_CLK'
  Total number of paths / destination ports: 17 / 17
-------------------------------------------------------------------------
Offset:              2.508ns (Levels of Logic = 2)
  Source:            RST (PAD)
  Destination:       XLXI_2/Q_0 (FF)
  Destination Clock: SET_DIV_CLK rising

  Data Path: RST to XLXI_2/Q_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            10   1.222   0.856  RST_IBUF (RST_IBUF)
     begin scope: 'XLXI_2:CLR'
     FDCE:CLR                  0.430          Q_0
    ----------------------------------------
    Total                      2.508ns (1.652ns logic, 0.856ns route)
                                       (65.9% logic, 34.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'XLXI_4/EQ'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              2.508ns (Levels of Logic = 2)
  Source:            RST (PAD)
  Destination:       XLXI_7/Q (FF)
  Destination Clock: XLXI_4/EQ rising

  Data Path: RST to XLXI_7/Q
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            10   1.222   0.856  RST_IBUF (RST_IBUF)
     begin scope: 'XLXI_7:CLR'
     FDC:CLR                   0.430          Q
    ----------------------------------------
    Total                      2.508ns (1.652ns logic, 0.856ns route)
                                       (65.9% logic, 34.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_4/EQ'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              3.634ns (Levels of Logic = 2)
  Source:            XLXI_7/Q (FF)
  Destination:       MAIN_TICK (PAD)
  Source Clock:      XLXI_4/EQ rising

  Data Path: XLXI_7/Q to MAIN_TICK
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   0.447   0.616  Q (Q)
     end scope: 'XLXI_7:Q'
     OBUF:I->O                 2.571          MAIN_TICK_OBUF (MAIN_TICK)
    ----------------------------------------
    Total                      3.634ns (3.018ns logic, 0.616ns route)
                                       (83.0% logic, 17.0% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock SET_DIV_CLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
SET_DIV_CLK    |    1.165|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock SYS_CLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
SET_DIV_CLK    |    6.081|         |         |         |
SYS_CLK        |    5.947|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock XLXI_4/EQ
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
XLXI_4/EQ      |    1.950|         |         |         |
---------------+---------+---------+---------+---------+

=========================================================================


Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 3.75 secs
 
--> 


Total memory usage is 386936 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    3 (   0 filtered)