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sdc_divider_summary.html

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  1. <HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
    2. 

  2. <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
    3. 

  3. <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
    4. 

  4. <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
    5. 

  5. <TD ALIGN=CENTER COLSPAN='4'><B>i7led_decoder_i7led_decoder_sch_tb Project Status</B></TD></TR>
    6. 

  6. <TR ALIGN=LEFT>
    7. 

  7. <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
    8. 

  8. <TD>step_driver_control.xise</TD>
    9. 

  9. <TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
    10. 

  10. <TD> No Errors </TD>
    11. 

  11. </TR>
    12. 

  12. <TR ALIGN=LEFT>
    13. 

  13. <TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
    14. 

  14. <TD>sdc_divider</TD>
    15. 

  15. <TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
    16. 

  16. <TD>Placed and Routed</TD>
    17. 

  17. </TR>
    18. 

  18. <TR ALIGN=LEFT>
    19. 

  19. <TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
    20. 

  20. <TD>xc6slx9-3tqg144</TD>
    21. 

  21. <TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
    22. 

  22. <TD>&nbsp;</TD>
    23. 

  23. </TR>
    24. 

  24. <TR ALIGN=LEFT>
    25. 

  25. <TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
    26. 

  26. <TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
    27. 

  27. <TD>&nbsp;</TD>
    28. 

  28. </TR>
    29. 

  29. <TR ALIGN=LEFT>
    30. 

  30. <TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
    31. 

  31. <TD>Balanced</TD>
    32. 

  32. <TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
    33. 

  33. <TD>
    34. 

  34. <A HREF_DISABLED='/home/lusius/Devel/STM32_Devel/FPGA/CNC/step_driver_control/sdc_divider.unroutes'>All Signals Completely Routed</A></TD>
    35. 

  35. </TR>
    36. 

  36. <TR ALIGN=LEFT>
    37. 

  37. <TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
    38. 

  38. <TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
    39. 

  39. <TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
    40. 

  40. <TD>
    41. 

  41. <A HREF_DISABLED='/home/lusius/Devel/STM32_Devel/FPGA/CNC/step_driver_control/sdc_divider.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
    42. 

  42. </TR>
    43. 

  43. <TR ALIGN=LEFT>
    44. 

  44. <TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
    45. 

  45. <TD>
    46. 

  46. <A HREF_DISABLED='/home/lusius/Devel/STM32_Devel/FPGA/CNC/step_driver_control/sdc_divider_envsettings.html'>
    47. 

  47. System Settings</A>
    48. 

  48. </TD>
    49. 

  49. <TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
    50. 

  50. <TD>0 &nbsp;<A HREF_DISABLED='/home/lusius/Devel/STM32_Devel/FPGA/CNC/step_driver_control/sdc_divider.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
    51. 

  51. </TR>
    52. 

  52. </TABLE>
    53. 

  53. 

  54. 

  55. 

  56. &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
    57. 

  57. <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
    58. 

  58. <TR ALIGN=CENTER BGCOLOR='#FFFF99'>
    59. 

  59. <TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
    60. 

  60. </TR>
    61. 

  61. <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
    62. 

  62. <TD ALIGN=RIGHT>17</TD>
    63. 

  63. <TD ALIGN=RIGHT>11,440</TD>
    64. 

  64. <TD ALIGN=RIGHT>1%</TD>
    65. 

  65. <TD COLSPAN='2'>&nbsp;</TD>
    66. 

  66. </TR>
    67. 

  67. <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD>
    68. 

  68. <TD ALIGN=RIGHT>17</TD>
    69. 

  69. <TD>&nbsp;</TD>
    70. 

  70. <TD>&nbsp;</TD>
    71. 

  71. <TD COLSPAN='2'>&nbsp;</TD>
    72. 

  72. </TR>
    73. 

  73. <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latches</TD>
    74. 

  74. <TD ALIGN=RIGHT>0</TD>
    75. 

  75. <TD>&nbsp;</TD>
    76. 

  76. <TD>&nbsp;</TD>
    77. 

  77. <TD COLSPAN='2'>&nbsp;</TD>
    78. 

  78. </TR>
    79. 

  79. <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latch-thrus</TD>
    80. 

  80. <TD ALIGN=RIGHT>0</TD>
    81. 

  81. <TD>&nbsp;</TD>
    82. 

  82. <TD>&nbsp;</TD>
    83. 

  83. <TD COLSPAN='2'>&nbsp;</TD>
    84. 

  84. </TR>
    85. 

  85. <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as AND/OR logics</TD>
    86. 

  86. <TD ALIGN=RIGHT>0</TD>
    87. 

  87. <TD>&nbsp;</TD>
    88. 

  88. <TD>&nbsp;</TD>
    89. 

  89. <TD COLSPAN='2'>&nbsp;</TD>
    90. 

  90. </TR>
    91. 

  91. <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
    92. 

  92. <TD ALIGN=RIGHT>13</TD>
    93. 

  93. <TD ALIGN=RIGHT>5,720</TD>
    94. 

  94. <TD ALIGN=RIGHT>1%</TD>
    95. 

  95. <TD COLSPAN='2'>&nbsp;</TD>
    96. 

  96. </TR>
    97. 

  97. <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
    98. 

  98. <TD ALIGN=RIGHT>12</TD>
    99. 

  99. <TD ALIGN=RIGHT>5,720</TD>
    100. 

  100. <TD ALIGN=RIGHT>1%</TD>
    101. 

  101. <TD COLSPAN='2'>&nbsp;</TD>
    102. 

  102. </TR>
    103. 

  103. <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
    104. 

  104. <TD ALIGN=RIGHT>5</TD>
    105. 

  105. <TD>&nbsp;</TD>
    106. 

  106. <TD>&nbsp;</TD>
    107. 

  107. <TD COLSPAN='2'>&nbsp;</TD>
    108. 

  108. </TR>
    109. 

  109. <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
    110. 

  110. <TD ALIGN=RIGHT>6</TD>
    111. 

  111. <TD>&nbsp;</TD>
    112. 

  112. <TD>&nbsp;</TD>
    113. 

  113. <TD COLSPAN='2'>&nbsp;</TD>
    114. 

  114. </TR>
    115. 

  115. <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
    116. 

  116. <TD ALIGN=RIGHT>1</TD>
    117. 

  117. <TD>&nbsp;</TD>
    118. 

  118. <TD>&nbsp;</TD>
    119. 

  119. <TD COLSPAN='2'>&nbsp;</TD>
    120. 

  120. </TR>
    121. 

  121. <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as ROM</TD>
    122. 

  122. <TD ALIGN=RIGHT>0</TD>
    123. 

  123. <TD>&nbsp;</TD>
    124. 

  124. <TD>&nbsp;</TD>
    125. 

  125. <TD COLSPAN='2'>&nbsp;</TD>
    126. 

  126. </TR>
    127. 

  127. <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Memory</TD>
    128. 

  128. <TD ALIGN=RIGHT>0</TD>
    129. 

  129. <TD ALIGN=RIGHT>1,440</TD>
    130. 

  130. <TD ALIGN=RIGHT>0%</TD>
    131. 

  131. <TD COLSPAN='2'>&nbsp;</TD>
    132. 

  132. </TR>
    133. 

  133. <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used exclusively as route-thrus</TD>
    134. 

  134. <TD ALIGN=RIGHT>1</TD>
    135. 

  135. <TD>&nbsp;</TD>
    136. 

  136. <TD>&nbsp;</TD>
    137. 

  137. <TD COLSPAN='2'>&nbsp;</TD>
    138. 

  138. </TR>
    139. 

  139. <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice register load</TD>
    140. 

  140. <TD ALIGN=RIGHT>0</TD>
    141. 

  141. <TD>&nbsp;</TD>
    142. 

  142. <TD>&nbsp;</TD>
    143. 

  143. <TD COLSPAN='2'>&nbsp;</TD>
    144. 

  144. </TR>
    145. 

  145. <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice carry load</TD>
    146. 

  146. <TD ALIGN=RIGHT>1</TD>
    147. 

  147. <TD>&nbsp;</TD>
    148. 

  148. <TD>&nbsp;</TD>
    149. 

  149. <TD COLSPAN='2'>&nbsp;</TD>
    150. 

  150. </TR>
    151. 

  151. <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with other load</TD>
    152. 

  152. <TD ALIGN=RIGHT>0</TD>
    153. 

  153. <TD>&nbsp;</TD>
    154. 

  154. <TD>&nbsp;</TD>
    155. 

  155. <TD COLSPAN='2'>&nbsp;</TD>
    156. 

  156. </TR>
    157. 

  157. <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
    158. 

  158. <TD ALIGN=RIGHT>5</TD>
    159. 

  159. <TD ALIGN=RIGHT>1,430</TD>
    160. 

  160. <TD ALIGN=RIGHT>1%</TD>
    161. 

  161. <TD COLSPAN='2'>&nbsp;</TD>
    162. 

  162. </TR>
    163. 

  163. <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MUXCYs used</TD>
    164. 

  164. <TD ALIGN=RIGHT>8</TD>
    165. 

  165. <TD ALIGN=RIGHT>2,860</TD>
    166. 

  166. <TD ALIGN=RIGHT>1%</TD>
    167. 

  167. <TD COLSPAN='2'>&nbsp;</TD>
    168. 

  168. </TR>
    169. 

  169. <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
    170. 

  170. <TD ALIGN=RIGHT>17</TD>
    171. 

  171. <TD>&nbsp;</TD>
    172. 

  172. <TD>&nbsp;</TD>
    173. 

  173. <TD COLSPAN='2'>&nbsp;</TD>
    174. 

  174. </TR>
    175. 

  175. <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD>
    176. 

  176. <TD ALIGN=RIGHT>0</TD>
    177. 

  177. <TD ALIGN=RIGHT>17</TD>
    178. 

  178. <TD ALIGN=RIGHT>0%</TD>
    179. 

  179. <TD COLSPAN='2'>&nbsp;</TD>
    180. 

  180. </TR>
    181. 

  181. <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD>
    182. 

  182. <TD ALIGN=RIGHT>4</TD>
    183. 

  183. <TD ALIGN=RIGHT>17</TD>
    184. 

  184. <TD ALIGN=RIGHT>23%</TD>
    185. 

  185. <TD COLSPAN='2'>&nbsp;</TD>
    186. 

  186. </TR>
    187. 

  187. <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD>
    188. 

  188. <TD ALIGN=RIGHT>13</TD>
    189. 

  189. <TD ALIGN=RIGHT>17</TD>
    190. 

  190. <TD ALIGN=RIGHT>76%</TD>
    191. 

  191. <TD COLSPAN='2'>&nbsp;</TD>
    192. 

  192. </TR>
    193. 

  193. <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of unique control sets</TD>
    194. 

  194. <TD ALIGN=RIGHT>3</TD>
    195. 

  195. <TD>&nbsp;</TD>
    196. 

  196. <TD>&nbsp;</TD>
    197. 

  197. <TD COLSPAN='2'>&nbsp;</TD>
    198. 

  198. </TR>
    199. 

  199. <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of slice register sites lost<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;to control set restrictions</TD>
    200. 

  200. <TD ALIGN=RIGHT>7</TD>
    201. 

  201. <TD ALIGN=RIGHT>11,440</TD>
    202. 

  202. <TD ALIGN=RIGHT>1%</TD>
    203. 

  203. <TD COLSPAN='2'>&nbsp;</TD>
    204. 

  204. </TR>
    205. 

  205. <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='/home/lusius/Devel/STM32_Devel/FPGA/CNC/step_driver_control/sdc_divider_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
    206. 

  206. <TD ALIGN=RIGHT>7</TD>
    207. 

  207. <TD ALIGN=RIGHT>102</TD>
    208. 

  208. <TD ALIGN=RIGHT>6%</TD>
    209. 

  209. <TD COLSPAN='2'>&nbsp;</TD>
    210. 

  210. </TR>
    211. 

  211. <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>
    212. 

  212. <TD ALIGN=RIGHT>0</TD>
    213. 

  213. <TD ALIGN=RIGHT>32</TD>
    214. 

  214. <TD ALIGN=RIGHT>0%</TD>
    215. 

  215. <TD COLSPAN='2'>&nbsp;</TD>
    216. 

  216. </TR>
    217. 

  217. <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
    218. 

  218. <TD ALIGN=RIGHT>0</TD>
    219. 

  219. <TD ALIGN=RIGHT>64</TD>
    220. 

  220. <TD ALIGN=RIGHT>0%</TD>
    221. 

  221. <TD COLSPAN='2'>&nbsp;</TD>
    222. 

  222. </TR>
    223. 

  223. <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>
    224. 

  224. <TD ALIGN=RIGHT>0</TD>
    225. 

  225. <TD ALIGN=RIGHT>32</TD>
    226. 

  226. <TD ALIGN=RIGHT>0%</TD>
    227. 

  227. <TD COLSPAN='2'>&nbsp;</TD>
    228. 

  228. </TR>
    229. 

  229. <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD>
    230. 

  230. <TD ALIGN=RIGHT>0</TD>
    231. 

  231. <TD ALIGN=RIGHT>32</TD>
    232. 

  232. <TD ALIGN=RIGHT>0%</TD>
    233. 

  233. <TD COLSPAN='2'>&nbsp;</TD>
    234. 

  234. </TR>
    235. 

  235. <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
    236. 

  236. <TD ALIGN=RIGHT>2</TD>
    237. 

  237. <TD ALIGN=RIGHT>16</TD>
    238. 

  238. <TD ALIGN=RIGHT>12%</TD>
    239. 

  239. <TD COLSPAN='2'>&nbsp;</TD>
    240. 

  240. </TR>
    241. 

  241. <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGs</TD>
    242. 

  242. <TD ALIGN=RIGHT>2</TD>
    243. 

  243. <TD>&nbsp;</TD>
    244. 

  244. <TD>&nbsp;</TD>
    245. 

  245. <TD COLSPAN='2'>&nbsp;</TD>
    246. 

  246. </TR>
    247. 

  247. <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGMUX</TD>
    248. 

  248. <TD ALIGN=RIGHT>0</TD>
    249. 

  249. <TD>&nbsp;</TD>
    250. 

  250. <TD>&nbsp;</TD>
    251. 

  251. <TD COLSPAN='2'>&nbsp;</TD>
    252. 

  252. </TR>
    253. 

  253. <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD>
    254. 

  254. <TD ALIGN=RIGHT>0</TD>
    255. 

  255. <TD ALIGN=RIGHT>4</TD>
    256. 

  256. <TD ALIGN=RIGHT>0%</TD>
    257. 

  257. <TD COLSPAN='2'>&nbsp;</TD>
    258. 

  258. </TR>
    259. 

  259. <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD>
    260. 

  260. <TD ALIGN=RIGHT>0</TD>
    261. 

  261. <TD ALIGN=RIGHT>200</TD>
    262. 

  262. <TD ALIGN=RIGHT>0%</TD>
    263. 

  263. <TD COLSPAN='2'>&nbsp;</TD>
    264. 

  264. </TR>
    265. 

  265. <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD>
    266. 

  266. <TD ALIGN=RIGHT>0</TD>
    267. 

  267. <TD ALIGN=RIGHT>200</TD>
    268. 

  268. <TD ALIGN=RIGHT>0%</TD>
    269. 

  269. <TD COLSPAN='2'>&nbsp;</TD>
    270. 

  270. </TR>
    271. 

  271. <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD>
    272. 

  272. <TD ALIGN=RIGHT>0</TD>
    273. 

  273. <TD ALIGN=RIGHT>200</TD>
    274. 

  274. <TD ALIGN=RIGHT>0%</TD>
    275. 

  275. <TD COLSPAN='2'>&nbsp;</TD>
    276. 

  276. </TR>
    277. 

  277. <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD>
    278. 

  278. <TD ALIGN=RIGHT>0</TD>
    279. 

  279. <TD ALIGN=RIGHT>4</TD>
    280. 

  280. <TD ALIGN=RIGHT>0%</TD>
    281. 

  281. <TD COLSPAN='2'>&nbsp;</TD>
    282. 

  282. </TR>
    283. 

  283. <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD>
    284. 

  284. <TD ALIGN=RIGHT>0</TD>
    285. 

  285. <TD ALIGN=RIGHT>128</TD>
    286. 

  286. <TD ALIGN=RIGHT>0%</TD>
    287. 

  287. <TD COLSPAN='2'>&nbsp;</TD>
    288. 

  288. </TR>
    289. 

  289. <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD>
    290. 

  290. <TD ALIGN=RIGHT>0</TD>
    291. 

  291. <TD ALIGN=RIGHT>8</TD>
    292. 

  292. <TD ALIGN=RIGHT>0%</TD>
    293. 

  293. <TD COLSPAN='2'>&nbsp;</TD>
    294. 

  294. </TR>
    295. 

  295. <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD>
    296. 

  296. <TD ALIGN=RIGHT>0</TD>
    297. 

  297. <TD ALIGN=RIGHT>4</TD>
    298. 

  298. <TD ALIGN=RIGHT>0%</TD>
    299. 

  299. <TD COLSPAN='2'>&nbsp;</TD>
    300. 

  300. </TR>
    301. 

  301. <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD>
    302. 

  302. <TD ALIGN=RIGHT>0</TD>
    303. 

  303. <TD ALIGN=RIGHT>16</TD>
    304. 

  304. <TD ALIGN=RIGHT>0%</TD>
    305. 

  305. <TD COLSPAN='2'>&nbsp;</TD>
    306. 

  306. </TR>
    307. 

  307. <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD>
    308. 

  308. <TD ALIGN=RIGHT>0</TD>
    309. 

  309. <TD ALIGN=RIGHT>1</TD>
    310. 

  310. <TD ALIGN=RIGHT>0%</TD>
    311. 

  311. <TD COLSPAN='2'>&nbsp;</TD>
    312. 

  312. </TR>
    313. 

  313. <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD>
    314. 

  314. <TD ALIGN=RIGHT>0</TD>
    315. 

  315. <TD ALIGN=RIGHT>2</TD>
    316. 

  316. <TD ALIGN=RIGHT>0%</TD>
    317. 

  317. <TD COLSPAN='2'>&nbsp;</TD>
    318. 

  318. </TR>
    319. 

  319. <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD>
    320. 

  320. <TD ALIGN=RIGHT>0</TD>
    321. 

  321. <TD ALIGN=RIGHT>2</TD>
    322. 

  322. <TD ALIGN=RIGHT>0%</TD>
    323. 

  323. <TD COLSPAN='2'>&nbsp;</TD>
    324. 

  324. </TR>
    325. 

  325. <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD>
    326. 

  326. <TD ALIGN=RIGHT>0</TD>
    327. 

  327. <TD ALIGN=RIGHT>2</TD>
    328. 

  328. <TD ALIGN=RIGHT>0%</TD>
    329. 

  329. <TD COLSPAN='2'>&nbsp;</TD>
    330. 

  330. </TR>
    331. 

  331. <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD>
    332. 

  332. <TD ALIGN=RIGHT>0</TD>
    333. 

  333. <TD ALIGN=RIGHT>1</TD>
    334. 

  334. <TD ALIGN=RIGHT>0%</TD>
    335. 

  335. <TD COLSPAN='2'>&nbsp;</TD>
    336. 

  336. </TR>
    337. 

  337. <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD>
    338. 

  338. <TD ALIGN=RIGHT>0</TD>
    339. 

  339. <TD ALIGN=RIGHT>1</TD>
    340. 

  340. <TD ALIGN=RIGHT>0%</TD>
    341. 

  341. <TD COLSPAN='2'>&nbsp;</TD>
    342. 

  342. </TR>
    343. 

  343. <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD>
    344. 

  344. <TD ALIGN=RIGHT>0</TD>
    345. 

  345. <TD ALIGN=RIGHT>1</TD>
    346. 

  346. <TD ALIGN=RIGHT>0%</TD>
    347. 

  347. <TD COLSPAN='2'>&nbsp;</TD>
    348. 

  348. </TR>
    349. 

  349. <TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
    350. 

  350. <TD ALIGN=RIGHT>2.74</TD>
    351. 

  351. <TD>&nbsp;</TD>
    352. 

  352. <TD>&nbsp;</TD>
    353. 

  353. <TD COLSPAN='2'>&nbsp;</TD>
    354. 

  354. </TR>
    355. 

  355. </TABLE>
    356. 

  356. 

  357. 

  358. 

  359. &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
    360. 

  360. <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
    361. 

  361. <TR ALIGN=LEFT>
    362. 

  362. <TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
    363. 

  363. <TD>0 (Setup: 0, Hold: 0)</TD>
    364. 

  364. <TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
    365. 

  365. <TD COLSPAN='2'><A HREF_DISABLED='/home/lusius/Devel/STM32_Devel/FPGA/CNC/step_driver_control/sdc_divider_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
    366. 

  366. </TR>
    367. 

  367. <TR ALIGN=LEFT>
    368. 

  368. <TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
    369. 

  369. <A HREF_DISABLED='/home/lusius/Devel/STM32_Devel/FPGA/CNC/step_driver_control/sdc_divider.unroutes'>All Signals Completely Routed</A></TD>
    370. 

  370. <TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
    371. 

  371. <TD COLSPAN='2'><A HREF_DISABLED='/home/lusius/Devel/STM32_Devel/FPGA/CNC/step_driver_control/sdc_divider_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
    372. 

  372. </TR>
    373. 

  373. <TR ALIGN=LEFT>
    374. 

  374. <TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
    375. 

  375. <TD>
    376. 

  376. <A HREF_DISABLED='/home/lusius/Devel/STM32_Devel/FPGA/CNC/step_driver_control/sdc_divider.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
    377. 

  377. <TD BGCOLOR='#FFFF99'><B>&nbsp;</B></TD>
    378. 

  378. <TD COLSPAN='2'>&nbsp;</TD>
    379. 

  379. </TABLE>
    380. 

  380. 

  381. 

  382. 

  383. &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
    384. 

  384. <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
    385. 

  385. <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
    386. 

  386. <TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
    387. 

  387. <TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/lusius/Devel/STM32_Devel/FPGA/CNC/step_driver_control/sdc_divider.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Пн июля 23 01:50:21 2018</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    388. 

  388. <TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/lusius/Devel/STM32_Devel/FPGA/CNC/step_driver_control/sdc_divider.bld'>Translation Report</A></TD><TD>Current</TD><TD>Пн июля 23 01:50:21 2018</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    389. 

  389. <TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/lusius/Devel/STM32_Devel/FPGA/CNC/step_driver_control/sdc_divider_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Пн июля 23 01:50:21 2018</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    390. 

  390. <TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/lusius/Devel/STM32_Devel/FPGA/CNC/step_driver_control/sdc_divider.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Пн июля 23 01:50:21 2018</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    391. 

  391. <TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    392. 

  392. <TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/lusius/Devel/STM32_Devel/FPGA/CNC/step_driver_control/sdc_divider.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Пн июля 23 01:50:21 2018</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    393. 

  393. <TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
    394. 

  394. </TABLE>
    395. 

  395. &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
    396. 

  396. <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
    397. 

  397. <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
    398. 

  398. <TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/lusius/Devel/STM32_Devel/FPGA/CNC/step_driver_control/isim.log'>ISIM Simulator Log</A></TD><TD>Current</TD><TD COLSPAN='2'>Вт июля 24 01:57:04 2018</TD></TR>
    399. 

  399. <TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/lusius/Devel/STM32_Devel/FPGA/CNC/step_driver_control/usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Пн июля 23 01:50:40 2018</TD></TR>
    400. 

  400. <TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/lusius/Devel/STM32_Devel/FPGA/CNC/step_driver_control/webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Пн июля 23 01:50:40 2018</TD></TR>
    401. 

  401. </TABLE>
    402. 

  402. 

  403. 

  404. <br><center><b>Date Generated:</
    405.