step_driver_control.gise 30 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403
  1. <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
  2. <generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
  3. <!-- -->
  4. <!-- For tool use only. Do not edit. -->
  5. <!-- -->
  6. <!-- ProjectNavigator created generated project file. -->
  7. <!-- For use in tracking generated file and other information -->
  8. <!-- allowing preservation of process status. -->
  9. <!-- -->
  10. <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
  11. <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
  12. <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="step_driver_control.xise"/>
  13. <files xmlns="http://www.xilinx.com/XMLSchema">
  14. <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
  15. <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
  16. <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
  17. <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
  18. <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
  19. <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
  20. <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
  21. <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_VERILOG" xil_pn:name="count_bidir_4.vf"/>
  22. <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="count_bidir_4_count_bidir_4_sch_tb_beh.prj"/>
  23. <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="count_bidir_4_count_bidir_4_sch_tb_isim_beh.exe"/>
  24. <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="count_bidir_4_count_bidir_4_sch_tb_isim_beh.wdb"/>
  25. <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="count_bidir_4_count_bidir_4_sch_tb_stx_beh.prj"/>
  26. <file xil_pn:fileType="FILE_VERILOG" xil_pn:name="count_bidir_4_drc.vf"/>
  27. <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_VERILOG" xil_pn:name="count_test.vf"/>
  28. <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="count_test_count_test_sch_tb_beh.prj"/>
  29. <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="count_test_count_test_sch_tb_isim_beh.exe"/>
  30. <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="count_test_count_test_sch_tb_isim_beh.wdb"/>
  31. <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="count_test_count_test_sch_tb_stx_beh.prj"/>
  32. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="distance_module.bgn" xil_pn:subbranch="FPGAConfiguration"/>
  33. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="distance_module.bit" xil_pn:subbranch="FPGAConfiguration"/>
  34. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="distance_module.bld"/>
  35. <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="distance_module.cmd_log"/>
  36. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="distance_module.drc" xil_pn:subbranch="FPGAConfiguration"/>
  37. <file xil_pn:fileType="FILE_JHD" xil_pn:name="distance_module.jhd"/>
  38. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="distance_module.lso"/>
  39. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="distance_module.ncd" xil_pn:subbranch="Par"/>
  40. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="distance_module.ngc"/>
  41. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="distance_module.ngd"/>
  42. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="distance_module.ngr"/>
  43. <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="distance_module.pad"/>
  44. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="distance_module.par" xil_pn:subbranch="Par"/>
  45. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="distance_module.pcf" xil_pn:subbranch="Map"/>
  46. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="distance_module.prj"/>
  47. <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="distance_module.ptwx"/>
  48. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="distance_module.stx"/>
  49. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="distance_module.syr"/>
  50. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="distance_module.twr" xil_pn:subbranch="Par"/>
  51. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="distance_module.twx" xil_pn:subbranch="Par"/>
  52. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="distance_module.unroutes" xil_pn:subbranch="Par"/>
  53. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="distance_module.ut" xil_pn:subbranch="FPGAConfiguration"/>
  54. <file xil_pn:fileType="FILE_VERILOG" xil_pn:name="distance_module.vf">
  55. <branch xil_pn:name="Implementation"/>
  56. <branch xil_pn:name="BehavioralSim"/>
  57. </file>
  58. <file xil_pn:fileType="FILE_XPI" xil_pn:name="distance_module.xpi"/>
  59. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="distance_module.xst"/>
  60. <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="distance_module_distance_module_sch_tb_beh.prj"/>
  61. <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="distance_module_distance_module_sch_tb_isim_beh.exe"/>
  62. <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="distance_module_distance_module_sch_tb_isim_beh.wdb"/>
  63. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="distance_module_distance_module_sch_tb_stx_beh.prj"/>
  64. <file xil_pn:fileType="FILE_NCD" xil_pn:name="distance_module_guide.ncd" xil_pn:origination="imported"/>
  65. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="distance_module_map.map" xil_pn:subbranch="Map"/>
  66. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="distance_module_map.mrp" xil_pn:subbranch="Map"/>
  67. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="distance_module_map.ncd" xil_pn:subbranch="Map"/>
  68. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="distance_module_map.ngm" xil_pn:subbranch="Map"/>
  69. <file xil_pn:fileType="FILE_XRPT" xil_pn:name="distance_module_map.xrpt"/>
  70. <file xil_pn:fileType="FILE_XRPT" xil_pn:name="distance_module_ngdbuild.xrpt"/>
  71. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="distance_module_pad.csv" xil_pn:subbranch="Par"/>
  72. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="distance_module_pad.txt" xil_pn:subbranch="Par"/>
  73. <file xil_pn:fileType="FILE_XRPT" xil_pn:name="distance_module_par.xrpt"/>
  74. <file xil_pn:fileType="FILE_HTML" xil_pn:name="distance_module_summary.html"/>
  75. <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="distance_module_summary.xml"/>
  76. <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="distance_module_usage.xml"/>
  77. <file xil_pn:fileType="FILE_XRPT" xil_pn:name="distance_module_xst.xrpt"/>
  78. <file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
  79. <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_VERILOG" xil_pn:name="i7led_decoder.vf"/>
  80. <file xil_pn:fileType="FILE_SPL" xil_pn:name="i7led_decoder_i7led_decoder_sch_tb.spl"/>
  81. <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="i7led_decoder_i7led_decoder_sch_tb.sym" xil_pn:origination="imported"/>
  82. <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="i7led_decoder_i7led_decoder_sch_tb_isim_beh.exe"/>
  83. <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="i7led_decoder_i7led_decoder_sch_tb_stx_beh.prj"/>
  84. <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_VERILOG" xil_pn:name="indic_4reg_decoder.vf"/>
  85. <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="indic_4reg_decoder_indic_4reg_decoder_sch_tb_beh.prj"/>
  86. <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="indic_4reg_decoder_indic_4reg_decoder_sch_tb_isim_beh.exe"/>
  87. <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="indic_4reg_decoder_indic_4reg_decoder_sch_tb_isim_beh.wdb"/>
  88. <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="indic_4reg_decoder_indic_4reg_decoder_sch_tb_stx_beh.prj"/>
  89. <file xil_pn:fileType="FILE_VERILOG" xil_pn:name="input_cascade_drc.vf"/>
  90. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="input_schheme.bld"/>
  91. <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="input_schheme.cmd_log"/>
  92. <file xil_pn:fileType="FILE_JHD" xil_pn:name="input_schheme.jhd"/>
  93. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="input_schheme.lso"/>
  94. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="input_schheme.ncd" xil_pn:subbranch="Par"/>
  95. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="input_schheme.ngc"/>
  96. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="input_schheme.ngd"/>
  97. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="input_schheme.ngr"/>
  98. <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="input_schheme.pad"/>
  99. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="input_schheme.par" xil_pn:subbranch="Par"/>
  100. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="input_schheme.pcf" xil_pn:subbranch="Map"/>
  101. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="input_schheme.prj"/>
  102. <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="input_schheme.ptwx"/>
  103. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="input_schheme.stx"/>
  104. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="input_schheme.syr"/>
  105. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="input_schheme.twr" xil_pn:subbranch="Par"/>
  106. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="input_schheme.twx" xil_pn:subbranch="Par"/>
  107. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="input_schheme.unroutes" xil_pn:subbranch="Par"/>
  108. <file xil_pn:fileType="FILE_VERILOG" xil_pn:name="input_schheme.vf">
  109. <branch xil_pn:name="Implementation"/>
  110. <branch xil_pn:name="BehavioralSim"/>
  111. </file>
  112. <file xil_pn:fileType="FILE_XPI" xil_pn:name="input_schheme.xpi"/>
  113. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="input_schheme.xst"/>
  114. <file xil_pn:fileType="FILE_VERILOG" xil_pn:name="input_schheme_drc.vf"/>
  115. <file xil_pn:fileType="FILE_HTML" xil_pn:name="input_schheme_envsettings.html"/>
  116. <file xil_pn:fileType="FILE_NCD" xil_pn:name="input_schheme_guide.ncd" xil_pn:origination="imported"/>
  117. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="input_schheme_input_schheme_sch_tb_beh.prj"/>
  118. <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="input_schheme_input_schheme_sch_tb_isim_beh.exe"/>
  119. <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="input_schheme_input_schheme_sch_tb_isim_beh.wdb"/>
  120. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="input_schheme_input_schheme_sch_tb_stx_beh.prj"/>
  121. <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="input_schheme_isim_beh.exe"/>
  122. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="input_schheme_map.map" xil_pn:subbranch="Map"/>
  123. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="input_schheme_map.mrp" xil_pn:subbranch="Map"/>
  124. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="input_schheme_map.ncd" xil_pn:subbranch="Map"/>
  125. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="input_schheme_map.ngm" xil_pn:subbranch="Map"/>
  126. <file xil_pn:fileType="FILE_XRPT" xil_pn:name="input_schheme_map.xrpt"/>
  127. <file xil_pn:fileType="FILE_XRPT" xil_pn:name="input_schheme_ngdbuild.xrpt"/>
  128. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="input_schheme_pad.csv" xil_pn:subbranch="Par"/>
  129. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="input_schheme_pad.txt" xil_pn:subbranch="Par"/>
  130. <file xil_pn:fileType="FILE_XRPT" xil_pn:name="input_schheme_par.xrpt"/>
  131. <file xil_pn:fileType="FILE_HTML" xil_pn:name="input_schheme_summary.html"/>
  132. <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="input_schheme_summary.xml"/>
  133. <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="input_schheme_usage.xml"/>
  134. <file xil_pn:fileType="FILE_XRPT" xil_pn:name="input_schheme_xst.xrpt"/>
  135. <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
  136. <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
  137. <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
  138. <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_VERILOG" xil_pn:name="sdc.vf"/>
  139. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="sdc_divider.bld"/>
  140. <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="sdc_divider.cmd_log"/>
  141. <file xil_pn:fileType="FILE_JHD" xil_pn:name="sdc_divider.jhd"/>
  142. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="sdc_divider.lso"/>
  143. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="sdc_divider.ncd" xil_pn:subbranch="Par"/>
  144. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="sdc_divider.ngc"/>
  145. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="sdc_divider.ngd"/>
  146. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="sdc_divider.ngr"/>
  147. <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="sdc_divider.pad"/>
  148. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="sdc_divider.par" xil_pn:subbranch="Par"/>
  149. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="sdc_divider.pcf" xil_pn:subbranch="Map"/>
  150. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="sdc_divider.prj"/>
  151. <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="sdc_divider.ptwx"/>
  152. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="sdc_divider.stx"/>
  153. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="sdc_divider.syr"/>
  154. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="sdc_divider.twr" xil_pn:subbranch="Par"/>
  155. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="sdc_divider.twx" xil_pn:subbranch="Par"/>
  156. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="sdc_divider.unroutes" xil_pn:subbranch="Par"/>
  157. <file xil_pn:fileType="FILE_VERILOG" xil_pn:name="sdc_divider.vf">
  158. <branch xil_pn:name="Implementation"/>
  159. <branch xil_pn:name="BehavioralSim"/>
  160. </file>
  161. <file xil_pn:fileType="FILE_XPI" xil_pn:name="sdc_divider.xpi"/>
  162. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="sdc_divider.xst"/>
  163. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="sdc_divider_beh.prj"/>
  164. <file xil_pn:fileType="FILE_VERILOG" xil_pn:name="sdc_divider_drc.vf"/>
  165. <file xil_pn:fileType="FILE_NCD" xil_pn:name="sdc_divider_guide.ncd" xil_pn:origination="imported"/>
  166. <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="sdc_divider_isim_beh.exe"/>
  167. <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="sdc_divider_isim_beh.wdb"/>
  168. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="sdc_divider_map.map" xil_pn:subbranch="Map"/>
  169. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="sdc_divider_map.mrp" xil_pn:subbranch="Map"/>
  170. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="sdc_divider_map.ncd" xil_pn:subbranch="Map"/>
  171. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="sdc_divider_map.ngm" xil_pn:subbranch="Map"/>
  172. <file xil_pn:fileType="FILE_XRPT" xil_pn:name="sdc_divider_map.xrpt"/>
  173. <file xil_pn:fileType="FILE_XRPT" xil_pn:name="sdc_divider_ngdbuild.xrpt"/>
  174. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="sdc_divider_pad.csv" xil_pn:subbranch="Par"/>
  175. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="sdc_divider_pad.txt" xil_pn:subbranch="Par"/>
  176. <file xil_pn:fileType="FILE_XRPT" xil_pn:name="sdc_divider_par.xrpt"/>
  177. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="sdc_divider_sdc_divider_sch_tb_beh.prj"/>
  178. <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="sdc_divider_sdc_divider_sch_tb_isim_beh.exe"/>
  179. <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="sdc_divider_sdc_divider_sch_tb_isim_beh.wdb"/>
  180. <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="sdc_divider_sdc_divider_sch_tb_stx_beh.prj"/>
  181. <file xil_pn:fileType="FILE_HTML" xil_pn:name="sdc_divider_summary.html"/>
  182. <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="sdc_divider_summary.xml"/>
  183. <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="sdc_divider_usage.xml"/>
  184. <file xil_pn:fileType="FILE_XRPT" xil_pn:name="sdc_divider_xst.xrpt"/>
  185. <file xil_pn:fileType="FILE_VERILOG" xil_pn:name="sdc_drc.vf"/>
  186. <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_VERILOG" xil_pn:name="topboard.vf"/>
  187. <file xil_pn:fileType="FILE_VERILOG" xil_pn:name="topboard_drc.vf"/>
  188. <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="topboard_topboard_sch_tb_beh.prj"/>
  189. <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="topboard_topboard_sch_tb_isim_beh.exe"/>
  190. <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="topboard_topboard_sch_tb_isim_beh.wdb"/>
  191. <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="topboard_topboard_sch_tb_stx_beh.prj"/>
  192. <file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
  193. <file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
  194. <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
  195. <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
  196. <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
  197. <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
  198. </files>
  199. <transforms xmlns="http://www.xilinx.com/XMLSchema">
  200. <transform xil_pn:end_ts="1531998375" xil_pn:name="TRANEXT_compLibraries_FPGA" xil_pn:prop_ck="-3594876569575637225" xil_pn:start_ts="1531998375">
  201. <status xil_pn:value="FailedRun"/>
  202. <status xil_pn:value="ReadyToRun"/>
  203. </transform>
  204. <transform xil_pn:end_ts="1531998112" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1531998112">
  205. <status xil_pn:value="SuccessfullyRun"/>
  206. <status xil_pn:value="ReadyToRun"/>
  207. </transform>
  208. <transform xil_pn:end_ts="1532394340" xil_pn:in_ck="1296334298709172982" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1532394340">
  209. <status xil_pn:value="SuccessfullyRun"/>
  210. <status xil_pn:value="ReadyToRun"/>
  211. <outfile xil_pn:name="i7led_test.vhd"/>
  212. <outfile xil_pn:name="indic_4reg_dec_test.vhd"/>
  213. </transform>
  214. <transform xil_pn:end_ts="1532393834" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-4683930382322674536" xil_pn:start_ts="1532393834">
  215. <status xil_pn:value="SuccessfullyRun"/>
  216. <status xil_pn:value="ReadyToRun"/>
  217. </transform>
  218. <transform xil_pn:end_ts="1532394274" xil_pn:in_ck="-9210463584011096700" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7951357827644154794" xil_pn:start_ts="1532394273">
  219. <status xil_pn:value="SuccessfullyRun"/>
  220. <status xil_pn:value="ReadyToRun"/>
  221. <status xil_pn:value="OutOfDateForInputs"/>
  222. <status xil_pn:value="InputAdded"/>
  223. <outfile xil_pn:name="i7led_decoder.vf"/>
  224. <outfile xil_pn:name="indic_4reg_decoder.vf"/>
  225. <outfile xil_pn:name="topboard.vf"/>
  226. </transform>
  227. <transform xil_pn:end_ts="1532392526" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="2696822253146379744" xil_pn:start_ts="1532392526">
  228. <status xil_pn:value="SuccessfullyRun"/>
  229. <status xil_pn:value="ReadyToRun"/>
  230. </transform>
  231. <transform xil_pn:end_ts="1532394340" xil_pn:in_ck="-5010341382388211675" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1532394340">
  232. <status xil_pn:value="SuccessfullyRun"/>
  233. <status xil_pn:value="ReadyToRun"/>
  234. <status xil_pn:value="OutOfDateForPredecessor"/>
  235. <outfile xil_pn:name="count_bidir_4.vf"/>
  236. <outfile xil_pn:name="count_test.vf"/>
  237. <outfile xil_pn:name="distance_module.vf"/>
  238. <outfile xil_pn:name="i7led_decoder.vf"/>
  239. <outfile xil_pn:name="i7led_test.vhd"/>
  240. <outfile xil_pn:name="indic_4reg_dec_test.vhd"/>
  241. <outfile xil_pn:name="indic_4reg_decoder.vf"/>
  242. <outfile xil_pn:name="input_schheme.vf"/>
  243. <outfile xil_pn:name="sdc.vf"/>
  244. <outfile xil_pn:name="sdc_divider.vf"/>
  245. <outfile xil_pn:name="topboard.vf"/>
  246. </transform>
  247. <transform xil_pn:end_ts="1532394341" xil_pn:in_ck="-5010341382388211675" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-9184879157114868359" xil_pn:start_ts="1532394340">
  248. <status xil_pn:value="SuccessfullyRun"/>
  249. <status xil_pn:value="ReadyToRun"/>
  250. <status xil_pn:value="OutOfDateForProperties"/>
  251. <status xil_pn:value="OutOfDateForPredecessor"/>
  252. <status xil_pn:value="OutOfDateForOutputs"/>
  253. <status xil_pn:value="OutputChanged"/>
  254. <outfile xil_pn:name="fuse.log"/>
  255. <outfile xil_pn:name="indic_4reg_decoder_indic_4reg_decoder_sch_tb_beh.prj"/>
  256. <outfile xil_pn:name="indic_4reg_decoder_indic_4reg_decoder_sch_tb_isim_beh.exe"/>
  257. <outfile xil_pn:name="isim"/>
  258. <outfile xil_pn:name="isim.log"/>
  259. <outfile xil_pn:name="xilinxsim.ini"/>
  260. </transform>
  261. <transform xil_pn:end_ts="1532394686" xil_pn:in_ck="6450670889684223136" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="9060817770807054812" xil_pn:start_ts="1532394686">
  262. <status xil_pn:value="SuccessfullyRun"/>
  263. <status xil_pn:value="ReadyToRun"/>
  264. <status xil_pn:value="OutOfDateForProperties"/>
  265. <status xil_pn:value="OutOfDateForPredecessor"/>
  266. <status xil_pn:value="OutOfDateForOutputs"/>
  267. <status xil_pn:value="OutputChanged"/>
  268. <outfile xil_pn:name="indic_4reg_decoder_indic_4reg_decoder_sch_tb_isim_beh.wdb"/>
  269. <outfile xil_pn:name="isim.cmd"/>
  270. <outfile xil_pn:name="isim.log"/>
  271. </transform>
  272. <transform xil_pn:end_ts="1531998161" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1531998161">
  273. <status xil_pn:value="SuccessfullyRun"/>
  274. <status xil_pn:value="ReadyToRun"/>
  275. </transform>
  276. <transform xil_pn:end_ts="1532018435" xil_pn:in_ck="-1820753065944761524" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="5424861493002722005" xil_pn:start_ts="1532018434">
  277. <status xil_pn:value="SuccessfullyRun"/>
  278. <status xil_pn:value="ReadyToRun"/>
  279. <status xil_pn:value="OutOfDateForInputs"/>
  280. <status xil_pn:value="OutOfDateForProperties"/>
  281. <status xil_pn:value="OutOfDateForOutputs"/>
  282. <status xil_pn:value="InputAdded"/>
  283. <status xil_pn:value="InputChanged"/>
  284. <status xil_pn:value="InputRemoved"/>
  285. <status xil_pn:value="OutputChanged"/>
  286. <status xil_pn:value="OutputRemoved"/>
  287. </transform>
  288. <transform xil_pn:end_ts="1532018435" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-7373371107571360923" xil_pn:start_ts="1532018435">
  289. <status xil_pn:value="SuccessfullyRun"/>
  290. <status xil_pn:value="ReadyToRun"/>
  291. <status xil_pn:value="OutOfDateForProperties"/>
  292. </transform>
  293. <transform xil_pn:end_ts="1531998162" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1531998162">
  294. <status xil_pn:value="SuccessfullyRun"/>
  295. <status xil_pn:value="ReadyToRun"/>
  296. </transform>
  297. <transform xil_pn:end_ts="1532018435" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="8536404007872501143" xil_pn:start_ts="1532018435">
  298. <status xil_pn:value="SuccessfullyRun"/>
  299. <status xil_pn:value="ReadyToRun"/>
  300. <status xil_pn:value="OutOfDateForProperties"/>
  301. </transform>
  302. <transform xil_pn:end_ts="1531998162" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745955965653" xil_pn:start_ts="1531998162">
  303. <status xil_pn:value="SuccessfullyRun"/>
  304. <status xil_pn:value="ReadyToRun"/>
  305. <status xil_pn:value="OutOfDateForPredecessor"/>
  306. </transform>
  307. <transform xil_pn:end_ts="1532018435" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="5862331808201450223" xil_pn:start_ts="1532018435">
  308. <status xil_pn:value="SuccessfullyRun"/>
  309. <status xil_pn:value="ReadyToRun"/>
  310. <status xil_pn:value="OutOfDateForProperties"/>
  311. <status xil_pn:value="OutOfDateForPredecessor"/>
  312. </transform>
  313. <transform xil_pn:end_ts="1532018440" xil_pn:in_ck="9168920268850267136" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5089254454393185324" xil_pn:start_ts="1532018435">
  314. <status xil_pn:value="SuccessfullyRun"/>
  315. <status xil_pn:value="WarningsGenerated"/>
  316. <status xil_pn:value="ReadyToRun"/>
  317. <status xil_pn:value="OutOfDateForInputs"/>
  318. <status xil_pn:value="OutOfDateForProperties"/>
  319. <status xil_pn:value="OutOfDateForPredecessor"/>
  320. <status xil_pn:value="OutOfDateForOutputs"/>
  321. <status xil_pn:value="InputAdded"/>
  322. <status xil_pn:value="InputChanged"/>
  323. <status xil_pn:value="InputRemoved"/>
  324. <status xil_pn:value="OutputChanged"/>
  325. <status xil_pn:value="OutputRemoved"/>
  326. </transform>
  327. <transform xil_pn:end_ts="1532018440" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-5806287109881508414" xil_pn:start_ts="1532018440">
  328. <status xil_pn:value="SuccessfullyRun"/>
  329. <status xil_pn:value="ReadyToRun"/>
  330. <status xil_pn:value="OutOfDateForProperties"/>
  331. <status xil_pn:value="OutOfDateForPredecessor"/>
  332. </transform>
  333. <transform xil_pn:end_ts="1532018444" xil_pn:in_ck="332064574067544718" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-3378726865775739546" xil_pn:start_ts="1532018440">
  334. <status xil_pn:value="SuccessfullyRun"/>
  335. <status xil_pn:value="ReadyToRun"/>
  336. <status xil_pn:value="OutOfDateForInputs"/>
  337. <status xil_pn:value="OutOfDateForProperties"/>
  338. <status xil_pn:value="OutOfDateForPredecessor"/>
  339. <status xil_pn:value="OutOfDateForOutputs"/>
  340. <status xil_pn:value="InputRemoved"/>
  341. <status xil_pn:value="OutputRemoved"/>
  342. </transform>
  343. <transform xil_pn:end_ts="1532018450" xil_pn:in_ck="7360221192264252529" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="6093601622908603872" xil_pn:start_ts="1532018444">
  344. <status xil_pn:value="SuccessfullyRun"/>
  345. <status xil_pn:value="ReadyToRun"/>
  346. <status xil_pn:value="OutOfDateForInputs"/>
  347. <status xil_pn:value="OutOfDateForPredecessor"/>
  348. <status xil_pn:value="OutOfDateForOutputs"/>
  349. <status xil_pn:value="InputRemoved"/>
  350. <status xil_pn:value="OutputRemoved"/>
  351. </transform>
  352. <transform xil_pn:end_ts="1532018458" xil_pn:in_ck="2144869441163446044" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1532018450">
  353. <status xil_pn:value="SuccessfullyRun"/>
  354. <status xil_pn:value="ReadyToRun"/>
  355. <status xil_pn:value="OutOfDateForInputs"/>
  356. <status xil_pn:value="OutOfDateForPredecessor"/>
  357. <status xil_pn:value="OutOfDateForOutputs"/>
  358. <status xil_pn:value="InputRemoved"/>
  359. <status xil_pn:value="OutputRemoved"/>
  360. </transform>
  361. <transform xil_pn:end_ts="1532010373" xil_pn:in_ck="-5779554856324537901" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="5341574683187206424" xil_pn:start_ts="1532010367">
  362. <status xil_pn:value="SuccessfullyRun"/>
  363. <status xil_pn:value="ReadyToRun"/>
  364. <status xil_pn:value="OutOfDateForInputs"/>
  365. <status xil_pn:value="OutOfDateForPredecessor"/>
  366. <status xil_pn:value="OutOfDateForOutputs"/>
  367. <status xil_pn:value="InputAdded"/>
  368. <status xil_pn:value="InputRemoved"/>
  369. <status xil_pn:value="OutputRemoved"/>
  370. </transform>
  371. <transform xil_pn:end_ts="1532010374" xil_pn:in_ck="-5779554856324550755" xil_pn:name="TRAN_analyzeDesignUsingChipscope" xil_pn:prop_ck="-8030755723438207434" xil_pn:start_ts="1532010373">
  372. <status xil_pn:value="SuccessfullyRun"/>
  373. <status xil_pn:value="ReadyToRun"/>
  374. <status xil_pn:value="OutOfDateForInputs"/>
  375. <status xil_pn:value="OutOfDateForProperties"/>
  376. <status xil_pn:value="OutOfDateForPredecessor"/>
  377. <status xil_pn:value="InputRemoved"/>
  378. </transform>
  379. <transform xil_pn:end_ts="1532018458" xil_pn:in_ck="1980751275776402277" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1532018455">
  380. <status xil_pn:value="SuccessfullyRun"/>
  381. <status xil_pn:value="ReadyToRun"/>
  382. <status xil_pn:value="OutOfDateForInputs"/>
  383. <status xil_pn:value="OutOfDateForPredecessor"/>
  384. <status xil_pn:value="OutOfDateForOutputs"/>
  385. <status xil_pn:value="InputRemoved"/>
  386. <status xil_pn:value="OutputRemoved"/>
  387. </transform>
  388. </transforms>
  389. </generated_project>