Alexander M Gladtsin 4 years ago
parent
commit
1e988f95a4
100 changed files with 16480 additions and 419 deletions
  1. BIN
      stm32f1_01/build/main.o
  2. 0 120
      stm32f1_01/main.c
  3. 0 297
      stm32f1_01/source/startup_stm32f10x_ld.s
  4. 2 2
      stm32f1_01/Makefile
  5. BIN
      stm32f1_01_systick/build/main.bin
  6. BIN
      stm32f1_01_systick/build/main.elf
  7. 79 0
      stm32f1_01_systick/build/main.hex
  8. 747 0
      stm32f1_01_systick/build/main.lst
  9. BIN
      stm32f1_01_systick/build/main.o
  10. BIN
      stm32f1_01_systick/build/startup_stm32f10x_ld.o
  11. 0 0
      stm32f1_01_systick/inc/core_cm3.h
  12. 0 0
      stm32f1_01_systick/inc/misc.h
  13. 0 0
      stm32f1_01_systick/inc/stm3210c_eval.h
  14. 0 0
      stm32f1_01_systick/inc/stm3210c_eval_ioe.h
  15. 0 0
      stm32f1_01_systick/inc/stm3210c_eval_lcd.h
  16. 0 0
      stm32f1_01_systick/inc/stm32_eval.h
  17. 0 0
      stm32f1_01_systick/inc/stm32f10x.h
  18. 0 0
      stm32f1_01_systick/inc/stm32f10x_adc.h
  19. 0 0
      stm32f1_01_systick/inc/stm32f10x_bkp.h
  20. 0 0
      stm32f1_01_systick/inc/stm32f10x_can.h
  21. 0 0
      stm32f1_01_systick/inc/stm32f10x_cec.h
  22. 0 0
      stm32f1_01_systick/inc/stm32f10x_crc.h
  23. 0 0
      stm32f1_01_systick/inc/stm32f10x_dac.h
  24. 0 0
      stm32f1_01_systick/inc/stm32f10x_dbgmcu.h
  25. 0 0
      stm32f1_01_systick/inc/stm32f10x_dma.h
  26. 0 0
      stm32f1_01_systick/inc/stm32f10x_exti.h
  27. 0 0
      stm32f1_01_systick/inc/stm32f10x_flash.h
  28. 0 0
      stm32f1_01_systick/inc/stm32f10x_fsmc.h
  29. 0 0
      stm32f1_01_systick/inc/stm32f10x_gpio.h
  30. 0 0
      stm32f1_01_systick/inc/stm32f10x_i2c.h
  31. 0 0
      stm32f1_01_systick/inc/stm32f10x_iwdg.h
  32. 0 0
      stm32f1_01_systick/inc/stm32f10x_pwr.h
  33. 0 0
      stm32f1_01_systick/inc/stm32f10x_rcc.h
  34. 0 0
      stm32f1_01_systick/inc/stm32f10x_rtc.h
  35. 0 0
      stm32f1_01_systick/inc/stm32f10x_sdio.h
  36. 0 0
      stm32f1_01_systick/inc/stm32f10x_spi.h
  37. 0 0
      stm32f1_01_systick/inc/stm32f10x_tim.h
  38. 0 0
      stm32f1_01_systick/inc/stm32f10x_usart.h
  39. 0 0
      stm32f1_01_systick/inc/stm32f10x_wwdg.h
  40. 0 0
      stm32f1_01_systick/inc/system_stm32f10x.h
  41. 0 0
      stm32f1_01_systick/lib/core_cm3.c
  42. 0 0
      stm32f1_01_systick/lib/misc.c
  43. 0 0
      stm32f1_01_systick/lib/stm3210c_eval.c
  44. 0 0
      stm32f1_01_systick/lib/stm3210c_eval_ioe.c
  45. 0 0
      stm32f1_01_systick/lib/stm3210c_eval_lcd.c
  46. 0 0
      stm32f1_01_systick/lib/stm32_eval.c
  47. 0 0
      stm32f1_01_systick/lib/stm32f10x_adc.c
  48. 0 0
      stm32f1_01_systick/lib/stm32f10x_bkp.c
  49. 0 0
      stm32f1_01_systick/lib/stm32f10x_can.c
  50. 0 0
      stm32f1_01_systick/lib/stm32f10x_cec.c
  51. 0 0
      stm32f1_01_systick/lib/stm32f10x_crc.c
  52. 0 0
      stm32f1_01_systick/lib/stm32f10x_dac.c
  53. 0 0
      stm32f1_01_systick/lib/stm32f10x_dbgmcu.c
  54. 0 0
      stm32f1_01_systick/lib/stm32f10x_dma.c
  55. 0 0
      stm32f1_01_systick/lib/stm32f10x_exti.c
  56. 0 0
      stm32f1_01_systick/lib/stm32f10x_flash.c
  57. 0 0
      stm32f1_01_systick/lib/stm32f10x_fsmc.c
  58. 0 0
      stm32f1_01_systick/lib/stm32f10x_gpio.c
  59. 0 0
      stm32f1_01_systick/lib/stm32f10x_i2c.c
  60. 0 0
      stm32f1_01_systick/lib/stm32f10x_iwdg.c
  61. 0 0
      stm32f1_01_systick/lib/stm32f10x_pwr.c
  62. 0 0
      stm32f1_01_systick/lib/stm32f10x_rcc.c
  63. 0 0
      stm32f1_01_systick/lib/stm32f10x_rtc.c
  64. 0 0
      stm32f1_01_systick/lib/stm32f10x_sdio.c
  65. 0 0
      stm32f1_01_systick/lib/stm32f10x_spi.c
  66. 0 0
      stm32f1_01_systick/lib/stm32f10x_tim.c
  67. 0 0
      stm32f1_01_systick/lib/stm32f10x_usart.c
  68. 0 0
      stm32f1_01_systick/lib/stm32f10x_wwdg.c
  69. 0 0
      stm32f1_01_systick/lib/system_stm32f10x.c
  70. 21 0
      stm32f1_01_systick/main.c
  71. 2 0
      stm32f1_01/main.h
  72. 0 0
      stm32f1_01_systick/readme.txt
  73. 343 0
      stm32f1_01_systick/source/startup_stm32f10x_ld.s
  74. 0 0
      stm32f1_01_systick/stm32_flash.ld
  75. 0 0
      stm32f1_01_systick/stm32f10x_conf.h
  76. 0 0
      stm32f1_01_systick/stm32f10x_it.c
  77. 0 0
      stm32f1_01_systick/stm32f10x_it.h
  78. 0 0
      stm32f1_01_systick/system_stm32f10x.c
  79. 31 0
      stm32f1_02/Makefile
  80. 4 0
      stm32f1_02/gdb.txt
  81. 1818 0
      stm32f1_02/inc/core_cm3.h
  82. 118 0
      stm32f1_02/inc/fonts.h
  83. 220 0
      stm32f1_02/inc/misc.h
  84. 277 0
      stm32f1_02/inc/stm3210c_eval.h
  85. 537 0
      stm32f1_02/inc/stm3210c_eval_ioe.h
  86. 379 0
      stm32f1_02/inc/stm3210c_eval_lcd.h
  87. 368 0
      stm32f1_02/inc/stm32_eval.h
  88. 201 0
      stm32f1_02/inc/stm32_eval_i2c_ee.h
  89. 173 0
      stm32f1_02/inc/stm32_eval_i2c_tsensor.h
  90. 397 0
      stm32f1_02/inc/stm32_eval_sdio_sd.h
  91. 151 0
      stm32f1_02/inc/stm32_eval_spi_flash.h
  92. 280 0
      stm32f1_02/inc/stm32_eval_spi_sd.h
  93. 8336 0
      stm32f1_02/inc/stm32f10x.h
  94. 483 0
      stm32f1_02/inc/stm32f10x_adc.h
  95. 195 0
      stm32f1_02/inc/stm32f10x_bkp.h
  96. 697 0
      stm32f1_02/inc/stm32f10x_can.h
  97. 210 0
      stm32f1_02/inc/stm32f10x_cec.h
  98. 94 0
      stm32f1_02/inc/stm32f10x_crc.h
  99. 317 0
      stm32f1_02/inc/stm32f10x_dac.h
  100. 0 0
      stm32f1_02/inc/stm32f10x_dbgmcu.h

BIN
stm32f1_01/build/main.o


+ 0 - 120
stm32f1_01/main.c

@@ -1,120 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SysTick/TimeBase/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "main.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup SysTick_TimeBase
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-static __IO uint32_t TimingDelay;
-
-/* Private function prototypes -----------------------------------------------*/
-void Delay(__IO uint32_t nTime);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  if (SysTick_Config(SystemCoreClock / 1000))
-  { 
-    /* Capture error */ 
-    while (1);
-  }
-
-  while (1)
-  {
-    /* Insert 50 ms delay */
-    Delay(50);
-    Delay(100);
-  }
-}
-
-/**
-  * @brief  Inserts a delay time.
-  * @param  nTime: specifies the delay time length, in milliseconds.
-  * @retval None
-  */
-void Delay(__IO uint32_t nTime)
-{ 
-  TimingDelay = nTime;
-
-  while(TimingDelay != 0);
-}
-
-/**
-  * @brief  Decrements the TimingDelay variable.
-  * @param  None
-  * @retval None
-  */
-void TimingDelay_Decrement(void)
-{
-  if (TimingDelay != 0x00)
-  { 
-    TimingDelay--;
-  }
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

+ 0 - 297
stm32f1_01/source/startup_stm32f10x_ld.s

@@ -1,297 +0,0 @@
-;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
-;* File Name          : startup_stm32f10x_ld.s
-;* Author             : MCD Application Team
-;* Version            : V3.5.0
-;* Date               : 11-March-2011
-;* Description        : STM32F10x Low Density Devices vector table for MDK-ARM 
-;*                      toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the CortexM3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>   
-;*******************************************************************************
-; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler            ; Window Watchdog
-                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler          ; Tamper
-                DCD     RTC_IRQHandler             ; RTC
-                DCD     FLASH_IRQHandler           ; Flash
-                DCD     RCC_IRQHandler             ; RCC
-                DCD     EXTI0_IRQHandler           ; EXTI Line 0
-                DCD     EXTI1_IRQHandler           ; EXTI Line 1
-                DCD     EXTI2_IRQHandler           ; EXTI Line 2
-                DCD     EXTI3_IRQHandler           ; EXTI Line 3
-                DCD     EXTI4_IRQHandler           ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
-                DCD     ADC1_2_IRQHandler          ; ADC1_2
-                DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
-                DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
-                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
-                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
-                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
-                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
-                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
-                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
-                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler            ; TIM2
-                DCD     TIM3_IRQHandler            ; TIM3
-                DCD     0                          ; Reserved
-                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SPI1_IRQHandler            ; SPI1
-                DCD     0                          ; Reserved
-                DCD     USART1_IRQHandler          ; USART1
-                DCD     USART2_IRQHandler          ; USART2
-                DCD     0                          ; Reserved
-                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
-                DCD     RTCAlarm_IRQHandler        ; RTC Alarm through EXTI Line
-                DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-     IMPORT  __main
-     IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_IRQHandler          [WEAK]
-                EXPORT  RTC_IRQHandler             [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_2_IRQHandler          [WEAK]
-                EXPORT  USB_HP_CAN1_TX_IRQHandler  [WEAK]
-                EXPORT  USB_LP_CAN1_RX0_IRQHandler [WEAK]
-                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
-                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
-                EXPORT  TIM1_UP_IRQHandler         [WEAK]
-                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
-                EXPORT  TIM1_CC_IRQHandler         [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTCAlarm_IRQHandler        [WEAK]
-                EXPORT  USBWakeUp_IRQHandler       [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_IRQHandler
-TIM1_UP_IRQHandler
-TIM1_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-SPI1_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-EXTI15_10_IRQHandler
-RTCAlarm_IRQHandler
-USBWakeUp_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****

+ 2 - 2
stm32f1_01/Makefile

@@ -4,7 +4,7 @@ CP      = arm-none-eabi-objcopy
 OD      = arm-none-eabi-objdump
 
 CFLAGS  =  -I./ -I./lib -I./inc -c -fno-common -O0 -g -mcpu=cortex-m3 -mthumb 
-LFLAGS  = -Tstm32f10.ld -nostartfiles
+LFLAGS  = -Tstm32_flash.ld -nostartfiles
 ODFLAGS = -S
 AR+= -rcs
 
@@ -26,6 +26,6 @@ main.o: main.c
 	@ echo ".compiling"
 	$(CC) $(CFLAGS) main.c -o build/main.o
 
-startup.o: source/startup_stm32f10x.s
+startup.o: source/startup_stm32f10x_ld.s
 	@ echo ".compiling"
 	$(CC) $(CFLAGS) source/startup_stm32f10x_ld.s -o build/startup_stm32f10x_ld.o

BIN
stm32f1_01_systick/build/main.bin


BIN
stm32f1_01_systick/build/main.elf


+ 79 - 0
stm32f1_01_systick/build/main.hex

@@ -0,0 +1,79 @@
+:020000040800F2
+:1000000000280020550400089904000899040008FD
+:1000100099040008990400089904000800000000F1
+:10002000000000000000000000000000990400082B
+:10003000990400080000000099040008F10300087A
+:10004000990400089904000899040008990400081C
+:10005000990400089904000899040008990400080C
+:1000600099040008990400089904000899040008FC
+:1000700099040008990400089904000899040008EC
+:1000800099040008990400089904000899040008DC
+:1000900099040008990400089904000899040008CC
+:1000A00099040008990400089904000899040008BC
+:1000B0009904000899040008000000009904000851
+:1000C00099040008000000000000000099040008E6
+:1000D00000000000990400089904000800000000D6
+:1000E0009904000899040008990400080000000021
+:1000F0000000000000000000000000000000000000
+:0C01000000000000000000005FF808F1A3
+:10010C0080B483B000AF03463960FB7197F90730B8
+:10011C00002B0BDA0D49FB7903F00F03043B3A6813
+:10012C00D2B21201D2B20B441A7609E0084997F9FF
+:10013C0007303A68D2B21201D2B20B4483F80023D2
+:10014C0000BF0C37BD4680BC704700BF00ED00E01F
+:10015C0000E100E080B582B000AF78607B68B3F15D
+:10016C00807F01D3012311E00A4A7B6823F07F438F
+:10017C00013B53600F214FF0FF30FFF7C1FF054BE0
+:10018C0000229A60034B07221A6000231846083796
+:10019C00BD4680BD10E000E080B500AF154A154BA0
+:1001AC001B6843F0010313601249124B5A68124B3F
+:1001BC0013404B600F4A0F4B1B6823F0847323F4DE
+:1001CC00803313600B4A0B4B1B6823F480231360A2
+:1001DC00084A084B5B6823F4FE035360054B4FF44D
+:1001EC001F029A6000F078F8044B4FF000629A609E
+:1001FC0000BF80BD001002400000FFF800ED00E0E1
+:10020C0080B485B000AF0023FB600023BB600023EB
+:10021C007B602C4B5B6803F00C03FB60FB68042BCE
+:10022C0007D0082B09D0002B33D1274B274A1A6053
+:10023C0033E0254B254A1A602FE0224B5B6803F410
+:10024C007013BB601F4B5B6803F480337B60BB682F
+:10025C009B0C0233BB607B68002B06D1BB681C4A2D
+:10026C0002FB03F3184A136017E0164B5B6803F4A8
+:10027C000033002B06D0BB68154A02FB03F3124A6D
+:10028C0013600AE0BB68114A02FB03F30E4A1360C9
+:10029C0003E00D4B0D4A1A6000BF0A4B5B6803F07C
+:1002AC00F0031B090B4AD35CDBB2FB60064B1A68EC
+:1002BC00FB6822FA03F3044A136000BF1437BD46EF
+:1002CC0080BC7047001002400000002000127A0031
+:1002DC0000093D000400002080B500AF00F002F8DA
+:1002EC0000BF80BD80B483B000AF00237B600023CF
+:1002FC003B603A4A394B1B6843F480331360374BED
+:10030C001B6803F400333B607B6801337B603B6804
+:10031C00002B03D17B68B3F5A06FF0D12F4B1B687A
+:10032C0003F40033002B02D001233B6001E00023D7
+:10033C003B603B68012B4BD1294A294B1B6843F08E
+:10034C0010031360264A264B1B6823F0030313602B
+:10035C00234A234B1B6843F0020313601F4A1F4BB5
+:10036C005B6853601D4A1D4B5B6853601B4A1B4BFB
+:10037C005B6843F480635360184A184B5B6823F442
+:10038C007C135360154A154B5B6843F4E8135360B8
+:10039C00124A124B1B6843F08073136000BF0F4B63
+:1003AC001B6803F00073002BF9D00C4A0B4B5B68F5
+:1003BC0023F003035360094A084B5B6843F00203C4
+:1003CC00536000BF054B5B6803F00C03082BF9D19D
+:1003DC0000BF0C37BD4680BC704700BF0010024008
+:1003EC000020024080B400AF044B1B680133034A69
+:1003FC00136000BFBD4680BC704700BF14000020D6
+:10040C0080B500AFFFF7FCFE074B1B68074AA2FB49
+:10041C0003235B0B1846FFF79DFE034B1B681A4624
+:10042C00034B1A60F9E700BF000000205917B7D141
+:10043C00180000209C04000800000020140000207C
+:10044C00140000201C000020002103E00A4B5B5824
+:10045C004350043109480A4B42189A42F6D3094AD0
+:10046C0002E0002342F8043B074B9A42F9D3FFF712
+:10047C0093FEFFF7C5FF70479C04000800000020A6
+:10048C0014000020140000201C000020FEE70000D7
+:10049C0000A24A0400000000000000000102030456
+:0404AC00060708092E
+:040000050800045596
+:00000001FF

+ 747 - 0
stm32f1_01_systick/build/main.lst

@@ -0,0 +1,747 @@
+
+build/main.elf:     file format elf32-littlearm
+
+
+Disassembly of section .text:
+
+0800010c <NVIC_SetPriority>:
+ * interrupt, or negative to specify an internal (core) interrupt.
+ *
+ * Note: The priority cannot be set for every core interrupt.
+ */
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ 800010c:	b480      	push	{r7}
+ 800010e:	b083      	sub	sp, #12
+ 8000110:	af00      	add	r7, sp, #0
+ 8000112:	4603      	mov	r3, r0
+ 8000114:	6039      	str	r1, [r7, #0]
+ 8000116:	71fb      	strb	r3, [r7, #7]
+  if(IRQn < 0) {
+ 8000118:	f997 3007 	ldrsb.w	r3, [r7, #7]
+ 800011c:	2b00      	cmp	r3, #0
+ 800011e:	da0b      	bge.n	8000138 <NVIC_SetPriority+0x2c>
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
+ 8000120:	490d      	ldr	r1, [pc, #52]	; (8000158 <NVIC_SetPriority+0x4c>)
+ 8000122:	79fb      	ldrb	r3, [r7, #7]
+ 8000124:	f003 030f 	and.w	r3, r3, #15
+ 8000128:	3b04      	subs	r3, #4
+ 800012a:	683a      	ldr	r2, [r7, #0]
+ 800012c:	b2d2      	uxtb	r2, r2
+ 800012e:	0112      	lsls	r2, r2, #4
+ 8000130:	b2d2      	uxtb	r2, r2
+ 8000132:	440b      	add	r3, r1
+ 8000134:	761a      	strb	r2, [r3, #24]
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+ 8000136:	e009      	b.n	800014c <NVIC_SetPriority+0x40>
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+ 8000138:	4908      	ldr	r1, [pc, #32]	; (800015c <NVIC_SetPriority+0x50>)
+ 800013a:	f997 3007 	ldrsb.w	r3, [r7, #7]
+ 800013e:	683a      	ldr	r2, [r7, #0]
+ 8000140:	b2d2      	uxtb	r2, r2
+ 8000142:	0112      	lsls	r2, r2, #4
+ 8000144:	b2d2      	uxtb	r2, r2
+ 8000146:	440b      	add	r3, r1
+ 8000148:	f883 2300 	strb.w	r2, [r3, #768]	; 0x300
+}
+ 800014c:	bf00      	nop
+ 800014e:	370c      	adds	r7, #12
+ 8000150:	46bd      	mov	sp, r7
+ 8000152:	bc80      	pop	{r7}
+ 8000154:	4770      	bx	lr
+ 8000156:	bf00      	nop
+ 8000158:	e000ed00 	.word	0xe000ed00
+ 800015c:	e000e100 	.word	0xe000e100
+
+08000160 <SysTick_Config>:
+ * Initialise the system tick timer and its interrupt and start the
+ * system tick timer / counter in free running mode to generate 
+ * periodical interrupts.
+ */
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+{ 
+ 8000160:	b580      	push	{r7, lr}
+ 8000162:	b082      	sub	sp, #8
+ 8000164:	af00      	add	r7, sp, #0
+ 8000166:	6078      	str	r0, [r7, #4]
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+ 8000168:	687b      	ldr	r3, [r7, #4]
+ 800016a:	f1b3 7f80 	cmp.w	r3, #16777216	; 0x1000000
+ 800016e:	d301      	bcc.n	8000174 <SysTick_Config+0x14>
+ 8000170:	2301      	movs	r3, #1
+ 8000172:	e011      	b.n	8000198 <SysTick_Config+0x38>
+                                                               
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+ 8000174:	4a0a      	ldr	r2, [pc, #40]	; (80001a0 <SysTick_Config+0x40>)
+ 8000176:	687b      	ldr	r3, [r7, #4]
+ 8000178:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
+ 800017c:	3b01      	subs	r3, #1
+ 800017e:	6053      	str	r3, [r2, #4]
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
+ 8000180:	210f      	movs	r1, #15
+ 8000182:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
+ 8000186:	f7ff ffc1 	bl	800010c <NVIC_SetPriority>
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+ 800018a:	4b05      	ldr	r3, [pc, #20]	; (80001a0 <SysTick_Config+0x40>)
+ 800018c:	2200      	movs	r2, #0
+ 800018e:	609a      	str	r2, [r3, #8]
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk | 
+ 8000190:	4b03      	ldr	r3, [pc, #12]	; (80001a0 <SysTick_Config+0x40>)
+ 8000192:	2207      	movs	r2, #7
+ 8000194:	601a      	str	r2, [r3, #0]
+                   SysTick_CTRL_TICKINT_Msk   | 
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+ 8000196:	2300      	movs	r3, #0
+}
+ 8000198:	4618      	mov	r0, r3
+ 800019a:	3708      	adds	r7, #8
+ 800019c:	46bd      	mov	sp, r7
+ 800019e:	bd80      	pop	{r7, pc}
+ 80001a0:	e000e010 	.word	0xe000e010
+
+080001a4 <SystemInit>:
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+ 80001a4:	b580      	push	{r7, lr}
+ 80001a6:	af00      	add	r7, sp, #0
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+ 80001a8:	4a15      	ldr	r2, [pc, #84]	; (8000200 <SystemInit+0x5c>)
+ 80001aa:	4b15      	ldr	r3, [pc, #84]	; (8000200 <SystemInit+0x5c>)
+ 80001ac:	681b      	ldr	r3, [r3, #0]
+ 80001ae:	f043 0301 	orr.w	r3, r3, #1
+ 80001b2:	6013      	str	r3, [r2, #0]
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+ 80001b4:	4912      	ldr	r1, [pc, #72]	; (8000200 <SystemInit+0x5c>)
+ 80001b6:	4b12      	ldr	r3, [pc, #72]	; (8000200 <SystemInit+0x5c>)
+ 80001b8:	685a      	ldr	r2, [r3, #4]
+ 80001ba:	4b12      	ldr	r3, [pc, #72]	; (8000204 <SystemInit+0x60>)
+ 80001bc:	4013      	ands	r3, r2
+ 80001be:	604b      	str	r3, [r1, #4]
+#else
+  RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */   
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+ 80001c0:	4a0f      	ldr	r2, [pc, #60]	; (8000200 <SystemInit+0x5c>)
+ 80001c2:	4b0f      	ldr	r3, [pc, #60]	; (8000200 <SystemInit+0x5c>)
+ 80001c4:	681b      	ldr	r3, [r3, #0]
+ 80001c6:	f023 7384 	bic.w	r3, r3, #17301504	; 0x1080000
+ 80001ca:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
+ 80001ce:	6013      	str	r3, [r2, #0]
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+ 80001d0:	4a0b      	ldr	r2, [pc, #44]	; (8000200 <SystemInit+0x5c>)
+ 80001d2:	4b0b      	ldr	r3, [pc, #44]	; (8000200 <SystemInit+0x5c>)
+ 80001d4:	681b      	ldr	r3, [r3, #0]
+ 80001d6:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
+ 80001da:	6013      	str	r3, [r2, #0]
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+ 80001dc:	4a08      	ldr	r2, [pc, #32]	; (8000200 <SystemInit+0x5c>)
+ 80001de:	4b08      	ldr	r3, [pc, #32]	; (8000200 <SystemInit+0x5c>)
+ 80001e0:	685b      	ldr	r3, [r3, #4]
+ 80001e2:	f423 03fe 	bic.w	r3, r3, #8323072	; 0x7f0000
+ 80001e6:	6053      	str	r3, [r2, #4]
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+ 80001e8:	4b05      	ldr	r3, [pc, #20]	; (8000200 <SystemInit+0x5c>)
+ 80001ea:	f44f 021f 	mov.w	r2, #10420224	; 0x9f0000
+ 80001ee:	609a      	str	r2, [r3, #8]
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
+ 80001f0:	f000 f878 	bl	80002e4 <SetSysClock>
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+ 80001f4:	4b04      	ldr	r3, [pc, #16]	; (8000208 <SystemInit+0x64>)
+ 80001f6:	f04f 6200 	mov.w	r2, #134217728	; 0x8000000
+ 80001fa:	609a      	str	r2, [r3, #8]
+#endif 
+}
+ 80001fc:	bf00      	nop
+ 80001fe:	bd80      	pop	{r7, pc}
+ 8000200:	40021000 	.word	0x40021000
+ 8000204:	f8ff0000 	.word	0xf8ff0000
+ 8000208:	e000ed00 	.word	0xe000ed00
+
+0800020c <SystemCoreClockUpdate>:
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+ 800020c:	b480      	push	{r7}
+ 800020e:	b085      	sub	sp, #20
+ 8000210:	af00      	add	r7, sp, #0
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+ 8000212:	2300      	movs	r3, #0
+ 8000214:	60fb      	str	r3, [r7, #12]
+ 8000216:	2300      	movs	r3, #0
+ 8000218:	60bb      	str	r3, [r7, #8]
+ 800021a:	2300      	movs	r3, #0
+ 800021c:	607b      	str	r3, [r7, #4]
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+ 800021e:	4b2c      	ldr	r3, [pc, #176]	; (80002d0 <SystemCoreClockUpdate+0xc4>)
+ 8000220:	685b      	ldr	r3, [r3, #4]
+ 8000222:	f003 030c 	and.w	r3, r3, #12
+ 8000226:	60fb      	str	r3, [r7, #12]
+  
+  switch (tmp)
+ 8000228:	68fb      	ldr	r3, [r7, #12]
+ 800022a:	2b04      	cmp	r3, #4
+ 800022c:	d007      	beq.n	800023e <SystemCoreClockUpdate+0x32>
+ 800022e:	2b08      	cmp	r3, #8
+ 8000230:	d009      	beq.n	8000246 <SystemCoreClockUpdate+0x3a>
+ 8000232:	2b00      	cmp	r3, #0
+ 8000234:	d133      	bne.n	800029e <SystemCoreClockUpdate+0x92>
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+ 8000236:	4b27      	ldr	r3, [pc, #156]	; (80002d4 <SystemCoreClockUpdate+0xc8>)
+ 8000238:	4a27      	ldr	r2, [pc, #156]	; (80002d8 <SystemCoreClockUpdate+0xcc>)
+ 800023a:	601a      	str	r2, [r3, #0]
+      break;
+ 800023c:	e033      	b.n	80002a6 <SystemCoreClockUpdate+0x9a>
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+ 800023e:	4b25      	ldr	r3, [pc, #148]	; (80002d4 <SystemCoreClockUpdate+0xc8>)
+ 8000240:	4a25      	ldr	r2, [pc, #148]	; (80002d8 <SystemCoreClockUpdate+0xcc>)
+ 8000242:	601a      	str	r2, [r3, #0]
+      break;
+ 8000244:	e02f      	b.n	80002a6 <SystemCoreClockUpdate+0x9a>
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+ 8000246:	4b22      	ldr	r3, [pc, #136]	; (80002d0 <SystemCoreClockUpdate+0xc4>)
+ 8000248:	685b      	ldr	r3, [r3, #4]
+ 800024a:	f403 1370 	and.w	r3, r3, #3932160	; 0x3c0000
+ 800024e:	60bb      	str	r3, [r7, #8]
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+ 8000250:	4b1f      	ldr	r3, [pc, #124]	; (80002d0 <SystemCoreClockUpdate+0xc4>)
+ 8000252:	685b      	ldr	r3, [r3, #4]
+ 8000254:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
+ 8000258:	607b      	str	r3, [r7, #4]
+      
+#ifndef STM32F10X_CL      
+      pllmull = ( pllmull >> 18) + 2;
+ 800025a:	68bb      	ldr	r3, [r7, #8]
+ 800025c:	0c9b      	lsrs	r3, r3, #18
+ 800025e:	3302      	adds	r3, #2
+ 8000260:	60bb      	str	r3, [r7, #8]
+      
+      if (pllsource == 0x00)
+ 8000262:	687b      	ldr	r3, [r7, #4]
+ 8000264:	2b00      	cmp	r3, #0
+ 8000266:	d106      	bne.n	8000276 <SystemCoreClockUpdate+0x6a>
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ 8000268:	68bb      	ldr	r3, [r7, #8]
+ 800026a:	4a1c      	ldr	r2, [pc, #112]	; (80002dc <SystemCoreClockUpdate+0xd0>)
+ 800026c:	fb02 f303 	mul.w	r3, r2, r3
+ 8000270:	4a18      	ldr	r2, [pc, #96]	; (80002d4 <SystemCoreClockUpdate+0xc8>)
+ 8000272:	6013      	str	r3, [r2, #0]
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F10X_CL */ 
+      break;
+ 8000274:	e017      	b.n	80002a6 <SystemCoreClockUpdate+0x9a>
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+ 8000276:	4b16      	ldr	r3, [pc, #88]	; (80002d0 <SystemCoreClockUpdate+0xc4>)
+ 8000278:	685b      	ldr	r3, [r3, #4]
+ 800027a:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 800027e:	2b00      	cmp	r3, #0
+ 8000280:	d006      	beq.n	8000290 <SystemCoreClockUpdate+0x84>
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+ 8000282:	68bb      	ldr	r3, [r7, #8]
+ 8000284:	4a15      	ldr	r2, [pc, #84]	; (80002dc <SystemCoreClockUpdate+0xd0>)
+ 8000286:	fb02 f303 	mul.w	r3, r2, r3
+ 800028a:	4a12      	ldr	r2, [pc, #72]	; (80002d4 <SystemCoreClockUpdate+0xc8>)
+ 800028c:	6013      	str	r3, [r2, #0]
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F10X_CL */ 
+      break;
+ 800028e:	e00a      	b.n	80002a6 <SystemCoreClockUpdate+0x9a>
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+ 8000290:	68bb      	ldr	r3, [r7, #8]
+ 8000292:	4a11      	ldr	r2, [pc, #68]	; (80002d8 <SystemCoreClockUpdate+0xcc>)
+ 8000294:	fb02 f303 	mul.w	r3, r2, r3
+ 8000298:	4a0e      	ldr	r2, [pc, #56]	; (80002d4 <SystemCoreClockUpdate+0xc8>)
+ 800029a:	6013      	str	r3, [r2, #0]
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F10X_CL */ 
+      break;
+ 800029c:	e003      	b.n	80002a6 <SystemCoreClockUpdate+0x9a>
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+ 800029e:	4b0d      	ldr	r3, [pc, #52]	; (80002d4 <SystemCoreClockUpdate+0xc8>)
+ 80002a0:	4a0d      	ldr	r2, [pc, #52]	; (80002d8 <SystemCoreClockUpdate+0xcc>)
+ 80002a2:	601a      	str	r2, [r3, #0]
+      break;
+ 80002a4:	bf00      	nop
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ 80002a6:	4b0a      	ldr	r3, [pc, #40]	; (80002d0 <SystemCoreClockUpdate+0xc4>)
+ 80002a8:	685b      	ldr	r3, [r3, #4]
+ 80002aa:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
+ 80002ae:	091b      	lsrs	r3, r3, #4
+ 80002b0:	4a0b      	ldr	r2, [pc, #44]	; (80002e0 <SystemCoreClockUpdate+0xd4>)
+ 80002b2:	5cd3      	ldrb	r3, [r2, r3]
+ 80002b4:	b2db      	uxtb	r3, r3
+ 80002b6:	60fb      	str	r3, [r7, #12]
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+ 80002b8:	4b06      	ldr	r3, [pc, #24]	; (80002d4 <SystemCoreClockUpdate+0xc8>)
+ 80002ba:	681a      	ldr	r2, [r3, #0]
+ 80002bc:	68fb      	ldr	r3, [r7, #12]
+ 80002be:	fa22 f303 	lsr.w	r3, r2, r3
+ 80002c2:	4a04      	ldr	r2, [pc, #16]	; (80002d4 <SystemCoreClockUpdate+0xc8>)
+ 80002c4:	6013      	str	r3, [r2, #0]
+}
+ 80002c6:	bf00      	nop
+ 80002c8:	3714      	adds	r7, #20
+ 80002ca:	46bd      	mov	sp, r7
+ 80002cc:	bc80      	pop	{r7}
+ 80002ce:	4770      	bx	lr
+ 80002d0:	40021000 	.word	0x40021000
+ 80002d4:	20000000 	.word	0x20000000
+ 80002d8:	007a1200 	.word	0x007a1200
+ 80002dc:	003d0900 	.word	0x003d0900
+ 80002e0:	20000004 	.word	0x20000004
+
+080002e4 <SetSysClock>:
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+ 80002e4:	b580      	push	{r7, lr}
+ 80002e6:	af00      	add	r7, sp, #0
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+ 80002e8:	f000 f802 	bl	80002f0 <SetSysClockTo72>
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */ 
+}
+ 80002ec:	bf00      	nop
+ 80002ee:	bd80      	pop	{r7, pc}
+
+080002f0 <SetSysClockTo72>:
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+ 80002f0:	b480      	push	{r7}
+ 80002f2:	b083      	sub	sp, #12
+ 80002f4:	af00      	add	r7, sp, #0
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+ 80002f6:	2300      	movs	r3, #0
+ 80002f8:	607b      	str	r3, [r7, #4]
+ 80002fa:	2300      	movs	r3, #0
+ 80002fc:	603b      	str	r3, [r7, #0]
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 80002fe:	4a3a      	ldr	r2, [pc, #232]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 8000300:	4b39      	ldr	r3, [pc, #228]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 8000302:	681b      	ldr	r3, [r3, #0]
+ 8000304:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
+ 8000308:	6013      	str	r3, [r2, #0]
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ 800030a:	4b37      	ldr	r3, [pc, #220]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 800030c:	681b      	ldr	r3, [r3, #0]
+ 800030e:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 8000312:	603b      	str	r3, [r7, #0]
+    StartUpCounter++;  
+ 8000314:	687b      	ldr	r3, [r7, #4]
+ 8000316:	3301      	adds	r3, #1
+ 8000318:	607b      	str	r3, [r7, #4]
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+ 800031a:	683b      	ldr	r3, [r7, #0]
+ 800031c:	2b00      	cmp	r3, #0
+ 800031e:	d103      	bne.n	8000328 <SetSysClockTo72+0x38>
+ 8000320:	687b      	ldr	r3, [r7, #4]
+ 8000322:	f5b3 6fa0 	cmp.w	r3, #1280	; 0x500
+ 8000326:	d1f0      	bne.n	800030a <SetSysClockTo72+0x1a>
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ 8000328:	4b2f      	ldr	r3, [pc, #188]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 800032a:	681b      	ldr	r3, [r3, #0]
+ 800032c:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 8000330:	2b00      	cmp	r3, #0
+ 8000332:	d002      	beq.n	800033a <SetSysClockTo72+0x4a>
+  {
+    HSEStatus = (uint32_t)0x01;
+ 8000334:	2301      	movs	r3, #1
+ 8000336:	603b      	str	r3, [r7, #0]
+ 8000338:	e001      	b.n	800033e <SetSysClockTo72+0x4e>
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+ 800033a:	2300      	movs	r3, #0
+ 800033c:	603b      	str	r3, [r7, #0]
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+ 800033e:	683b      	ldr	r3, [r7, #0]
+ 8000340:	2b01      	cmp	r3, #1
+ 8000342:	d14b      	bne.n	80003dc <SetSysClockTo72+0xec>
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+ 8000344:	4a29      	ldr	r2, [pc, #164]	; (80003ec <SetSysClockTo72+0xfc>)
+ 8000346:	4b29      	ldr	r3, [pc, #164]	; (80003ec <SetSysClockTo72+0xfc>)
+ 8000348:	681b      	ldr	r3, [r3, #0]
+ 800034a:	f043 0310 	orr.w	r3, r3, #16
+ 800034e:	6013      	str	r3, [r2, #0]
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ 8000350:	4a26      	ldr	r2, [pc, #152]	; (80003ec <SetSysClockTo72+0xfc>)
+ 8000352:	4b26      	ldr	r3, [pc, #152]	; (80003ec <SetSysClockTo72+0xfc>)
+ 8000354:	681b      	ldr	r3, [r3, #0]
+ 8000356:	f023 0303 	bic.w	r3, r3, #3
+ 800035a:	6013      	str	r3, [r2, #0]
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 800035c:	4a23      	ldr	r2, [pc, #140]	; (80003ec <SetSysClockTo72+0xfc>)
+ 800035e:	4b23      	ldr	r3, [pc, #140]	; (80003ec <SetSysClockTo72+0xfc>)
+ 8000360:	681b      	ldr	r3, [r3, #0]
+ 8000362:	f043 0302 	orr.w	r3, r3, #2
+ 8000366:	6013      	str	r3, [r2, #0]
+
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+ 8000368:	4a1f      	ldr	r2, [pc, #124]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 800036a:	4b1f      	ldr	r3, [pc, #124]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 800036c:	685b      	ldr	r3, [r3, #4]
+ 800036e:	6053      	str	r3, [r2, #4]
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+ 8000370:	4a1d      	ldr	r2, [pc, #116]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 8000372:	4b1d      	ldr	r3, [pc, #116]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 8000374:	685b      	ldr	r3, [r3, #4]
+ 8000376:	6053      	str	r3, [r2, #4]
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+ 8000378:	4a1b      	ldr	r2, [pc, #108]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 800037a:	4b1b      	ldr	r3, [pc, #108]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 800037c:	685b      	ldr	r3, [r3, #4]
+ 800037e:	f443 6380 	orr.w	r3, r3, #1024	; 0x400
+ 8000382:	6053      	str	r3, [r2, #4]
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+ 8000384:	4a18      	ldr	r2, [pc, #96]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 8000386:	4b18      	ldr	r3, [pc, #96]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 8000388:	685b      	ldr	r3, [r3, #4]
+ 800038a:	f423 137c 	bic.w	r3, r3, #4128768	; 0x3f0000
+ 800038e:	6053      	str	r3, [r2, #4]
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+ 8000390:	4a15      	ldr	r2, [pc, #84]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 8000392:	4b15      	ldr	r3, [pc, #84]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 8000394:	685b      	ldr	r3, [r3, #4]
+ 8000396:	f443 13e8 	orr.w	r3, r3, #1900544	; 0x1d0000
+ 800039a:	6053      	str	r3, [r2, #4]
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+ 800039c:	4a12      	ldr	r2, [pc, #72]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 800039e:	4b12      	ldr	r3, [pc, #72]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 80003a0:	681b      	ldr	r3, [r3, #0]
+ 80003a2:	f043 7380 	orr.w	r3, r3, #16777216	; 0x1000000
+ 80003a6:	6013      	str	r3, [r2, #0]
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ 80003a8:	bf00      	nop
+ 80003aa:	4b0f      	ldr	r3, [pc, #60]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 80003ac:	681b      	ldr	r3, [r3, #0]
+ 80003ae:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
+ 80003b2:	2b00      	cmp	r3, #0
+ 80003b4:	d0f9      	beq.n	80003aa <SetSysClockTo72+0xba>
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ 80003b6:	4a0c      	ldr	r2, [pc, #48]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 80003b8:	4b0b      	ldr	r3, [pc, #44]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 80003ba:	685b      	ldr	r3, [r3, #4]
+ 80003bc:	f023 0303 	bic.w	r3, r3, #3
+ 80003c0:	6053      	str	r3, [r2, #4]
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+ 80003c2:	4a09      	ldr	r2, [pc, #36]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 80003c4:	4b08      	ldr	r3, [pc, #32]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 80003c6:	685b      	ldr	r3, [r3, #4]
+ 80003c8:	f043 0302 	orr.w	r3, r3, #2
+ 80003cc:	6053      	str	r3, [r2, #4]
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ 80003ce:	bf00      	nop
+ 80003d0:	4b05      	ldr	r3, [pc, #20]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 80003d2:	685b      	ldr	r3, [r3, #4]
+ 80003d4:	f003 030c 	and.w	r3, r3, #12
+ 80003d8:	2b08      	cmp	r3, #8
+ 80003da:	d1f9      	bne.n	80003d0 <SetSysClockTo72+0xe0>
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }
+}
+ 80003dc:	bf00      	nop
+ 80003de:	370c      	adds	r7, #12
+ 80003e0:	46bd      	mov	sp, r7
+ 80003e2:	bc80      	pop	{r7}
+ 80003e4:	4770      	bx	lr
+ 80003e6:	bf00      	nop
+ 80003e8:	40021000 	.word	0x40021000
+ 80003ec:	40022000 	.word	0x40022000
+
+080003f0 <SysTick_Handler>:
+
+
+volatile long int aa=0,bb=0;
+
+
+void SysTick_Handler(void) {
+ 80003f0:	b480      	push	{r7}
+ 80003f2:	af00      	add	r7, sp, #0
+    aa++;
+ 80003f4:	4b04      	ldr	r3, [pc, #16]	; (8000408 <SysTick_Handler+0x18>)
+ 80003f6:	681b      	ldr	r3, [r3, #0]
+ 80003f8:	3301      	adds	r3, #1
+ 80003fa:	4a03      	ldr	r2, [pc, #12]	; (8000408 <SysTick_Handler+0x18>)
+ 80003fc:	6013      	str	r3, [r2, #0]
+
+}
+ 80003fe:	bf00      	nop
+ 8000400:	46bd      	mov	sp, r7
+ 8000402:	bc80      	pop	{r7}
+ 8000404:	4770      	bx	lr
+ 8000406:	bf00      	nop
+ 8000408:	20000014 	.word	0x20000014
+
+0800040c <main>:
+
+int main(void) {
+ 800040c:	b580      	push	{r7, lr}
+ 800040e:	af00      	add	r7, sp, #0
+    SystemCoreClockUpdate();
+ 8000410:	f7ff fefc 	bl	800020c <SystemCoreClockUpdate>
+    SysTick_Config(SystemCoreClock/10000);
+ 8000414:	4b07      	ldr	r3, [pc, #28]	; (8000434 <main+0x28>)
+ 8000416:	681b      	ldr	r3, [r3, #0]
+ 8000418:	4a07      	ldr	r2, [pc, #28]	; (8000438 <main+0x2c>)
+ 800041a:	fba2 2303 	umull	r2, r3, r2, r3
+ 800041e:	0b5b      	lsrs	r3, r3, #13
+ 8000420:	4618      	mov	r0, r3
+ 8000422:	f7ff fe9d 	bl	8000160 <SysTick_Config>
+
+    while (1) {
+    bb=SystemCoreClock;
+ 8000426:	4b03      	ldr	r3, [pc, #12]	; (8000434 <main+0x28>)
+ 8000428:	681b      	ldr	r3, [r3, #0]
+ 800042a:	461a      	mov	r2, r3
+ 800042c:	4b03      	ldr	r3, [pc, #12]	; (800043c <main+0x30>)
+ 800042e:	601a      	str	r2, [r3, #0]
+    }
+ 8000430:	e7f9      	b.n	8000426 <main+0x1a>
+ 8000432:	bf00      	nop
+ 8000434:	20000000 	.word	0x20000000
+ 8000438:	d1b71759 	.word	0xd1b71759
+ 800043c:	20000018 	.word	0x20000018
+ 8000440:	0800049c 	.word	0x0800049c
+ 8000444:	20000000 	.word	0x20000000
+ 8000448:	20000014 	.word	0x20000014
+ 800044c:	20000014 	.word	0x20000014
+ 8000450:	2000001c 	.word	0x2000001c
+
+08000454 <Reset_Handler>:
+	.weak	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:	
+
+/* Copy the data segment initializers from flash to SRAM */  
+  movs	r1, #0
+ 8000454:	2100      	movs	r1, #0
+  b	LoopCopyDataInit
+ 8000456:	e003      	b.n	8000460 <LoopCopyDataInit>
+
+08000458 <CopyDataInit>:
+
+CopyDataInit:
+	ldr	r3, =_sidata
+ 8000458:	4b0a      	ldr	r3, [pc, #40]	; (8000484 <LoopFillZerobss+0x10>)
+	ldr	r3, [r3, r1]
+ 800045a:	585b      	ldr	r3, [r3, r1]
+	str	r3, [r0, r1]
+ 800045c:	5043      	str	r3, [r0, r1]
+	adds	r1, r1, #4
+ 800045e:	3104      	adds	r1, #4
+
+08000460 <LoopCopyDataInit>:
+    
+LoopCopyDataInit:
+	ldr	r0, =_sdata
+ 8000460:	4809      	ldr	r0, [pc, #36]	; (8000488 <LoopFillZerobss+0x14>)
+	ldr	r3, =_edata
+ 8000462:	4b0a      	ldr	r3, [pc, #40]	; (800048c <LoopFillZerobss+0x18>)
+	adds	r2, r0, r1
+ 8000464:	1842      	adds	r2, r0, r1
+	cmp	r2, r3
+ 8000466:	429a      	cmp	r2, r3
+	bcc	CopyDataInit
+ 8000468:	d3f6      	bcc.n	8000458 <CopyDataInit>
+	ldr	r2, =_sbss
+ 800046a:	4a09      	ldr	r2, [pc, #36]	; (8000490 <LoopFillZerobss+0x1c>)
+	b	LoopFillZerobss
+ 800046c:	e002      	b.n	8000474 <LoopFillZerobss>
+
+0800046e <FillZerobss>:
+/* Zero fill the bss segment. */  
+FillZerobss:
+	movs	r3, #0
+ 800046e:	2300      	movs	r3, #0
+	str	r3, [r2], #4
+ 8000470:	f842 3b04 	str.w	r3, [r2], #4
+
+08000474 <LoopFillZerobss>:
+    
+LoopFillZerobss:
+	ldr	r3, = _ebss
+ 8000474:	4b07      	ldr	r3, [pc, #28]	; (8000494 <LoopFillZerobss+0x20>)
+	cmp	r2, r3
+ 8000476:	429a      	cmp	r2, r3
+	bcc	FillZerobss
+ 8000478:	d3f9      	bcc.n	800046e <FillZerobss>
+/* Call the clock system intitialization function.*/
+  bl  SystemInit  
+ 800047a:	f7ff fe93 	bl	80001a4 <SystemInit>
+/* Call the application's entry point.*/
+	bl	main
+ 800047e:	f7ff ffc5 	bl	800040c <main>
+	bx	lr    
+ 8000482:	4770      	bx	lr
+/* Copy the data segment initializers from flash to SRAM */  
+  movs	r1, #0
+  b	LoopCopyDataInit
+
+CopyDataInit:
+	ldr	r3, =_sidata
+ 8000484:	0800049c 	.word	0x0800049c
+	ldr	r3, [r3, r1]
+	str	r3, [r0, r1]
+	adds	r1, r1, #4
+    
+LoopCopyDataInit:
+	ldr	r0, =_sdata
+ 8000488:	20000000 	.word	0x20000000
+	ldr	r3, =_edata
+ 800048c:	20000014 	.word	0x20000014
+	adds	r2, r0, r1
+	cmp	r2, r3
+	bcc	CopyDataInit
+	ldr	r2, =_sbss
+ 8000490:	20000014 	.word	0x20000014
+FillZerobss:
+	movs	r3, #0
+	str	r3, [r2], #4
+    
+LoopFillZerobss:
+	ldr	r3, = _ebss
+ 8000494:	2000001c 	.word	0x2000001c
+
+08000498 <ADC1_2_IRQHandler>:
+ * @retval None       
+*/
+    .section	.text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+ 8000498:	e7fe      	b.n	8000498 <ADC1_2_IRQHandler>
+	...

BIN
stm32f1_01_systick/build/main.o


BIN
stm32f1_01_systick/build/startup_stm32f10x_ld.o


stm32f1_01/inc/core_cm3.h → stm32f1_01_systick/inc/core_cm3.h


stm32f1_01/inc/misc.h → stm32f1_01_systick/inc/misc.h


stm32f1_01/inc/stm3210c_eval.h → stm32f1_01_systick/inc/stm3210c_eval.h


stm32f1_01/inc/stm3210c_eval_ioe.h → stm32f1_01_systick/inc/stm3210c_eval_ioe.h


stm32f1_01/inc/stm3210c_eval_lcd.h → stm32f1_01_systick/inc/stm3210c_eval_lcd.h


stm32f1_01/inc/stm32_eval.h → stm32f1_01_systick/inc/stm32_eval.h


stm32f1_01/inc/stm32f10x.h → stm32f1_01_systick/inc/stm32f10x.h


stm32f1_01/inc/stm32f10x_adc.h → stm32f1_01_systick/inc/stm32f10x_adc.h


stm32f1_01/inc/stm32f10x_bkp.h → stm32f1_01_systick/inc/stm32f10x_bkp.h


stm32f1_01/inc/stm32f10x_can.h → stm32f1_01_systick/inc/stm32f10x_can.h


stm32f1_01/inc/stm32f10x_cec.h → stm32f1_01_systick/inc/stm32f10x_cec.h


stm32f1_01/inc/stm32f10x_crc.h → stm32f1_01_systick/inc/stm32f10x_crc.h


stm32f1_01/inc/stm32f10x_dac.h → stm32f1_01_systick/inc/stm32f10x_dac.h


stm32f1_01/inc/stm32f10x_dbgmcu.h → stm32f1_01_systick/inc/stm32f10x_dbgmcu.h


stm32f1_01/inc/stm32f10x_dma.h → stm32f1_01_systick/inc/stm32f10x_dma.h


stm32f1_01/inc/stm32f10x_exti.h → stm32f1_01_systick/inc/stm32f10x_exti.h


stm32f1_01/inc/stm32f10x_flash.h → stm32f1_01_systick/inc/stm32f10x_flash.h


stm32f1_01/inc/stm32f10x_fsmc.h → stm32f1_01_systick/inc/stm32f10x_fsmc.h


stm32f1_01/inc/stm32f10x_gpio.h → stm32f1_01_systick/inc/stm32f10x_gpio.h


stm32f1_01/inc/stm32f10x_i2c.h → stm32f1_01_systick/inc/stm32f10x_i2c.h


stm32f1_01/inc/stm32f10x_iwdg.h → stm32f1_01_systick/inc/stm32f10x_iwdg.h


stm32f1_01/inc/stm32f10x_pwr.h → stm32f1_01_systick/inc/stm32f10x_pwr.h


stm32f1_01/inc/stm32f10x_rcc.h → stm32f1_01_systick/inc/stm32f10x_rcc.h


stm32f1_01/inc/stm32f10x_rtc.h → stm32f1_01_systick/inc/stm32f10x_rtc.h


stm32f1_01/inc/stm32f10x_sdio.h → stm32f1_01_systick/inc/stm32f10x_sdio.h


stm32f1_01/inc/stm32f10x_spi.h → stm32f1_01_systick/inc/stm32f10x_spi.h


stm32f1_01/inc/stm32f10x_tim.h → stm32f1_01_systick/inc/stm32f10x_tim.h


stm32f1_01/inc/stm32f10x_usart.h → stm32f1_01_systick/inc/stm32f10x_usart.h


stm32f1_01/inc/stm32f10x_wwdg.h → stm32f1_01_systick/inc/stm32f10x_wwdg.h


stm32f1_01/inc/system_stm32f10x.h → stm32f1_01_systick/inc/system_stm32f10x.h


stm32f1_01/lib/core_cm3.c → stm32f1_01_systick/lib/core_cm3.c


stm32f1_01/lib/misc.c → stm32f1_01_systick/lib/misc.c


stm32f1_01/lib/stm3210c_eval.c → stm32f1_01_systick/lib/stm3210c_eval.c


stm32f1_01/lib/stm3210c_eval_ioe.c → stm32f1_01_systick/lib/stm3210c_eval_ioe.c


stm32f1_01/lib/stm3210c_eval_lcd.c → stm32f1_01_systick/lib/stm3210c_eval_lcd.c


stm32f1_01/lib/stm32_eval.c → stm32f1_01_systick/lib/stm32_eval.c


stm32f1_01/lib/stm32f10x_adc.c → stm32f1_01_systick/lib/stm32f10x_adc.c


stm32f1_01/lib/stm32f10x_bkp.c → stm32f1_01_systick/lib/stm32f10x_bkp.c


stm32f1_01/lib/stm32f10x_can.c → stm32f1_01_systick/lib/stm32f10x_can.c


stm32f1_01/lib/stm32f10x_cec.c → stm32f1_01_systick/lib/stm32f10x_cec.c


stm32f1_01/lib/stm32f10x_crc.c → stm32f1_01_systick/lib/stm32f10x_crc.c


stm32f1_01/lib/stm32f10x_dac.c → stm32f1_01_systick/lib/stm32f10x_dac.c


stm32f1_01/lib/stm32f10x_dbgmcu.c → stm32f1_01_systick/lib/stm32f10x_dbgmcu.c


stm32f1_01/lib/stm32f10x_dma.c → stm32f1_01_systick/lib/stm32f10x_dma.c


stm32f1_01/lib/stm32f10x_exti.c → stm32f1_01_systick/lib/stm32f10x_exti.c


stm32f1_01/lib/stm32f10x_flash.c → stm32f1_01_systick/lib/stm32f10x_flash.c


stm32f1_01/lib/stm32f10x_fsmc.c → stm32f1_01_systick/lib/stm32f10x_fsmc.c


stm32f1_01/lib/stm32f10x_gpio.c → stm32f1_01_systick/lib/stm32f10x_gpio.c


stm32f1_01/lib/stm32f10x_i2c.c → stm32f1_01_systick/lib/stm32f10x_i2c.c


stm32f1_01/lib/stm32f10x_iwdg.c → stm32f1_01_systick/lib/stm32f10x_iwdg.c


stm32f1_01/lib/stm32f10x_pwr.c → stm32f1_01_systick/lib/stm32f10x_pwr.c


stm32f1_01/lib/stm32f10x_rcc.c → stm32f1_01_systick/lib/stm32f10x_rcc.c


stm32f1_01/lib/stm32f10x_rtc.c → stm32f1_01_systick/lib/stm32f10x_rtc.c


stm32f1_01/lib/stm32f10x_sdio.c → stm32f1_01_systick/lib/stm32f10x_sdio.c


stm32f1_01/lib/stm32f10x_spi.c → stm32f1_01_systick/lib/stm32f10x_spi.c


stm32f1_01/lib/stm32f10x_tim.c → stm32f1_01_systick/lib/stm32f10x_tim.c


stm32f1_01/lib/stm32f10x_usart.c → stm32f1_01_systick/lib/stm32f10x_usart.c


stm32f1_01/lib/stm32f10x_wwdg.c → stm32f1_01_systick/lib/stm32f10x_wwdg.c


stm32f1_01/lib/system_stm32f10x.c → stm32f1_01_systick/lib/system_stm32f10x.c


+ 21 - 0
stm32f1_01_systick/main.c

@@ -0,0 +1,21 @@
+#include "main.h"
+
+
+volatile long int aa=0,bb=0;
+
+
+void SysTick_Handler(void) {
+    aa++;
+
+}
+
+int main(void) {
+    SystemCoreClockUpdate();
+    SysTick_Config(SystemCoreClock/10000);
+
+    while (1) {
+    bb=SystemCoreClock;
+    }
+
+    return 0;
+}

+ 2 - 0
stm32f1_01/main.h

@@ -25,6 +25,8 @@
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f10x.h"
+#include "system_stm32f10x.h"
+#include "system_stm32f10x.c"
 //#include "stm32_eval.h"
 
 /* Exported types ------------------------------------------------------------*/

stm32f1_01/readme.txt → stm32f1_01_systick/readme.txt


+ 343 - 0
stm32f1_01_systick/source/startup_stm32f10x_ld.s

@@ -0,0 +1,343 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f10x_ld.s
+  * @author    MCD Application Team
+  * @version   V3.5.0
+  * @date      11-March-2011
+  * @brief     STM32F10x Low Density Devices vector table for RIDE7 toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system  
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M3 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */	
+    
+  .syntax unified
+	.cpu cortex-m3
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section. 
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */  
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+
+.equ  BootRAM, 0xF108F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called. 
+ * @param  None
+ * @retval : None
+*/
+
+    .section	.text.Reset_Handler
+	.weak	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:	
+
+/* Copy the data segment initializers from flash to SRAM */  
+  movs	r1, #0
+  b	LoopCopyDataInit
+
+CopyDataInit:
+	ldr	r3, =_sidata
+	ldr	r3, [r3, r1]
+	str	r3, [r0, r1]
+	adds	r1, r1, #4
+    
+LoopCopyDataInit:
+	ldr	r0, =_sdata
+	ldr	r3, =_edata
+	adds	r2, r0, r1
+	cmp	r2, r3
+	bcc	CopyDataInit
+	ldr	r2, =_sbss
+	b	LoopFillZerobss
+/* Zero fill the bss segment. */  
+FillZerobss:
+	movs	r3, #0
+	str	r3, [r2], #4
+    
+LoopFillZerobss:
+	ldr	r3, = _ebss
+	cmp	r2, r3
+	bcc	FillZerobss
+/* Call the clock system intitialization function.*/
+  bl  SystemInit  
+/* Call the application's entry point.*/
+	bl	main
+	bx	lr    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an 
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None     
+ * @retval None       
+*/
+    .section	.text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/    
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+    
+    
+g_pfnVectors:
+	.word	_estack
+	.word	Reset_Handler
+	.word	NMI_Handler
+	.word	HardFault_Handler
+	.word	MemManage_Handler
+	.word	BusFault_Handler
+	.word	UsageFault_Handler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	SVC_Handler
+	.word	DebugMon_Handler
+	.word	0
+	.word	PendSV_Handler
+	.word	SysTick_Handler
+	.word	WWDG_IRQHandler
+	.word	PVD_IRQHandler
+	.word	TAMPER_IRQHandler
+	.word	RTC_IRQHandler
+	.word	FLASH_IRQHandler
+	.word	RCC_IRQHandler
+	.word	EXTI0_IRQHandler
+	.word	EXTI1_IRQHandler
+	.word	EXTI2_IRQHandler
+	.word	EXTI3_IRQHandler
+	.word	EXTI4_IRQHandler
+	.word	DMA1_Channel1_IRQHandler
+	.word	DMA1_Channel2_IRQHandler
+	.word	DMA1_Channel3_IRQHandler
+	.word	DMA1_Channel4_IRQHandler
+	.word	DMA1_Channel5_IRQHandler
+	.word	DMA1_Channel6_IRQHandler
+	.word	DMA1_Channel7_IRQHandler
+	.word	ADC1_2_IRQHandler
+	.word	USB_HP_CAN1_TX_IRQHandler
+	.word	USB_LP_CAN1_RX0_IRQHandler
+	.word	CAN1_RX1_IRQHandler
+	.word	CAN1_SCE_IRQHandler
+	.word	EXTI9_5_IRQHandler
+	.word	TIM1_BRK_IRQHandler
+	.word	TIM1_UP_IRQHandler
+	.word	TIM1_TRG_COM_IRQHandler
+	.word	TIM1_CC_IRQHandler
+	.word	TIM2_IRQHandler
+	.word	TIM3_IRQHandler
+	.word	0
+	.word	I2C1_EV_IRQHandler
+	.word	I2C1_ER_IRQHandler
+	.word	0
+	.word	0
+	.word	SPI1_IRQHandler
+	.word	0
+	.word	USART1_IRQHandler
+	.word	USART2_IRQHandler
+	.word	0
+	.word	EXTI15_10_IRQHandler
+	.word	RTCAlarm_IRQHandler
+	.word	USBWakeUp_IRQHandler	
+  .word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	BootRAM        /* @0x108. This is for boot in RAM mode for 
+                          STM32F10x Low Density devices.*/
+   
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+*
+*******************************************************************************/
+    
+  .weak	NMI_Handler
+	.thumb_set NMI_Handler,Default_Handler
+	
+  .weak	HardFault_Handler
+	.thumb_set HardFault_Handler,Default_Handler
+	
+  .weak	MemManage_Handler
+	.thumb_set MemManage_Handler,Default_Handler
+	
+  .weak	BusFault_Handler
+	.thumb_set BusFault_Handler,Default_Handler
+
+	.weak	UsageFault_Handler
+	.thumb_set UsageFault_Handler,Default_Handler
+
+	.weak	SVC_Handler
+	.thumb_set SVC_Handler,Default_Handler
+
+	.weak	DebugMon_Handler
+	.thumb_set DebugMon_Handler,Default_Handler
+
+	.weak	PendSV_Handler
+	.thumb_set PendSV_Handler,Default_Handler
+
+	.weak	SysTick_Handler
+	.thumb_set SysTick_Handler,Default_Handler
+
+	.weak	WWDG_IRQHandler
+	.thumb_set WWDG_IRQHandler,Default_Handler
+
+	.weak	PVD_IRQHandler
+	.thumb_set PVD_IRQHandler,Default_Handler
+
+	.weak	TAMPER_IRQHandler
+	.thumb_set TAMPER_IRQHandler,Default_Handler
+
+	.weak	RTC_IRQHandler
+	.thumb_set RTC_IRQHandler,Default_Handler
+
+	.weak	FLASH_IRQHandler
+	.thumb_set FLASH_IRQHandler,Default_Handler
+
+	.weak	RCC_IRQHandler
+	.thumb_set RCC_IRQHandler,Default_Handler
+
+	.weak	EXTI0_IRQHandler
+	.thumb_set EXTI0_IRQHandler,Default_Handler
+
+	.weak	EXTI1_IRQHandler
+	.thumb_set EXTI1_IRQHandler,Default_Handler
+
+	.weak	EXTI2_IRQHandler
+	.thumb_set EXTI2_IRQHandler,Default_Handler
+
+	.weak	EXTI3_IRQHandler
+	.thumb_set EXTI3_IRQHandler,Default_Handler
+
+	.weak	EXTI4_IRQHandler
+	.thumb_set EXTI4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel1_IRQHandler
+	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel2_IRQHandler
+	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel3_IRQHandler
+	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel4_IRQHandler
+	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel5_IRQHandler
+	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel6_IRQHandler
+	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel7_IRQHandler
+	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+	.weak	ADC1_2_IRQHandler
+	.thumb_set ADC1_2_IRQHandler,Default_Handler
+
+	.weak	USB_HP_CAN1_TX_IRQHandler
+	.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+	.weak	USB_LP_CAN1_RX0_IRQHandler
+	.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+	.weak	CAN1_RX1_IRQHandler
+	.thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+	.weak	CAN1_SCE_IRQHandler
+	.thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+	.weak	EXTI9_5_IRQHandler
+	.thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+	.weak	TIM1_BRK_IRQHandler
+	.thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM1_UP_IRQHandler
+	.thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+	.weak	TIM1_TRG_COM_IRQHandler
+	.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM1_CC_IRQHandler
+	.thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+	.weak	TIM2_IRQHandler
+	.thumb_set TIM2_IRQHandler,Default_Handler
+
+	.weak	TIM3_IRQHandler
+	.thumb_set TIM3_IRQHandler,Default_Handler
+
+	.weak	I2C1_EV_IRQHandler
+	.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+	.weak	I2C1_ER_IRQHandler
+	.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+	.weak	SPI1_IRQHandler
+	.thumb_set SPI1_IRQHandler,Default_Handler
+
+	.weak	USART1_IRQHandler
+	.thumb_set USART1_IRQHandler,Default_Handler
+
+	.weak	USART2_IRQHandler
+	.thumb_set USART2_IRQHandler,Default_Handler
+
+	.weak	EXTI15_10_IRQHandler
+	.thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+	.weak	RTCAlarm_IRQHandler
+	.thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+	.weak	USBWakeUp_IRQHandler
+	.thumb_set USBWakeUp_IRQHandler,Default_Handler  
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

stm32f1_01/stm32_flash.ld → stm32f1_01_systick/stm32_flash.ld


stm32f1_01/stm32f10x_conf.h → stm32f1_01_systick/stm32f10x_conf.h


stm32f1_01/stm32f10x_it.c → stm32f1_01_systick/stm32f10x_it.c


stm32f1_01/stm32f10x_it.h → stm32f1_01_systick/stm32f10x_it.h


stm32f1_01/system_stm32f10x.c → stm32f1_01_systick/system_stm32f10x.c


+ 31 - 0
stm32f1_02/Makefile

@@ -0,0 +1,31 @@
+CC      = arm-none-eabi-gcc
+LD      = arm-none-eabi-gcc -v
+CP      = arm-none-eabi-objcopy
+OD      = arm-none-eabi-objdump
+
+CFLAGS  =  -I./ -I./lib -I./inc -c -fno-common -O0 -g -mcpu=cortex-m3 -mthumb 
+LFLAGS  = -Tstm32_flash.ld -nostartfiles
+ODFLAGS = -S
+AR+= -rcs
+
+all: test
+
+clean: -rm build/main.lst build/startup_stm32f10x_ld.o build/main.o build/main.elf build/main.lst build/main.bin
+
+test: main.elf 
+	@ echo "...copying"
+	$(CP) -O binary build/main.elf build/main.bin
+	$(CP) -O ihex build/main.elf build/main.hex
+	$(OD) $(ODFLAGS) build/main.elf > build/main.lst
+
+main.elf: main.o startup.o stm32_flash.ld
+	@ echo "..linking"
+	$(LD) $(LFLAGS) -o build/main.elf build/main.o build/startup_stm32f10x_ld.o
+
+main.o: main.c
+	@ echo ".compiling"
+	$(CC) $(CFLAGS) main.c -o build/main.o
+
+startup.o: source/startup_stm32f10x_ld.s
+	@ echo ".compiling"
+	$(CC) $(CFLAGS) source/startup_stm32f10x_ld.s -o build/startup_stm32f10x_ld.o

+ 4 - 0
stm32f1_02/gdb.txt

@@ -0,0 +1,4 @@
+tar ext :4242
+load
+continue
+print SCNT

File diff suppressed because it is too large
+ 1818 - 0
stm32f1_02/inc/core_cm3.h


+ 118 - 0
stm32f1_02/inc/fonts.h

@@ -0,0 +1,118 @@
+/**
+  ******************************************************************************
+  * @file    fonts.h
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   Header for fonts.c
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FONTS_H
+#define __FONTS_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stdint.h>
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup Common
+  * @{
+  */
+
+/** @addtogroup FONTS
+  * @{
+  */ 
+
+/** @defgroup FONTS_Exported_Types
+  * @{
+  */ 
+typedef struct _tFont
+{    
+  const uint16_t *table;
+  uint16_t Width;
+  uint16_t Height;
+  
+} sFONT;
+
+extern sFONT Font16x24;
+extern sFONT Font12x12;
+extern sFONT Font8x12;
+extern sFONT Font8x8;
+
+/**
+  * @}
+  */ 
+
+/** @defgroup FONTS_Exported_Constants
+  * @{
+  */ 
+#define LINE(x) ((x) * (((sFONT *)LCD_GetFont())->Height))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup FONTS_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup FONTS_Exported_Functions
+  * @{
+  */ 
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+  
+#endif /* __FONTS_H */
+ 
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */      
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

+ 220 - 0
stm32f1_02/inc/misc.h

@@ -0,0 +1,220 @@
+/**
+  ******************************************************************************
+  * @file    misc.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the miscellaneous
+  *          firmware library functions (add-on to CMSIS functions).
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MISC_H
+#define __MISC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup MISC
+  * @{
+  */
+
+/** @defgroup MISC_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  NVIC Init Structure definition  
+  */
+
+typedef struct
+{
+  uint8_t NVIC_IRQChannel;                    /*!< Specifies the IRQ channel to be enabled or disabled.
+                                                   This parameter can be a value of @ref IRQn_Type 
+                                                   (For the complete STM32 Devices IRQ Channels list, please
+                                                    refer to stm32f10x.h file) */
+
+  uint8_t NVIC_IRQChannelPreemptionPriority;  /*!< Specifies the pre-emption priority for the IRQ channel
+                                                   specified in NVIC_IRQChannel. This parameter can be a value
+                                                   between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+  uint8_t NVIC_IRQChannelSubPriority;         /*!< Specifies the subpriority level for the IRQ channel specified
+                                                   in NVIC_IRQChannel. This parameter can be a value
+                                                   between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+  FunctionalState NVIC_IRQChannelCmd;         /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+                                                   will be enabled or disabled. 
+                                                   This parameter can be set either to ENABLE or DISABLE */   
+} NVIC_InitTypeDef;
+ 
+/**
+  * @}
+  */
+
+/** @defgroup NVIC_Priority_Table 
+  * @{
+  */
+
+/**
+@code  
+ The table below gives the allowed values of the pre-emption priority and subpriority according
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+  ============================================================================================================================
+    NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  | Description
+  ============================================================================================================================
+   NVIC_PriorityGroup_0  |                0                  |            0-15             |   0 bits for pre-emption priority
+                         |                                   |                             |   4 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------
+   NVIC_PriorityGroup_1  |                0-1                |            0-7              |   1 bits for pre-emption priority
+                         |                                   |                             |   3 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------    
+   NVIC_PriorityGroup_2  |                0-3                |            0-3              |   2 bits for pre-emption priority
+                         |                                   |                             |   2 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------    
+   NVIC_PriorityGroup_3  |                0-7                |            0-1              |   3 bits for pre-emption priority
+                         |                                   |                             |   1 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------    
+   NVIC_PriorityGroup_4  |                0-15               |            0                |   4 bits for pre-emption priority
+                         |                                   |                             |   0 bits for subpriority                       
+  ============================================================================================================================
+@endcode
+*/
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup Vector_Table_Base 
+  * @{
+  */
+
+#define NVIC_VectTab_RAM             ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH           ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
+                                  ((VECTTAB) == NVIC_VectTab_FLASH))
+/**
+  * @}
+  */
+
+/** @defgroup System_Low_Power 
+  * @{
+  */
+
+#define NVIC_LP_SEVONPEND            ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP            ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT          ((uint8_t)0x02)
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
+                        ((LP) == NVIC_LP_SLEEPDEEP) || \
+                        ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+  * @}
+  */
+
+/** @defgroup Preemption_Priority_Group 
+  * @{
+  */
+
+#define NVIC_PriorityGroup_0         ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
+                                                            4 bits for subpriority */
+#define NVIC_PriorityGroup_1         ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
+                                                            3 bits for subpriority */
+#define NVIC_PriorityGroup_2         ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
+                                                            2 bits for subpriority */
+#define NVIC_PriorityGroup_3         ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
+                                                            1 bits for subpriority */
+#define NVIC_PriorityGroup_4         ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
+                                                            0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
+                                       ((GROUP) == NVIC_PriorityGroup_1) || \
+                                       ((GROUP) == NVIC_PriorityGroup_2) || \
+                                       ((GROUP) == NVIC_PriorityGroup_3) || \
+                                       ((GROUP) == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET(OFFSET)  ((OFFSET) < 0x000FFFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup SysTick_clock_source 
+  * @{
+  */
+
+#define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
+                                       ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Exported_Functions
+  * @{
+  */
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MISC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

+ 277 - 0
stm32f1_02/inc/stm3210c_eval.h

@@ -0,0 +1,277 @@
+/**
+  ******************************************************************************
+  * @file    stm3210c_eval.h
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   This file contains definitions for STM3210C_EVAL's Leds, push-buttons
+  *          COM ports, SD Card on SPI and sEE on I2C hardware resources.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 210 STMicroelectronics</center></h2>
+  */ 
+  
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM3210C_EVAL_H
+#define __STM3210C_EVAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32_eval.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */
+    
+/** @addtogroup STM3210C_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM3210C_EVAL_LOW_LEVEL
+  * @{
+  */ 
+  
+/** @defgroup STM3210C_EVAL_LOW_LEVEL_Exported_Types
+  * @{
+  */
+/**
+  * @}
+  */ 
+
+/** @defgroup STM3210C_EVAL_LOW_LEVEL_Exported_Constants
+  * @{
+  */ 
+
+/** @addtogroup STM3210C_EVAL_LOW_LEVEL_LED
+  * @{
+  */
+#define LEDn                             4
+
+#define LED1_PIN                         GPIO_Pin_7
+#define LED1_GPIO_PORT                   GPIOD
+#define LED1_GPIO_CLK                    RCC_APB2Periph_GPIOD  
+  
+#define LED2_PIN                         GPIO_Pin_13
+#define LED2_GPIO_PORT                   GPIOD
+#define LED2_GPIO_CLK                    RCC_APB2Periph_GPIOD  
+
+#define LED3_PIN                         GPIO_Pin_3  
+#define LED3_GPIO_PORT                   GPIOD
+#define LED3_GPIO_CLK                    RCC_APB2Periph_GPIOD  
+
+#define LED4_PIN                         GPIO_Pin_4  
+#define LED4_GPIO_PORT                   GPIOD
+#define LED4_GPIO_CLK                    RCC_APB2Periph_GPIOD  
+
+
+/**
+  * @}
+  */ 
+  
+/** @addtogroup STM3210C_EVAL_LOW_LEVEL_BUTTON
+  * @{
+  */  
+#define BUTTONn                          3 /*!< Joystick pins are connected to 
+                                                an IO Expander (accessible through 
+                                                I2C1 interface) */
+
+/**
+ * @brief Wakeup push-button
+ */
+#define WAKEUP_BUTTON_PIN                GPIO_Pin_0
+#define WAKEUP_BUTTON_GPIO_PORT          GPIOA
+#define WAKEUP_BUTTON_GPIO_CLK           RCC_APB2Periph_GPIOA
+#define WAKEUP_BUTTON_EXTI_LINE          EXTI_Line0
+#define WAKEUP_BUTTON_EXTI_PORT_SOURCE   GPIO_PortSourceGPIOA
+#define WAKEUP_BUTTON_EXTI_PIN_SOURCE    GPIO_PinSource0
+#define WAKEUP_BUTTON_EXTI_IRQn          EXTI0_IRQn 
+
+/**
+ * @brief Tamper push-button
+ */
+#define TAMPER_BUTTON_PIN                GPIO_Pin_13
+#define TAMPER_BUTTON_GPIO_PORT          GPIOC
+#define TAMPER_BUTTON_GPIO_CLK           RCC_APB2Periph_GPIOC
+#define TAMPER_BUTTON_EXTI_LINE          EXTI_Line13
+#define TAMPER_BUTTON_EXTI_PORT_SOURCE   GPIO_PortSourceGPIOC
+#define TAMPER_BUTTON_EXTI_PIN_SOURCE    GPIO_PinSource13
+#define TAMPER_BUTTON_EXTI_IRQn          EXTI15_10_IRQn 
+
+/**
+ * @brief Key push-button
+ */
+#define KEY_BUTTON_PIN                   GPIO_Pin_9
+#define KEY_BUTTON_GPIO_PORT             GPIOB
+#define KEY_BUTTON_GPIO_CLK              RCC_APB2Periph_GPIOB
+#define KEY_BUTTON_EXTI_LINE             EXTI_Line9
+#define KEY_BUTTON_EXTI_PORT_SOURCE      GPIO_PortSourceGPIOB
+#define KEY_BUTTON_EXTI_PIN_SOURCE       GPIO_PinSource9
+#define KEY_BUTTON_EXTI_IRQn             EXTI9_5_IRQn
+/**
+  * @}
+  */ 
+
+/** @addtogroup STM3210C_EVAL_LOW_LEVEL_COM
+  * @{
+  */
+#define COMn                             1
+
+/**
+ * @brief Definition for COM port1, connected to USART2 (USART2 pins remapped on GPIOD)
+ */ 
+#define EVAL_COM1                        USART2
+#define EVAL_COM1_CLK                    RCC_APB1Periph_USART2
+#define EVAL_COM1_TX_PIN                 GPIO_Pin_5
+#define EVAL_COM1_TX_GPIO_PORT           GPIOD
+#define EVAL_COM1_TX_GPIO_CLK            RCC_APB2Periph_GPIOD
+#define EVAL_COM1_RX_PIN                 GPIO_Pin_6
+#define EVAL_COM1_RX_GPIO_PORT           GPIOD
+#define EVAL_COM1_RX_GPIO_CLK            RCC_APB2Periph_GPIOD
+#define EVAL_COM1_IRQn                   USART2_IRQn
+
+/**
+  * @}
+  */ 
+
+/** @addtogroup STM3210B_EVAL_SD_SPI
+  * @{
+  */
+/**
+  * @brief  SD SPI Interface pins
+  */
+#define SD_SPI                           SPI3
+#define SD_SPI_CLK                       RCC_APB1Periph_SPI3
+#define SD_SPI_SCK_PIN                   GPIO_Pin_10                 /* PC.10 */
+#define SD_SPI_SCK_GPIO_PORT             GPIOC                       /* GPIOC */
+#define SD_SPI_SCK_GPIO_CLK              RCC_APB2Periph_GPIOC
+#define SD_SPI_MISO_PIN                  GPIO_Pin_11                 /* PC.11 */
+#define SD_SPI_MISO_GPIO_PORT            GPIOC                       /* GPIOC */
+#define SD_SPI_MISO_GPIO_CLK             RCC_APB2Periph_GPIOC
+#define SD_SPI_MOSI_PIN                  GPIO_Pin_12                 /* PC.12 */
+#define SD_SPI_MOSI_GPIO_PORT            GPIOC                       /* GPIOC */
+#define SD_SPI_MOSI_GPIO_CLK             RCC_APB2Periph_GPIOC
+#define SD_CS_PIN                        GPIO_Pin_4                  /* PA.04 */
+#define SD_CS_GPIO_PORT                  GPIOA                       /* GPIOA */
+#define SD_CS_GPIO_CLK                   RCC_APB2Periph_GPIOA
+#define SD_DETECT_PIN                    GPIO_Pin_0                  /* PE.00 */
+#define SD_DETECT_GPIO_PORT              GPIOE                       /* GPIOE */
+#define SD_DETECT_GPIO_CLK               RCC_APB2Periph_GPIOE
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM3210C_EVAL_LOW_LEVEL_I2C_EE
+  * @{
+  */
+/**
+  * @brief  I2C EEPROM Interface pins
+  */  
+#define sEE_I2C                          I2C1
+#define sEE_I2C_CLK                      RCC_APB1Periph_I2C1
+#define sEE_I2C_SCL_PIN                  GPIO_Pin_6                  /* PB.06 */
+#define sEE_I2C_SCL_GPIO_PORT            GPIOB                       /* GPIOB */
+#define sEE_I2C_SCL_GPIO_CLK             RCC_APB2Periph_GPIOB
+#define sEE_I2C_SDA_PIN                  GPIO_Pin_7                  /* PB.07 */
+#define sEE_I2C_SDA_GPIO_PORT            GPIOB                       /* GPIOB */
+#define sEE_I2C_SDA_GPIO_CLK             RCC_APB2Periph_GPIOB
+#define sEE_M24C64_32
+
+#define sEE_I2C_DMA                      DMA1   
+#define sEE_I2C_DMA_CHANNEL_TX           DMA1_Channel6
+#define sEE_I2C_DMA_CHANNEL_RX           DMA1_Channel7 
+#define sEE_I2C_DMA_FLAG_TX_TC           DMA1_IT_TC6   
+#define sEE_I2C_DMA_FLAG_TX_GL           DMA1_IT_GL6 
+#define sEE_I2C_DMA_FLAG_RX_TC           DMA1_IT_TC7 
+#define sEE_I2C_DMA_FLAG_RX_GL           DMA1_IT_GL7    
+#define sEE_I2C_DMA_CLK                  RCC_AHBPeriph_DMA1
+#define sEE_I2C_DR_Address               ((uint32_t)0x40005410)
+#define sEE_USE_DMA
+   
+#define sEE_I2C_DMA_TX_IRQn              DMA1_Channel6_IRQn
+#define sEE_I2C_DMA_RX_IRQn              DMA1_Channel7_IRQn
+#define sEE_I2C_DMA_TX_IRQHandler        DMA1_Channel6_IRQHandler
+#define sEE_I2C_DMA_RX_IRQHandler        DMA1_Channel7_IRQHandler   
+#define sEE_I2C_DMA_PREPRIO              0
+#define sEE_I2C_DMA_SUBPRIO              0   
+   
+#define sEE_DIRECTION_TX                 0
+#define sEE_DIRECTION_RX                 1   
+
+/* Time constant for the delay caclulation allowing to have a millisecond 
+   incrementing counter. This value should be equal to (System Clock / 1000).
+   ie. if system clock = 72MHz then sEE_TIME_CONST should be 72. */
+#define sEE_TIME_CONST                   72 
+   
+/**
+  * @}
+  */
+   
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM3210C_EVAL_LOW_LEVEL_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210C_EVAL_LOW_LEVEL_Exported_Functions
+  * @{
+  */ 
+void STM_EVAL_LEDInit(Led_TypeDef Led);
+void STM_EVAL_LEDOn(Led_TypeDef Led);
+void STM_EVAL_LEDOff(Led_TypeDef Led);
+void STM_EVAL_LEDToggle(Led_TypeDef Led);
+void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
+uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
+void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct); 
+void SD_LowLevel_DeInit(void);
+void SD_LowLevel_Init(void); 
+void sEE_LowLevel_DeInit(void);
+void sEE_LowLevel_Init(void); 
+void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction);
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM3210C_EVAL_H */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+    
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

+ 537 - 0
stm32f1_02/inc/stm3210c_eval_ioe.h

@@ -0,0 +1,537 @@
+/**
+  ******************************************************************************
+  * @file    stm3210c_eval_ioe.h
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   This file contains all the functions prototypes for the IO Expander
+  *   firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+
+  /* File Info : ---------------------------------------------------------------
+    SUPPORTED FEATURES:
+      - IO Read/write : Set/Reset and Read (Polling/Interrupt)
+      - Joystick: config and Read (Polling/Interrupt)
+      - Touch Screen Features: Single point mode (Polling/Interrupt)
+      - TempSensor Feature: accuracy not determined (Polling).
+
+    UNSUPPORTED FEATURES:
+      - Row ADC Feature is not supported (not implemented on STM3210C-EVAL board)
+  ----------------------------------------------------------------------------*/
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM3210C_EVAL_IOE_H
+#define __STM3210C_EVAL_IOE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif   
+   
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM3210C_EVAL
+  * @{
+  */
+    
+/** @defgroup STM3210C_EVAL_IOE 
+  * @{
+  */ 
+
+/** @defgroup STM3210C_EVAL_IOE_Exported_Types
+  * @{
+  */ 
+
+/** 
+  * @brief  Touch Screen Information structure  
+  */ 
+typedef struct
+{
+  uint16_t TouchDetected;
+  uint16_t X;
+  uint16_t Y;
+  uint16_t Z;
+}TS_STATE; 
+  
+/** 
+  * @brief  Joystick State definitions  
+  */ 
+#ifndef __STM32_EVAL_H
+typedef enum 
+{ 
+  JOY_NONE = 0,
+  JOY_SEL = 1,
+  JOY_DOWN = 2,
+  JOY_LEFT = 3,
+  JOY_RIGHT = 4,
+  JOY_UP = 5
+} JOYState_TypeDef
+;
+#endif /* __STM32_EVAL_H */
+ 
+/** 
+  * @brief  IO_Expander Error codes  
+  */ 
+typedef enum
+{
+  IOE_OK = 0,
+  IOE_FAILURE, 
+  IOE_TIMEOUT,
+  PARAM_ERROR,
+  IOE1_NOT_OPERATIONAL, 
+  IOE2_NOT_OPERATIONAL
+}IOE_Status_TypDef;
+
+/** 
+  * @brief  IO bit values  
+  */ 
+typedef enum
+{
+  BitReset = 0,
+  BitSet = 1
+}IOE_BitValue_TypeDef;
+
+/** 
+  * @brief  IOE DMA Direction  
+  */ 
+typedef enum
+{
+  IOE_DMA_TX = 0,
+  IOE_DMA_RX = 1
+}IOE_DMADirection_TypeDef;
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210C_EVAL_IOE_Exported_Constants
+  * @{
+  */ 
+
+/**
+ * @brief Uncomment the line below to enable verfying each written byte in write
+ *        operation. The I2C_WriteDeviceRegister() function will then compare the
+ *        written and read data and return error status if a mismatch occurs.
+ */
+/* #define VERIFY_WRITTENDATA */
+
+/**
+ * @brief Uncomment the line below if you want to use user defined Delay function
+ *        (for precise timing), otherwise default _delay_ function defined within
+ *         this driver is used (less precise timing).  
+ */
+/* #define USE_Delay */
+
+/**
+ * @brief Uncomment the line below if you want to use user timeout callback.
+ *        Function prototypes is declared in this file but function body may be
+ *        implemented into user application.  
+ */
+/* #define USE_TIMEOUT_USER_CALLBACK */
+
+#ifdef USE_Delay
+#include "main.h"
+ 
+  #define _delay_     Delay  /* !< User can provide more timing precise _delay_ function
+                                   (with 10ms time base), using SysTick for example */
+#else
+  #define _delay_     delay      /* !< Default _delay_ function with less precise timing */
+#endif    
+
+/*------------------------------------------------------------------------------
+    Hardware Configuration 
+------------------------------------------------------------------------------*/
+/** 
+  * @brief  I2C port definitions  
+  */
+#define IOE_I2C                          I2C1
+#define IOE_I2C_CLK                      RCC_APB1Periph_I2C1
+#define IOE_I2C_SCL_PIN                  GPIO_Pin_6
+#define IOE_I2C_SCL_GPIO_PORT            GPIOB
+#define IOE_I2C_SCL_GPIO_CLK             RCC_APB2Periph_GPIOB
+#define IOE_I2C_SDA_PIN                  GPIO_Pin_7
+#define IOE_I2C_SDA_GPIO_PORT            GPIOB
+#define IOE_I2C_SDA_GPIO_CLK             RCC_APB2Periph_GPIOB
+#define IOE_I2C_DR                       ((uint32_t)0x40005410)
+#define IOE_I2C_SPEED                    300000  
+
+/** 
+  * @brief  IOE DMA definitions  
+  */
+#define IOE_DMA                          DMA1
+#define IOE_DMA_CLK                      RCC_AHBPeriph_DMA1
+#define IOE_DMA_TX_CHANNEL               DMA1_Channel6
+#define IOE_DMA_RX_CHANNEL               DMA1_Channel7
+#define IOE_DMA_TX_TCFLAG                DMA1_FLAG_TC6
+#define IOE_DMA_RX_TCFLAG                DMA1_FLAG_TC7
+
+
+/** 
+  * @brief  IO Expander Interrupt line on EXTI  
+  */ 
+#define IOE_IT_PIN                       GPIO_Pin_14
+#define IOE_IT_GPIO_PORT                 GPIOB
+#define IOE_IT_GPIO_CLK                  RCC_APB2Periph_GPIOB
+#define IOE_IT_EXTI_PORT_SOURCE          GPIO_PortSourceGPIOB
+#define IOE_IT_EXTI_PIN_SOURCE           GPIO_PinSource14
+#define IOE_IT_EXTI_LINE                 EXTI_Line14
+#define IOE_IT_EXTI_IRQn                 EXTI15_10_IRQn       
+
+/**
+  * @brief Eval Board IO Pins definition 
+  */ 
+#define AUDIO_RESET_PIN             IO_Pin_2 /* IO_Exapnader_2 */ /* Output */
+#define MII_INT_PIN                 IO_Pin_0 /* IO_Exapnader_2 */ /* Output */
+#define VBAT_DIV_PIN                IO_Pin_0 /* IO_Exapnader_1 */ /* Output */
+#define MEMS_INT1_PIN               IO_Pin_3 /* IO_Exapnader_1 */ /* Input */
+#define MEMS_INT2_PIN               IO_Pin_2 /* IO_Exapnader_1 */ /* Input */
+
+ 
+/**
+  * @brief Eval Board both IO Exapanders Pins definition 
+  */ 
+#define IO1_IN_ALL_PINS          (uint32_t)(MEMS_INT1_PIN | MEMS_INT2_PIN)
+#define IO2_IN_ALL_PINS          (uint32_t)(JOY_IO_PINS)
+#define IO1_OUT_ALL_PINS         (uint32_t)(VBAT_DIV_PIN)
+#define IO2_OUT_ALL_PINS         (uint32_t)(AUDIO_RESET_PIN | MII_INT_PIN)
+
+/** 
+  * @brief  The 7 bits IO Expanders adresses and chip IDs  
+  */ 
+#define IOE_1_ADDR                 0x82    
+#define IOE_2_ADDR                 0x88    
+#define STMPE811_ID                0x0811
+
+
+/*------------------------------------------------------------------------------
+    Functional and Interrupt Management
+------------------------------------------------------------------------------*/
+/** 
+  * @brief  IO Expander Functionalities definitions  
+  */ 
+#define IOE_ADC_FCT              0x01
+#define IOE_TS_FCT               0x02
+#define IOE_IO_FCT               0x04
+#define IOE_TEMPSENS_FCT         0x08
+
+/** 
+  * @brief  Interrupt source configuration definitons  
+  */ 
+#define IOE_ITSRC_TSC           0x01  /* IO_Exapnder 1 */
+#define IOE_ITSRC_INMEMS        0x02  /* IO_Exapnder 1 */
+#define IOE_ITSRC_JOYSTICK      0x04  /* IO_Exapnder 2 */
+#define IOE_ITSRC_TEMPSENS      0x08  /* IO_Exapnder 2 */
+
+/** 
+  * @brief  Glaobal Interrupts definitions  
+  */ 
+#define IOE_GIT_GPIO             0x80
+#define IOE_GIT_ADC              0x40
+#define IOE_GIT_TEMP             0x20
+#define IOE_GIT_FE               0x10
+#define IOE_GIT_FF               0x08
+#define IOE_GIT_FOV              0x04
+#define IOE_GIT_FTH              0x02
+#define IOE_GIT_TOUCH            0x01
+
+
+/*------------------------------------------------------------------------------
+    STMPE811 device register definition
+------------------------------------------------------------------------------*/
+/** 
+  * @brief  Identification registers  
+  */ 
+#define IOE_REG_CHP_ID             0x00
+#define IOE_REG_ID_VER             0x02
+
+/** 
+  * @brief  General Control Registers  
+  */ 
+#define IOE_REG_SYS_CTRL1          0x03
+#define IOE_REG_SYS_CTRL2          0x04
+#define IOE_REG_SPI_CFG            0x08 
+
+/** 
+  * @brief  Interrupt Control register  
+  */ 
+#define IOE_REG_INT_CTRL           0x09
+#define IOE_REG_INT_EN             0x0A
+#define IOE_REG_INT_STA            0x0B
+#define IOE_REG_GPIO_INT_EN        0x0C
+#define IOE_REG_GPIO_INT_STA       0x0D
+
+/** 
+  * @brief  GPIO Registers  
+  */ 
+#define IOE_REG_GPIO_SET_PIN       0x10
+#define IOE_REG_GPIO_CLR_PIN       0x11
+#define IOE_REG_GPIO_MP_STA        0x12
+#define IOE_REG_GPIO_DIR           0x13
+#define IOE_REG_GPIO_ED            0x14
+#define IOE_REG_GPIO_RE            0x15
+#define IOE_REG_GPIO_FE            0x16
+#define IOE_REG_GPIO_AF            0x17
+
+/** 
+  * @brief  ADC Registers  
+  */ 
+#define IOE_REG_ADC_INT_EN         0x0E
+#define IOE_REG_ADC_INT_STA        0x0F
+#define IOE_REG_ADC_CTRL1          0x20
+#define IOE_REG_ADC_CTRL2          0x21
+#define IOE_REG_ADC_CAPT           0x22
+#define IOE_REG_ADC_DATA_CH0       0x30 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH1       0x32 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH2       0x34 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH3       0x36 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH4       0x38 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH5       0x3A /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH6       0x3B /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH7       0x3C /* 16-Bit register */ 
+
+/** 
+  * @brief  TouchScreen Registers  
+  */ 
+#define IOE_REG_TSC_CTRL           0x40
+#define IOE_REG_TSC_CFG            0x41
+#define IOE_REG_WDM_TR_X           0x42 
+#define IOE_REG_WDM_TR_Y           0x44
+#define IOE_REG_WDM_BL_X           0x46
+#define IOE_REG_WDM_BL_Y           0x48
+#define IOE_REG_FIFO_TH            0x4A
+#define IOE_REG_FIFO_STA           0x4B
+#define IOE_REG_FIFO_SIZE          0x4C
+#define IOE_REG_TSC_DATA_X         0x4D 
+#define IOE_REG_TSC_DATA_Y         0x4F
+#define IOE_REG_TSC_DATA_Z         0x51
+#define IOE_REG_TSC_DATA_XYZ       0x52 
+#define IOE_REG_TSC_FRACT_XYZ      0x56
+#define IOE_REG_TSC_DATA           0x57
+#define IOE_REG_TSC_I_DRIVE        0x58
+#define IOE_REG_TSC_SHIELD         0x59
+
+/** 
+  * @brief  Temperature Sensor registers  
+  */ 
+#define IOE_REG_TEMP_CTRL          0x60
+#define IOE_REG_TEMP_DATA          0x61
+#define IOE_REG_TEMP_TH            0x62
+
+
+/*------------------------------------------------------------------------------
+    Functions parameters defines
+------------------------------------------------------------------------------*/
+/**
+  * @brief Touch Screen Pins definition 
+  */ 
+#define TOUCH_YD                    IO_Pin_1 /* IO_Exapnader_1 */ /* Input */
+#define TOUCH_XD                    IO_Pin_2 /* IO_Exapnader_1 */ /* Input */
+#define TOUCH_YU                    IO_Pin_3 /* IO_Exapnader_1 */ /* Input */
+#define TOUCH_XU                    IO_Pin_4 /* IO_Exapnader_1 */ /* Input */
+#define TOUCH_IO_ALL                (uint32_t)(IO_Pin_1 | IO_Pin_2 | IO_Pin_3 | IO_Pin_4)
+
+/**
+  * @brief  JOYSTICK Pins definition 
+  */ 
+#define JOY_IO_SEL                   IO_Pin_7
+#define JOY_IO_DOWN                  IO_Pin_6
+#define JOY_IO_LEFT                  IO_Pin_5
+#define JOY_IO_RIGHT                 IO_Pin_4
+#define JOY_IO_UP                    IO_Pin_3
+#define JOY_IO_NONE                  JOY_IO_PINS
+#define JOY_IO_PINS                  (uint32_t)(IO_Pin_3 | IO_Pin_4 | IO_Pin_5 | IO_Pin_6 | IO_Pin_7)
+
+/** 
+  * @brief  IO Pins  
+  */ 
+#define IO_Pin_0                 0x01