Alexander M Gladtsin лет назад: 8
Родитель
Сommit
1e988f95a4
100 измененных файлов с 16480 добавлено и 419 удалено
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      stm32f1_01/build/main.o
  2. 0 120
      stm32f1_01/main.c
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      stm32f1_01/source/startup_stm32f10x_ld.s
  4. 2 2
      stm32f1_01/Makefile
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      stm32f1_01_systick/inc/misc.h
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      stm32f1_01_systick/inc/stm32f10x_crc.h
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      stm32f1_01_systick/inc/stm32f10x_dbgmcu.h
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      stm32f1_01_systick/inc/stm32f10x_gpio.h
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      stm32f1_01_systick/lib/core_cm3.c
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      stm32f1_01_systick/lib/misc.c
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      stm32f1_01_systick/lib/stm32f10x_dbgmcu.c
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      stm32f1_01_systick/lib/stm32f10x_dma.c
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      stm32f1_01_systick/lib/stm32f10x_exti.c
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      stm32f1_01_systick/lib/stm32f10x_flash.c
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      stm32f1_01_systick/lib/stm32f10x_fsmc.c
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      stm32f1_01_systick/lib/stm32f10x_gpio.c
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      stm32f1_01_systick/lib/stm32f10x_pwr.c
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      stm32f1_01_systick/main.c
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      stm32f1_01/main.h
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      stm32f1_01_systick/readme.txt
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      stm32f1_01_systick/source/startup_stm32f10x_ld.s
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      stm32f1_01_systick/stm32f10x_conf.h
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      stm32f1_01_systick/system_stm32f10x.c
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      stm32f1_02/Makefile
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      stm32f1_02/gdb.txt
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      stm32f1_02/inc/core_cm3.h
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      stm32f1_02/inc/fonts.h
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      stm32f1_02/inc/misc.h
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      stm32f1_02/inc/stm3210c_eval.h
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      stm32f1_02/inc/stm3210c_eval_ioe.h
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      stm32f1_02/inc/stm3210c_eval_lcd.h
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      stm32f1_02/inc/stm32_eval.h
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      stm32f1_02/inc/stm32_eval_i2c_ee.h
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      stm32f1_02/inc/stm32_eval_i2c_tsensor.h
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      stm32f1_02/inc/stm32_eval_sdio_sd.h
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      stm32f1_02/inc/stm32_eval_spi_flash.h
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      stm32f1_02/inc/stm32_eval_spi_sd.h
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      stm32f1_02/inc/stm32f10x.h
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      stm32f1_02/inc/stm32f10x_adc.h
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      stm32f1_02/inc/stm32f10x_can.h
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      stm32f1_02/inc/stm32f10x_cec.h
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      stm32f1_02/inc/stm32f10x_dac.h
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      stm32f1_02/inc/stm32f10x_dbgmcu.h

BIN
stm32f1_01/build/main.o


+ 0 - 120
stm32f1_01/main.c

@@ -1,120 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SysTick/TimeBase/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "main.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup SysTick_TimeBase
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-static __IO uint32_t TimingDelay;
-
-/* Private function prototypes -----------------------------------------------*/
-void Delay(__IO uint32_t nTime);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  if (SysTick_Config(SystemCoreClock / 1000))
-  { 
-    /* Capture error */ 
-    while (1);
-  }
-
-  while (1)
-  {
-    /* Insert 50 ms delay */
-    Delay(50);
-    Delay(100);
-  }
-}
-
-/**
-  * @brief  Inserts a delay time.
-  * @param  nTime: specifies the delay time length, in milliseconds.
-  * @retval None
-  */
-void Delay(__IO uint32_t nTime)
-{ 
-  TimingDelay = nTime;
-
-  while(TimingDelay != 0);
-}
-
-/**
-  * @brief  Decrements the TimingDelay variable.
-  * @param  None
-  * @retval None
-  */
-void TimingDelay_Decrement(void)
-{
-  if (TimingDelay != 0x00)
-  { 
-    TimingDelay--;
-  }
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

+ 0 - 297
stm32f1_01/source/startup_stm32f10x_ld.s

@@ -1,297 +0,0 @@
-;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
-;* File Name          : startup_stm32f10x_ld.s
-;* Author             : MCD Application Team
-;* Version            : V3.5.0
-;* Date               : 11-March-2011
-;* Description        : STM32F10x Low Density Devices vector table for MDK-ARM 
-;*                      toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the CortexM3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>   
-;*******************************************************************************
-; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler            ; Window Watchdog
-                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler          ; Tamper
-                DCD     RTC_IRQHandler             ; RTC
-                DCD     FLASH_IRQHandler           ; Flash
-                DCD     RCC_IRQHandler             ; RCC
-                DCD     EXTI0_IRQHandler           ; EXTI Line 0
-                DCD     EXTI1_IRQHandler           ; EXTI Line 1
-                DCD     EXTI2_IRQHandler           ; EXTI Line 2
-                DCD     EXTI3_IRQHandler           ; EXTI Line 3
-                DCD     EXTI4_IRQHandler           ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
-                DCD     ADC1_2_IRQHandler          ; ADC1_2
-                DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
-                DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
-                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
-                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
-                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
-                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
-                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
-                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
-                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler            ; TIM2
-                DCD     TIM3_IRQHandler            ; TIM3
-                DCD     0                          ; Reserved
-                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SPI1_IRQHandler            ; SPI1
-                DCD     0                          ; Reserved
-                DCD     USART1_IRQHandler          ; USART1
-                DCD     USART2_IRQHandler          ; USART2
-                DCD     0                          ; Reserved
-                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
-                DCD     RTCAlarm_IRQHandler        ; RTC Alarm through EXTI Line
-                DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-     IMPORT  __main
-     IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_IRQHandler          [WEAK]
-                EXPORT  RTC_IRQHandler             [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_2_IRQHandler          [WEAK]
-                EXPORT  USB_HP_CAN1_TX_IRQHandler  [WEAK]
-                EXPORT  USB_LP_CAN1_RX0_IRQHandler [WEAK]
-                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
-                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
-                EXPORT  TIM1_UP_IRQHandler         [WEAK]
-                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
-                EXPORT  TIM1_CC_IRQHandler         [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTCAlarm_IRQHandler        [WEAK]
-                EXPORT  USBWakeUp_IRQHandler       [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_IRQHandler
-TIM1_UP_IRQHandler
-TIM1_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-SPI1_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-EXTI15_10_IRQHandler
-RTCAlarm_IRQHandler
-USBWakeUp_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****

+ 2 - 2
stm32f1_01/Makefile

@@ -4,7 +4,7 @@ CP      = arm-none-eabi-objcopy
 OD      = arm-none-eabi-objdump
 OD      = arm-none-eabi-objdump
 
 
 CFLAGS  =  -I./ -I./lib -I./inc -c -fno-common -O0 -g -mcpu=cortex-m3 -mthumb 
 CFLAGS  =  -I./ -I./lib -I./inc -c -fno-common -O0 -g -mcpu=cortex-m3 -mthumb 
-LFLAGS  = -Tstm32f10.ld -nostartfiles
+LFLAGS  = -Tstm32_flash.ld -nostartfiles
 ODFLAGS = -S
 ODFLAGS = -S
 AR+= -rcs
 AR+= -rcs
 
 
@@ -26,6 +26,6 @@ main.o: main.c
 	@ echo ".compiling"
 	@ echo ".compiling"
 	$(CC) $(CFLAGS) main.c -o build/main.o
 	$(CC) $(CFLAGS) main.c -o build/main.o
 
 
-startup.o: source/startup_stm32f10x.s
+startup.o: source/startup_stm32f10x_ld.s
 	@ echo ".compiling"
 	@ echo ".compiling"
 	$(CC) $(CFLAGS) source/startup_stm32f10x_ld.s -o build/startup_stm32f10x_ld.o
 	$(CC) $(CFLAGS) source/startup_stm32f10x_ld.s -o build/startup_stm32f10x_ld.o

BIN
stm32f1_01_systick/build/main.bin


BIN
stm32f1_01_systick/build/main.elf


+ 79 - 0
stm32f1_01_systick/build/main.hex

@@ -0,0 +1,79 @@
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+ 747 - 0
stm32f1_01_systick/build/main.lst

@@ -0,0 +1,747 @@
+
+build/main.elf:     file format elf32-littlearm
+
+
+Disassembly of section .text:
+
+0800010c <NVIC_SetPriority>:
+ * interrupt, or negative to specify an internal (core) interrupt.
+ *
+ * Note: The priority cannot be set for every core interrupt.
+ */
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ 800010c:	b480      	push	{r7}
+ 800010e:	b083      	sub	sp, #12
+ 8000110:	af00      	add	r7, sp, #0
+ 8000112:	4603      	mov	r3, r0
+ 8000114:	6039      	str	r1, [r7, #0]
+ 8000116:	71fb      	strb	r3, [r7, #7]
+  if(IRQn < 0) {
+ 8000118:	f997 3007 	ldrsb.w	r3, [r7, #7]
+ 800011c:	2b00      	cmp	r3, #0
+ 800011e:	da0b      	bge.n	8000138 <NVIC_SetPriority+0x2c>
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
+ 8000120:	490d      	ldr	r1, [pc, #52]	; (8000158 <NVIC_SetPriority+0x4c>)
+ 8000122:	79fb      	ldrb	r3, [r7, #7]
+ 8000124:	f003 030f 	and.w	r3, r3, #15
+ 8000128:	3b04      	subs	r3, #4
+ 800012a:	683a      	ldr	r2, [r7, #0]
+ 800012c:	b2d2      	uxtb	r2, r2
+ 800012e:	0112      	lsls	r2, r2, #4
+ 8000130:	b2d2      	uxtb	r2, r2
+ 8000132:	440b      	add	r3, r1
+ 8000134:	761a      	strb	r2, [r3, #24]
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+ 8000136:	e009      	b.n	800014c <NVIC_SetPriority+0x40>
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+ 8000138:	4908      	ldr	r1, [pc, #32]	; (800015c <NVIC_SetPriority+0x50>)
+ 800013a:	f997 3007 	ldrsb.w	r3, [r7, #7]
+ 800013e:	683a      	ldr	r2, [r7, #0]
+ 8000140:	b2d2      	uxtb	r2, r2
+ 8000142:	0112      	lsls	r2, r2, #4
+ 8000144:	b2d2      	uxtb	r2, r2
+ 8000146:	440b      	add	r3, r1
+ 8000148:	f883 2300 	strb.w	r2, [r3, #768]	; 0x300
+}
+ 800014c:	bf00      	nop
+ 800014e:	370c      	adds	r7, #12
+ 8000150:	46bd      	mov	sp, r7
+ 8000152:	bc80      	pop	{r7}
+ 8000154:	4770      	bx	lr
+ 8000156:	bf00      	nop
+ 8000158:	e000ed00 	.word	0xe000ed00
+ 800015c:	e000e100 	.word	0xe000e100
+
+08000160 <SysTick_Config>:
+ * Initialise the system tick timer and its interrupt and start the
+ * system tick timer / counter in free running mode to generate 
+ * periodical interrupts.
+ */
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+{ 
+ 8000160:	b580      	push	{r7, lr}
+ 8000162:	b082      	sub	sp, #8
+ 8000164:	af00      	add	r7, sp, #0
+ 8000166:	6078      	str	r0, [r7, #4]
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+ 8000168:	687b      	ldr	r3, [r7, #4]
+ 800016a:	f1b3 7f80 	cmp.w	r3, #16777216	; 0x1000000
+ 800016e:	d301      	bcc.n	8000174 <SysTick_Config+0x14>
+ 8000170:	2301      	movs	r3, #1
+ 8000172:	e011      	b.n	8000198 <SysTick_Config+0x38>
+                                                               
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+ 8000174:	4a0a      	ldr	r2, [pc, #40]	; (80001a0 <SysTick_Config+0x40>)
+ 8000176:	687b      	ldr	r3, [r7, #4]
+ 8000178:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
+ 800017c:	3b01      	subs	r3, #1
+ 800017e:	6053      	str	r3, [r2, #4]
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
+ 8000180:	210f      	movs	r1, #15
+ 8000182:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
+ 8000186:	f7ff ffc1 	bl	800010c <NVIC_SetPriority>
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+ 800018a:	4b05      	ldr	r3, [pc, #20]	; (80001a0 <SysTick_Config+0x40>)
+ 800018c:	2200      	movs	r2, #0
+ 800018e:	609a      	str	r2, [r3, #8]
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk | 
+ 8000190:	4b03      	ldr	r3, [pc, #12]	; (80001a0 <SysTick_Config+0x40>)
+ 8000192:	2207      	movs	r2, #7
+ 8000194:	601a      	str	r2, [r3, #0]
+                   SysTick_CTRL_TICKINT_Msk   | 
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+ 8000196:	2300      	movs	r3, #0
+}
+ 8000198:	4618      	mov	r0, r3
+ 800019a:	3708      	adds	r7, #8
+ 800019c:	46bd      	mov	sp, r7
+ 800019e:	bd80      	pop	{r7, pc}
+ 80001a0:	e000e010 	.word	0xe000e010
+
+080001a4 <SystemInit>:
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+ 80001a4:	b580      	push	{r7, lr}
+ 80001a6:	af00      	add	r7, sp, #0
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+ 80001a8:	4a15      	ldr	r2, [pc, #84]	; (8000200 <SystemInit+0x5c>)
+ 80001aa:	4b15      	ldr	r3, [pc, #84]	; (8000200 <SystemInit+0x5c>)
+ 80001ac:	681b      	ldr	r3, [r3, #0]
+ 80001ae:	f043 0301 	orr.w	r3, r3, #1
+ 80001b2:	6013      	str	r3, [r2, #0]
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+ 80001b4:	4912      	ldr	r1, [pc, #72]	; (8000200 <SystemInit+0x5c>)
+ 80001b6:	4b12      	ldr	r3, [pc, #72]	; (8000200 <SystemInit+0x5c>)
+ 80001b8:	685a      	ldr	r2, [r3, #4]
+ 80001ba:	4b12      	ldr	r3, [pc, #72]	; (8000204 <SystemInit+0x60>)
+ 80001bc:	4013      	ands	r3, r2
+ 80001be:	604b      	str	r3, [r1, #4]
+#else
+  RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */   
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+ 80001c0:	4a0f      	ldr	r2, [pc, #60]	; (8000200 <SystemInit+0x5c>)
+ 80001c2:	4b0f      	ldr	r3, [pc, #60]	; (8000200 <SystemInit+0x5c>)
+ 80001c4:	681b      	ldr	r3, [r3, #0]
+ 80001c6:	f023 7384 	bic.w	r3, r3, #17301504	; 0x1080000
+ 80001ca:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
+ 80001ce:	6013      	str	r3, [r2, #0]
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+ 80001d0:	4a0b      	ldr	r2, [pc, #44]	; (8000200 <SystemInit+0x5c>)
+ 80001d2:	4b0b      	ldr	r3, [pc, #44]	; (8000200 <SystemInit+0x5c>)
+ 80001d4:	681b      	ldr	r3, [r3, #0]
+ 80001d6:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
+ 80001da:	6013      	str	r3, [r2, #0]
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+ 80001dc:	4a08      	ldr	r2, [pc, #32]	; (8000200 <SystemInit+0x5c>)
+ 80001de:	4b08      	ldr	r3, [pc, #32]	; (8000200 <SystemInit+0x5c>)
+ 80001e0:	685b      	ldr	r3, [r3, #4]
+ 80001e2:	f423 03fe 	bic.w	r3, r3, #8323072	; 0x7f0000
+ 80001e6:	6053      	str	r3, [r2, #4]
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+ 80001e8:	4b05      	ldr	r3, [pc, #20]	; (8000200 <SystemInit+0x5c>)
+ 80001ea:	f44f 021f 	mov.w	r2, #10420224	; 0x9f0000
+ 80001ee:	609a      	str	r2, [r3, #8]
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
+ 80001f0:	f000 f878 	bl	80002e4 <SetSysClock>
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+ 80001f4:	4b04      	ldr	r3, [pc, #16]	; (8000208 <SystemInit+0x64>)
+ 80001f6:	f04f 6200 	mov.w	r2, #134217728	; 0x8000000
+ 80001fa:	609a      	str	r2, [r3, #8]
+#endif 
+}
+ 80001fc:	bf00      	nop
+ 80001fe:	bd80      	pop	{r7, pc}
+ 8000200:	40021000 	.word	0x40021000
+ 8000204:	f8ff0000 	.word	0xf8ff0000
+ 8000208:	e000ed00 	.word	0xe000ed00
+
+0800020c <SystemCoreClockUpdate>:
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+ 800020c:	b480      	push	{r7}
+ 800020e:	b085      	sub	sp, #20
+ 8000210:	af00      	add	r7, sp, #0
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+ 8000212:	2300      	movs	r3, #0
+ 8000214:	60fb      	str	r3, [r7, #12]
+ 8000216:	2300      	movs	r3, #0
+ 8000218:	60bb      	str	r3, [r7, #8]
+ 800021a:	2300      	movs	r3, #0
+ 800021c:	607b      	str	r3, [r7, #4]
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+ 800021e:	4b2c      	ldr	r3, [pc, #176]	; (80002d0 <SystemCoreClockUpdate+0xc4>)
+ 8000220:	685b      	ldr	r3, [r3, #4]
+ 8000222:	f003 030c 	and.w	r3, r3, #12
+ 8000226:	60fb      	str	r3, [r7, #12]
+  
+  switch (tmp)
+ 8000228:	68fb      	ldr	r3, [r7, #12]
+ 800022a:	2b04      	cmp	r3, #4
+ 800022c:	d007      	beq.n	800023e <SystemCoreClockUpdate+0x32>
+ 800022e:	2b08      	cmp	r3, #8
+ 8000230:	d009      	beq.n	8000246 <SystemCoreClockUpdate+0x3a>
+ 8000232:	2b00      	cmp	r3, #0
+ 8000234:	d133      	bne.n	800029e <SystemCoreClockUpdate+0x92>
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+ 8000236:	4b27      	ldr	r3, [pc, #156]	; (80002d4 <SystemCoreClockUpdate+0xc8>)
+ 8000238:	4a27      	ldr	r2, [pc, #156]	; (80002d8 <SystemCoreClockUpdate+0xcc>)
+ 800023a:	601a      	str	r2, [r3, #0]
+      break;
+ 800023c:	e033      	b.n	80002a6 <SystemCoreClockUpdate+0x9a>
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+ 800023e:	4b25      	ldr	r3, [pc, #148]	; (80002d4 <SystemCoreClockUpdate+0xc8>)
+ 8000240:	4a25      	ldr	r2, [pc, #148]	; (80002d8 <SystemCoreClockUpdate+0xcc>)
+ 8000242:	601a      	str	r2, [r3, #0]
+      break;
+ 8000244:	e02f      	b.n	80002a6 <SystemCoreClockUpdate+0x9a>
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+ 8000246:	4b22      	ldr	r3, [pc, #136]	; (80002d0 <SystemCoreClockUpdate+0xc4>)
+ 8000248:	685b      	ldr	r3, [r3, #4]
+ 800024a:	f403 1370 	and.w	r3, r3, #3932160	; 0x3c0000
+ 800024e:	60bb      	str	r3, [r7, #8]
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+ 8000250:	4b1f      	ldr	r3, [pc, #124]	; (80002d0 <SystemCoreClockUpdate+0xc4>)
+ 8000252:	685b      	ldr	r3, [r3, #4]
+ 8000254:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
+ 8000258:	607b      	str	r3, [r7, #4]
+      
+#ifndef STM32F10X_CL      
+      pllmull = ( pllmull >> 18) + 2;
+ 800025a:	68bb      	ldr	r3, [r7, #8]
+ 800025c:	0c9b      	lsrs	r3, r3, #18
+ 800025e:	3302      	adds	r3, #2
+ 8000260:	60bb      	str	r3, [r7, #8]
+      
+      if (pllsource == 0x00)
+ 8000262:	687b      	ldr	r3, [r7, #4]
+ 8000264:	2b00      	cmp	r3, #0
+ 8000266:	d106      	bne.n	8000276 <SystemCoreClockUpdate+0x6a>
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ 8000268:	68bb      	ldr	r3, [r7, #8]
+ 800026a:	4a1c      	ldr	r2, [pc, #112]	; (80002dc <SystemCoreClockUpdate+0xd0>)
+ 800026c:	fb02 f303 	mul.w	r3, r2, r3
+ 8000270:	4a18      	ldr	r2, [pc, #96]	; (80002d4 <SystemCoreClockUpdate+0xc8>)
+ 8000272:	6013      	str	r3, [r2, #0]
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F10X_CL */ 
+      break;
+ 8000274:	e017      	b.n	80002a6 <SystemCoreClockUpdate+0x9a>
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+ 8000276:	4b16      	ldr	r3, [pc, #88]	; (80002d0 <SystemCoreClockUpdate+0xc4>)
+ 8000278:	685b      	ldr	r3, [r3, #4]
+ 800027a:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 800027e:	2b00      	cmp	r3, #0
+ 8000280:	d006      	beq.n	8000290 <SystemCoreClockUpdate+0x84>
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+ 8000282:	68bb      	ldr	r3, [r7, #8]
+ 8000284:	4a15      	ldr	r2, [pc, #84]	; (80002dc <SystemCoreClockUpdate+0xd0>)
+ 8000286:	fb02 f303 	mul.w	r3, r2, r3
+ 800028a:	4a12      	ldr	r2, [pc, #72]	; (80002d4 <SystemCoreClockUpdate+0xc8>)
+ 800028c:	6013      	str	r3, [r2, #0]
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F10X_CL */ 
+      break;
+ 800028e:	e00a      	b.n	80002a6 <SystemCoreClockUpdate+0x9a>
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+ 8000290:	68bb      	ldr	r3, [r7, #8]
+ 8000292:	4a11      	ldr	r2, [pc, #68]	; (80002d8 <SystemCoreClockUpdate+0xcc>)
+ 8000294:	fb02 f303 	mul.w	r3, r2, r3
+ 8000298:	4a0e      	ldr	r2, [pc, #56]	; (80002d4 <SystemCoreClockUpdate+0xc8>)
+ 800029a:	6013      	str	r3, [r2, #0]
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F10X_CL */ 
+      break;
+ 800029c:	e003      	b.n	80002a6 <SystemCoreClockUpdate+0x9a>
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+ 800029e:	4b0d      	ldr	r3, [pc, #52]	; (80002d4 <SystemCoreClockUpdate+0xc8>)
+ 80002a0:	4a0d      	ldr	r2, [pc, #52]	; (80002d8 <SystemCoreClockUpdate+0xcc>)
+ 80002a2:	601a      	str	r2, [r3, #0]
+      break;
+ 80002a4:	bf00      	nop
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ 80002a6:	4b0a      	ldr	r3, [pc, #40]	; (80002d0 <SystemCoreClockUpdate+0xc4>)
+ 80002a8:	685b      	ldr	r3, [r3, #4]
+ 80002aa:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
+ 80002ae:	091b      	lsrs	r3, r3, #4
+ 80002b0:	4a0b      	ldr	r2, [pc, #44]	; (80002e0 <SystemCoreClockUpdate+0xd4>)
+ 80002b2:	5cd3      	ldrb	r3, [r2, r3]
+ 80002b4:	b2db      	uxtb	r3, r3
+ 80002b6:	60fb      	str	r3, [r7, #12]
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+ 80002b8:	4b06      	ldr	r3, [pc, #24]	; (80002d4 <SystemCoreClockUpdate+0xc8>)
+ 80002ba:	681a      	ldr	r2, [r3, #0]
+ 80002bc:	68fb      	ldr	r3, [r7, #12]
+ 80002be:	fa22 f303 	lsr.w	r3, r2, r3
+ 80002c2:	4a04      	ldr	r2, [pc, #16]	; (80002d4 <SystemCoreClockUpdate+0xc8>)
+ 80002c4:	6013      	str	r3, [r2, #0]
+}
+ 80002c6:	bf00      	nop
+ 80002c8:	3714      	adds	r7, #20
+ 80002ca:	46bd      	mov	sp, r7
+ 80002cc:	bc80      	pop	{r7}
+ 80002ce:	4770      	bx	lr
+ 80002d0:	40021000 	.word	0x40021000
+ 80002d4:	20000000 	.word	0x20000000
+ 80002d8:	007a1200 	.word	0x007a1200
+ 80002dc:	003d0900 	.word	0x003d0900
+ 80002e0:	20000004 	.word	0x20000004
+
+080002e4 <SetSysClock>:
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+ 80002e4:	b580      	push	{r7, lr}
+ 80002e6:	af00      	add	r7, sp, #0
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+ 80002e8:	f000 f802 	bl	80002f0 <SetSysClockTo72>
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */ 
+}
+ 80002ec:	bf00      	nop
+ 80002ee:	bd80      	pop	{r7, pc}
+
+080002f0 <SetSysClockTo72>:
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+ 80002f0:	b480      	push	{r7}
+ 80002f2:	b083      	sub	sp, #12
+ 80002f4:	af00      	add	r7, sp, #0
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+ 80002f6:	2300      	movs	r3, #0
+ 80002f8:	607b      	str	r3, [r7, #4]
+ 80002fa:	2300      	movs	r3, #0
+ 80002fc:	603b      	str	r3, [r7, #0]
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 80002fe:	4a3a      	ldr	r2, [pc, #232]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 8000300:	4b39      	ldr	r3, [pc, #228]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 8000302:	681b      	ldr	r3, [r3, #0]
+ 8000304:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
+ 8000308:	6013      	str	r3, [r2, #0]
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ 800030a:	4b37      	ldr	r3, [pc, #220]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 800030c:	681b      	ldr	r3, [r3, #0]
+ 800030e:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 8000312:	603b      	str	r3, [r7, #0]
+    StartUpCounter++;  
+ 8000314:	687b      	ldr	r3, [r7, #4]
+ 8000316:	3301      	adds	r3, #1
+ 8000318:	607b      	str	r3, [r7, #4]
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+ 800031a:	683b      	ldr	r3, [r7, #0]
+ 800031c:	2b00      	cmp	r3, #0
+ 800031e:	d103      	bne.n	8000328 <SetSysClockTo72+0x38>
+ 8000320:	687b      	ldr	r3, [r7, #4]
+ 8000322:	f5b3 6fa0 	cmp.w	r3, #1280	; 0x500
+ 8000326:	d1f0      	bne.n	800030a <SetSysClockTo72+0x1a>
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ 8000328:	4b2f      	ldr	r3, [pc, #188]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 800032a:	681b      	ldr	r3, [r3, #0]
+ 800032c:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 8000330:	2b00      	cmp	r3, #0
+ 8000332:	d002      	beq.n	800033a <SetSysClockTo72+0x4a>
+  {
+    HSEStatus = (uint32_t)0x01;
+ 8000334:	2301      	movs	r3, #1
+ 8000336:	603b      	str	r3, [r7, #0]
+ 8000338:	e001      	b.n	800033e <SetSysClockTo72+0x4e>
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+ 800033a:	2300      	movs	r3, #0
+ 800033c:	603b      	str	r3, [r7, #0]
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+ 800033e:	683b      	ldr	r3, [r7, #0]
+ 8000340:	2b01      	cmp	r3, #1
+ 8000342:	d14b      	bne.n	80003dc <SetSysClockTo72+0xec>
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+ 8000344:	4a29      	ldr	r2, [pc, #164]	; (80003ec <SetSysClockTo72+0xfc>)
+ 8000346:	4b29      	ldr	r3, [pc, #164]	; (80003ec <SetSysClockTo72+0xfc>)
+ 8000348:	681b      	ldr	r3, [r3, #0]
+ 800034a:	f043 0310 	orr.w	r3, r3, #16
+ 800034e:	6013      	str	r3, [r2, #0]
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ 8000350:	4a26      	ldr	r2, [pc, #152]	; (80003ec <SetSysClockTo72+0xfc>)
+ 8000352:	4b26      	ldr	r3, [pc, #152]	; (80003ec <SetSysClockTo72+0xfc>)
+ 8000354:	681b      	ldr	r3, [r3, #0]
+ 8000356:	f023 0303 	bic.w	r3, r3, #3
+ 800035a:	6013      	str	r3, [r2, #0]
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 800035c:	4a23      	ldr	r2, [pc, #140]	; (80003ec <SetSysClockTo72+0xfc>)
+ 800035e:	4b23      	ldr	r3, [pc, #140]	; (80003ec <SetSysClockTo72+0xfc>)
+ 8000360:	681b      	ldr	r3, [r3, #0]
+ 8000362:	f043 0302 	orr.w	r3, r3, #2
+ 8000366:	6013      	str	r3, [r2, #0]
+
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+ 8000368:	4a1f      	ldr	r2, [pc, #124]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 800036a:	4b1f      	ldr	r3, [pc, #124]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 800036c:	685b      	ldr	r3, [r3, #4]
+ 800036e:	6053      	str	r3, [r2, #4]
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+ 8000370:	4a1d      	ldr	r2, [pc, #116]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 8000372:	4b1d      	ldr	r3, [pc, #116]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 8000374:	685b      	ldr	r3, [r3, #4]
+ 8000376:	6053      	str	r3, [r2, #4]
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+ 8000378:	4a1b      	ldr	r2, [pc, #108]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 800037a:	4b1b      	ldr	r3, [pc, #108]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 800037c:	685b      	ldr	r3, [r3, #4]
+ 800037e:	f443 6380 	orr.w	r3, r3, #1024	; 0x400
+ 8000382:	6053      	str	r3, [r2, #4]
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+ 8000384:	4a18      	ldr	r2, [pc, #96]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 8000386:	4b18      	ldr	r3, [pc, #96]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 8000388:	685b      	ldr	r3, [r3, #4]
+ 800038a:	f423 137c 	bic.w	r3, r3, #4128768	; 0x3f0000
+ 800038e:	6053      	str	r3, [r2, #4]
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+ 8000390:	4a15      	ldr	r2, [pc, #84]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 8000392:	4b15      	ldr	r3, [pc, #84]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 8000394:	685b      	ldr	r3, [r3, #4]
+ 8000396:	f443 13e8 	orr.w	r3, r3, #1900544	; 0x1d0000
+ 800039a:	6053      	str	r3, [r2, #4]
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+ 800039c:	4a12      	ldr	r2, [pc, #72]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 800039e:	4b12      	ldr	r3, [pc, #72]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 80003a0:	681b      	ldr	r3, [r3, #0]
+ 80003a2:	f043 7380 	orr.w	r3, r3, #16777216	; 0x1000000
+ 80003a6:	6013      	str	r3, [r2, #0]
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ 80003a8:	bf00      	nop
+ 80003aa:	4b0f      	ldr	r3, [pc, #60]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 80003ac:	681b      	ldr	r3, [r3, #0]
+ 80003ae:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
+ 80003b2:	2b00      	cmp	r3, #0
+ 80003b4:	d0f9      	beq.n	80003aa <SetSysClockTo72+0xba>
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ 80003b6:	4a0c      	ldr	r2, [pc, #48]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 80003b8:	4b0b      	ldr	r3, [pc, #44]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 80003ba:	685b      	ldr	r3, [r3, #4]
+ 80003bc:	f023 0303 	bic.w	r3, r3, #3
+ 80003c0:	6053      	str	r3, [r2, #4]
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+ 80003c2:	4a09      	ldr	r2, [pc, #36]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 80003c4:	4b08      	ldr	r3, [pc, #32]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 80003c6:	685b      	ldr	r3, [r3, #4]
+ 80003c8:	f043 0302 	orr.w	r3, r3, #2
+ 80003cc:	6053      	str	r3, [r2, #4]
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ 80003ce:	bf00      	nop
+ 80003d0:	4b05      	ldr	r3, [pc, #20]	; (80003e8 <SetSysClockTo72+0xf8>)
+ 80003d2:	685b      	ldr	r3, [r3, #4]
+ 80003d4:	f003 030c 	and.w	r3, r3, #12
+ 80003d8:	2b08      	cmp	r3, #8
+ 80003da:	d1f9      	bne.n	80003d0 <SetSysClockTo72+0xe0>
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }
+}
+ 80003dc:	bf00      	nop
+ 80003de:	370c      	adds	r7, #12
+ 80003e0:	46bd      	mov	sp, r7
+ 80003e2:	bc80      	pop	{r7}
+ 80003e4:	4770      	bx	lr
+ 80003e6:	bf00      	nop
+ 80003e8:	40021000 	.word	0x40021000
+ 80003ec:	40022000 	.word	0x40022000
+
+080003f0 <SysTick_Handler>:
+
+
+volatile long int aa=0,bb=0;
+
+
+void SysTick_Handler(void) {
+ 80003f0:	b480      	push	{r7}
+ 80003f2:	af00      	add	r7, sp, #0
+    aa++;
+ 80003f4:	4b04      	ldr	r3, [pc, #16]	; (8000408 <SysTick_Handler+0x18>)
+ 80003f6:	681b      	ldr	r3, [r3, #0]
+ 80003f8:	3301      	adds	r3, #1
+ 80003fa:	4a03      	ldr	r2, [pc, #12]	; (8000408 <SysTick_Handler+0x18>)
+ 80003fc:	6013      	str	r3, [r2, #0]
+
+}
+ 80003fe:	bf00      	nop
+ 8000400:	46bd      	mov	sp, r7
+ 8000402:	bc80      	pop	{r7}
+ 8000404:	4770      	bx	lr
+ 8000406:	bf00      	nop
+ 8000408:	20000014 	.word	0x20000014
+
+0800040c <main>:
+
+int main(void) {
+ 800040c:	b580      	push	{r7, lr}
+ 800040e:	af00      	add	r7, sp, #0
+    SystemCoreClockUpdate();
+ 8000410:	f7ff fefc 	bl	800020c <SystemCoreClockUpdate>
+    SysTick_Config(SystemCoreClock/10000);
+ 8000414:	4b07      	ldr	r3, [pc, #28]	; (8000434 <main+0x28>)
+ 8000416:	681b      	ldr	r3, [r3, #0]
+ 8000418:	4a07      	ldr	r2, [pc, #28]	; (8000438 <main+0x2c>)
+ 800041a:	fba2 2303 	umull	r2, r3, r2, r3
+ 800041e:	0b5b      	lsrs	r3, r3, #13
+ 8000420:	4618      	mov	r0, r3
+ 8000422:	f7ff fe9d 	bl	8000160 <SysTick_Config>
+
+    while (1) {
+    bb=SystemCoreClock;
+ 8000426:	4b03      	ldr	r3, [pc, #12]	; (8000434 <main+0x28>)
+ 8000428:	681b      	ldr	r3, [r3, #0]
+ 800042a:	461a      	mov	r2, r3
+ 800042c:	4b03      	ldr	r3, [pc, #12]	; (800043c <main+0x30>)
+ 800042e:	601a      	str	r2, [r3, #0]
+    }
+ 8000430:	e7f9      	b.n	8000426 <main+0x1a>
+ 8000432:	bf00      	nop
+ 8000434:	20000000 	.word	0x20000000
+ 8000438:	d1b71759 	.word	0xd1b71759
+ 800043c:	20000018 	.word	0x20000018
+ 8000440:	0800049c 	.word	0x0800049c
+ 8000444:	20000000 	.word	0x20000000
+ 8000448:	20000014 	.word	0x20000014
+ 800044c:	20000014 	.word	0x20000014
+ 8000450:	2000001c 	.word	0x2000001c
+
+08000454 <Reset_Handler>:
+	.weak	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:	
+
+/* Copy the data segment initializers from flash to SRAM */  
+  movs	r1, #0
+ 8000454:	2100      	movs	r1, #0
+  b	LoopCopyDataInit
+ 8000456:	e003      	b.n	8000460 <LoopCopyDataInit>
+
+08000458 <CopyDataInit>:
+
+CopyDataInit:
+	ldr	r3, =_sidata
+ 8000458:	4b0a      	ldr	r3, [pc, #40]	; (8000484 <LoopFillZerobss+0x10>)
+	ldr	r3, [r3, r1]
+ 800045a:	585b      	ldr	r3, [r3, r1]
+	str	r3, [r0, r1]
+ 800045c:	5043      	str	r3, [r0, r1]
+	adds	r1, r1, #4
+ 800045e:	3104      	adds	r1, #4
+
+08000460 <LoopCopyDataInit>:
+    
+LoopCopyDataInit:
+	ldr	r0, =_sdata
+ 8000460:	4809      	ldr	r0, [pc, #36]	; (8000488 <LoopFillZerobss+0x14>)
+	ldr	r3, =_edata
+ 8000462:	4b0a      	ldr	r3, [pc, #40]	; (800048c <LoopFillZerobss+0x18>)
+	adds	r2, r0, r1
+ 8000464:	1842      	adds	r2, r0, r1
+	cmp	r2, r3
+ 8000466:	429a      	cmp	r2, r3
+	bcc	CopyDataInit
+ 8000468:	d3f6      	bcc.n	8000458 <CopyDataInit>
+	ldr	r2, =_sbss
+ 800046a:	4a09      	ldr	r2, [pc, #36]	; (8000490 <LoopFillZerobss+0x1c>)
+	b	LoopFillZerobss
+ 800046c:	e002      	b.n	8000474 <LoopFillZerobss>
+
+0800046e <FillZerobss>:
+/* Zero fill the bss segment. */  
+FillZerobss:
+	movs	r3, #0
+ 800046e:	2300      	movs	r3, #0
+	str	r3, [r2], #4
+ 8000470:	f842 3b04 	str.w	r3, [r2], #4
+
+08000474 <LoopFillZerobss>:
+    
+LoopFillZerobss:
+	ldr	r3, = _ebss
+ 8000474:	4b07      	ldr	r3, [pc, #28]	; (8000494 <LoopFillZerobss+0x20>)
+	cmp	r2, r3
+ 8000476:	429a      	cmp	r2, r3
+	bcc	FillZerobss
+ 8000478:	d3f9      	bcc.n	800046e <FillZerobss>
+/* Call the clock system intitialization function.*/
+  bl  SystemInit  
+ 800047a:	f7ff fe93 	bl	80001a4 <SystemInit>
+/* Call the application's entry point.*/
+	bl	main
+ 800047e:	f7ff ffc5 	bl	800040c <main>
+	bx	lr    
+ 8000482:	4770      	bx	lr
+/* Copy the data segment initializers from flash to SRAM */  
+  movs	r1, #0
+  b	LoopCopyDataInit
+
+CopyDataInit:
+	ldr	r3, =_sidata
+ 8000484:	0800049c 	.word	0x0800049c
+	ldr	r3, [r3, r1]
+	str	r3, [r0, r1]
+	adds	r1, r1, #4
+    
+LoopCopyDataInit:
+	ldr	r0, =_sdata
+ 8000488:	20000000 	.word	0x20000000
+	ldr	r3, =_edata
+ 800048c:	20000014 	.word	0x20000014
+	adds	r2, r0, r1
+	cmp	r2, r3
+	bcc	CopyDataInit
+	ldr	r2, =_sbss
+ 8000490:	20000014 	.word	0x20000014
+FillZerobss:
+	movs	r3, #0
+	str	r3, [r2], #4
+    
+LoopFillZerobss:
+	ldr	r3, = _ebss
+ 8000494:	2000001c 	.word	0x2000001c
+
+08000498 <ADC1_2_IRQHandler>:
+ * @retval None       
+*/
+    .section	.text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+ 8000498:	e7fe      	b.n	8000498 <ADC1_2_IRQHandler>
+	...

BIN
stm32f1_01_systick/build/main.o


BIN
stm32f1_01_systick/build/startup_stm32f10x_ld.o


stm32f1_01/inc/core_cm3.h → stm32f1_01_systick/inc/core_cm3.h


stm32f1_01/inc/misc.h → stm32f1_01_systick/inc/misc.h


stm32f1_01/inc/stm3210c_eval.h → stm32f1_01_systick/inc/stm3210c_eval.h


stm32f1_01/inc/stm3210c_eval_ioe.h → stm32f1_01_systick/inc/stm3210c_eval_ioe.h


stm32f1_01/inc/stm3210c_eval_lcd.h → stm32f1_01_systick/inc/stm3210c_eval_lcd.h


stm32f1_01/inc/stm32_eval.h → stm32f1_01_systick/inc/stm32_eval.h


stm32f1_01/inc/stm32f10x.h → stm32f1_01_systick/inc/stm32f10x.h


stm32f1_01/inc/stm32f10x_adc.h → stm32f1_01_systick/inc/stm32f10x_adc.h


stm32f1_01/inc/stm32f10x_bkp.h → stm32f1_01_systick/inc/stm32f10x_bkp.h


stm32f1_01/inc/stm32f10x_can.h → stm32f1_01_systick/inc/stm32f10x_can.h


stm32f1_01/inc/stm32f10x_cec.h → stm32f1_01_systick/inc/stm32f10x_cec.h


stm32f1_01/inc/stm32f10x_crc.h → stm32f1_01_systick/inc/stm32f10x_crc.h


stm32f1_01/inc/stm32f10x_dac.h → stm32f1_01_systick/inc/stm32f10x_dac.h


stm32f1_01/inc/stm32f10x_dbgmcu.h → stm32f1_01_systick/inc/stm32f10x_dbgmcu.h


stm32f1_01/inc/stm32f10x_dma.h → stm32f1_01_systick/inc/stm32f10x_dma.h


stm32f1_01/inc/stm32f10x_exti.h → stm32f1_01_systick/inc/stm32f10x_exti.h


stm32f1_01/inc/stm32f10x_flash.h → stm32f1_01_systick/inc/stm32f10x_flash.h


stm32f1_01/inc/stm32f10x_fsmc.h → stm32f1_01_systick/inc/stm32f10x_fsmc.h


stm32f1_01/inc/stm32f10x_gpio.h → stm32f1_01_systick/inc/stm32f10x_gpio.h


stm32f1_01/inc/stm32f10x_i2c.h → stm32f1_01_systick/inc/stm32f10x_i2c.h


stm32f1_01/inc/stm32f10x_iwdg.h → stm32f1_01_systick/inc/stm32f10x_iwdg.h


stm32f1_01/inc/stm32f10x_pwr.h → stm32f1_01_systick/inc/stm32f10x_pwr.h


stm32f1_01/inc/stm32f10x_rcc.h → stm32f1_01_systick/inc/stm32f10x_rcc.h


stm32f1_01/inc/stm32f10x_rtc.h → stm32f1_01_systick/inc/stm32f10x_rtc.h


stm32f1_01/inc/stm32f10x_sdio.h → stm32f1_01_systick/inc/stm32f10x_sdio.h


stm32f1_01/inc/stm32f10x_spi.h → stm32f1_01_systick/inc/stm32f10x_spi.h


stm32f1_01/inc/stm32f10x_tim.h → stm32f1_01_systick/inc/stm32f10x_tim.h


stm32f1_01/inc/stm32f10x_usart.h → stm32f1_01_systick/inc/stm32f10x_usart.h


stm32f1_01/inc/stm32f10x_wwdg.h → stm32f1_01_systick/inc/stm32f10x_wwdg.h


stm32f1_01/inc/system_stm32f10x.h → stm32f1_01_systick/inc/system_stm32f10x.h


stm32f1_01/lib/core_cm3.c → stm32f1_01_systick/lib/core_cm3.c


stm32f1_01/lib/misc.c → stm32f1_01_systick/lib/misc.c


stm32f1_01/lib/stm3210c_eval.c → stm32f1_01_systick/lib/stm3210c_eval.c


stm32f1_01/lib/stm3210c_eval_ioe.c → stm32f1_01_systick/lib/stm3210c_eval_ioe.c


stm32f1_01/lib/stm3210c_eval_lcd.c → stm32f1_01_systick/lib/stm3210c_eval_lcd.c


stm32f1_01/lib/stm32_eval.c → stm32f1_01_systick/lib/stm32_eval.c


stm32f1_01/lib/stm32f10x_adc.c → stm32f1_01_systick/lib/stm32f10x_adc.c


stm32f1_01/lib/stm32f10x_bkp.c → stm32f1_01_systick/lib/stm32f10x_bkp.c


stm32f1_01/lib/stm32f10x_can.c → stm32f1_01_systick/lib/stm32f10x_can.c


stm32f1_01/lib/stm32f10x_cec.c → stm32f1_01_systick/lib/stm32f10x_cec.c


stm32f1_01/lib/stm32f10x_crc.c → stm32f1_01_systick/lib/stm32f10x_crc.c


stm32f1_01/lib/stm32f10x_dac.c → stm32f1_01_systick/lib/stm32f10x_dac.c


stm32f1_01/lib/stm32f10x_dbgmcu.c → stm32f1_01_systick/lib/stm32f10x_dbgmcu.c


stm32f1_01/lib/stm32f10x_dma.c → stm32f1_01_systick/lib/stm32f10x_dma.c


stm32f1_01/lib/stm32f10x_exti.c → stm32f1_01_systick/lib/stm32f10x_exti.c


stm32f1_01/lib/stm32f10x_flash.c → stm32f1_01_systick/lib/stm32f10x_flash.c


stm32f1_01/lib/stm32f10x_fsmc.c → stm32f1_01_systick/lib/stm32f10x_fsmc.c


stm32f1_01/lib/stm32f10x_gpio.c → stm32f1_01_systick/lib/stm32f10x_gpio.c


stm32f1_01/lib/stm32f10x_i2c.c → stm32f1_01_systick/lib/stm32f10x_i2c.c


stm32f1_01/lib/stm32f10x_iwdg.c → stm32f1_01_systick/lib/stm32f10x_iwdg.c


stm32f1_01/lib/stm32f10x_pwr.c → stm32f1_01_systick/lib/stm32f10x_pwr.c


stm32f1_01/lib/stm32f10x_rcc.c → stm32f1_01_systick/lib/stm32f10x_rcc.c


stm32f1_01/lib/stm32f10x_rtc.c → stm32f1_01_systick/lib/stm32f10x_rtc.c


stm32f1_01/lib/stm32f10x_sdio.c → stm32f1_01_systick/lib/stm32f10x_sdio.c


stm32f1_01/lib/stm32f10x_spi.c → stm32f1_01_systick/lib/stm32f10x_spi.c


stm32f1_01/lib/stm32f10x_tim.c → stm32f1_01_systick/lib/stm32f10x_tim.c


stm32f1_01/lib/stm32f10x_usart.c → stm32f1_01_systick/lib/stm32f10x_usart.c


stm32f1_01/lib/stm32f10x_wwdg.c → stm32f1_01_systick/lib/stm32f10x_wwdg.c


stm32f1_01/lib/system_stm32f10x.c → stm32f1_01_systick/lib/system_stm32f10x.c


+ 21 - 0
stm32f1_01_systick/main.c

@@ -0,0 +1,21 @@
+#include "main.h"
+
+
+volatile long int aa=0,bb=0;
+
+
+void SysTick_Handler(void) {
+    aa++;
+
+}
+
+int main(void) {
+    SystemCoreClockUpdate();
+    SysTick_Config(SystemCoreClock/10000);
+
+    while (1) {
+    bb=SystemCoreClock;
+    }
+
+    return 0;
+}

+ 2 - 0
stm32f1_01/main.h

@@ -25,6 +25,8 @@
 
 
 /* Includes ------------------------------------------------------------------*/
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f10x.h"
 #include "stm32f10x.h"
+#include "system_stm32f10x.h"
+#include "system_stm32f10x.c"
 //#include "stm32_eval.h"
 //#include "stm32_eval.h"
 
 
 /* Exported types ------------------------------------------------------------*/
 /* Exported types ------------------------------------------------------------*/

stm32f1_01/readme.txt → stm32f1_01_systick/readme.txt


+ 343 - 0
stm32f1_01_systick/source/startup_stm32f10x_ld.s

@@ -0,0 +1,343 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f10x_ld.s
+  * @author    MCD Application Team
+  * @version   V3.5.0
+  * @date      11-March-2011
+  * @brief     STM32F10x Low Density Devices vector table for RIDE7 toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system  
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M3 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */	
+    
+  .syntax unified
+	.cpu cortex-m3
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section. 
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */  
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+
+.equ  BootRAM, 0xF108F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called. 
+ * @param  None
+ * @retval : None
+*/
+
+    .section	.text.Reset_Handler
+	.weak	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:	
+
+/* Copy the data segment initializers from flash to SRAM */  
+  movs	r1, #0
+  b	LoopCopyDataInit
+
+CopyDataInit:
+	ldr	r3, =_sidata
+	ldr	r3, [r3, r1]
+	str	r3, [r0, r1]
+	adds	r1, r1, #4
+    
+LoopCopyDataInit:
+	ldr	r0, =_sdata
+	ldr	r3, =_edata
+	adds	r2, r0, r1
+	cmp	r2, r3
+	bcc	CopyDataInit
+	ldr	r2, =_sbss
+	b	LoopFillZerobss
+/* Zero fill the bss segment. */  
+FillZerobss:
+	movs	r3, #0
+	str	r3, [r2], #4
+    
+LoopFillZerobss:
+	ldr	r3, = _ebss
+	cmp	r2, r3
+	bcc	FillZerobss
+/* Call the clock system intitialization function.*/
+  bl  SystemInit  
+/* Call the application's entry point.*/
+	bl	main
+	bx	lr    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an 
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None     
+ * @retval None       
+*/
+    .section	.text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/    
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+    
+    
+g_pfnVectors:
+	.word	_estack
+	.word	Reset_Handler
+	.word	NMI_Handler
+	.word	HardFault_Handler
+	.word	MemManage_Handler
+	.word	BusFault_Handler
+	.word	UsageFault_Handler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	SVC_Handler
+	.word	DebugMon_Handler
+	.word	0
+	.word	PendSV_Handler
+	.word	SysTick_Handler
+	.word	WWDG_IRQHandler
+	.word	PVD_IRQHandler
+	.word	TAMPER_IRQHandler
+	.word	RTC_IRQHandler
+	.word	FLASH_IRQHandler
+	.word	RCC_IRQHandler
+	.word	EXTI0_IRQHandler
+	.word	EXTI1_IRQHandler
+	.word	EXTI2_IRQHandler
+	.word	EXTI3_IRQHandler
+	.word	EXTI4_IRQHandler
+	.word	DMA1_Channel1_IRQHandler
+	.word	DMA1_Channel2_IRQHandler
+	.word	DMA1_Channel3_IRQHandler
+	.word	DMA1_Channel4_IRQHandler
+	.word	DMA1_Channel5_IRQHandler
+	.word	DMA1_Channel6_IRQHandler
+	.word	DMA1_Channel7_IRQHandler
+	.word	ADC1_2_IRQHandler
+	.word	USB_HP_CAN1_TX_IRQHandler
+	.word	USB_LP_CAN1_RX0_IRQHandler
+	.word	CAN1_RX1_IRQHandler
+	.word	CAN1_SCE_IRQHandler
+	.word	EXTI9_5_IRQHandler
+	.word	TIM1_BRK_IRQHandler
+	.word	TIM1_UP_IRQHandler
+	.word	TIM1_TRG_COM_IRQHandler
+	.word	TIM1_CC_IRQHandler
+	.word	TIM2_IRQHandler
+	.word	TIM3_IRQHandler
+	.word	0
+	.word	I2C1_EV_IRQHandler
+	.word	I2C1_ER_IRQHandler
+	.word	0
+	.word	0
+	.word	SPI1_IRQHandler
+	.word	0
+	.word	USART1_IRQHandler
+	.word	USART2_IRQHandler
+	.word	0
+	.word	EXTI15_10_IRQHandler
+	.word	RTCAlarm_IRQHandler
+	.word	USBWakeUp_IRQHandler	
+  .word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	BootRAM        /* @0x108. This is for boot in RAM mode for 
+                          STM32F10x Low Density devices.*/
+   
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+*
+*******************************************************************************/
+    
+  .weak	NMI_Handler
+	.thumb_set NMI_Handler,Default_Handler
+	
+  .weak	HardFault_Handler
+	.thumb_set HardFault_Handler,Default_Handler
+	
+  .weak	MemManage_Handler
+	.thumb_set MemManage_Handler,Default_Handler
+	
+  .weak	BusFault_Handler
+	.thumb_set BusFault_Handler,Default_Handler
+
+	.weak	UsageFault_Handler
+	.thumb_set UsageFault_Handler,Default_Handler
+
+	.weak	SVC_Handler
+	.thumb_set SVC_Handler,Default_Handler
+
+	.weak	DebugMon_Handler
+	.thumb_set DebugMon_Handler,Default_Handler
+
+	.weak	PendSV_Handler
+	.thumb_set PendSV_Handler,Default_Handler
+
+	.weak	SysTick_Handler
+	.thumb_set SysTick_Handler,Default_Handler
+
+	.weak	WWDG_IRQHandler
+	.thumb_set WWDG_IRQHandler,Default_Handler
+
+	.weak	PVD_IRQHandler
+	.thumb_set PVD_IRQHandler,Default_Handler
+
+	.weak	TAMPER_IRQHandler
+	.thumb_set TAMPER_IRQHandler,Default_Handler
+
+	.weak	RTC_IRQHandler
+	.thumb_set RTC_IRQHandler,Default_Handler
+
+	.weak	FLASH_IRQHandler
+	.thumb_set FLASH_IRQHandler,Default_Handler
+
+	.weak	RCC_IRQHandler
+	.thumb_set RCC_IRQHandler,Default_Handler
+
+	.weak	EXTI0_IRQHandler
+	.thumb_set EXTI0_IRQHandler,Default_Handler
+
+	.weak	EXTI1_IRQHandler
+	.thumb_set EXTI1_IRQHandler,Default_Handler
+
+	.weak	EXTI2_IRQHandler
+	.thumb_set EXTI2_IRQHandler,Default_Handler
+
+	.weak	EXTI3_IRQHandler
+	.thumb_set EXTI3_IRQHandler,Default_Handler
+
+	.weak	EXTI4_IRQHandler
+	.thumb_set EXTI4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel1_IRQHandler
+	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel2_IRQHandler
+	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel3_IRQHandler
+	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel4_IRQHandler
+	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel5_IRQHandler
+	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel6_IRQHandler
+	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel7_IRQHandler
+	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+	.weak	ADC1_2_IRQHandler
+	.thumb_set ADC1_2_IRQHandler,Default_Handler
+
+	.weak	USB_HP_CAN1_TX_IRQHandler
+	.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+	.weak	USB_LP_CAN1_RX0_IRQHandler
+	.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+	.weak	CAN1_RX1_IRQHandler
+	.thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+	.weak	CAN1_SCE_IRQHandler
+	.thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+	.weak	EXTI9_5_IRQHandler
+	.thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+	.weak	TIM1_BRK_IRQHandler
+	.thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM1_UP_IRQHandler
+	.thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+	.weak	TIM1_TRG_COM_IRQHandler
+	.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM1_CC_IRQHandler
+	.thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+	.weak	TIM2_IRQHandler
+	.thumb_set TIM2_IRQHandler,Default_Handler
+
+	.weak	TIM3_IRQHandler
+	.thumb_set TIM3_IRQHandler,Default_Handler
+
+	.weak	I2C1_EV_IRQHandler
+	.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+	.weak	I2C1_ER_IRQHandler
+	.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+	.weak	SPI1_IRQHandler
+	.thumb_set SPI1_IRQHandler,Default_Handler
+
+	.weak	USART1_IRQHandler
+	.thumb_set USART1_IRQHandler,Default_Handler
+
+	.weak	USART2_IRQHandler
+	.thumb_set USART2_IRQHandler,Default_Handler
+
+	.weak	EXTI15_10_IRQHandler
+	.thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+	.weak	RTCAlarm_IRQHandler
+	.thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+	.weak	USBWakeUp_IRQHandler
+	.thumb_set USBWakeUp_IRQHandler,Default_Handler  
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

stm32f1_01/stm32_flash.ld → stm32f1_01_systick/stm32_flash.ld


stm32f1_01/stm32f10x_conf.h → stm32f1_01_systick/stm32f10x_conf.h


stm32f1_01/stm32f10x_it.c → stm32f1_01_systick/stm32f10x_it.c


stm32f1_01/stm32f10x_it.h → stm32f1_01_systick/stm32f10x_it.h


stm32f1_01/system_stm32f10x.c → stm32f1_01_systick/system_stm32f10x.c


+ 31 - 0
stm32f1_02/Makefile

@@ -0,0 +1,31 @@
+CC      = arm-none-eabi-gcc
+LD      = arm-none-eabi-gcc -v
+CP      = arm-none-eabi-objcopy
+OD      = arm-none-eabi-objdump
+
+CFLAGS  =  -I./ -I./lib -I./inc -c -fno-common -O0 -g -mcpu=cortex-m3 -mthumb 
+LFLAGS  = -Tstm32_flash.ld -nostartfiles
+ODFLAGS = -S
+AR+= -rcs
+
+all: test
+
+clean: -rm build/main.lst build/startup_stm32f10x_ld.o build/main.o build/main.elf build/main.lst build/main.bin
+
+test: main.elf 
+	@ echo "...copying"
+	$(CP) -O binary build/main.elf build/main.bin
+	$(CP) -O ihex build/main.elf build/main.hex
+	$(OD) $(ODFLAGS) build/main.elf > build/main.lst
+
+main.elf: main.o startup.o stm32_flash.ld
+	@ echo "..linking"
+	$(LD) $(LFLAGS) -o build/main.elf build/main.o build/startup_stm32f10x_ld.o
+
+main.o: main.c
+	@ echo ".compiling"
+	$(CC) $(CFLAGS) main.c -o build/main.o
+
+startup.o: source/startup_stm32f10x_ld.s
+	@ echo ".compiling"
+	$(CC) $(CFLAGS) source/startup_stm32f10x_ld.s -o build/startup_stm32f10x_ld.o

+ 4 - 0
stm32f1_02/gdb.txt

@@ -0,0 +1,4 @@
+tar ext :4242
+load
+continue
+print SCNT

Разница между файлами не показана из-за своего большого размера
+ 1818 - 0
stm32f1_02/inc/core_cm3.h


+ 118 - 0
stm32f1_02/inc/fonts.h

@@ -0,0 +1,118 @@
+/**
+  ******************************************************************************
+  * @file    fonts.h
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   Header for fonts.c
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FONTS_H
+#define __FONTS_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stdint.h>
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup Common
+  * @{
+  */
+
+/** @addtogroup FONTS
+  * @{
+  */ 
+
+/** @defgroup FONTS_Exported_Types
+  * @{
+  */ 
+typedef struct _tFont
+{    
+  const uint16_t *table;
+  uint16_t Width;
+  uint16_t Height;
+  
+} sFONT;
+
+extern sFONT Font16x24;
+extern sFONT Font12x12;
+extern sFONT Font8x12;
+extern sFONT Font8x8;
+
+/**
+  * @}
+  */ 
+
+/** @defgroup FONTS_Exported_Constants
+  * @{
+  */ 
+#define LINE(x) ((x) * (((sFONT *)LCD_GetFont())->Height))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup FONTS_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup FONTS_Exported_Functions
+  * @{
+  */ 
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+  
+#endif /* __FONTS_H */
+ 
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */      
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

+ 220 - 0
stm32f1_02/inc/misc.h

@@ -0,0 +1,220 @@
+/**
+  ******************************************************************************
+  * @file    misc.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the miscellaneous
+  *          firmware library functions (add-on to CMSIS functions).
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MISC_H
+#define __MISC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup MISC
+  * @{
+  */
+
+/** @defgroup MISC_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  NVIC Init Structure definition  
+  */
+
+typedef struct
+{
+  uint8_t NVIC_IRQChannel;                    /*!< Specifies the IRQ channel to be enabled or disabled.
+                                                   This parameter can be a value of @ref IRQn_Type 
+                                                   (For the complete STM32 Devices IRQ Channels list, please
+                                                    refer to stm32f10x.h file) */
+
+  uint8_t NVIC_IRQChannelPreemptionPriority;  /*!< Specifies the pre-emption priority for the IRQ channel
+                                                   specified in NVIC_IRQChannel. This parameter can be a value
+                                                   between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+  uint8_t NVIC_IRQChannelSubPriority;         /*!< Specifies the subpriority level for the IRQ channel specified
+                                                   in NVIC_IRQChannel. This parameter can be a value
+                                                   between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+  FunctionalState NVIC_IRQChannelCmd;         /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+                                                   will be enabled or disabled. 
+                                                   This parameter can be set either to ENABLE or DISABLE */   
+} NVIC_InitTypeDef;
+ 
+/**
+  * @}
+  */
+
+/** @defgroup NVIC_Priority_Table 
+  * @{
+  */
+
+/**
+@code  
+ The table below gives the allowed values of the pre-emption priority and subpriority according
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+  ============================================================================================================================
+    NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  | Description
+  ============================================================================================================================
+   NVIC_PriorityGroup_0  |                0                  |            0-15             |   0 bits for pre-emption priority
+                         |                                   |                             |   4 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------
+   NVIC_PriorityGroup_1  |                0-1                |            0-7              |   1 bits for pre-emption priority
+                         |                                   |                             |   3 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------    
+   NVIC_PriorityGroup_2  |                0-3                |            0-3              |   2 bits for pre-emption priority
+                         |                                   |                             |   2 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------    
+   NVIC_PriorityGroup_3  |                0-7                |            0-1              |   3 bits for pre-emption priority
+                         |                                   |                             |   1 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------    
+   NVIC_PriorityGroup_4  |                0-15               |            0                |   4 bits for pre-emption priority
+                         |                                   |                             |   0 bits for subpriority                       
+  ============================================================================================================================
+@endcode
+*/
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup Vector_Table_Base 
+  * @{
+  */
+
+#define NVIC_VectTab_RAM             ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH           ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
+                                  ((VECTTAB) == NVIC_VectTab_FLASH))
+/**
+  * @}
+  */
+
+/** @defgroup System_Low_Power 
+  * @{
+  */
+
+#define NVIC_LP_SEVONPEND            ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP            ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT          ((uint8_t)0x02)
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
+                        ((LP) == NVIC_LP_SLEEPDEEP) || \
+                        ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+  * @}
+  */
+
+/** @defgroup Preemption_Priority_Group 
+  * @{
+  */
+
+#define NVIC_PriorityGroup_0         ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
+                                                            4 bits for subpriority */
+#define NVIC_PriorityGroup_1         ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
+                                                            3 bits for subpriority */
+#define NVIC_PriorityGroup_2         ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
+                                                            2 bits for subpriority */
+#define NVIC_PriorityGroup_3         ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
+                                                            1 bits for subpriority */
+#define NVIC_PriorityGroup_4         ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
+                                                            0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
+                                       ((GROUP) == NVIC_PriorityGroup_1) || \
+                                       ((GROUP) == NVIC_PriorityGroup_2) || \
+                                       ((GROUP) == NVIC_PriorityGroup_3) || \
+                                       ((GROUP) == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET(OFFSET)  ((OFFSET) < 0x000FFFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup SysTick_clock_source 
+  * @{
+  */
+
+#define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
+                                       ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Exported_Functions
+  * @{
+  */
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MISC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

+ 277 - 0
stm32f1_02/inc/stm3210c_eval.h

@@ -0,0 +1,277 @@
+/**
+  ******************************************************************************
+  * @file    stm3210c_eval.h
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   This file contains definitions for STM3210C_EVAL's Leds, push-buttons
+  *          COM ports, SD Card on SPI and sEE on I2C hardware resources.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 210 STMicroelectronics</center></h2>
+  */ 
+  
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM3210C_EVAL_H
+#define __STM3210C_EVAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32_eval.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */
+    
+/** @addtogroup STM3210C_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM3210C_EVAL_LOW_LEVEL
+  * @{
+  */ 
+  
+/** @defgroup STM3210C_EVAL_LOW_LEVEL_Exported_Types
+  * @{
+  */
+/**
+  * @}
+  */ 
+
+/** @defgroup STM3210C_EVAL_LOW_LEVEL_Exported_Constants
+  * @{
+  */ 
+
+/** @addtogroup STM3210C_EVAL_LOW_LEVEL_LED
+  * @{
+  */
+#define LEDn                             4
+
+#define LED1_PIN                         GPIO_Pin_7
+#define LED1_GPIO_PORT                   GPIOD
+#define LED1_GPIO_CLK                    RCC_APB2Periph_GPIOD  
+  
+#define LED2_PIN                         GPIO_Pin_13
+#define LED2_GPIO_PORT                   GPIOD
+#define LED2_GPIO_CLK                    RCC_APB2Periph_GPIOD  
+
+#define LED3_PIN                         GPIO_Pin_3  
+#define LED3_GPIO_PORT                   GPIOD
+#define LED3_GPIO_CLK                    RCC_APB2Periph_GPIOD  
+
+#define LED4_PIN                         GPIO_Pin_4  
+#define LED4_GPIO_PORT                   GPIOD
+#define LED4_GPIO_CLK                    RCC_APB2Periph_GPIOD  
+
+
+/**
+  * @}
+  */ 
+  
+/** @addtogroup STM3210C_EVAL_LOW_LEVEL_BUTTON
+  * @{
+  */  
+#define BUTTONn                          3 /*!< Joystick pins are connected to 
+                                                an IO Expander (accessible through 
+                                                I2C1 interface) */
+
+/**
+ * @brief Wakeup push-button
+ */
+#define WAKEUP_BUTTON_PIN                GPIO_Pin_0
+#define WAKEUP_BUTTON_GPIO_PORT          GPIOA
+#define WAKEUP_BUTTON_GPIO_CLK           RCC_APB2Periph_GPIOA
+#define WAKEUP_BUTTON_EXTI_LINE          EXTI_Line0
+#define WAKEUP_BUTTON_EXTI_PORT_SOURCE   GPIO_PortSourceGPIOA
+#define WAKEUP_BUTTON_EXTI_PIN_SOURCE    GPIO_PinSource0
+#define WAKEUP_BUTTON_EXTI_IRQn          EXTI0_IRQn 
+
+/**
+ * @brief Tamper push-button
+ */
+#define TAMPER_BUTTON_PIN                GPIO_Pin_13
+#define TAMPER_BUTTON_GPIO_PORT          GPIOC
+#define TAMPER_BUTTON_GPIO_CLK           RCC_APB2Periph_GPIOC
+#define TAMPER_BUTTON_EXTI_LINE          EXTI_Line13
+#define TAMPER_BUTTON_EXTI_PORT_SOURCE   GPIO_PortSourceGPIOC
+#define TAMPER_BUTTON_EXTI_PIN_SOURCE    GPIO_PinSource13
+#define TAMPER_BUTTON_EXTI_IRQn          EXTI15_10_IRQn 
+
+/**
+ * @brief Key push-button
+ */
+#define KEY_BUTTON_PIN                   GPIO_Pin_9
+#define KEY_BUTTON_GPIO_PORT             GPIOB
+#define KEY_BUTTON_GPIO_CLK              RCC_APB2Periph_GPIOB
+#define KEY_BUTTON_EXTI_LINE             EXTI_Line9
+#define KEY_BUTTON_EXTI_PORT_SOURCE      GPIO_PortSourceGPIOB
+#define KEY_BUTTON_EXTI_PIN_SOURCE       GPIO_PinSource9
+#define KEY_BUTTON_EXTI_IRQn             EXTI9_5_IRQn
+/**
+  * @}
+  */ 
+
+/** @addtogroup STM3210C_EVAL_LOW_LEVEL_COM
+  * @{
+  */
+#define COMn                             1
+
+/**
+ * @brief Definition for COM port1, connected to USART2 (USART2 pins remapped on GPIOD)
+ */ 
+#define EVAL_COM1                        USART2
+#define EVAL_COM1_CLK                    RCC_APB1Periph_USART2
+#define EVAL_COM1_TX_PIN                 GPIO_Pin_5
+#define EVAL_COM1_TX_GPIO_PORT           GPIOD
+#define EVAL_COM1_TX_GPIO_CLK            RCC_APB2Periph_GPIOD
+#define EVAL_COM1_RX_PIN                 GPIO_Pin_6
+#define EVAL_COM1_RX_GPIO_PORT           GPIOD
+#define EVAL_COM1_RX_GPIO_CLK            RCC_APB2Periph_GPIOD
+#define EVAL_COM1_IRQn                   USART2_IRQn
+
+/**
+  * @}
+  */ 
+
+/** @addtogroup STM3210B_EVAL_SD_SPI
+  * @{
+  */
+/**
+  * @brief  SD SPI Interface pins
+  */
+#define SD_SPI                           SPI3
+#define SD_SPI_CLK                       RCC_APB1Periph_SPI3
+#define SD_SPI_SCK_PIN                   GPIO_Pin_10                 /* PC.10 */
+#define SD_SPI_SCK_GPIO_PORT             GPIOC                       /* GPIOC */
+#define SD_SPI_SCK_GPIO_CLK              RCC_APB2Periph_GPIOC
+#define SD_SPI_MISO_PIN                  GPIO_Pin_11                 /* PC.11 */
+#define SD_SPI_MISO_GPIO_PORT            GPIOC                       /* GPIOC */
+#define SD_SPI_MISO_GPIO_CLK             RCC_APB2Periph_GPIOC
+#define SD_SPI_MOSI_PIN                  GPIO_Pin_12                 /* PC.12 */
+#define SD_SPI_MOSI_GPIO_PORT            GPIOC                       /* GPIOC */
+#define SD_SPI_MOSI_GPIO_CLK             RCC_APB2Periph_GPIOC
+#define SD_CS_PIN                        GPIO_Pin_4                  /* PA.04 */
+#define SD_CS_GPIO_PORT                  GPIOA                       /* GPIOA */
+#define SD_CS_GPIO_CLK                   RCC_APB2Periph_GPIOA
+#define SD_DETECT_PIN                    GPIO_Pin_0                  /* PE.00 */
+#define SD_DETECT_GPIO_PORT              GPIOE                       /* GPIOE */
+#define SD_DETECT_GPIO_CLK               RCC_APB2Periph_GPIOE
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM3210C_EVAL_LOW_LEVEL_I2C_EE
+  * @{
+  */
+/**
+  * @brief  I2C EEPROM Interface pins
+  */  
+#define sEE_I2C                          I2C1
+#define sEE_I2C_CLK                      RCC_APB1Periph_I2C1
+#define sEE_I2C_SCL_PIN                  GPIO_Pin_6                  /* PB.06 */
+#define sEE_I2C_SCL_GPIO_PORT            GPIOB                       /* GPIOB */
+#define sEE_I2C_SCL_GPIO_CLK             RCC_APB2Periph_GPIOB
+#define sEE_I2C_SDA_PIN                  GPIO_Pin_7                  /* PB.07 */
+#define sEE_I2C_SDA_GPIO_PORT            GPIOB                       /* GPIOB */
+#define sEE_I2C_SDA_GPIO_CLK             RCC_APB2Periph_GPIOB
+#define sEE_M24C64_32
+
+#define sEE_I2C_DMA                      DMA1   
+#define sEE_I2C_DMA_CHANNEL_TX           DMA1_Channel6
+#define sEE_I2C_DMA_CHANNEL_RX           DMA1_Channel7 
+#define sEE_I2C_DMA_FLAG_TX_TC           DMA1_IT_TC6   
+#define sEE_I2C_DMA_FLAG_TX_GL           DMA1_IT_GL6 
+#define sEE_I2C_DMA_FLAG_RX_TC           DMA1_IT_TC7 
+#define sEE_I2C_DMA_FLAG_RX_GL           DMA1_IT_GL7    
+#define sEE_I2C_DMA_CLK                  RCC_AHBPeriph_DMA1
+#define sEE_I2C_DR_Address               ((uint32_t)0x40005410)
+#define sEE_USE_DMA
+   
+#define sEE_I2C_DMA_TX_IRQn              DMA1_Channel6_IRQn
+#define sEE_I2C_DMA_RX_IRQn              DMA1_Channel7_IRQn
+#define sEE_I2C_DMA_TX_IRQHandler        DMA1_Channel6_IRQHandler
+#define sEE_I2C_DMA_RX_IRQHandler        DMA1_Channel7_IRQHandler   
+#define sEE_I2C_DMA_PREPRIO              0
+#define sEE_I2C_DMA_SUBPRIO              0   
+   
+#define sEE_DIRECTION_TX                 0
+#define sEE_DIRECTION_RX                 1   
+
+/* Time constant for the delay caclulation allowing to have a millisecond 
+   incrementing counter. This value should be equal to (System Clock / 1000).
+   ie. if system clock = 72MHz then sEE_TIME_CONST should be 72. */
+#define sEE_TIME_CONST                   72 
+   
+/**
+  * @}
+  */
+   
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM3210C_EVAL_LOW_LEVEL_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210C_EVAL_LOW_LEVEL_Exported_Functions
+  * @{
+  */ 
+void STM_EVAL_LEDInit(Led_TypeDef Led);
+void STM_EVAL_LEDOn(Led_TypeDef Led);
+void STM_EVAL_LEDOff(Led_TypeDef Led);
+void STM_EVAL_LEDToggle(Led_TypeDef Led);
+void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
+uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
+void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct); 
+void SD_LowLevel_DeInit(void);
+void SD_LowLevel_Init(void); 
+void sEE_LowLevel_DeInit(void);
+void sEE_LowLevel_Init(void); 
+void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction);
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM3210C_EVAL_H */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+    
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

+ 537 - 0
stm32f1_02/inc/stm3210c_eval_ioe.h

@@ -0,0 +1,537 @@
+/**
+  ******************************************************************************
+  * @file    stm3210c_eval_ioe.h
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   This file contains all the functions prototypes for the IO Expander
+  *   firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+
+  /* File Info : ---------------------------------------------------------------
+    SUPPORTED FEATURES:
+      - IO Read/write : Set/Reset and Read (Polling/Interrupt)
+      - Joystick: config and Read (Polling/Interrupt)
+      - Touch Screen Features: Single point mode (Polling/Interrupt)
+      - TempSensor Feature: accuracy not determined (Polling).
+
+    UNSUPPORTED FEATURES:
+      - Row ADC Feature is not supported (not implemented on STM3210C-EVAL board)
+  ----------------------------------------------------------------------------*/
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM3210C_EVAL_IOE_H
+#define __STM3210C_EVAL_IOE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif   
+   
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM3210C_EVAL
+  * @{
+  */
+    
+/** @defgroup STM3210C_EVAL_IOE 
+  * @{
+  */ 
+
+/** @defgroup STM3210C_EVAL_IOE_Exported_Types
+  * @{
+  */ 
+
+/** 
+  * @brief  Touch Screen Information structure  
+  */ 
+typedef struct
+{
+  uint16_t TouchDetected;
+  uint16_t X;
+  uint16_t Y;
+  uint16_t Z;
+}TS_STATE; 
+  
+/** 
+  * @brief  Joystick State definitions  
+  */ 
+#ifndef __STM32_EVAL_H
+typedef enum 
+{ 
+  JOY_NONE = 0,
+  JOY_SEL = 1,
+  JOY_DOWN = 2,
+  JOY_LEFT = 3,
+  JOY_RIGHT = 4,
+  JOY_UP = 5
+} JOYState_TypeDef
+;
+#endif /* __STM32_EVAL_H */
+ 
+/** 
+  * @brief  IO_Expander Error codes  
+  */ 
+typedef enum
+{
+  IOE_OK = 0,
+  IOE_FAILURE, 
+  IOE_TIMEOUT,
+  PARAM_ERROR,
+  IOE1_NOT_OPERATIONAL, 
+  IOE2_NOT_OPERATIONAL
+}IOE_Status_TypDef;
+
+/** 
+  * @brief  IO bit values  
+  */ 
+typedef enum
+{
+  BitReset = 0,
+  BitSet = 1
+}IOE_BitValue_TypeDef;
+
+/** 
+  * @brief  IOE DMA Direction  
+  */ 
+typedef enum
+{
+  IOE_DMA_TX = 0,
+  IOE_DMA_RX = 1
+}IOE_DMADirection_TypeDef;
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210C_EVAL_IOE_Exported_Constants
+  * @{
+  */ 
+
+/**
+ * @brief Uncomment the line below to enable verfying each written byte in write
+ *        operation. The I2C_WriteDeviceRegister() function will then compare the
+ *        written and read data and return error status if a mismatch occurs.
+ */
+/* #define VERIFY_WRITTENDATA */
+
+/**
+ * @brief Uncomment the line below if you want to use user defined Delay function
+ *        (for precise timing), otherwise default _delay_ function defined within
+ *         this driver is used (less precise timing).  
+ */
+/* #define USE_Delay */
+
+/**
+ * @brief Uncomment the line below if you want to use user timeout callback.
+ *        Function prototypes is declared in this file but function body may be
+ *        implemented into user application.  
+ */
+/* #define USE_TIMEOUT_USER_CALLBACK */
+
+#ifdef USE_Delay
+#include "main.h"
+ 
+  #define _delay_     Delay  /* !< User can provide more timing precise _delay_ function
+                                   (with 10ms time base), using SysTick for example */
+#else
+  #define _delay_     delay      /* !< Default _delay_ function with less precise timing */
+#endif    
+
+/*------------------------------------------------------------------------------
+    Hardware Configuration 
+------------------------------------------------------------------------------*/
+/** 
+  * @brief  I2C port definitions  
+  */
+#define IOE_I2C                          I2C1
+#define IOE_I2C_CLK                      RCC_APB1Periph_I2C1
+#define IOE_I2C_SCL_PIN                  GPIO_Pin_6
+#define IOE_I2C_SCL_GPIO_PORT            GPIOB
+#define IOE_I2C_SCL_GPIO_CLK             RCC_APB2Periph_GPIOB
+#define IOE_I2C_SDA_PIN                  GPIO_Pin_7
+#define IOE_I2C_SDA_GPIO_PORT            GPIOB
+#define IOE_I2C_SDA_GPIO_CLK             RCC_APB2Periph_GPIOB
+#define IOE_I2C_DR                       ((uint32_t)0x40005410)
+#define IOE_I2C_SPEED                    300000  
+
+/** 
+  * @brief  IOE DMA definitions  
+  */
+#define IOE_DMA                          DMA1
+#define IOE_DMA_CLK                      RCC_AHBPeriph_DMA1
+#define IOE_DMA_TX_CHANNEL               DMA1_Channel6
+#define IOE_DMA_RX_CHANNEL               DMA1_Channel7
+#define IOE_DMA_TX_TCFLAG                DMA1_FLAG_TC6
+#define IOE_DMA_RX_TCFLAG                DMA1_FLAG_TC7
+
+
+/** 
+  * @brief  IO Expander Interrupt line on EXTI  
+  */ 
+#define IOE_IT_PIN                       GPIO_Pin_14
+#define IOE_IT_GPIO_PORT                 GPIOB
+#define IOE_IT_GPIO_CLK                  RCC_APB2Periph_GPIOB
+#define IOE_IT_EXTI_PORT_SOURCE          GPIO_PortSourceGPIOB
+#define IOE_IT_EXTI_PIN_SOURCE           GPIO_PinSource14
+#define IOE_IT_EXTI_LINE                 EXTI_Line14
+#define IOE_IT_EXTI_IRQn                 EXTI15_10_IRQn       
+
+/**
+  * @brief Eval Board IO Pins definition 
+  */ 
+#define AUDIO_RESET_PIN             IO_Pin_2 /* IO_Exapnader_2 */ /* Output */
+#define MII_INT_PIN                 IO_Pin_0 /* IO_Exapnader_2 */ /* Output */
+#define VBAT_DIV_PIN                IO_Pin_0 /* IO_Exapnader_1 */ /* Output */
+#define MEMS_INT1_PIN               IO_Pin_3 /* IO_Exapnader_1 */ /* Input */
+#define MEMS_INT2_PIN               IO_Pin_2 /* IO_Exapnader_1 */ /* Input */
+
+ 
+/**
+  * @brief Eval Board both IO Exapanders Pins definition 
+  */ 
+#define IO1_IN_ALL_PINS          (uint32_t)(MEMS_INT1_PIN | MEMS_INT2_PIN)
+#define IO2_IN_ALL_PINS          (uint32_t)(JOY_IO_PINS)
+#define IO1_OUT_ALL_PINS         (uint32_t)(VBAT_DIV_PIN)
+#define IO2_OUT_ALL_PINS         (uint32_t)(AUDIO_RESET_PIN | MII_INT_PIN)
+
+/** 
+  * @brief  The 7 bits IO Expanders adresses and chip IDs  
+  */ 
+#define IOE_1_ADDR                 0x82    
+#define IOE_2_ADDR                 0x88    
+#define STMPE811_ID                0x0811
+
+
+/*------------------------------------------------------------------------------
+    Functional and Interrupt Management
+------------------------------------------------------------------------------*/
+/** 
+  * @brief  IO Expander Functionalities definitions  
+  */ 
+#define IOE_ADC_FCT              0x01
+#define IOE_TS_FCT               0x02
+#define IOE_IO_FCT               0x04
+#define IOE_TEMPSENS_FCT         0x08
+
+/** 
+  * @brief  Interrupt source configuration definitons  
+  */ 
+#define IOE_ITSRC_TSC           0x01  /* IO_Exapnder 1 */
+#define IOE_ITSRC_INMEMS        0x02  /* IO_Exapnder 1 */
+#define IOE_ITSRC_JOYSTICK      0x04  /* IO_Exapnder 2 */
+#define IOE_ITSRC_TEMPSENS      0x08  /* IO_Exapnder 2 */
+
+/** 
+  * @brief  Glaobal Interrupts definitions  
+  */ 
+#define IOE_GIT_GPIO             0x80
+#define IOE_GIT_ADC              0x40
+#define IOE_GIT_TEMP             0x20
+#define IOE_GIT_FE               0x10
+#define IOE_GIT_FF               0x08
+#define IOE_GIT_FOV              0x04
+#define IOE_GIT_FTH              0x02
+#define IOE_GIT_TOUCH            0x01
+
+
+/*------------------------------------------------------------------------------
+    STMPE811 device register definition
+------------------------------------------------------------------------------*/
+/** 
+  * @brief  Identification registers  
+  */ 
+#define IOE_REG_CHP_ID             0x00
+#define IOE_REG_ID_VER             0x02
+
+/** 
+  * @brief  General Control Registers  
+  */ 
+#define IOE_REG_SYS_CTRL1          0x03
+#define IOE_REG_SYS_CTRL2          0x04
+#define IOE_REG_SPI_CFG            0x08 
+
+/** 
+  * @brief  Interrupt Control register  
+  */ 
+#define IOE_REG_INT_CTRL           0x09
+#define IOE_REG_INT_EN             0x0A
+#define IOE_REG_INT_STA            0x0B
+#define IOE_REG_GPIO_INT_EN        0x0C
+#define IOE_REG_GPIO_INT_STA       0x0D
+
+/** 
+  * @brief  GPIO Registers  
+  */ 
+#define IOE_REG_GPIO_SET_PIN       0x10
+#define IOE_REG_GPIO_CLR_PIN       0x11
+#define IOE_REG_GPIO_MP_STA        0x12
+#define IOE_REG_GPIO_DIR           0x13
+#define IOE_REG_GPIO_ED            0x14
+#define IOE_REG_GPIO_RE            0x15
+#define IOE_REG_GPIO_FE            0x16
+#define IOE_REG_GPIO_AF            0x17
+
+/** 
+  * @brief  ADC Registers  
+  */ 
+#define IOE_REG_ADC_INT_EN         0x0E
+#define IOE_REG_ADC_INT_STA        0x0F
+#define IOE_REG_ADC_CTRL1          0x20
+#define IOE_REG_ADC_CTRL2          0x21
+#define IOE_REG_ADC_CAPT           0x22
+#define IOE_REG_ADC_DATA_CH0       0x30 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH1       0x32 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH2       0x34 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH3       0x36 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH4       0x38 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH5       0x3A /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH6       0x3B /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH7       0x3C /* 16-Bit register */ 
+
+/** 
+  * @brief  TouchScreen Registers  
+  */ 
+#define IOE_REG_TSC_CTRL           0x40
+#define IOE_REG_TSC_CFG            0x41
+#define IOE_REG_WDM_TR_X           0x42 
+#define IOE_REG_WDM_TR_Y           0x44
+#define IOE_REG_WDM_BL_X           0x46
+#define IOE_REG_WDM_BL_Y           0x48
+#define IOE_REG_FIFO_TH            0x4A
+#define IOE_REG_FIFO_STA           0x4B
+#define IOE_REG_FIFO_SIZE          0x4C
+#define IOE_REG_TSC_DATA_X         0x4D 
+#define IOE_REG_TSC_DATA_Y         0x4F
+#define IOE_REG_TSC_DATA_Z         0x51
+#define IOE_REG_TSC_DATA_XYZ       0x52 
+#define IOE_REG_TSC_FRACT_XYZ      0x56
+#define IOE_REG_TSC_DATA           0x57
+#define IOE_REG_TSC_I_DRIVE        0x58
+#define IOE_REG_TSC_SHIELD         0x59
+
+/** 
+  * @brief  Temperature Sensor registers  
+  */ 
+#define IOE_REG_TEMP_CTRL          0x60
+#define IOE_REG_TEMP_DATA          0x61
+#define IOE_REG_TEMP_TH            0x62
+
+
+/*------------------------------------------------------------------------------
+    Functions parameters defines
+------------------------------------------------------------------------------*/
+/**
+  * @brief Touch Screen Pins definition 
+  */ 
+#define TOUCH_YD                    IO_Pin_1 /* IO_Exapnader_1 */ /* Input */
+#define TOUCH_XD                    IO_Pin_2 /* IO_Exapnader_1 */ /* Input */
+#define TOUCH_YU                    IO_Pin_3 /* IO_Exapnader_1 */ /* Input */
+#define TOUCH_XU                    IO_Pin_4 /* IO_Exapnader_1 */ /* Input */
+#define TOUCH_IO_ALL                (uint32_t)(IO_Pin_1 | IO_Pin_2 | IO_Pin_3 | IO_Pin_4)
+
+/**
+  * @brief  JOYSTICK Pins definition 
+  */ 
+#define JOY_IO_SEL                   IO_Pin_7
+#define JOY_IO_DOWN                  IO_Pin_6
+#define JOY_IO_LEFT                  IO_Pin_5
+#define JOY_IO_RIGHT                 IO_Pin_4
+#define JOY_IO_UP                    IO_Pin_3
+#define JOY_IO_NONE                  JOY_IO_PINS
+#define JOY_IO_PINS                  (uint32_t)(IO_Pin_3 | IO_Pin_4 | IO_Pin_5 | IO_Pin_6 | IO_Pin_7)
+
+/** 
+  * @brief  IO Pins  
+  */ 
+#define IO_Pin_0                 0x01
+#define IO_Pin_1                 0x02
+#define IO_Pin_2                 0x04
+#define IO_Pin_3                 0x08
+#define IO_Pin_4                 0x10
+#define IO_Pin_5                 0x20
+#define IO_Pin_6                 0x40
+#define IO_Pin_7                 0x80
+#define IO_Pin_ALL               0xFF
+
+/** 
+  * @brief  IO Pin directions  
+  */ 
+#define Direction_IN             0x00
+#define Direction_OUT            0x01
+
+/** 
+  * @brief  Interrupt Line output parameters  
+  */ 
+#define Polarity_Low             0x00
+#define Polarity_High            0x04
+#define Type_Level               0x00
+#define Type_Edge                0x02
+
+/** 
+  * @brief IO Interrupts  
+  */ 
+#define IO_IT_0                  0x01
+#define IO_IT_1                  0x02
+#define IO_IT_2                  0x04
+#define IO_IT_3                  0x08
+#define IO_IT_4                  0x10
+#define IO_IT_5                  0x20
+#define IO_IT_6                  0x40
+#define IO_IT_7                  0x80
+#define ALL_IT                   0xFF
+#define IOE_JOY_IT               (uint8_t)(IO_IT_3 | IO_IT_4 | IO_IT_5 | IO_IT_6 | IO_IT_7)
+#define IOE_TS_IT                (uint8_t)(IO_IT_0 | IO_IT_1 | IO_IT_2)
+#define IOE_INMEMS_IT            (uint8_t)(IO_IT_2 | IO_IT_3)
+
+/** 
+  * @brief  Edge detection value  
+  */ 
+#define EDGE_FALLING              0x01
+#define EDGE_RISING               0x02
+
+/** 
+  * @brief  Global interrupt Enable bit  
+  */ 
+#define IOE_GIT_EN                0x01
+
+/**
+  * @}
+  */ 
+
+
+
+/** @defgroup STM3210C_EVAL_IOE_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+
+/** @defgroup STM3210C_EVAL_IOE_Exported_Functions
+  * @{
+  */ 
+
+/** 
+  * @brief  Configuration and initialization functions  
+  */
+uint8_t IOE_Config(void);
+uint8_t IOE_ITConfig(uint32_t IOE_ITSRC_Source);
+
+/** 
+  * @brief  Timeout user callback function. This function is called when a timeout
+  *         condition occurs during communication with IO Expander. Only protoype
+  *         of this function is decalred in IO Expander driver. Its implementation
+  *         may be done into user application. This function may typically stop
+  *         current operations and reset the I2C peripheral and IO Expander.
+  *         To enable this function use uncomment the define USE_TIMEOUT_USER_CALLBACK
+  *         at the top of this file.          
+  */
+#ifdef USE_TIMEOUT_USER_CALLBACK 
+ uint8_t IOE_TimeoutUserCallback(void);
+#else
+ #define IOE_TimeoutUserCallback()  IOE_TIMEOUT
+#endif /* USE_TIMEOUT_USER_CALLBACK */
+
+/** 
+  * @brief IO pins control functions
+  */
+uint8_t IOE_WriteIOPin(uint8_t IO_Pin, IOE_BitValue_TypeDef BitVal);
+uint8_t IOE_ReadIOPin(uint32_t IO_Pin);
+JOYState_TypeDef
+ IOE_JoyStickGetState(void);
+
+/** 
+  * @brief Touch Screen controller functions
+  */
+TS_STATE* IOE_TS_GetState(void);
+
+/** 
+  * @brief Interrupts Mangement functions
+  */
+FlagStatus IOE_GetGITStatus(uint8_t DeviceAddr, uint8_t Global_IT);
+uint8_t IOE_ClearGITPending(uint8_t DeviceAddr, uint8_t IO_IT);
+FlagStatus IOE_GetIOITStatus(uint8_t DeviceAddr, uint8_t IO_IT);
+uint8_t IOE_ClearIOITPending(uint8_t DeviceAddr, uint8_t IO_IT);
+
+/** 
+  * @brief Temperature Sensor functions
+  */
+uint32_t IOE_TempSens_GetData(void);
+
+/** 
+  * @brief IO-Expander Control functions
+  */
+uint8_t IOE_IsOperational(uint8_t DeviceAddr);
+uint8_t IOE_Reset(uint8_t DeviceAddr);
+uint16_t IOE_ReadID(uint8_t DeviceAddr);
+
+uint8_t IOE_FnctCmd(uint8_t DeviceAddr, uint8_t Fct, FunctionalState NewState);
+uint8_t IOE_IOPinConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Direction);
+uint8_t IOE_GITCmd(uint8_t DeviceAddr, FunctionalState NewState);
+uint8_t IOE_GITConfig(uint8_t DeviceAddr, uint8_t Global_IT, FunctionalState NewState);
+uint8_t IOE_IOITConfig(uint8_t DeviceAddr, uint8_t IO_IT, FunctionalState NewState);
+
+/** 
+  * @brief Low Layer functions
+  */
+uint8_t IOE_TS_Config(void);
+uint8_t IOE_TempSens_Config(void);
+uint8_t IOE_IOAFConfig(uint8_t DeviceAddr, uint8_t IO_Pin, FunctionalState NewState);
+uint8_t IOE_IOEdgeConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Edge);
+uint8_t IOE_ITOutConfig(uint8_t Polarity, uint8_t Type);
+
+uint8_t I2C_WriteDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t RegisterValue);
+uint8_t I2C_ReadDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr);
+uint16_t I2C_ReadDataBuffer(uint8_t DeviceAddr, uint32_t RegisterAddr);
+
+#ifdef __cplusplus
+}
+
+#endif
+#endif /* __STM3210C_EVAL_IOE_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */     
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

+ 379 - 0
stm32f1_02/inc/stm3210c_eval_lcd.h

@@ -0,0 +1,379 @@
+/**
+  ******************************************************************************
+  * @file    stm3210c_eval_lcd.h
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   This file contains all the functions prototypes for the lcd firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM3210C_EVAL_LCD_H
+#define __STM3210C_EVAL_LCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+#include "../Common/fonts.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM3210C_EVAL
+  * @{
+  */
+    
+/** @addtogroup STM3210C_EVAL_LCD
+  * @{
+  */ 
+
+
+/** @defgroup STM3210C_EVAL_LCD_Exported_Types
+  * @{
+  */
+typedef struct 
+{
+  int16_t X;
+  int16_t Y;
+} Point, * pPoint;   
+/**
+  * @}
+  */ 
+
+/** @defgroup STM3210C_EVAL_LCD_Exported_Constants
+  * @{
+  */ 
+
+/**
+ * @brief Uncomment the line below if you want to use LCD_DrawBMP function to
+ *        display a bitmap picture on the LCD. This function assumes that the bitmap
+ *        file is loaded in the SPI Flash (mounted on STM3210C-EVAL board), however
+ *        user can tailor it according to his application hardware requirement.     
+ */
+/*#define USE_LCD_DrawBMP*/
+
+/**
+ * @brief Uncomment the line below if you want to use user defined Delay function
+ *        (for precise timing), otherwise default _delay_ function defined within
+ *         this driver is used (less precise timing).  
+ */
+/* #define USE_Delay */
+
+#ifdef USE_Delay
+#include "main.h"
+ 
+  #define _delay_     Delay  /* !< User can provide more timing precise _delay_ function
+                                   (with 10ms time base), using SysTick for example */
+#else
+  #define _delay_     delay      /* !< Default _delay_ function with less precise timing */
+#endif 
+
+/** 
+  * @brief  LCD Control pins  
+  */ 
+#define LCD_NCS_PIN             GPIO_Pin_2                  
+#define LCD_NCS_GPIO_PORT       GPIOB                       
+#define LCD_NCS_GPIO_CLK        RCC_APB2Periph_GPIOB  
+
+/** 
+  * @brief  LCD SPI Interface pins 
+  */ 
+#define LCD_SPI			            SPI3
+#define LCD_SPI_CLK		          RCC_APB1Periph_SPI3
+#define LCD_SPI_SCK_PIN         GPIO_Pin_10                 
+#define LCD_SPI_SCK_GPIO_PORT   GPIOC                       
+#define LCD_SPI_SCK_GPIO_CLK    RCC_APB2Periph_GPIOC  
+#define LCD_SPI_MISO_PIN        GPIO_Pin_11                 
+#define LCD_SPI_MISO_GPIO_PORT  GPIOC                       
+#define LCD_SPI_MISO_GPIO_CLK   RCC_APB2Periph_GPIOC  
+#define LCD_SPI_MOSI_PIN        GPIO_Pin_12                 
+#define LCD_SPI_MOSI_GPIO_PORT  GPIOC                       
+#define LCD_SPI_MOSI_GPIO_CLK   RCC_APB2Periph_GPIOC       
+
+/** 
+  * @brief  LCD Registers  
+  */ 
+#define LCD_REG_0             0x00
+#define LCD_REG_1             0x01
+#define LCD_REG_2             0x02
+#define LCD_REG_3             0x03
+#define LCD_REG_4             0x04
+#define LCD_REG_5             0x05
+#define LCD_REG_6             0x06
+#define LCD_REG_7             0x07
+#define LCD_REG_8             0x08
+#define LCD_REG_9             0x09
+#define LCD_REG_10            0x0A
+#define LCD_REG_12            0x0C
+#define LCD_REG_13            0x0D
+#define LCD_REG_14            0x0E
+#define LCD_REG_15            0x0F
+#define LCD_REG_16            0x10
+#define LCD_REG_17            0x11
+#define LCD_REG_18            0x12
+#define LCD_REG_19            0x13
+#define LCD_REG_20            0x14
+#define LCD_REG_21            0x15
+#define LCD_REG_22            0x16
+#define LCD_REG_23            0x17
+#define LCD_REG_24            0x18
+#define LCD_REG_25            0x19
+#define LCD_REG_26            0x1A
+#define LCD_REG_27            0x1B
+#define LCD_REG_28            0x1C
+#define LCD_REG_29            0x1D
+#define LCD_REG_30            0x1E
+#define LCD_REG_31            0x1F
+#define LCD_REG_32            0x20
+#define LCD_REG_33            0x21
+#define LCD_REG_34            0x22
+#define LCD_REG_36            0x24
+#define LCD_REG_37            0x25
+#define LCD_REG_40            0x28
+#define LCD_REG_41            0x29
+#define LCD_REG_43            0x2B
+#define LCD_REG_45            0x2D
+#define LCD_REG_48            0x30
+#define LCD_REG_49            0x31
+#define LCD_REG_50            0x32
+#define LCD_REG_51            0x33
+#define LCD_REG_52            0x34
+#define LCD_REG_53            0x35
+#define LCD_REG_54            0x36
+#define LCD_REG_55            0x37
+#define LCD_REG_56            0x38
+#define LCD_REG_57            0x39
+#define LCD_REG_59            0x3B
+#define LCD_REG_60            0x3C
+#define LCD_REG_61            0x3D
+#define LCD_REG_62            0x3E
+#define LCD_REG_63            0x3F
+#define LCD_REG_64            0x40
+#define LCD_REG_65            0x41
+#define LCD_REG_66            0x42
+#define LCD_REG_67            0x43
+#define LCD_REG_68            0x44
+#define LCD_REG_69            0x45
+#define LCD_REG_70            0x46
+#define LCD_REG_71            0x47
+#define LCD_REG_72            0x48
+#define LCD_REG_73            0x49
+#define LCD_REG_74            0x4A
+#define LCD_REG_75            0x4B
+#define LCD_REG_76            0x4C
+#define LCD_REG_77            0x4D
+#define LCD_REG_78            0x4E
+#define LCD_REG_79            0x4F
+#define LCD_REG_80            0x50
+#define LCD_REG_81            0x51
+#define LCD_REG_82            0x52
+#define LCD_REG_83            0x53
+#define LCD_REG_96            0x60
+#define LCD_REG_97            0x61
+#define LCD_REG_106           0x6A
+#define LCD_REG_118           0x76
+#define LCD_REG_128           0x80
+#define LCD_REG_129           0x81
+#define LCD_REG_130           0x82
+#define LCD_REG_131           0x83
+#define LCD_REG_132           0x84
+#define LCD_REG_133           0x85
+#define LCD_REG_134           0x86
+#define LCD_REG_135           0x87
+#define LCD_REG_136           0x88
+#define LCD_REG_137           0x89
+#define LCD_REG_139           0x8B
+#define LCD_REG_140           0x8C
+#define LCD_REG_141           0x8D
+#define LCD_REG_143           0x8F
+#define LCD_REG_144           0x90
+#define LCD_REG_145           0x91
+#define LCD_REG_146           0x92
+#define LCD_REG_147           0x93
+#define LCD_REG_148           0x94
+#define LCD_REG_149           0x95
+#define LCD_REG_150           0x96
+#define LCD_REG_151           0x97
+#define LCD_REG_152           0x98
+#define LCD_REG_153           0x99
+#define LCD_REG_154           0x9A
+#define LCD_REG_157           0x9D
+#define LCD_REG_192           0xC0
+#define LCD_REG_193           0xC1
+#define LCD_REG_229           0xE5
+
+/** 
+  * @brief  LCD color  
+  */ 
+#define LCD_COLOR_WHITE          0xFFFF
+#define LCD_COLOR_BLACK          0x0000
+#define LCD_COLOR_GREY           0xF7DE
+#define LCD_COLOR_BLUE           0x001F
+#define LCD_COLOR_BLUE2          0x051F
+#define LCD_COLOR_RED            0xF800
+#define LCD_COLOR_MAGENTA        0xF81F
+#define LCD_COLOR_GREEN          0x07E0
+#define LCD_COLOR_CYAN           0x7FFF
+#define LCD_COLOR_YELLOW         0xFFE0
+
+/** 
+  * @brief  LCD Lines depending on the chosen fonts.  
+  */ 
+#define LCD_LINE_0               LINE(0)
+#define LCD_LINE_1               LINE(1)
+#define LCD_LINE_2               LINE(2)
+#define LCD_LINE_3               LINE(3)
+#define LCD_LINE_4               LINE(4)
+#define LCD_LINE_5               LINE(5)
+#define LCD_LINE_6               LINE(6)
+#define LCD_LINE_7               LINE(7)
+#define LCD_LINE_8               LINE(8)
+#define LCD_LINE_9               LINE(9)
+#define LCD_LINE_10              LINE(10)
+#define LCD_LINE_11              LINE(11)
+#define LCD_LINE_12              LINE(12)
+#define LCD_LINE_13              LINE(13)
+#define LCD_LINE_14              LINE(14)
+#define LCD_LINE_15              LINE(15)
+#define LCD_LINE_16              LINE(16)
+#define LCD_LINE_17              LINE(17)
+#define LCD_LINE_18              LINE(18)
+#define LCD_LINE_19              LINE(19)
+#define LCD_LINE_20              LINE(20)
+#define LCD_LINE_21              LINE(21)
+#define LCD_LINE_22              LINE(22)
+#define LCD_LINE_23              LINE(23)
+#define LCD_LINE_24              LINE(24)
+#define LCD_LINE_25              LINE(25)
+#define LCD_LINE_26              LINE(26)
+#define LCD_LINE_27              LINE(27)
+#define LCD_LINE_28              LINE(28)
+#define LCD_LINE_29              LINE(29)
+
+/** 
+  * @brief LCD default font 
+  */ 
+#define LCD_DEFAULT_FONT         Font16x24
+
+/** 
+  * @brief  LCD Direction  
+  */ 
+#define LCD_DIR_HORIZONTAL       0x0000
+#define LCD_DIR_VERTICAL         0x0001
+
+/** 
+  * @brief  LCD Size (Width and Height)  
+  */ 
+#define LCD_PIXEL_WIDTH          0x0140
+#define LCD_PIXEL_HEIGHT         0x00F0
+
+/**
+  * @}
+  */ 
+
+/** @defgroup STM3210C_EVAL_LCD_Exported_Macros
+  * @{
+  */
+#define ASSEMBLE_RGB(R, G, B)    ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))   
+/**
+  * @}
+  */ 
+
+/** @defgroup STM3210C_EVAL_LCD_Exported_Functions
+  * @{
+  */
+void LCD_DeInit(void);   
+void LCD_Setup(void);
+void STM3210C_LCD_Init(void);
+void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor); 
+void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor);
+void LCD_SetTextColor(__IO uint16_t Color);
+void LCD_SetBackColor(__IO uint16_t Color);
+void LCD_ClearLine(uint8_t Line);
+void LCD_Clear(uint16_t Color);
+void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos);
+void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c);
+void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii);
+void LCD_SetFont(sFONT *fonts);
+sFONT *LCD_GetFont(void);
+void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr);
+void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
+void LCD_WindowModeDisable(void);
+void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction);
+void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
+void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius);
+void LCD_DrawMonoPict(const uint32_t *Pict);
+#ifdef USE_LCD_DrawBMP
+//void LCD_DrawBMP(uint32_t BmpAddress);
+void LCD_DrawBMP(const uint16_t *BmpAddress);
+#endif 
+void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2);
+void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);
+void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius);
+void LCD_PolyLine(pPoint Points, uint16_t PointCount);
+void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount);
+void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount);
+void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount);
+void LCD_FillPolyLine(pPoint Points, uint16_t PointCount);
+
+void LCD_nCS_StartByte(uint8_t Start_Byte);
+void LCD_WriteRegIndex(uint8_t LCD_Reg);
+void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue);
+void LCD_WriteRAM_Prepare(void);
+void LCD_WriteRAMWord(uint16_t RGB_Code);
+uint16_t LCD_ReadReg(uint8_t LCD_Reg);
+void LCD_WriteRAM(uint16_t RGB_Code);
+void LCD_PowerOn(void);
+void LCD_DisplayOn(void);
+void LCD_DisplayOff(void);
+
+void LCD_CtrlLinesConfig(void);
+void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal);
+void LCD_SPIConfig(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM3210C_EVAL_LCD_H */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+     
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

+ 368 - 0
stm32f1_02/inc/stm32_eval.h

@@ -0,0 +1,368 @@
+/**
+  ******************************************************************************
+  * @file    stm32_eval.h
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   Header file for stm32_eval.c module.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+  
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_EVAL_H
+#define __STM32_EVAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Includes ------------------------------------------------------------------*/
+
+/** @addtogroup Utilities
+  * @{
+  */ 
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @defgroup STM32_EVAL_Abstraction_Layer
+  * @{
+  */
+  
+/** @defgroup STM32_EVAL_HARDWARE_RESOURCES
+  * @{
+  */
+
+/**
+@code  
+ The table below gives an overview of the hardware resources supported by each 
+ STM32 EVAL board.
+     - LCD: TFT Color LCD (Parallel (FSMC) and Serial (SPI))
+     - IOE: IO Expander on I2C
+     - sFLASH: serial SPI FLASH (M25Pxxx)
+     - sEE: serial I2C EEPROM (M24C08, M24C32, M24C64)
+     - TSENSOR: Temperature Sensor (LM75)
+     - SD: SD Card memory (SPI and SDIO (SD Card MODE)) 
+  =================================================================================================================+
+    STM32 EVAL     | LED | Buttons  | Com Ports |    LCD    | IOE  | sFLASH | sEE | TSENSOR | SD (SPI) | SD(SDIO)  |
+  =================================================================================================================+
+   STM3210B-EVAL   |  4  |    8     |     2     | YES (SPI) | NO   |  YES   | NO  |   YES   |    YES   |    NO     |
+  -----------------------------------------------------------------------------------------------------------------+
+   STM3210E-EVAL   |  4  |    8     |     2     | YES (FSMC)| NO   |  YES   | NO  |   YES   |    NO    |    YES    |
+  -----------------------------------------------------------------------------------------------------------------+
+   STM3210C-EVAL   |  4  |    3     |     1     | YES (SPI) | YES  |  NO    | YES |   NO    |    YES   |    NO     |
+  -----------------------------------------------------------------------------------------------------------------+
+   STM32100B-EVAL  |  4  |    8     |     2     | YES (SPI) | NO   |  YES   | NO  |   YES   |    YES   |    NO     |
+  -----------------------------------------------------------------------------------------------------------------+
+   STM32L152-EVAL  |  4  |    8     |     2     | YES (SPI) | NO   |  NO    | NO  |   YES   |    YES   |    NO     |
+  -----------------------------------------------------------------------------------------------------------------+
+   STM32100E-EVAL  |  4  |    8     |     2     | YES (FSMC)| YES  |  YES   | YES |   YES   |    YES   |    NO     |
+  =================================================================================================================+
+@endcode
+*/
+
+/**
+  * @}
+  */
+  
+/** @defgroup STM32_EVAL_Exported_Types
+  * @{
+  */
+typedef enum 
+{
+  LED1 = 0,
+  LED2 = 1,
+  LED3 = 2,
+  LED4 = 3
+} Led_TypeDef;
+
+typedef enum 
+{  
+  BUTTON_WAKEUP = 0,
+  BUTTON_TAMPER = 1,
+  BUTTON_KEY = 2,
+  BUTTON_RIGHT = 3,
+  BUTTON_LEFT = 4,
+  BUTTON_UP = 5,
+  BUTTON_DOWN = 6,
+  BUTTON_SEL = 7
+} Button_TypeDef;
+
+typedef enum 
+{  
+  BUTTON_MODE_GPIO = 0,
+  BUTTON_MODE_EXTI = 1
+} ButtonMode_TypeDef;
+
+typedef enum 
+{ 
+  JOY_NONE = 0,
+  JOY_SEL = 1,
+  JOY_DOWN = 2,
+  JOY_LEFT = 3,
+  JOY_RIGHT = 4,
+  JOY_UP = 5
+} JOYState_TypeDef
+;
+
+typedef enum 
+{
+  COM1 = 0,
+  COM2 = 1
+} COM_TypeDef;   
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM32_EVAL_Exported_Constants
+  * @{
+  */
+
+/** 
+  * @brief  Uncomment the line corresponding to the STMicroelectronics evaluation
+  *   board used in your application.
+  *   
+  *  Tip: To avoid modifying this file each time you need to switch between these
+  *       boards, you can define the board in your toolchain compiler preprocessor.    
+  */ 
+#if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL)\
+   &&  !defined (USE_STM3210C_EVAL) &&  !defined (USE_STM32L152_EVAL) &&  !defined (USE_STM32100E_EVAL)
+ //#define USE_STM32100B_EVAL
+ //#define USE_STM3210B_EVAL
+ //#define USE_STM3210E_EVAL
+#define USE_STM3210C_EVAL
+ //#define USE_STM32L152_EVAL
+ //#define USE_STM32100E_EVAL
+#endif
+
+#ifdef USE_STM32100B_EVAL
+ #include "stm32f10x.h"
+ #include "stm32100b_eval/stm32100b_eval.h"
+#elif defined USE_STM3210B_EVAL
+ #include "stm32f10x.h"
+ #include "stm3210b_eval/stm3210b_eval.h" 
+#elif defined USE_STM3210E_EVAL
+ #include "stm32f10x.h"
+ #include "stm3210e_eval/stm3210e_eval.h"
+#elif defined USE_STM3210C_EVAL
+ #include "stm32f10x.h"
+ #include "stm3210c_eval.h"
+#elif defined USE_STM32L152_EVAL
+ #include "stm32l1xx.h"
+ #include "stm32l152_eval/stm32l152_eval.h" 
+#elif defined USE_STM32100E_EVAL
+ #include "stm32f10x.h"
+ #include "stm32100e_eval/stm32100e_eval.h"
+#else 
+ #error "Please select first the STM32 EVAL board to be used (in stm32_eval.h)"
+#endif                      
+
+
+/** 
+  * @brief  STM32 Button Defines Legacy  
+  */ 
+#define Button_WAKEUP        BUTTON_WAKEUP
+#define Button_TAMPER        BUTTON_TAMPER
+#define Button_KEY           BUTTON_KEY
+#define Button_RIGHT         BUTTON_RIGHT
+#define Button_LEFT          BUTTON_LEFT
+#define Button_UP            BUTTON_UP
+#define Button_DOWN          BUTTON_DOWN
+#define Button_SEL           BUTTON_SEL
+#define Mode_GPIO            BUTTON_MODE_GPIO
+#define Mode_EXTI            BUTTON_MODE_EXTI
+#define Button_Mode_TypeDef  ButtonMode_TypeDef
+#define JOY_CENTER           JOY_SEL
+#define JOY_State_TypeDef    JOYState_TypeDef 
+
+/** 
+  * @brief  LCD Defines Legacy  
+  */ 
+#define LCD_RSNWR_GPIO_CLK  LCD_NWR_GPIO_CLK
+#define LCD_SPI_GPIO_PORT   LCD_SPI_SCK_GPIO_PORT
+#define LCD_SPI_GPIO_CLK    LCD_SPI_SCK_GPIO_CLK
+#define R0                  LCD_REG_0
+#define R1                  LCD_REG_1
+#define R2                  LCD_REG_2
+#define R3                  LCD_REG_3
+#define R4                  LCD_REG_4
+#define R5                  LCD_REG_5
+#define R6                  LCD_REG_6
+#define R7                  LCD_REG_7
+#define R8                  LCD_REG_8
+#define R9                  LCD_REG_9
+#define R10                 LCD_REG_10
+#define R12                 LCD_REG_12
+#define R13                 LCD_REG_13
+#define R14                 LCD_REG_14
+#define R15                 LCD_REG_15
+#define R16                 LCD_REG_16
+#define R17                 LCD_REG_17
+#define R18                 LCD_REG_18
+#define R19                 LCD_REG_19
+#define R20                 LCD_REG_20
+#define R21                 LCD_REG_21
+#define R22                 LCD_REG_22
+#define R23                 LCD_REG_23
+#define R24                 LCD_REG_24
+#define R25                 LCD_REG_25
+#define R26                 LCD_REG_26
+#define R27                 LCD_REG_27
+#define R28                 LCD_REG_28
+#define R29                 LCD_REG_29
+#define R30                 LCD_REG_30
+#define R31                 LCD_REG_31
+#define R32                 LCD_REG_32
+#define R33                 LCD_REG_33
+#define R34                 LCD_REG_34
+#define R36                 LCD_REG_36
+#define R37                 LCD_REG_37
+#define R40                 LCD_REG_40
+#define R41                 LCD_REG_41
+#define R43                 LCD_REG_43
+#define R45                 LCD_REG_45
+#define R48                 LCD_REG_48
+#define R49                 LCD_REG_49
+#define R50                 LCD_REG_50
+#define R51                 LCD_REG_51
+#define R52                 LCD_REG_52
+#define R53                 LCD_REG_53
+#define R54                 LCD_REG_54
+#define R55                 LCD_REG_55
+#define R56                 LCD_REG_56
+#define R57                 LCD_REG_57
+#define R59                 LCD_REG_59
+#define R60                 LCD_REG_60
+#define R61                 LCD_REG_61
+#define R62                 LCD_REG_62
+#define R63                 LCD_REG_63
+#define R64                 LCD_REG_64
+#define R65                 LCD_REG_65
+#define R66                 LCD_REG_66
+#define R67                 LCD_REG_67
+#define R68                 LCD_REG_68
+#define R69                 LCD_REG_69
+#define R70                 LCD_REG_70
+#define R71                 LCD_REG_71
+#define R72                 LCD_REG_72
+#define R73                 LCD_REG_73
+#define R74                 LCD_REG_74
+#define R75                 LCD_REG_75
+#define R76                 LCD_REG_76
+#define R77                 LCD_REG_77
+#define R78                 LCD_REG_78
+#define R79                 LCD_REG_79
+#define R80                 LCD_REG_80
+#define R81                 LCD_REG_81
+#define R82                 LCD_REG_82
+#define R83                 LCD_REG_83
+#define R96                 LCD_REG_96
+#define R97                 LCD_REG_97
+#define R106                LCD_REG_106
+#define R118                LCD_REG_118
+#define R128                LCD_REG_128
+#define R129                LCD_REG_129
+#define R130                LCD_REG_130
+#define R131                LCD_REG_131
+#define R132                LCD_REG_132
+#define R133                LCD_REG_133
+#define R134                LCD_REG_134
+#define R135                LCD_REG_135
+#define R136                LCD_REG_136
+#define R137                LCD_REG_137
+#define R139                LCD_REG_139
+#define R140                LCD_REG_140
+#define R141                LCD_REG_141
+#define R143                LCD_REG_143
+#define R144                LCD_REG_144
+#define R145                LCD_REG_145
+#define R146                LCD_REG_146
+#define R147                LCD_REG_147
+#define R148                LCD_REG_148
+#define R149                LCD_REG_149
+#define R150                LCD_REG_150
+#define R151                LCD_REG_151
+#define R152                LCD_REG_152
+#define R153                LCD_REG_153
+#define R154                LCD_REG_154
+#define R157                LCD_REG_157
+#define R192                LCD_REG_192
+#define R193                LCD_REG_193
+#define R227                LCD_REG_227
+#define R229                LCD_REG_229
+#define R231                LCD_REG_231
+#define R239                LCD_REG_239
+#define White               LCD_COLOR_WHITE
+#define Black               LCD_COLOR_BLACK
+#define Grey                LCD_COLOR_GREY
+#define Blue                LCD_COLOR_BLUE
+#define Blue2               LCD_COLOR_BLUE2
+#define Red                 LCD_COLOR_RED
+#define Magenta             LCD_COLOR_MAGENTA
+#define Green               LCD_COLOR_GREEN
+#define Cyan                LCD_COLOR_CYAN
+#define Yellow              LCD_COLOR_YELLOW
+#define Line0               LCD_LINE_0
+#define Line1               LCD_LINE_1
+#define Line2               LCD_LINE_2
+#define Line3               LCD_LINE_3
+#define Line4               LCD_LINE_4
+#define Line5               LCD_LINE_5
+#define Line6               LCD_LINE_6
+#define Line7               LCD_LINE_7
+#define Line8               LCD_LINE_8
+#define Line9               LCD_LINE_9
+#define Horizontal          LCD_DIR_HORIZONTAL
+#define Vertical            LCD_DIR_VERTICAL
+
+
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32_EVAL_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32_EVAL_Exported_Functions
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32_EVAL_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */   
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

+ 201 - 0
stm32f1_02/inc/stm32_eval_i2c_ee.h

@@ -0,0 +1,201 @@
+/**
+  ******************************************************************************
+  * @file    stm32_eval_i2c_ee.h
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   This file contains all the functions prototypes for the stm32_eval_i2c_ee
+  *          firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_EVAL_I2C_EE_H
+#define __STM32_EVAL_I2C_EE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32_eval.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup Common
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL_I2C_EE
+  * @{
+  */  
+
+/** @defgroup STM32_EVAL_I2C_EE_Exported_Types
+  * @{
+  */ 
+
+/**
+  * @}
+  */
+  
+/** @defgroup STM32_EVAL_I2C_EE_Exported_Constants
+  * @{
+  */
+  
+/* Uncomment this line to use the default start and end of critical section 
+   callbacks (it disables then enabled all interrupts) */
+#define USE_DEFAULT_CRITICAL_CALLBACK 
+/* Start and End of critical section: these callbacks should be typically used
+   to disable interrupts when entering a critical section of I2C communication
+   You may use default callbacks provided into this driver by uncommenting the 
+   define USE_DEFAULT_CRITICAL_CALLBACK.
+   Or you can comment that line and implement these callbacks into your 
+   application */
+
+/* Uncomment the following line to use the default sEE_TIMEOUT_UserCallback() 
+   function implemented in stm32_evel_i2c_ee.c file.
+   sEE_TIMEOUT_UserCallback() function is called whenever a timeout condition 
+   occure during communication (waiting on an event that doesn't occur, bus 
+   errors, busy devices ...). */   
+/* #define USE_DEFAULT_TIMEOUT_CALLBACK */
+   
+#if !defined (sEE_M24C08) && !defined (sEE_M24C64_32)
+/* Use the defines below the choose the EEPROM type */
+/* #define sEE_M24C08*/  /* Support the device: M24C08. */
+/* note: Could support: M24C01, M24C02, M24C04 and M24C16 if the blocks and 
+   HW address are correctly defined*/
+#define sEE_M24C64_32  /* Support the devices: M24C32 and M24C64 */
+#endif
+
+#ifdef sEE_M24C64_32
+/* For M24C32 and M24C64 devices, E0,E1 and E2 pins are all used for device 
+  address selection (ne need for additional address lines). According to the 
+  Harware connection on the board (on STM3210C-EVAL board E0 = E1 = E2 = 0) */
+
+ #define sEE_HW_ADDRESS         0xA0   /* E0 = E1 = E2 = 0 */ 
+
+#elif defined (sEE_M24C08)
+/* The M24C08W contains 4 blocks (128byte each) with the adresses below: E2 = 0 
+   EEPROM Addresses defines */
+ #define sEE_Block0_ADDRESS     0xA0   /* E2 = 0 */ 
+ /*#define sEE_Block1_ADDRESS     0xA2*/ /* E2 = 0 */  
+ /*#define sEE_Block2_ADDRESS     0xA4*/ /* E2 = 0 */
+ /*#define sEE_Block3_ADDRESS     0xA6*/ /* E2 = 0 */
+
+#endif /* sEE_M24C64_32 */
+
+#define I2C_SPEED               300000
+#define I2C_SLAVE_ADDRESS7      0xA0
+
+#if defined (sEE_M24C08)
+ #define sEE_PAGESIZE           16
+#elif defined (sEE_M24C64_32)
+ #define sEE_PAGESIZE           32
+#endif
+   
+/* Maximum Timeout values for flags and events waiting loops. These timeouts are
+   not based on accurate values, they just guarantee that the application will 
+   not remain stuck if the I2C communication is corrupted.
+   You may modify these timeout values depending on CPU frequency and application
+   conditions (interrupts routines ...). */   
+#define sEE_FLAG_TIMEOUT         ((uint32_t)0x1000)
+#define sEE_LONG_TIMEOUT         ((uint32_t)(10 * sEE_FLAG_TIMEOUT))
+
+/* Maximum number of trials for sEE_WaitEepromStandbyState() function */
+#define sEE_MAX_TRIALS_NUMBER     150
+   
+/* Defintions for the state of the DMA transfer */   
+#define sEE_STATE_READY           0
+#define sEE_STATE_BUSY            1
+#define sEE_STATE_ERROR           2
+   
+#define sEE_OK                    0
+#define sEE_FAIL                  1   
+
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM32_EVAL_I2C_EE_Exported_Macros
+  * @{
+  */    
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32_EVAL_I2C_EE_Exported_Functions
+  * @{
+  */ 
+void     sEE_DeInit(void);
+void     sEE_Init(void);
+uint32_t sEE_ReadBuffer(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t* NumByteToRead);
+uint32_t sEE_WritePage(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t* NumByteToWrite);
+void     sEE_WriteBuffer(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite);
+uint32_t sEE_WaitEepromStandbyState(void);
+
+/* USER Callbacks: These are functions for which prototypes only are declared in
+   EEPROM driver and that should be implemented into user applicaiton. */  
+/* sEE_TIMEOUT_UserCallback() function is called whenever a timeout condition 
+   occure during communication (waiting on an event that doesn't occur, bus 
+   errors, busy devices ...).
+   You can use the default timeout callback implementation by uncommenting the 
+   define USE_DEFAULT_TIMEOUT_CALLBACK in stm32_evel_i2c_ee.h file.
+   Typically the user implementation of this callback should reset I2C peripheral
+   and re-initialize communication or in worst case reset all the application. */
+uint32_t sEE_TIMEOUT_UserCallback(void);
+
+/* Start and End of critical section: these callbacks should be typically used
+   to disable interrupts when entering a critical section of I2C communication
+   You may use default callbacks provided into this driver by uncommenting the 
+   define USE_DEFAULT_CRITICAL_CALLBACK in stm32_evel_i2c_ee.h file..
+   Or you can comment that line and implement these callbacks into your 
+   application */
+void sEE_EnterCriticalSection_UserCallback(void);
+void sEE_ExitCriticalSection_UserCallback(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_EVAL_I2C_EE_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
+

+ 173 - 0
stm32f1_02/inc/stm32_eval_i2c_tsensor.h

@@ -0,0 +1,173 @@
+/**
+  ******************************************************************************
+  * @file    stm32_eval_i2c_tsensor.h
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   This file contains all the functions prototypes for the 
+  *          stm32_eval_i2c_tsensor firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_EVAL_I2C_TSENSOR_H
+#define __STM32_EVAL_I2C_TSENSOR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32_eval.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup Common
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL_I2C_TSENSOR
+  * @{
+  */  
+
+/** @defgroup STM32_EVAL_I2C_TSENSOR_Exported_Types
+  * @{
+  */
+   
+ /** 
+  * @brief  IOE DMA Direction  
+  */ 
+typedef enum
+{
+  LM75_DMA_TX = 0,
+  LM75_DMA_RX = 1
+}LM75_DMADirection_TypeDef;
+
+/** 
+  * @brief  TSENSOR Status  
+  */ 
+typedef enum
+{
+  LM75_OK = 0,
+  LM75_FAIL
+}LM75_Status_TypDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup STM32_EVAL_I2C_TSENSOR_Exported_Constants
+  * @{
+  */ 
+    
+/* Uncomment the following line to use Timeout_User_Callback LM75_TimeoutUserCallback(). 
+   If This Callback is enabled, it should be implemented by user in main function .
+   LM75_TimeoutUserCallback() function is called whenever a timeout condition 
+   occure during communication (waiting on an event that doesn't occur, bus 
+   errors, busy devices ...). */   
+/* #define USE_TIMEOUT_USER_CALLBACK */    
+    
+/* Maximum Timeout values for flags and events waiting loops. These timeouts are
+   not based on accurate values, they just guarantee that the application will 
+   not remain stuck if the I2C communication is corrupted.
+   You may modify these timeout values depending on CPU frequency and application
+   conditions (interrupts routines ...). */   
+#define LM75_FLAG_TIMEOUT         ((uint32_t)0x1000)
+#define LM75_LONG_TIMEOUT         ((uint32_t)(10 * LM75_FLAG_TIMEOUT))    
+    
+
+/**
+  * @brief  Block Size
+  */
+#define LM75_REG_TEMP       0x00  /*!< Temperature Register of LM75 */
+#define LM75_REG_CONF       0x01  /*!< Configuration Register of LM75 */
+#define LM75_REG_THYS       0x02  /*!< Temperature Register of LM75 */
+#define LM75_REG_TOS        0x03  /*!< Over-temp Shutdown threshold Register of LM75 */
+#define I2C_TIMEOUT         ((uint32_t)0x3FFFF) /*!< I2C Time out */
+#define LM75_ADDR           0x90   /*!< LM75 address */
+#define LM75_I2C_SPEED      100000 /*!< I2C Speed */
+  
+   
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32_EVAL_I2C_TSENSOR_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32_EVAL_I2C_TSENSOR_Exported_Functions
+  * @{
+  */ 
+void LM75_DeInit(void);
+void LM75_Init(void);
+ErrorStatus LM75_GetStatus(void);
+uint16_t LM75_ReadTemp(void);
+uint16_t LM75_ReadReg(uint8_t RegName);
+uint8_t LM75_WriteReg(uint8_t RegName, uint16_t RegValue);
+uint8_t LM75_ReadConfReg(void);
+uint8_t LM75_WriteConfReg(uint8_t RegValue);
+uint8_t LM75_ShutDown(FunctionalState NewState);
+
+/** 
+  * @brief  Timeout user callback function. This function is called when a timeout
+  *         condition occurs during communication with IO Expander. Only protoype
+  *         of this function is decalred in IO Expander driver. Its implementation
+  *         may be done into user application. This function may typically stop
+  *         current operations and reset the I2C peripheral and IO Expander.
+  *         To enable this function use uncomment the define USE_TIMEOUT_USER_CALLBACK
+  *         at the top of this file.          
+  */
+#ifdef USE_TIMEOUT_USER_CALLBACK 
+ uint8_t LM75_TIMEOUT_UserCallback(void);
+#else
+ #define LM75_TIMEOUT_UserCallback()  LM75_FAIL
+#endif /* USE_TIMEOUT_USER_CALLBACK */
+ 
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_EVAL_I2C_TSENSOR_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

+ 397 - 0
stm32f1_02/inc/stm32_eval_sdio_sd.h

@@ -0,0 +1,397 @@
+/**
+  ******************************************************************************
+  * @file    stm32_eval_sdio_sd.h
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   This file contains all the functions prototypes for the SD Card 
+  *          stm32_eval_sdio_sd driver firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_EVAL_SDIO_SD_H
+#define __STM32_EVAL_SDIO_SD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32_eval.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup Common
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL_SDIO_SD
+  * @{
+  */  
+
+/** @defgroup STM32_EVAL_SDIO_SD_Exported_Types
+  * @{
+  */ 
+typedef enum
+{
+/** 
+  * @brief  SDIO specific error defines  
+  */   
+  SD_CMD_CRC_FAIL                    = (1), /*!< Command response received (but CRC check failed) */
+  SD_DATA_CRC_FAIL                   = (2), /*!< Data bock sent/received (CRC check Failed) */
+  SD_CMD_RSP_TIMEOUT                 = (3), /*!< Command response timeout */
+  SD_DATA_TIMEOUT                    = (4), /*!< Data time out */
+  SD_TX_UNDERRUN                     = (5), /*!< Transmit FIFO under-run */
+  SD_RX_OVERRUN                      = (6), /*!< Receive FIFO over-run */
+  SD_START_BIT_ERR                   = (7), /*!< Start bit not detected on all data signals in widE bus mode */
+  SD_CMD_OUT_OF_RANGE                = (8), /*!< CMD's argument was out of range.*/
+  SD_ADDR_MISALIGNED                 = (9), /*!< Misaligned address */
+  SD_BLOCK_LEN_ERR                   = (10), /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
+  SD_ERASE_SEQ_ERR                   = (11), /*!< An error in the sequence of erase command occurs.*/
+  SD_BAD_ERASE_PARAM                 = (12), /*!< An Invalid selection for erase groups */
+  SD_WRITE_PROT_VIOLATION            = (13), /*!< Attempt to program a write protect block */
+  SD_LOCK_UNLOCK_FAILED              = (14), /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
+  SD_COM_CRC_FAILED                  = (15), /*!< CRC check of the previous command failed */
+  SD_ILLEGAL_CMD                     = (16), /*!< Command is not legal for the card state */
+  SD_CARD_ECC_FAILED                 = (17), /*!< Card internal ECC was applied but failed to correct the data */
+  SD_CC_ERROR                        = (18), /*!< Internal card controller error */
+  SD_GENERAL_UNKNOWN_ERROR           = (19), /*!< General or Unknown error */
+  SD_STREAM_READ_UNDERRUN            = (20), /*!< The card could not sustain data transfer in stream read operation. */
+  SD_STREAM_WRITE_OVERRUN            = (21), /*!< The card could not sustain data programming in stream mode */
+  SD_CID_CSD_OVERWRITE               = (22), /*!< CID/CSD overwrite error */
+  SD_WP_ERASE_SKIP                   = (23), /*!< only partial address space was erased */
+  SD_CARD_ECC_DISABLED               = (24), /*!< Command has been executed without using internal ECC */
+  SD_ERASE_RESET                     = (25), /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
+  SD_AKE_SEQ_ERROR                   = (26), /*!< Error in sequence of authentication. */
+  SD_INVALID_VOLTRANGE               = (27),
+  SD_ADDR_OUT_OF_RANGE               = (28),
+  SD_SWITCH_ERROR                    = (29),
+  SD_SDIO_DISABLED                   = (30),
+  SD_SDIO_FUNCTION_BUSY              = (31),
+  SD_SDIO_FUNCTION_FAILED            = (32),
+  SD_SDIO_UNKNOWN_FUNCTION           = (33),
+
+/** 
+  * @brief  Standard error defines   
+  */ 
+  SD_INTERNAL_ERROR, 
+  SD_NOT_CONFIGURED,
+  SD_REQUEST_PENDING, 
+  SD_REQUEST_NOT_APPLICABLE, 
+  SD_INVALID_PARAMETER,  
+  SD_UNSUPPORTED_FEATURE,  
+  SD_UNSUPPORTED_HW,  
+  SD_ERROR,  
+  SD_OK = 0 
+} SD_Error;
+
+/** 
+  * @brief  SDIO Transfer state  
+  */   
+typedef enum
+{
+  SD_TRANSFER_OK  = 0,
+  SD_TRANSFER_BUSY = 1,
+  SD_TRANSFER_ERROR
+} SDTransferState;
+
+/** 
+  * @brief  SD Card States 
+  */   
+typedef enum
+{
+  SD_CARD_READY                  = ((uint32_t)0x00000001),
+  SD_CARD_IDENTIFICATION         = ((uint32_t)0x00000002),
+  SD_CARD_STANDBY                = ((uint32_t)0x00000003),
+  SD_CARD_TRANSFER               = ((uint32_t)0x00000004),
+  SD_CARD_SENDING                = ((uint32_t)0x00000005),
+  SD_CARD_RECEIVING              = ((uint32_t)0x00000006),
+  SD_CARD_PROGRAMMING            = ((uint32_t)0x00000007),
+  SD_CARD_DISCONNECTED           = ((uint32_t)0x00000008),
+  SD_CARD_ERROR                  = ((uint32_t)0x000000FF)
+}SDCardState;
+
+
+/** 
+  * @brief  Card Specific Data: CSD Register   
+  */ 
+typedef struct
+{
+  __IO uint8_t  CSDStruct;            /*!< CSD structure */
+  __IO uint8_t  SysSpecVersion;       /*!< System specification version */
+  __IO uint8_t  Reserved1;            /*!< Reserved */
+  __IO uint8_t  TAAC;                 /*!< Data read access-time 1 */
+  __IO uint8_t  NSAC;                 /*!< Data read access-time 2 in CLK cycles */
+  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency */
+  __IO uint16_t CardComdClasses;      /*!< Card command classes */
+  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length */
+  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed */
+  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment */
+  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment */
+  __IO uint8_t  DSRImpl;              /*!< DSR implemented */
+  __IO uint8_t  Reserved2;            /*!< Reserved */
+  __IO uint32_t DeviceSize;           /*!< Device Size */
+  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min */
+  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max */
+  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min */
+  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max */
+  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier */
+  __IO uint8_t  EraseGrSize;          /*!< Erase group size */
+  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier */
+  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size */
+  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable */
+  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC */
+  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor */
+  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length */
+  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed */
+  __IO uint8_t  Reserved3;            /*!< Reserded */
+  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application */
+  __IO uint8_t  FileFormatGrouop;     /*!< File format group */
+  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP) */
+  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection */
+  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection */
+  __IO uint8_t  FileFormat;           /*!< File Format */
+  __IO uint8_t  ECC;                  /*!< ECC code */
+  __IO uint8_t  CSD_CRC;              /*!< CSD CRC */
+  __IO uint8_t  Reserved4;            /*!< always 1*/
+} SD_CSD;
+
+/** 
+  * @brief  Card Identification Data: CID Register   
+  */
+typedef struct
+{
+  __IO uint8_t  ManufacturerID;       /*!< ManufacturerID */
+  __IO uint16_t OEM_AppliID;          /*!< OEM/Application ID */
+  __IO uint32_t ProdName1;            /*!< Product Name part1 */
+  __IO uint8_t  ProdName2;            /*!< Product Name part2*/
+  __IO uint8_t  ProdRev;              /*!< Product Revision */
+  __IO uint32_t ProdSN;               /*!< Product Serial Number */
+  __IO uint8_t  Reserved1;            /*!< Reserved1 */
+  __IO uint16_t ManufactDate;         /*!< Manufacturing Date */
+  __IO uint8_t  CID_CRC;              /*!< CID CRC */
+  __IO uint8_t  Reserved2;            /*!< always 1 */
+} SD_CID;
+
+/** 
+  * @brief SD Card Status 
+  */
+typedef struct
+{
+  __IO uint8_t DAT_BUS_WIDTH;
+  __IO uint8_t SECURED_MODE;
+  __IO uint16_t SD_CARD_TYPE;
+  __IO uint32_t SIZE_OF_PROTECTED_AREA;
+  __IO uint8_t SPEED_CLASS;
+  __IO uint8_t PERFORMANCE_MOVE;
+  __IO uint8_t AU_SIZE;
+  __IO uint16_t ERASE_SIZE;
+  __IO uint8_t ERASE_TIMEOUT;
+  __IO uint8_t ERASE_OFFSET;
+} SD_CardStatus;
+
+
+/** 
+  * @brief SD Card information 
+  */
+typedef struct
+{
+  SD_CSD SD_csd;
+  SD_CID SD_cid;
+  uint32_t CardCapacity;  /*!< Card Capacity */
+  uint32_t CardBlockSize; /*!< Card Block Size */
+  uint16_t RCA;
+  uint8_t CardType;
+} SD_CardInfo;
+
+/**
+  * @}
+  */
+  
+/** @defgroup STM32_EVAL_SDIO_SD_Exported_Constants
+  * @{
+  */ 
+
+/** 
+  * @brief SDIO Commands  Index 
+  */
+#define SD_CMD_GO_IDLE_STATE                       ((uint8_t)0)
+#define SD_CMD_SEND_OP_COND                        ((uint8_t)1)
+#define SD_CMD_ALL_SEND_CID                        ((uint8_t)2)
+#define SD_CMD_SET_REL_ADDR                        ((uint8_t)3) /*!< SDIO_SEND_REL_ADDR for SD Card */
+#define SD_CMD_SET_DSR                             ((uint8_t)4)
+#define SD_CMD_SDIO_SEN_OP_COND                    ((uint8_t)5)
+#define SD_CMD_HS_SWITCH                           ((uint8_t)6)
+#define SD_CMD_SEL_DESEL_CARD                      ((uint8_t)7)
+#define SD_CMD_HS_SEND_EXT_CSD                     ((uint8_t)8)
+#define SD_CMD_SEND_CSD                            ((uint8_t)9)
+#define SD_CMD_SEND_CID                            ((uint8_t)10)
+#define SD_CMD_READ_DAT_UNTIL_STOP                 ((uint8_t)11) /*!< SD Card doesn't support it */
+#define SD_CMD_STOP_TRANSMISSION                   ((uint8_t)12)
+#define SD_CMD_SEND_STATUS                         ((uint8_t)13)
+#define SD_CMD_HS_BUSTEST_READ                     ((uint8_t)14)
+#define SD_CMD_GO_INACTIVE_STATE                   ((uint8_t)15)
+#define SD_CMD_SET_BLOCKLEN                        ((uint8_t)16)
+#define SD_CMD_READ_SINGLE_BLOCK                   ((uint8_t)17)
+#define SD_CMD_READ_MULT_BLOCK                     ((uint8_t)18)
+#define SD_CMD_HS_BUSTEST_WRITE                    ((uint8_t)19)
+#define SD_CMD_WRITE_DAT_UNTIL_STOP                ((uint8_t)20) /*!< SD Card doesn't support it */
+#define SD_CMD_SET_BLOCK_COUNT                     ((uint8_t)23) /*!< SD Card doesn't support it */
+#define SD_CMD_WRITE_SINGLE_BLOCK                  ((uint8_t)24)
+#define SD_CMD_WRITE_MULT_BLOCK                    ((uint8_t)25)
+#define SD_CMD_PROG_CID                            ((uint8_t)26) /*!< reserved for manufacturers */
+#define SD_CMD_PROG_CSD                            ((uint8_t)27)
+#define SD_CMD_SET_WRITE_PROT                      ((uint8_t)28)
+#define SD_CMD_CLR_WRITE_PROT                      ((uint8_t)29)
+#define SD_CMD_SEND_WRITE_PROT                     ((uint8_t)30)
+#define SD_CMD_SD_ERASE_GRP_START                  ((uint8_t)32) /*!< To set the address of the first write
+                                                                  block to be erased. (For SD card only) */
+#define SD_CMD_SD_ERASE_GRP_END                    ((uint8_t)33) /*!< To set the address of the last write block of the
+                                                                  continuous range to be erased. (For SD card only) */
+#define SD_CMD_ERASE_GRP_START                     ((uint8_t)35) /*!< To set the address of the first write block to be erased.
+                                                                  (For MMC card only spec 3.31) */
+
+#define SD_CMD_ERASE_GRP_END                       ((uint8_t)36) /*!< To set the address of the last write block of the
+                                                                  continuous range to be erased. (For MMC card only spec 3.31) */
+
+#define SD_CMD_ERASE                               ((uint8_t)38)
+#define SD_CMD_FAST_IO                             ((uint8_t)39) /*!< SD Card doesn't support it */
+#define SD_CMD_GO_IRQ_STATE                        ((uint8_t)40) /*!< SD Card doesn't support it */
+#define SD_CMD_LOCK_UNLOCK                         ((uint8_t)42)
+#define SD_CMD_APP_CMD                             ((uint8_t)55)
+#define SD_CMD_GEN_CMD                             ((uint8_t)56)
+#define SD_CMD_NO_CMD                              ((uint8_t)64)
+
+/** 
+  * @brief Following commands are SD Card Specific commands.
+  *        SDIO_APP_CMD should be sent before sending these commands. 
+  */
+#define SD_CMD_APP_SD_SET_BUSWIDTH                 ((uint8_t)6)  /*!< For SD Card only */
+#define SD_CMD_SD_APP_STAUS                        ((uint8_t)13) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((uint8_t)22) /*!< For SD Card only */
+#define SD_CMD_SD_APP_OP_COND                      ((uint8_t)41) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT          ((uint8_t)42) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SEND_SCR                     ((uint8_t)51) /*!< For SD Card only */
+#define SD_CMD_SDIO_RW_DIRECT                      ((uint8_t)52) /*!< For SD I/O Card only */
+#define SD_CMD_SDIO_RW_EXTENDED                    ((uint8_t)53) /*!< For SD I/O Card only */
+
+/** 
+  * @brief Following commands are SD Card Specific security commands.
+  *        SDIO_APP_CMD should be sent before sending these commands. 
+  */
+#define SD_CMD_SD_APP_GET_MKB                      ((uint8_t)43) /*!< For SD Card only */
+#define SD_CMD_SD_APP_GET_MID                      ((uint8_t)44) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SET_CER_RN1                  ((uint8_t)45) /*!< For SD Card only */
+#define SD_CMD_SD_APP_GET_CER_RN2                  ((uint8_t)46) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SET_CER_RES2                 ((uint8_t)47) /*!< For SD Card only */
+#define SD_CMD_SD_APP_GET_CER_RES1                 ((uint8_t)48) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   ((uint8_t)18) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  ((uint8_t)25) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SECURE_ERASE                 ((uint8_t)38) /*!< For SD Card only */
+#define SD_CMD_SD_APP_CHANGE_SECURE_AREA           ((uint8_t)49) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SECURE_WRITE_MKB             ((uint8_t)48) /*!< For SD Card only */
+  
+/* Uncomment the following line to select the SDIO Data transfer mode */  
+#define SD_DMA_MODE                                ((uint32_t)0x00000000)
+/*#define SD_POLLING_MODE                            ((uint32_t)0x00000002)*/
+
+/**
+  * @brief  SD detection on its memory slot
+  */
+#define SD_PRESENT                                 ((uint8_t)0x01)
+#define SD_NOT_PRESENT                             ((uint8_t)0x00)
+
+/** 
+  * @brief Supported SD Memory Cards 
+  */
+#define SDIO_STD_CAPACITY_SD_CARD_V1_1             ((uint32_t)0x00000000)
+#define SDIO_STD_CAPACITY_SD_CARD_V2_0             ((uint32_t)0x00000001)
+#define SDIO_HIGH_CAPACITY_SD_CARD                 ((uint32_t)0x00000002)
+#define SDIO_MULTIMEDIA_CARD                       ((uint32_t)0x00000003)
+#define SDIO_SECURE_DIGITAL_IO_CARD                ((uint32_t)0x00000004)
+#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD            ((uint32_t)0x00000005)
+#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD          ((uint32_t)0x00000006)
+#define SDIO_HIGH_CAPACITY_MMC_CARD                ((uint32_t)0x00000007)
+
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM32_EVAL_SDIO_SD_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32_EVAL_SDIO_SD_Exported_Functions
+  * @{
+  */ 
+void SD_DeInit(void);
+SD_Error SD_Init(void);
+SDTransferState SD_GetStatus(void);
+SDCardState SD_GetState(void);
+uint8_t SD_Detect(void);
+SD_Error SD_PowerON(void);
+SD_Error SD_PowerOFF(void);
+SD_Error SD_InitializeCards(void);
+SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo);
+SD_Error SD_GetCardStatus(SD_CardStatus *cardstatus);
+SD_Error SD_EnableWideBusOperation(uint32_t WideMode);
+SD_Error SD_SelectDeselect(uint32_t addr);
+SD_Error SD_ReadBlock(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize);
+SD_Error SD_ReadMultiBlocks(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks);
+SD_Error SD_WriteBlock(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize);
+SD_Error SD_WriteMultiBlocks(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks);
+SDTransferState SD_GetTransferState(void);
+SD_Error SD_StopTransfer(void);
+SD_Error SD_Erase(uint32_t startaddr, uint32_t endaddr);
+SD_Error SD_SendStatus(uint32_t *pcardstatus);
+SD_Error SD_SendSDStatus(uint32_t *psdstatus);
+SD_Error SD_ProcessIRQSrc(void);
+SD_Error SD_WaitReadOperation(void);
+SD_Error SD_WaitWriteOperation(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_EVAL_SDIO_SD_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

+ 151 - 0
stm32f1_02/inc/stm32_eval_spi_flash.h

@@ -0,0 +1,151 @@
+/**
+  ******************************************************************************
+  * @file    stm32_eval_spi_flash.h
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   This file contains all the functions prototypes for the stm32_eval_spi_flash
+  *          firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_EVAL_SPI_FLASH_H
+#define __STM32_EVAL_SPI_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32_eval.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup Common
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL_SPI_FLASH
+  * @{
+  */  
+
+/** @defgroup STM32_EVAL_SPI_FLASH_Exported_Types
+  * @{
+  */ 
+/**
+  * @}
+  */
+  
+/** @defgroup STM32_EVAL_SPI_FLASH_Exported_Constants
+  * @{
+  */
+/**
+  * @brief  M25P SPI Flash supported commands
+  */  
+#define sFLASH_CMD_WRITE          0x02  /*!< Write to Memory instruction */
+#define sFLASH_CMD_WRSR           0x01  /*!< Write Status Register instruction */
+#define sFLASH_CMD_WREN           0x06  /*!< Write enable instruction */
+#define sFLASH_CMD_READ           0x03  /*!< Read from Memory instruction */
+#define sFLASH_CMD_RDSR           0x05  /*!< Read Status Register instruction  */
+#define sFLASH_CMD_RDID           0x9F  /*!< Read identification */
+#define sFLASH_CMD_SE             0xD8  /*!< Sector Erase instruction */
+#define sFLASH_CMD_BE             0xC7  /*!< Bulk Erase instruction */
+
+#define sFLASH_WIP_FLAG           0x01  /*!< Write In Progress (WIP) flag */
+
+#define sFLASH_DUMMY_BYTE         0xA5
+#define sFLASH_SPI_PAGESIZE       0x100
+
+#define sFLASH_M25P128_ID         0x202018
+#define sFLASH_M25P64_ID          0x202017
+  
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM32_EVAL_SPI_FLASH_Exported_Macros
+  * @{
+  */
+/**
+  * @brief  Select sFLASH: Chip Select pin low
+  */
+#define sFLASH_CS_LOW()       GPIO_ResetBits(sFLASH_CS_GPIO_PORT, sFLASH_CS_PIN)
+/**
+  * @brief  Deselect sFLASH: Chip Select pin high
+  */
+#define sFLASH_CS_HIGH()      GPIO_SetBits(sFLASH_CS_GPIO_PORT, sFLASH_CS_PIN)   
+/**
+  * @}
+  */ 
+  
+
+
+/** @defgroup STM32_EVAL_SPI_FLASH_Exported_Functions
+  * @{
+  */
+/**
+  * @brief  High layer functions
+  */
+void sFLASH_DeInit(void);
+void sFLASH_Init(void);
+void sFLASH_EraseSector(uint32_t SectorAddr);
+void sFLASH_EraseBulk(void);
+void sFLASH_WritePage(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite);
+void sFLASH_WriteBuffer(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite);
+void sFLASH_ReadBuffer(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t NumByteToRead);
+uint32_t sFLASH_ReadID(void);
+void sFLASH_StartReadSequence(uint32_t ReadAddr);
+
+/**
+  * @brief  Low layer functions
+  */
+uint8_t sFLASH_ReadByte(void);
+uint8_t sFLASH_SendByte(uint8_t byte);
+uint16_t sFLASH_SendHalfWord(uint16_t HalfWord);
+void sFLASH_WriteEnable(void);
+void sFLASH_WaitForWriteEnd(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_EVAL_SPI_FLASH_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */  
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

+ 280 - 0
stm32f1_02/inc/stm32_eval_spi_sd.h

@@ -0,0 +1,280 @@
+/**
+  ******************************************************************************
+  * @file    stm32_eval_spi_sd.h
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   This file contains all the functions prototypes for the stm32_eval_spi_sd
+  *          firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_EVAL_SPI_SD_H
+#define __STM32_EVAL_SPI_SD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32_eval.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup Common
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL_SPI_SD
+  * @{
+  */  
+
+/** @defgroup STM32_EVAL_SPI_SD_Exported_Types
+  * @{
+  */ 
+
+typedef enum
+{
+/**
+  * @brief  SD reponses and error flags
+  */
+  SD_RESPONSE_NO_ERROR      = (0x00),
+  SD_IN_IDLE_STATE          = (0x01),
+  SD_ERASE_RESET            = (0x02),
+  SD_ILLEGAL_COMMAND        = (0x04),
+  SD_COM_CRC_ERROR          = (0x08),
+  SD_ERASE_SEQUENCE_ERROR   = (0x10),
+  SD_ADDRESS_ERROR          = (0x20),
+  SD_PARAMETER_ERROR        = (0x40),
+  SD_RESPONSE_FAILURE       = (0xFF),
+
+/**
+  * @brief  Data response error
+  */
+  SD_DATA_OK                = (0x05),
+  SD_DATA_CRC_ERROR         = (0x0B),
+  SD_DATA_WRITE_ERROR       = (0x0D),
+  SD_DATA_OTHER_ERROR       = (0xFF)
+} SD_Error;
+
+/** 
+  * @brief  Card Specific Data: CSD Register   
+  */ 
+typedef struct
+{
+  __IO uint8_t  CSDStruct;            /*!< CSD structure */
+  __IO uint8_t  SysSpecVersion;       /*!< System specification version */
+  __IO uint8_t  Reserved1;            /*!< Reserved */
+  __IO uint8_t  TAAC;                 /*!< Data read access-time 1 */
+  __IO uint8_t  NSAC;                 /*!< Data read access-time 2 in CLK cycles */
+  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency */
+  __IO uint16_t CardComdClasses;      /*!< Card command classes */
+  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length */
+  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed */
+  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment */
+  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment */
+  __IO uint8_t  DSRImpl;              /*!< DSR implemented */
+  __IO uint8_t  Reserved2;            /*!< Reserved */
+  __IO uint32_t DeviceSize;           /*!< Device Size */
+  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min */
+  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max */
+  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min */
+  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max */
+  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier */
+  __IO uint8_t  EraseGrSize;          /*!< Erase group size */
+  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier */
+  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size */
+  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable */
+  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC */
+  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor */
+  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length */
+  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed */
+  __IO uint8_t  Reserved3;            /*!< Reserded */
+  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application */
+  __IO uint8_t  FileFormatGrouop;     /*!< File format group */
+  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP) */
+  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection */
+  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection */
+  __IO uint8_t  FileFormat;           /*!< File Format */
+  __IO uint8_t  ECC;                  /*!< ECC code */
+  __IO uint8_t  CSD_CRC;              /*!< CSD CRC */
+  __IO uint8_t  Reserved4;            /*!< always 1*/
+} SD_CSD;
+
+/** 
+  * @brief  Card Identification Data: CID Register   
+  */
+typedef struct
+{
+  __IO uint8_t  ManufacturerID;       /*!< ManufacturerID */
+  __IO uint16_t OEM_AppliID;          /*!< OEM/Application ID */
+  __IO uint32_t ProdName1;            /*!< Product Name part1 */
+  __IO uint8_t  ProdName2;            /*!< Product Name part2*/
+  __IO uint8_t  ProdRev;              /*!< Product Revision */
+  __IO uint32_t ProdSN;               /*!< Product Serial Number */
+  __IO uint8_t  Reserved1;            /*!< Reserved1 */
+  __IO uint16_t ManufactDate;         /*!< Manufacturing Date */
+  __IO uint8_t  CID_CRC;              /*!< CID CRC */
+  __IO uint8_t  Reserved2;            /*!< always 1 */
+} SD_CID;
+
+/** 
+  * @brief SD Card information 
+  */
+typedef struct
+{
+  SD_CSD SD_csd;
+  SD_CID SD_cid;
+  uint32_t CardCapacity;  /*!< Card Capacity */
+  uint32_t CardBlockSize; /*!< Card Block Size */
+} SD_CardInfo;
+
+/**
+  * @}
+  */
+  
+/** @defgroup STM32_EVAL_SPI_SD_Exported_Constants
+  * @{
+  */ 
+    
+/**
+  * @brief  Block Size
+  */
+#define SD_BLOCK_SIZE    0x200
+
+/**
+  * @brief  Dummy byte
+  */
+#define SD_DUMMY_BYTE   0xFF
+
+/**
+  * @brief  Start Data tokens:
+  *         Tokens (necessary because at nop/idle (and CS active) only 0xff is 
+  *         on the data/command line)  
+  */
+#define SD_START_DATA_SINGLE_BLOCK_READ    0xFE  /*!< Data token start byte, Start Single Block Read */
+#define SD_START_DATA_MULTIPLE_BLOCK_READ  0xFE  /*!< Data token start byte, Start Multiple Block Read */
+#define SD_START_DATA_SINGLE_BLOCK_WRITE   0xFE  /*!< Data token start byte, Start Single Block Write */
+#define SD_START_DATA_MULTIPLE_BLOCK_WRITE 0xFD  /*!< Data token start byte, Start Multiple Block Write */
+#define SD_STOP_DATA_MULTIPLE_BLOCK_WRITE  0xFD  /*!< Data toke stop byte, Stop Multiple Block Write */
+
+/**
+  * @brief  SD detection on its memory slot
+  */
+#define SD_PRESENT        ((uint8_t)0x01)
+#define SD_NOT_PRESENT    ((uint8_t)0x00)
+
+
+/**
+  * @brief  Commands: CMDxx = CMD-number | 0x40
+  */
+#define SD_CMD_GO_IDLE_STATE          0   /*!< CMD0 = 0x40 */
+#define SD_CMD_SEND_OP_COND           1   /*!< CMD1 = 0x41 */
+#define SD_CMD_SEND_CSD               9   /*!< CMD9 = 0x49 */
+#define SD_CMD_SEND_CID               10  /*!< CMD10 = 0x4A */
+#define SD_CMD_STOP_TRANSMISSION      12  /*!< CMD12 = 0x4C */
+#define SD_CMD_SEND_STATUS            13  /*!< CMD13 = 0x4D */
+#define SD_CMD_SET_BLOCKLEN           16  /*!< CMD16 = 0x50 */
+#define SD_CMD_READ_SINGLE_BLOCK      17  /*!< CMD17 = 0x51 */
+#define SD_CMD_READ_MULT_BLOCK        18  /*!< CMD18 = 0x52 */
+#define SD_CMD_SET_BLOCK_COUNT        23  /*!< CMD23 = 0x57 */
+#define SD_CMD_WRITE_SINGLE_BLOCK     24  /*!< CMD24 = 0x58 */
+#define SD_CMD_WRITE_MULT_BLOCK       25  /*!< CMD25 = 0x59 */
+#define SD_CMD_PROG_CSD               27  /*!< CMD27 = 0x5B */
+#define SD_CMD_SET_WRITE_PROT         28  /*!< CMD28 = 0x5C */
+#define SD_CMD_CLR_WRITE_PROT         29  /*!< CMD29 = 0x5D */
+#define SD_CMD_SEND_WRITE_PROT        30  /*!< CMD30 = 0x5E */
+#define SD_CMD_SD_ERASE_GRP_START     32  /*!< CMD32 = 0x60 */
+#define SD_CMD_SD_ERASE_GRP_END       33  /*!< CMD33 = 0x61 */
+#define SD_CMD_UNTAG_SECTOR           34  /*!< CMD34 = 0x62 */
+#define SD_CMD_ERASE_GRP_START        35  /*!< CMD35 = 0x63 */
+#define SD_CMD_ERASE_GRP_END          36  /*!< CMD36 = 0x64 */
+#define SD_CMD_UNTAG_ERASE_GROUP      37  /*!< CMD37 = 0x65 */
+#define SD_CMD_ERASE                  38  /*!< CMD38 = 0x66 */
+
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM32_EVAL_SPI_SD_Exported_Macros
+  * @{
+  */
+/** 
+  * @brief  Select SD Card: ChipSelect pin low   
+  */  
+#define SD_CS_LOW()     GPIO_ResetBits(SD_CS_GPIO_PORT, SD_CS_PIN)
+/** 
+  * @brief  Deselect SD Card: ChipSelect pin high   
+  */ 
+#define SD_CS_HIGH()    GPIO_SetBits(SD_CS_GPIO_PORT, SD_CS_PIN)
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32_EVAL_SPI_SD_Exported_Functions
+  * @{
+  */ 
+void SD_DeInit(void);  
+SD_Error SD_Init(void);
+uint8_t SD_Detect(void);
+SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo);
+SD_Error SD_ReadBlock(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t BlockSize);
+SD_Error SD_ReadMultiBlocks(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks);
+SD_Error SD_WriteBlock(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t BlockSize);
+SD_Error SD_WriteMultiBlocks(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks);
+SD_Error SD_GetCSDRegister(SD_CSD* SD_csd);
+SD_Error SD_GetCIDRegister(SD_CID* SD_cid);
+
+void SD_SendCmd(uint8_t Cmd, uint32_t Arg, uint8_t Crc);
+SD_Error SD_GetResponse(uint8_t Response);
+uint8_t SD_GetDataResponse(void);
+SD_Error SD_GoIdleState(void);
+uint16_t SD_GetStatus(void);
+
+uint8_t SD_WriteByte(uint8_t byte);
+uint8_t SD_ReadByte(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_EVAL_SPI_SD_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */    
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

Разница между файлами не показана из-за своего большого размера
+ 8336 - 0
stm32f1_02/inc/stm32f10x.h


+ 483 - 0
stm32f1_02/inc/stm32f10x_adc.h

@@ -0,0 +1,483 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_adc.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the ADC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_ADC_H
+#define __STM32F10x_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup ADC
+  * @{
+  */
+
+/** @defgroup ADC_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  ADC Init structure definition  
+  */
+
+typedef struct
+{
+  uint32_t ADC_Mode;                      /*!< Configures the ADC to operate in independent or
+                                               dual mode. 
+                                               This parameter can be a value of @ref ADC_mode */
+
+  FunctionalState ADC_ScanConvMode;       /*!< Specifies whether the conversion is performed in
+                                               Scan (multichannels) or Single (one channel) mode.
+                                               This parameter can be set to ENABLE or DISABLE */
+
+  FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
+                                               Continuous or Single mode.
+                                               This parameter can be set to ENABLE or DISABLE. */
+
+  uint32_t ADC_ExternalTrigConv;          /*!< Defines the external trigger used to start the analog
+                                               to digital conversion of regular channels. This parameter
+                                               can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
+
+  uint32_t ADC_DataAlign;                 /*!< Specifies whether the ADC data alignment is left or right.
+                                               This parameter can be a value of @ref ADC_data_align */
+
+  uint8_t ADC_NbrOfChannel;               /*!< Specifies the number of ADC channels that will be converted
+                                               using the sequencer for regular channel group.
+                                               This parameter must range from 1 to 16. */
+}ADC_InitTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Constants
+  * @{
+  */
+
+#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
+                                   ((PERIPH) == ADC2) || \
+                                   ((PERIPH) == ADC3))
+
+#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
+                                   ((PERIPH) == ADC3))
+
+/** @defgroup ADC_mode 
+  * @{
+  */
+
+#define ADC_Mode_Independent                       ((uint32_t)0x00000000)
+#define ADC_Mode_RegInjecSimult                    ((uint32_t)0x00010000)
+#define ADC_Mode_RegSimult_AlterTrig               ((uint32_t)0x00020000)
+#define ADC_Mode_InjecSimult_FastInterl            ((uint32_t)0x00030000)
+#define ADC_Mode_InjecSimult_SlowInterl            ((uint32_t)0x00040000)
+#define ADC_Mode_InjecSimult                       ((uint32_t)0x00050000)
+#define ADC_Mode_RegSimult                         ((uint32_t)0x00060000)
+#define ADC_Mode_FastInterl                        ((uint32_t)0x00070000)
+#define ADC_Mode_SlowInterl                        ((uint32_t)0x00080000)
+#define ADC_Mode_AlterTrig                         ((uint32_t)0x00090000)
+
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
+                           ((MODE) == ADC_Mode_RegInjecSimult) || \
+                           ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \
+                           ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \
+                           ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \
+                           ((MODE) == ADC_Mode_InjecSimult) || \
+                           ((MODE) == ADC_Mode_RegSimult) || \
+                           ((MODE) == ADC_Mode_FastInterl) || \
+                           ((MODE) == ADC_Mode_SlowInterl) || \
+                           ((MODE) == ADC_Mode_AlterTrig))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion 
+  * @{
+  */
+
+#define ADC_ExternalTrigConv_T1_CC1                ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T1_CC2                ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T2_CC2                ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T3_TRGO               ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T4_CC4                ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO    ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */
+
+#define ADC_ExternalTrigConv_T1_CC3                ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigConv_None                  ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */
+
+#define ADC_ExternalTrigConv_T3_CC1                ((uint32_t)0x00000000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T2_CC3                ((uint32_t)0x00020000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T8_CC1                ((uint32_t)0x00060000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T8_TRGO               ((uint32_t)0x00080000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T5_CC1                ((uint32_t)0x000A0000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T5_CC3                ((uint32_t)0x000C0000) /*!< For ADC3 only */
+
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_None) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_data_align 
+  * @{
+  */
+
+#define ADC_DataAlign_Right                        ((uint32_t)0x00000000)
+#define ADC_DataAlign_Left                         ((uint32_t)0x00000800)
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
+                                  ((ALIGN) == ADC_DataAlign_Left))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_channels 
+  * @{
+  */
+
+#define ADC_Channel_0                               ((uint8_t)0x00)
+#define ADC_Channel_1                               ((uint8_t)0x01)
+#define ADC_Channel_2                               ((uint8_t)0x02)
+#define ADC_Channel_3                               ((uint8_t)0x03)
+#define ADC_Channel_4                               ((uint8_t)0x04)
+#define ADC_Channel_5                               ((uint8_t)0x05)
+#define ADC_Channel_6                               ((uint8_t)0x06)
+#define ADC_Channel_7                               ((uint8_t)0x07)
+#define ADC_Channel_8                               ((uint8_t)0x08)
+#define ADC_Channel_9                               ((uint8_t)0x09)
+#define ADC_Channel_10                              ((uint8_t)0x0A)
+#define ADC_Channel_11                              ((uint8_t)0x0B)
+#define ADC_Channel_12                              ((uint8_t)0x0C)
+#define ADC_Channel_13                              ((uint8_t)0x0D)
+#define ADC_Channel_14                              ((uint8_t)0x0E)
+#define ADC_Channel_15                              ((uint8_t)0x0F)
+#define ADC_Channel_16                              ((uint8_t)0x10)
+#define ADC_Channel_17                              ((uint8_t)0x11)
+
+#define ADC_Channel_TempSensor                      ((uint8_t)ADC_Channel_16)
+#define ADC_Channel_Vrefint                         ((uint8_t)ADC_Channel_17)
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
+                                 ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
+                                 ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
+                                 ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
+                                 ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
+                                 ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
+                                 ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
+                                 ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
+                                 ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_sampling_time 
+  * @{
+  */
+
+#define ADC_SampleTime_1Cycles5                    ((uint8_t)0x00)
+#define ADC_SampleTime_7Cycles5                    ((uint8_t)0x01)
+#define ADC_SampleTime_13Cycles5                   ((uint8_t)0x02)
+#define ADC_SampleTime_28Cycles5                   ((uint8_t)0x03)
+#define ADC_SampleTime_41Cycles5                   ((uint8_t)0x04)
+#define ADC_SampleTime_55Cycles5                   ((uint8_t)0x05)
+#define ADC_SampleTime_71Cycles5                   ((uint8_t)0x06)
+#define ADC_SampleTime_239Cycles5                  ((uint8_t)0x07)
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_7Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_13Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_28Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_41Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_55Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_71Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_239Cycles5))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion 
+  * @{
+  */
+
+#define ADC_ExternalTrigInjecConv_T2_TRGO           ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_T2_CC1            ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_T3_CC4            ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_T4_TRGO           ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */
+
+#define ADC_ExternalTrigInjecConv_T1_TRGO           ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjecConv_T1_CC4            ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjecConv_None              ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */
+
+#define ADC_ExternalTrigInjecConv_T4_CC3            ((uint32_t)0x00002000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T8_CC2            ((uint32_t)0x00003000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T8_CC4            ((uint32_t)0x00004000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T5_TRGO           ((uint32_t)0x00005000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T5_CC4            ((uint32_t)0x00006000) /*!< For ADC3 only */
+
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_channel_selection 
+  * @{
+  */
+
+#define ADC_InjectedChannel_1                       ((uint8_t)0x14)
+#define ADC_InjectedChannel_2                       ((uint8_t)0x18)
+#define ADC_InjectedChannel_3                       ((uint8_t)0x1C)
+#define ADC_InjectedChannel_4                       ((uint8_t)0x20)
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_2) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_3) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_4))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_analog_watchdog_selection 
+  * @{
+  */
+
+#define ADC_AnalogWatchdog_SingleRegEnable         ((uint32_t)0x00800200)
+#define ADC_AnalogWatchdog_SingleInjecEnable       ((uint32_t)0x00400200)
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable  ((uint32_t)0x00C00200)
+#define ADC_AnalogWatchdog_AllRegEnable            ((uint32_t)0x00800000)
+#define ADC_AnalogWatchdog_AllInjecEnable          ((uint32_t)0x00400000)
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable    ((uint32_t)0x00C00000)
+#define ADC_AnalogWatchdog_None                    ((uint32_t)0x00000000)
+
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_None))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_interrupts_definition 
+  * @{
+  */
+
+#define ADC_IT_EOC                                 ((uint16_t)0x0220)
+#define ADC_IT_AWD                                 ((uint16_t)0x0140)
+#define ADC_IT_JEOC                                ((uint16_t)0x0480)
+
+#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))
+
+#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
+                           ((IT) == ADC_IT_JEOC))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_flags_definition 
+  * @{
+  */
+
+#define ADC_FLAG_AWD                               ((uint8_t)0x01)
+#define ADC_FLAG_EOC                               ((uint8_t)0x02)
+#define ADC_FLAG_JEOC                              ((uint8_t)0x04)
+#define ADC_FLAG_JSTRT                             ((uint8_t)0x08)
+#define ADC_FLAG_STRT                              ((uint8_t)0x10)
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
+                               ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
+                               ((FLAG) == ADC_FLAG_STRT))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_thresholds 
+  * @{
+  */
+
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_offset 
+  * @{
+  */
+
+#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_length 
+  * @{
+  */
+
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_rank 
+  * @{
+  */
+
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_regular_length 
+  * @{
+  */
+
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_rank 
+  * @{
+  */
+
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_discontinuous_mode_number 
+  * @{
+  */
+
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions
+  * @{
+  */
+
+void ADC_DeInit(ADC_TypeDef* ADCx);
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
+void ADC_ResetCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_StartCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
+uint32_t ADC_GetDualModeConversionValue(void);
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_ADC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

+ 195 - 0
stm32f1_02/inc/stm32f10x_bkp.h

@@ -0,0 +1,195 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_bkp.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the BKP firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_BKP_H
+#define __STM32F10x_BKP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup BKP
+  * @{
+  */
+
+/** @defgroup BKP_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Exported_Constants
+  * @{
+  */
+
+/** @defgroup Tamper_Pin_active_level 
+  * @{
+  */
+
+#define BKP_TamperPinLevel_High           ((uint16_t)0x0000)
+#define BKP_TamperPinLevel_Low            ((uint16_t)0x0001)
+#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \
+                                        ((LEVEL) == BKP_TamperPinLevel_Low))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin 
+  * @{
+  */
+
+#define BKP_RTCOutputSource_None          ((uint16_t)0x0000)
+#define BKP_RTCOutputSource_CalibClock    ((uint16_t)0x0080)
+#define BKP_RTCOutputSource_Alarm         ((uint16_t)0x0100)
+#define BKP_RTCOutputSource_Second        ((uint16_t)0x0300)
+#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \
+                                          ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \
+                                          ((SOURCE) == BKP_RTCOutputSource_Alarm) || \
+                                          ((SOURCE) == BKP_RTCOutputSource_Second))
+/**
+  * @}
+  */
+
+/** @defgroup Data_Backup_Register 
+  * @{
+  */
+
+#define BKP_DR1                           ((uint16_t)0x0004)
+#define BKP_DR2                           ((uint16_t)0x0008)
+#define BKP_DR3                           ((uint16_t)0x000C)
+#define BKP_DR4                           ((uint16_t)0x0010)
+#define BKP_DR5                           ((uint16_t)0x0014)
+#define BKP_DR6                           ((uint16_t)0x0018)
+#define BKP_DR7                           ((uint16_t)0x001C)
+#define BKP_DR8                           ((uint16_t)0x0020)
+#define BKP_DR9                           ((uint16_t)0x0024)
+#define BKP_DR10                          ((uint16_t)0x0028)
+#define BKP_DR11                          ((uint16_t)0x0040)
+#define BKP_DR12                          ((uint16_t)0x0044)
+#define BKP_DR13                          ((uint16_t)0x0048)
+#define BKP_DR14                          ((uint16_t)0x004C)
+#define BKP_DR15                          ((uint16_t)0x0050)
+#define BKP_DR16                          ((uint16_t)0x0054)
+#define BKP_DR17                          ((uint16_t)0x0058)
+#define BKP_DR18                          ((uint16_t)0x005C)
+#define BKP_DR19                          ((uint16_t)0x0060)
+#define BKP_DR20                          ((uint16_t)0x0064)
+#define BKP_DR21                          ((uint16_t)0x0068)
+#define BKP_DR22                          ((uint16_t)0x006C)
+#define BKP_DR23                          ((uint16_t)0x0070)
+#define BKP_DR24                          ((uint16_t)0x0074)
+#define BKP_DR25                          ((uint16_t)0x0078)
+#define BKP_DR26                          ((uint16_t)0x007C)
+#define BKP_DR27                          ((uint16_t)0x0080)
+#define BKP_DR28                          ((uint16_t)0x0084)
+#define BKP_DR29                          ((uint16_t)0x0088)
+#define BKP_DR30                          ((uint16_t)0x008C)
+#define BKP_DR31                          ((uint16_t)0x0090)
+#define BKP_DR32                          ((uint16_t)0x0094)
+#define BKP_DR33                          ((uint16_t)0x0098)
+#define BKP_DR34                          ((uint16_t)0x009C)
+#define BKP_DR35                          ((uint16_t)0x00A0)
+#define BKP_DR36                          ((uint16_t)0x00A4)
+#define BKP_DR37                          ((uint16_t)0x00A8)
+#define BKP_DR38                          ((uint16_t)0x00AC)
+#define BKP_DR39                          ((uint16_t)0x00B0)
+#define BKP_DR40                          ((uint16_t)0x00B4)
+#define BKP_DR41                          ((uint16_t)0x00B8)
+#define BKP_DR42                          ((uint16_t)0x00BC)
+
+#define IS_BKP_DR(DR) (((DR) == BKP_DR1)  || ((DR) == BKP_DR2)  || ((DR) == BKP_DR3)  || \
+                       ((DR) == BKP_DR4)  || ((DR) == BKP_DR5)  || ((DR) == BKP_DR6)  || \
+                       ((DR) == BKP_DR7)  || ((DR) == BKP_DR8)  || ((DR) == BKP_DR9)  || \
+                       ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \
+                       ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \
+                       ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \
+                       ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \
+                       ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \
+                       ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \
+                       ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \
+                       ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \
+                       ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \
+                       ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \
+                       ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))
+
+#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Exported_Functions
+  * @{
+  */
+
+void BKP_DeInit(void);
+void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
+void BKP_TamperPinCmd(FunctionalState NewState);
+void BKP_ITConfig(FunctionalState NewState);
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
+void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
+void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
+uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
+FlagStatus BKP_GetFlagStatus(void);
+void BKP_ClearFlag(void);
+ITStatus BKP_GetITStatus(void);
+void BKP_ClearITPendingBit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_BKP_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

+ 697 - 0
stm32f1_02/inc/stm32f10x_can.h

@@ -0,0 +1,697 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_can.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the CAN firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CAN_H
+#define __STM32F10x_CAN_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CAN
+  * @{
+  */
+
+/** @defgroup CAN_Exported_Types
+  * @{
+  */
+
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
+                                   ((PERIPH) == CAN2))
+
+/** 
+  * @brief  CAN init structure definition
+  */
+
+typedef struct
+{
+  uint16_t CAN_Prescaler;   /*!< Specifies the length of a time quantum. 
+                                 It ranges from 1 to 1024. */
+  
+  uint8_t CAN_Mode;         /*!< Specifies the CAN operating mode.
+                                 This parameter can be a value of 
+                                @ref CAN_operating_mode */
+
+  uint8_t CAN_SJW;          /*!< Specifies the maximum number of time quanta 
+                                 the CAN hardware is allowed to lengthen or 
+                                 shorten a bit to perform resynchronization.
+                                 This parameter can be a value of 
+                                 @ref CAN_synchronisation_jump_width */
+
+  uint8_t CAN_BS1;          /*!< Specifies the number of time quanta in Bit 
+                                 Segment 1. This parameter can be a value of 
+                                 @ref CAN_time_quantum_in_bit_segment_1 */
+
+  uint8_t CAN_BS2;          /*!< Specifies the number of time quanta in Bit 
+                                 Segment 2.
+                                 This parameter can be a value of 
+                                 @ref CAN_time_quantum_in_bit_segment_2 */
+  
+  FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered 
+                                 communication mode. This parameter can be set 
+                                 either to ENABLE or DISABLE. */
+  
+  FunctionalState CAN_ABOM;  /*!< Enable or disable the automatic bus-off 
+                                  management. This parameter can be set either 
+                                  to ENABLE or DISABLE. */
+
+  FunctionalState CAN_AWUM;  /*!< Enable or disable the automatic wake-up mode. 
+                                  This parameter can be set either to ENABLE or 
+                                  DISABLE. */
+
+  FunctionalState CAN_NART;  /*!< Enable or disable the no-automatic 
+                                  retransmission mode. This parameter can be 
+                                  set either to ENABLE or DISABLE. */
+
+  FunctionalState CAN_RFLM;  /*!< Enable or disable the Receive FIFO Locked mode.
+                                  This parameter can be set either to ENABLE 
+                                  or DISABLE. */
+
+  FunctionalState CAN_TXFP;  /*!< Enable or disable the transmit FIFO priority.
+                                  This parameter can be set either to ENABLE 
+                                  or DISABLE. */
+} CAN_InitTypeDef;
+
+/** 
+  * @brief  CAN filter init structure definition
+  */
+
+typedef struct
+{
+  uint16_t CAN_FilterIdHigh;         /*!< Specifies the filter identification number (MSBs for a 32-bit
+                                              configuration, first one for a 16-bit configuration).
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterIdLow;          /*!< Specifies the filter identification number (LSBs for a 32-bit
+                                              configuration, second one for a 16-bit configuration).
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterMaskIdHigh;     /*!< Specifies the filter mask number or identification number,
+                                              according to the mode (MSBs for a 32-bit configuration,
+                                              first one for a 16-bit configuration).
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterMaskIdLow;      /*!< Specifies the filter mask number or identification number,
+                                              according to the mode (LSBs for a 32-bit configuration,
+                                              second one for a 16-bit configuration).
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+                                              This parameter can be a value of @ref CAN_filter_FIFO */
+  
+  uint8_t CAN_FilterNumber;          /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
+
+  uint8_t CAN_FilterMode;            /*!< Specifies the filter mode to be initialized.
+                                              This parameter can be a value of @ref CAN_filter_mode */
+
+  uint8_t CAN_FilterScale;           /*!< Specifies the filter scale.
+                                              This parameter can be a value of @ref CAN_filter_scale */
+
+  FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
+                                              This parameter can be set either to ENABLE or DISABLE. */
+} CAN_FilterInitTypeDef;
+
+/** 
+  * @brief  CAN Tx message structure definition  
+  */
+
+typedef struct
+{
+  uint32_t StdId;  /*!< Specifies the standard identifier.
+                        This parameter can be a value between 0 to 0x7FF. */
+
+  uint32_t ExtId;  /*!< Specifies the extended identifier.
+                        This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+  uint8_t IDE;     /*!< Specifies the type of identifier for the message that 
+                        will be transmitted. This parameter can be a value 
+                        of @ref CAN_identifier_type */
+
+  uint8_t RTR;     /*!< Specifies the type of frame for the message that will 
+                        be transmitted. This parameter can be a value of 
+                        @ref CAN_remote_transmission_request */
+
+  uint8_t DLC;     /*!< Specifies the length of the frame that will be 
+                        transmitted. This parameter can be a value between 
+                        0 to 8 */
+
+  uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 
+                        to 0xFF. */
+} CanTxMsg;
+
+/** 
+  * @brief  CAN Rx message structure definition  
+  */
+
+typedef struct
+{
+  uint32_t StdId;  /*!< Specifies the standard identifier.
+                        This parameter can be a value between 0 to 0x7FF. */
+
+  uint32_t ExtId;  /*!< Specifies the extended identifier.
+                        This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+  uint8_t IDE;     /*!< Specifies the type of identifier for the message that 
+                        will be received. This parameter can be a value of 
+                        @ref CAN_identifier_type */
+
+  uint8_t RTR;     /*!< Specifies the type of frame for the received message.
+                        This parameter can be a value of 
+                        @ref CAN_remote_transmission_request */
+
+  uint8_t DLC;     /*!< Specifies the length of the frame that will be received.
+                        This parameter can be a value between 0 to 8 */
+
+  uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 
+                        0xFF. */
+
+  uint8_t FMI;     /*!< Specifies the index of the filter the message stored in 
+                        the mailbox passes through. This parameter can be a 
+                        value between 0 to 0xFF */
+} CanRxMsg;
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Exported_Constants
+  * @{
+  */
+
+/** @defgroup CAN_sleep_constants 
+  * @{
+  */
+
+#define CAN_InitStatus_Failed              ((uint8_t)0x00) /*!< CAN initialization failed */
+#define CAN_InitStatus_Success             ((uint8_t)0x01) /*!< CAN initialization OK */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Mode 
+  * @{
+  */
+
+#define CAN_Mode_Normal             ((uint8_t)0x00)  /*!< normal mode */
+#define CAN_Mode_LoopBack           ((uint8_t)0x01)  /*!< loopback mode */
+#define CAN_Mode_Silent             ((uint8_t)0x02)  /*!< silent mode */
+#define CAN_Mode_Silent_LoopBack    ((uint8_t)0x03)  /*!< loopback combined with silent mode */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
+                           ((MODE) == CAN_Mode_LoopBack)|| \
+                           ((MODE) == CAN_Mode_Silent) || \
+                           ((MODE) == CAN_Mode_Silent_LoopBack))
+/**
+  * @}
+  */
+
+
+/**
+  * @defgroup CAN_Operating_Mode 
+  * @{
+  */  
+#define CAN_OperatingMode_Initialization  ((uint8_t)0x00) /*!< Initialization mode */
+#define CAN_OperatingMode_Normal          ((uint8_t)0x01) /*!< Normal mode */
+#define CAN_OperatingMode_Sleep           ((uint8_t)0x02) /*!< sleep mode */
+
+
+#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
+                                    ((MODE) == CAN_OperatingMode_Normal)|| \
+																		((MODE) == CAN_OperatingMode_Sleep))
+/**
+  * @}
+  */
+  
+/**
+  * @defgroup CAN_Mode_Status
+  * @{
+  */  
+
+#define CAN_ModeStatus_Failed    ((uint8_t)0x00)                /*!< CAN entering the specific mode failed */
+#define CAN_ModeStatus_Success   ((uint8_t)!CAN_ModeStatus_Failed)   /*!< CAN entering the specific mode Succeed */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_synchronisation_jump_width 
+  * @{
+  */
+
+#define CAN_SJW_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_SJW_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_SJW_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_SJW_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
+
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
+                         ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1 
+  * @{
+  */
+
+#define CAN_BS1_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_BS1_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_BS1_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_BS1_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
+#define CAN_BS1_5tq                 ((uint8_t)0x04)  /*!< 5 time quantum */
+#define CAN_BS1_6tq                 ((uint8_t)0x05)  /*!< 6 time quantum */
+#define CAN_BS1_7tq                 ((uint8_t)0x06)  /*!< 7 time quantum */
+#define CAN_BS1_8tq                 ((uint8_t)0x07)  /*!< 8 time quantum */
+#define CAN_BS1_9tq                 ((uint8_t)0x08)  /*!< 9 time quantum */
+#define CAN_BS1_10tq                ((uint8_t)0x09)  /*!< 10 time quantum */
+#define CAN_BS1_11tq                ((uint8_t)0x0A)  /*!< 11 time quantum */
+#define CAN_BS1_12tq                ((uint8_t)0x0B)  /*!< 12 time quantum */
+#define CAN_BS1_13tq                ((uint8_t)0x0C)  /*!< 13 time quantum */
+#define CAN_BS1_14tq                ((uint8_t)0x0D)  /*!< 14 time quantum */
+#define CAN_BS1_15tq                ((uint8_t)0x0E)  /*!< 15 time quantum */
+#define CAN_BS1_16tq                ((uint8_t)0x0F)  /*!< 16 time quantum */
+
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2 
+  * @{
+  */
+
+#define CAN_BS2_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_BS2_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_BS2_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_BS2_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
+#define CAN_BS2_5tq                 ((uint8_t)0x04)  /*!< 5 time quantum */
+#define CAN_BS2_6tq                 ((uint8_t)0x05)  /*!< 6 time quantum */
+#define CAN_BS2_7tq                 ((uint8_t)0x06)  /*!< 7 time quantum */
+#define CAN_BS2_8tq                 ((uint8_t)0x07)  /*!< 8 time quantum */
+
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_clock_prescaler 
+  * @{
+  */
+
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_number 
+  * @{
+  */
+#ifndef STM32F10X_CL
+  #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)
+#else
+  #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+#endif /* STM32F10X_CL */ 
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_mode 
+  * @{
+  */
+
+#define CAN_FilterMode_IdMask       ((uint8_t)0x00)  /*!< identifier/mask mode */
+#define CAN_FilterMode_IdList       ((uint8_t)0x01)  /*!< identifier list mode */
+
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
+                                  ((MODE) == CAN_FilterMode_IdList))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_scale 
+  * @{
+  */
+
+#define CAN_FilterScale_16bit       ((uint8_t)0x00) /*!< Two 16-bit filters */
+#define CAN_FilterScale_32bit       ((uint8_t)0x01) /*!< One 32-bit filter */
+
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
+                                    ((SCALE) == CAN_FilterScale_32bit))
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_FIFO
+  * @{
+  */
+
+#define CAN_Filter_FIFO0             ((uint8_t)0x00)  /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_Filter_FIFO1             ((uint8_t)0x01)  /*!< Filter FIFO 1 assignment for filter x */
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
+                                  ((FIFO) == CAN_FilterFIFO1))
+/**
+  * @}
+  */
+
+/** @defgroup Start_bank_filter_for_slave_CAN 
+  * @{
+  */
+#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Tx 
+  * @{
+  */
+
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_identifier_type 
+  * @{
+  */
+
+#define CAN_Id_Standard             ((uint32_t)0x00000000)  /*!< Standard Id */
+#define CAN_Id_Extended             ((uint32_t)0x00000004)  /*!< Extended Id */
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
+                               ((IDTYPE) == CAN_Id_Extended))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_remote_transmission_request 
+  * @{
+  */
+
+#define CAN_RTR_Data                ((uint32_t)0x00000000)  /*!< Data frame */
+#define CAN_RTR_Remote              ((uint32_t)0x00000002)  /*!< Remote frame */
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_transmit_constants 
+  * @{
+  */
+
+#define CAN_TxStatus_Failed         ((uint8_t)0x00)/*!< CAN transmission failed */
+#define CAN_TxStatus_Ok             ((uint8_t)0x01) /*!< CAN transmission succeeded */
+#define CAN_TxStatus_Pending        ((uint8_t)0x02) /*!< CAN transmission pending */
+#define CAN_TxStatus_NoMailBox      ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_receive_FIFO_number_constants 
+  * @{
+  */
+
+#define CAN_FIFO0                 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
+#define CAN_FIFO1                 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
+
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_sleep_constants 
+  * @{
+  */
+
+#define CAN_Sleep_Failed     ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
+#define CAN_Sleep_Ok         ((uint8_t)0x01) /*!< CAN entered the sleep mode */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_wake_up_constants 
+  * @{
+  */
+
+#define CAN_WakeUp_Failed        ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
+#define CAN_WakeUp_Ok            ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
+
+/**
+  * @}
+  */
+
+/**
+  * @defgroup   CAN_Error_Code_constants
+  * @{
+  */  
+                                                                
+#define CAN_ErrorCode_NoErr           ((uint8_t)0x00) /*!< No Error */ 
+#define	CAN_ErrorCode_StuffErr        ((uint8_t)0x10) /*!< Stuff Error */ 
+#define	CAN_ErrorCode_FormErr         ((uint8_t)0x20) /*!< Form Error */ 
+#define	CAN_ErrorCode_ACKErr          ((uint8_t)0x30) /*!< Acknowledgment Error */ 
+#define	CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ 
+#define	CAN_ErrorCode_BitDominantErr  ((uint8_t)0x50) /*!< Bit Dominant Error */ 
+#define	CAN_ErrorCode_CRCErr          ((uint8_t)0x60) /*!< CRC Error  */ 
+#define	CAN_ErrorCode_SoftwareSetErr  ((uint8_t)0x70) /*!< Software Set Error */ 
+
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_flags 
+  * @{
+  */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
+   and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function.  */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0             ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
+#define CAN_FLAG_RQCP1             ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
+#define CAN_FLAG_RQCP2             ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FMP0              ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
+#define CAN_FLAG_FF0               ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag            */
+#define CAN_FLAG_FOV0              ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag         */
+#define CAN_FLAG_FMP1              ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
+#define CAN_FLAG_FF1               ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag            */
+#define CAN_FLAG_FOV1              ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag         */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WKU               ((uint32_t)0x31000008) /*!< Wake up Flag */
+#define CAN_FLAG_SLAK              ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
+/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. 
+         In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_EWG               ((uint32_t)0x10F00001) /*!< Error Warning Flag   */
+#define CAN_FLAG_EPV               ((uint32_t)0x10F00002) /*!< Error Passive Flag   */
+#define CAN_FLAG_BOF               ((uint32_t)0x10F00004) /*!< Bus-Off Flag         */
+#define CAN_FLAG_LEC               ((uint32_t)0x30F00070) /*!< Last error code Flag */
+
+#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC)  || ((FLAG) == CAN_FLAG_BOF)   || \
+                               ((FLAG) == CAN_FLAG_EPV)  || ((FLAG) == CAN_FLAG_EWG)   || \
+                               ((FLAG) == CAN_FLAG_WKU)  || ((FLAG) == CAN_FLAG_FOV0)  || \
+                               ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FMP0)  || \
+                               ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1)   || \
+                               ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
+                               ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
+                               ((FLAG) == CAN_FLAG_SLAK ))
+
+#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
+                                ((FLAG) == CAN_FLAG_RQCP1)  || ((FLAG) == CAN_FLAG_RQCP0) || \
+                                ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FOV0) ||\
+                                ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
+                                ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
+/**
+  * @}
+  */
+
+  
+/** @defgroup CAN_interrupts 
+  * @{
+  */
+
+
+  
+#define CAN_IT_TME                  ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
+
+/* Receive Interrupts */
+#define CAN_IT_FMP0                 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
+#define CAN_IT_FF0                  ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
+#define CAN_IT_FOV0                 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
+#define CAN_IT_FMP1                 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
+#define CAN_IT_FF1                  ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
+#define CAN_IT_FOV1                 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WKU                  ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
+#define CAN_IT_SLK                  ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
+
+/* Error Interrupts */
+#define CAN_IT_EWG                  ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
+#define CAN_IT_EPV                  ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
+#define CAN_IT_BOF                  ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
+#define CAN_IT_LEC                  ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
+#define CAN_IT_ERR                  ((uint32_t)0x00008000) /*!< Error Interrupt*/
+
+/* Flags named as Interrupts : kept only for FW compatibility */
+#define CAN_IT_RQCP0   CAN_IT_TME
+#define CAN_IT_RQCP1   CAN_IT_TME
+#define CAN_IT_RQCP2   CAN_IT_TME
+
+
+#define IS_CAN_IT(IT)        (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0)  ||\
+                             ((IT) == CAN_IT_FF0)  || ((IT) == CAN_IT_FOV0)  ||\
+                             ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1)   ||\
+                             ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG)   ||\
+                             ((IT) == CAN_IT_EPV)  || ((IT) == CAN_IT_BOF)   ||\
+                             ((IT) == CAN_IT_LEC)  || ((IT) == CAN_IT_ERR)   ||\
+                             ((IT) == CAN_IT_WKU)  || ((IT) == CAN_IT_SLK))
+
+#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0)    ||\
+                             ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1)    ||\
+                             ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG)    ||\
+                             ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF)    ||\
+                             ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR)    ||\
+                             ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Legacy 
+  * @{
+  */
+#define CANINITFAILED               CAN_InitStatus_Failed
+#define CANINITOK                   CAN_InitStatus_Success
+#define CAN_FilterFIFO0             CAN_Filter_FIFO0
+#define CAN_FilterFIFO1             CAN_Filter_FIFO1
+#define CAN_ID_STD                  CAN_Id_Standard           
+#define CAN_ID_EXT                  CAN_Id_Extended
+#define CAN_RTR_DATA                CAN_RTR_Data         
+#define CAN_RTR_REMOTE              CAN_RTR_Remote
+#define CANTXFAILE                  CAN_TxStatus_Failed
+#define CANTXOK                     CAN_TxStatus_Ok
+#define CANTXPENDING                CAN_TxStatus_Pending
+#define CAN_NO_MB                   CAN_TxStatus_NoMailBox
+#define CANSLEEPFAILED              CAN_Sleep_Failed
+#define CANSLEEPOK                  CAN_Sleep_Ok
+#define CANWAKEUPFAILED             CAN_WakeUp_Failed        
+#define CANWAKEUPOK                 CAN_WakeUp_Ok        
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Exported_Functions
+  * @{
+  */
+/*  Function used to set the CAN configuration to the default reset state *****/ 
+void CAN_DeInit(CAN_TypeDef* CANx);
+
+/* Initialization and Configuration functions *********************************/ 
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber); 
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
+void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
+
+/* Transmit functions *********************************************************/
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
+
+/* Receive functions **********************************************************/
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
+
+
+/* Operation modes functions **************************************************/
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
+uint8_t CAN_Sleep(CAN_TypeDef* CANx);
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
+
+/* Error management functions *************************************************/
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
+
+/* Interrupts and flags management functions **********************************/
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_CAN_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

+ 210 - 0
stm32f1_02/inc/stm32f10x_cec.h

@@ -0,0 +1,210 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_cec.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the CEC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CEC_H
+#define __STM32F10x_CEC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CEC
+  * @{
+  */
+  
+
+/** @defgroup CEC_Exported_Types
+  * @{
+  */
+   
+/** 
+  * @brief  CEC Init structure definition  
+  */ 
+typedef struct
+{
+  uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. 
+                               This parameter can be a value of @ref CEC_BitTiming_Mode */
+  uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. 
+                               This parameter can be a value of @ref CEC_BitPeriod_Mode */
+}CEC_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Exported_Constants
+  * @{
+  */ 
+  
+/** @defgroup CEC_BitTiming_Mode 
+  * @{
+  */ 
+#define CEC_BitTimingStdMode                    ((uint16_t)0x00) /*!< Bit timing error Standard Mode */
+#define CEC_BitTimingErrFreeMode                CEC_CFGR_BTEM   /*!< Bit timing error Free Mode */
+
+#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \
+                                            ((MODE) == CEC_BitTimingErrFreeMode))
+/**
+  * @}
+  */
+
+/** @defgroup CEC_BitPeriod_Mode 
+  * @{
+  */ 
+#define CEC_BitPeriodStdMode                    ((uint16_t)0x00) /*!< Bit period error Standard Mode */
+#define CEC_BitPeriodFlexibleMode                CEC_CFGR_BPEM   /*!< Bit period error Flexible Mode */
+
+#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \
+                                            ((MODE) == CEC_BitPeriodFlexibleMode))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup CEC_interrupts_definition 
+  * @{
+  */ 
+#define CEC_IT_TERR                              CEC_CSR_TERR
+#define CEC_IT_TBTRF                             CEC_CSR_TBTRF
+#define CEC_IT_RERR                              CEC_CSR_RERR
+#define CEC_IT_RBTF                              CEC_CSR_RBTF
+#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \
+                           ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup CEC_Own_Address 
+  * @{
+  */ 
+#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)
+/**
+  * @}
+  */ 
+
+/** @defgroup CEC_Prescaler 
+  * @{
+  */ 
+#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup CEC_flags_definition 
+  * @{
+  */
+   
+/** 
+  * @brief  ESR register flags  
+  */ 
+#define CEC_FLAG_BTE                            ((uint32_t)0x10010000)
+#define CEC_FLAG_BPE                            ((uint32_t)0x10020000)
+#define CEC_FLAG_RBTFE                          ((uint32_t)0x10040000)
+#define CEC_FLAG_SBE                            ((uint32_t)0x10080000)
+#define CEC_FLAG_ACKE                           ((uint32_t)0x10100000)
+#define CEC_FLAG_LINE                           ((uint32_t)0x10200000)
+#define CEC_FLAG_TBTFE                          ((uint32_t)0x10400000)
+
+/** 
+  * @brief  CSR register flags  
+  */ 
+#define CEC_FLAG_TEOM                           ((uint32_t)0x00000002)  
+#define CEC_FLAG_TERR                           ((uint32_t)0x00000004)
+#define CEC_FLAG_TBTRF                          ((uint32_t)0x00000008)
+#define CEC_FLAG_RSOM                           ((uint32_t)0x00000010)
+#define CEC_FLAG_REOM                           ((uint32_t)0x00000020)
+#define CEC_FLAG_RERR                           ((uint32_t)0x00000040)
+#define CEC_FLAG_RBTF                           ((uint32_t)0x00000080)
+
+#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00))
+                               
+#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \
+                               ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \
+                               ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \
+                               ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \
+                               ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \
+                               ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \
+                               ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF))
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup CEC_Exported_Macros
+  * @{
+  */
+ 
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Exported_Functions
+  * @{
+  */ 
+void CEC_DeInit(void);
+void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
+void CEC_Cmd(FunctionalState NewState);
+void CEC_ITConfig(FunctionalState NewState);
+void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
+void CEC_SetPrescaler(uint16_t CEC_Prescaler);
+void CEC_SendDataByte(uint8_t Data);
+uint8_t CEC_ReceiveDataByte(void);
+void CEC_StartOfMessage(void);
+void CEC_EndOfMessageCmd(FunctionalState NewState);
+FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG);
+void CEC_ClearFlag(uint32_t CEC_FLAG);
+ITStatus CEC_GetITStatus(uint8_t CEC_IT);
+void CEC_ClearITPendingBit(uint16_t CEC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_CEC_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

+ 94 - 0
stm32f1_02/inc/stm32f10x_crc.h

@@ -0,0 +1,94 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_crc.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the CRC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CRC_H
+#define __STM32F10x_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CRC
+  * @{
+  */
+
+/** @defgroup CRC_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Exported_Functions
+  * @{
+  */
+
+void CRC_ResetDR(void);
+uint32_t CRC_CalcCRC(uint32_t Data);
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC_GetCRC(void);
+void CRC_SetIDRegister(uint8_t IDValue);
+uint8_t CRC_GetIDRegister(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_CRC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

+ 317 - 0
stm32f1_02/inc/stm32f10x_dac.h

@@ -0,0 +1,317 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_dac.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the DAC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_DAC_H
+#define __STM32F10x_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DAC
+  * @{
+  */
+
+/** @defgroup DAC_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  DAC Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t DAC_Trigger;                      /*!< Specifies the external trigger for the selected DAC channel.
+                                                  This parameter can be a value of @ref DAC_trigger_selection */
+
+  uint32_t DAC_WaveGeneration;               /*!< Specifies whether DAC channel noise waves or triangle waves
+                                                  are generated, or whether no wave is generated.
+                                                  This parameter can be a value of @ref DAC_wave_generation */
+
+  uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
+                                                  the maximum amplitude triangle generation for the DAC channel. 
+                                                  This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
+
+  uint32_t DAC_OutputBuffer;                 /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+                                                  This parameter can be a value of @ref DAC_output_buffer */
+}DAC_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup DAC_trigger_selection 
+  * @{
+  */
+
+#define DAC_Trigger_None                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
+                                                                       has been loaded, and not by external trigger */
+#define DAC_Trigger_T6_TRGO                ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T8_TRGO                ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
+                                                                       only in High-density devices*/
+#define DAC_Trigger_T3_TRGO                ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
+                                                                       only in Connectivity line, Medium-density and Low-density Value Line devices */
+#define DAC_Trigger_T7_TRGO                ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T5_TRGO                ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T15_TRGO               ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel 
+                                                                       only in Medium-density and Low-density Value Line devices*/
+#define DAC_Trigger_T2_TRGO                ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T4_TRGO                ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Ext_IT9                ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Software               ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
+                                 ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T8_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T5_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
+                                 ((TRIGGER) == DAC_Trigger_Software))
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_wave_generation 
+  * @{
+  */
+
+#define DAC_WaveGeneration_None            ((uint32_t)0x00000000)
+#define DAC_WaveGeneration_Noise           ((uint32_t)0x00000040)
+#define DAC_WaveGeneration_Triangle        ((uint32_t)0x00000080)
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
+                                    ((WAVE) == DAC_WaveGeneration_Noise) || \
+                                    ((WAVE) == DAC_WaveGeneration_Triangle))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_lfsrunmask_triangleamplitude
+  * @{
+  */
+
+#define DAC_LFSRUnmask_Bit0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUnmask_Bits1_0             ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits2_0             ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits3_0             ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits4_0             ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits5_0             ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits6_0             ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits7_0             ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits8_0             ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits9_0             ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits10_0            ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits11_0            ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TriangleAmplitude_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TriangleAmplitude_3            ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
+#define DAC_TriangleAmplitude_7            ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
+#define DAC_TriangleAmplitude_15           ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
+#define DAC_TriangleAmplitude_31           ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
+#define DAC_TriangleAmplitude_63           ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
+#define DAC_TriangleAmplitude_127          ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
+#define DAC_TriangleAmplitude_255          ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
+#define DAC_TriangleAmplitude_511          ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
+#define DAC_TriangleAmplitude_1023         ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TriangleAmplitude_2047         ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TriangleAmplitude_4095         ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_1) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_3) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_7) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_15) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_31) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_63) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_127) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_255) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_511) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_1023) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_2047) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_4095))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_output_buffer 
+  * @{
+  */
+
+#define DAC_OutputBuffer_Enable            ((uint32_t)0x00000000)
+#define DAC_OutputBuffer_Disable           ((uint32_t)0x00000002)
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
+                                           ((STATE) == DAC_OutputBuffer_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Channel_selection 
+  * @{
+  */
+
+#define DAC_Channel_1                      ((uint32_t)0x00000000)
+#define DAC_Channel_2                      ((uint32_t)0x00000010)
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
+                                 ((CHANNEL) == DAC_Channel_2))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data_alignment 
+  * @{
+  */
+
+#define DAC_Align_12b_R                    ((uint32_t)0x00000000)
+#define DAC_Align_12b_L                    ((uint32_t)0x00000004)
+#define DAC_Align_8b_R                     ((uint32_t)0x00000008)
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
+                             ((ALIGN) == DAC_Align_12b_L) || \
+                             ((ALIGN) == DAC_Align_8b_R))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_wave_generation 
+  * @{
+  */
+
+#define DAC_Wave_Noise                     ((uint32_t)0x00000040)
+#define DAC_Wave_Triangle                  ((uint32_t)0x00000080)
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
+                           ((WAVE) == DAC_Wave_Triangle))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data 
+  * @{
+  */
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) 
+/**
+  * @}
+  */
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)  || defined (STM32F10X_HD_VL)
+/** @defgroup DAC_interrupts_definition 
+  * @{
+  */ 
+  
+#define DAC_IT_DMAUDR                      ((uint32_t)0x00002000)  
+#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup DAC_flags_definition 
+  * @{
+  */ 
+  
+#define DAC_FLAG_DMAUDR                    ((uint32_t)0x00002000)  
+#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))  
+
+/**
+  * @}
+  */
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Exported_Functions
+  * @{
+  */
+
+void DAC_DeInit(void);
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
+#endif
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) 
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_DAC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

+ 0 - 0
stm32f1_02/inc/stm32f10x_dbgmcu.h


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