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Попрыскал на говнокод освежителем воздуха

amgladtsin 4 years ago
parent
commit
bba7f2fc9c
100 changed files with 91928 additions and 723 deletions
  1. BIN
      stm32f1_03/build/main.bin
  2. 50 50
      stm32f1_03/build/main.hex
  3. 198 203
      stm32f1_03/build/main.lst
  4. BIN
      stm32f1_03/build/main.o
  5. BIN
      stm32f1_03/build/startup_stm32f10x_ld.o
  6. 59 470
      stm32f1_03/main.c
  7. 31 0
      stm32f1_04/Makefile
  8. 5 0
      stm32f1_04/build/gdb.scr
  9. BIN
      stm32f1_04/build/main.bin
  10. BIN
      stm32f1_04/build/main.elf
  11. 234 0
      stm32f1_04/build/main.hex
  12. 2793 0
      stm32f1_04/build/main.lst
  13. BIN
      stm32f1_04/build/main.o
  14. BIN
      stm32f1_04/build/startup_stm32f10x_ld.o
  15. 4 0
      stm32f1_04/gdb.txt
  16. 1818 0
      stm32f1_04/inc/core_cm3.h
  17. 220 0
      stm32f1_04/inc/misc.h
  18. 368 0
      stm32f1_04/inc/stm32_eval.h
  19. 8336 0
      stm32f1_04/inc/stm32f10x.h
  20. 483 0
      stm32f1_04/inc/stm32f10x_adc.h
  21. 195 0
      stm32f1_04/inc/stm32f10x_bkp.h
  22. 697 0
      stm32f1_04/inc/stm32f10x_can.h
  23. 210 0
      stm32f1_04/inc/stm32f10x_cec.h
  24. 94 0
      stm32f1_04/inc/stm32f10x_crc.h
  25. 317 0
      stm32f1_04/inc/stm32f10x_dac.h
  26. 119 0
      stm32f1_04/inc/stm32f10x_dbgmcu.h
  27. 439 0
      stm32f1_04/inc/stm32f10x_dma.h
  28. 184 0
      stm32f1_04/inc/stm32f10x_exti.h
  29. 426 0
      stm32f1_04/inc/stm32f10x_flash.h
  30. 733 0
      stm32f1_04/inc/stm32f10x_fsmc.h
  31. 385 0
      stm32f1_04/inc/stm32f10x_gpio.h
  32. 684 0
      stm32f1_04/inc/stm32f10x_i2c.h
  33. 140 0
      stm32f1_04/inc/stm32f10x_iwdg.h
  34. 156 0
      stm32f1_04/inc/stm32f10x_pwr.h
  35. 727 0
      stm32f1_04/inc/stm32f10x_rcc.h
  36. 135 0
      stm32f1_04/inc/stm32f10x_rtc.h
  37. 531 0
      stm32f1_04/inc/stm32f10x_sdio.h
  38. 487 0
      stm32f1_04/inc/stm32f10x_spi.h
  39. 1164 0
      stm32f1_04/inc/stm32f10x_tim.h
  40. 412 0
      stm32f1_04/inc/stm32f10x_usart.h
  41. 115 0
      stm32f1_04/inc/stm32f10x_wwdg.h
  42. 98 0
      stm32f1_04/inc/system_stm32f10x.h
  43. 784 0
      stm32f1_04/lib/core_cm3.c
  44. 225 0
      stm32f1_04/lib/misc.c
  45. 120 0
      stm32f1_04/lib/stm32_eval.c
  46. 1307 0
      stm32f1_04/lib/stm32f10x_adc.c
  47. 308 0
      stm32f1_04/lib/stm32f10x_bkp.c
  48. 1415 0
      stm32f1_04/lib/stm32f10x_can.c
  49. 433 0
      stm32f1_04/lib/stm32f10x_cec.c
  50. 160 0
      stm32f1_04/lib/stm32f10x_crc.c
  51. 571 0
      stm32f1_04/lib/stm32f10x_dac.c
  52. 162 0
      stm32f1_04/lib/stm32f10x_dbgmcu.c
  53. 714 0
      stm32f1_04/lib/stm32f10x_dma.c
  54. 269 0
      stm32f1_04/lib/stm32f10x_exti.c
  55. 1684 0
      stm32f1_04/lib/stm32f10x_flash.c
  56. 866 0
      stm32f1_04/lib/stm32f10x_fsmc.c
  57. 650 0
      stm32f1_04/lib/stm32f10x_gpio.c
  58. 1331 0
      stm32f1_04/lib/stm32f10x_i2c.c
  59. 190 0
      stm32f1_04/lib/stm32f10x_iwdg.c
  60. 307 0
      stm32f1_04/lib/stm32f10x_pwr.c
  61. 1470 0
      stm32f1_04/lib/stm32f10x_rcc.c
  62. 339 0
      stm32f1_04/lib/stm32f10x_rtc.c
  63. 799 0
      stm32f1_04/lib/stm32f10x_sdio.c
  64. 908 0
      stm32f1_04/lib/stm32f10x_spi.c
  65. 2890 0
      stm32f1_04/lib/stm32f10x_tim.c
  66. 1058 0
      stm32f1_04/lib/stm32f10x_usart.c
  67. 224 0
      stm32f1_04/lib/stm32f10x_wwdg.c
  68. 1094 0
      stm32f1_04/lib/system_stm32f10x.c
  69. 788 0
      stm32f1_04/main.c
  70. 592 0
      stm32f1_04/main.c1
  71. 58 0
      stm32f1_04/main.h
  72. 29384 0
      stm32f1_04/megacode.c
  73. 133 0
      stm32f1_04/readme.txt
  74. 584 0
      stm32f1_04/source/main.c
  75. 343 0
      stm32f1_04/source/startup_stm32f10x_ld.s
  76. 171 0
      stm32f1_04/stm32_flash.ld
  77. 81 0
      stm32f1_04/stm32f0xx_conf.h
  78. 125 0
      stm32f1_04/stm32f0xx_it.c
  79. 56 0
      stm32f1_04/stm32f0xx_it.h
  80. 77 0
      stm32f1_04/stm32f10x_conf.h
  81. 159 0
      stm32f1_04/stm32f10x_it.c
  82. 46 0
      stm32f1_04/stm32f10x_it.h
  83. 355 0
      stm32f1_04/system_stm32f0xx.c
  84. 1094 0
      stm32f1_04/system_stm32f10x.c
  85. 31 0
      stm32f1_05/Makefile
  86. BIN
      stm32f1_05/build/main.bin
  87. BIN
      stm32f1_03/build/main.elf
  88. 234 0
      stm32f1_05/build/main.hex
  89. 2777 0
      stm32f1_05/build/main.lst
  90. BIN
      stm32f1_05/build/main.o
  91. BIN
      stm32f1_05/build/startup_stm32f10x_ld.o
  92. 4 0
      stm32f1_05/gdb.txt
  93. 1818 0
      stm32f1_05/inc/core_cm3.h
  94. 143 0
      stm32f1_05/inc/defines.h
  95. 8336 0
      stm32f1_05/inc/stm32f10x.h
  96. 98 0
      stm32f1_05/inc/system_stm32f10x.h
  97. 175 0
      stm32f1_05/inc/typedefs.h
  98. 157 0
      stm32f1_05/lib/adc.c
  99. 784 0
      stm32f1_05/lib/core_cm3.c
  100. 0 0
      stm32f1_05/lib/gpio.c

BIN
stm32f1_03/build/main.bin


+ 50 - 50
stm32f1_03/build/main.hex

@@ -1,19 +1,19 @@
 :020000040800F2
-:1000000000280020050D0008490D0008490D0008D2
-:10001000490D0008490D0008490D000800000000C6
-:10002000000000000000000000000000490D000872
-:10003000490D000800000000490D0008C90B000828
-:10004000490D0008490D0008490D0008490D000838
-:10005000490D0008490D0008490D0008490D000828
-:10006000490D0008490D0008490D0008490D000818
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-:10008000490D0008490D0008490D0008490D0008F8
-:10009000490D0008490D0008490D0008490D0008E8
-:1000A000490D0008490D0008490D0008490D0008D8
-:1000B000490D0008490D000800000000490D000826
-:1000C000490D00080000000000000000490D000874
-:1000D00000000000490D0008490D00080000000064
-:1000E000490D0008490D0008490D000800000000F6
+:1000000000280020F90C00083D0D00083D0D0008F7
+:100010003D0D00083D0D00083D0D000800000000EA
+:100020000000000000000000000000003D0D00087E
+:100030003D0D0008000000003D0D0008BD0B00084C
+:100040003D0D00083D0D00083D0D00083D0D000868
+:100050003D0D00083D0D00083D0D00083D0D000858
+:100060003D0D00083D0D00083D0D00083D0D000848
+:100070003D0D00083D0D00083D0D00083D0D000838
+:100080003D0D00083D0D00083D0D00083D0D000828
+:100090003D0D00083D0D00083D0D00083D0D000818
+:1000A0003D0D00083D0D00083D0D00083D0D000808
+:1000B0003D0D00083D0D0008000000003D0D00084A
+:1000C0003D0D000800000000000000003D0D00088C
+:1000D000000000003D0D00083D0D0008000000007C
+:1000E0003D0D00083D0D00083D0D0008000000001A
 :1000F0000000000000000000000000000000000000
 :0C01000000000000000000005FF808F1A3
 :10010C0080B483B000AF03463960FB7197F90730B8
@@ -180,39 +180,39 @@
 :100B1C000848FFF7E3FDFF20FFF79AFC044B002287
 :100B2C001A70FB7A18461037BD4680BD300600207F
 :100B3C001B0000200008014030020020300400207F
-:100B4C0080B500AFFFF734FF03461A46144B1A600A
-:100B5C00FFF766FF134B00221A80134B4FF4007201
-:100B6C001A60FFF74DFB114B1B68114AA2FB0323C4
-:100B7C005B0B1846FFF7EEFA0E4B1B78002BFBD0E5
-:100B8C000D4B01221A70084B1B681846FFF752FFD9
-:100B9C00054B1B6803F50073034A1360ECE700BFB9
-:100BAC001400002026020020280200200000002053
-:100BBC005917B7D1300600203206002080B400AFA0
-:100BCC00404B1B78012B29D13F4B1B78012B25D097
-:100BDC003E4BB1221A803E4B1B781A463D4B19886E
-:100BEC003D4B23F812103A4B1B780133DAB2384BD9
-:100BFC001A70374B1B781A46344B1B8899B2364BFC
-:100C0C0023F81210324B1B780133DAB2304B1A70C6
-:100C1C00304B1B8801339AB22E4B1A80294B1B7810
-:100C2C00022B29D1284B1B78022B25D0274BB22223
-:100C3C001A80274B1B781A46264B1988274B23F80A
-:100C4C001210234B1B780133DAB2214B1A70204B54
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-:100C6C001B4B1B780133DAB2194B1A70194B1B88CA
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-:100D3C001C0000201C00002038060020FEE70000EC
-:100D4C0000A24A040000000000000000010203049D
-:0C0D5C00060708090A000000FFFF010262
-:0400000508000D05DD
+:100B4C0080B500AFFFF734FF03461A46114B1A600D
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+:0C0D5000060708090A000000FFFF01026E
+:0400000508000CF9EA
 :00000001FF

+ 198 - 203
stm32f1_03/build/main.lst

@@ -2146,25 +2146,25 @@ int main(void) {
  8000b50:	f7ff ff34 	bl	80009bc <SD_Init>
  8000b54:	4603      	mov	r3, r0
  8000b56:	461a      	mov	r2, r3
- 8000b58:	4b14      	ldr	r3, [pc, #80]	; (8000bac <main+0x60>)
+ 8000b58:	4b11      	ldr	r3, [pc, #68]	; (8000ba0 <main+0x54>)
  8000b5a:	601a      	str	r2, [r3, #0]
     checkSDStatus();
  8000b5c:	f7ff ff66 	bl	8000a2c <checkSDStatus>
     writeBufFilled = 0;
- 8000b60:	4b13      	ldr	r3, [pc, #76]	; (8000bb0 <main+0x64>)
+ 8000b60:	4b10      	ldr	r3, [pc, #64]	; (8000ba4 <main+0x58>)
  8000b62:	2200      	movs	r2, #0
  8000b64:	801a      	strh	r2, [r3, #0]
 //    SD_WriteHeaders();
     SDWriteOffset  = SD_BUFSIZE;
- 8000b66:	4b13      	ldr	r3, [pc, #76]	; (8000bb4 <main+0x68>)
+ 8000b66:	4b10      	ldr	r3, [pc, #64]	; (8000ba8 <main+0x5c>)
  8000b68:	f44f 7200 	mov.w	r2, #512	; 0x200
  8000b6c:	601a      	str	r2, [r3, #0]
     SystemCoreClockUpdate();
  8000b6e:	f7ff fb4d 	bl	800020c <SystemCoreClockUpdate>
     SysTick_Config(SystemCoreClock/10000);
- 8000b72:	4b11      	ldr	r3, [pc, #68]	; (8000bb8 <main+0x6c>)
+ 8000b72:	4b0e      	ldr	r3, [pc, #56]	; (8000bac <main+0x60>)
  8000b74:	681b      	ldr	r3, [r3, #0]
- 8000b76:	4a11      	ldr	r2, [pc, #68]	; (8000bbc <main+0x70>)
+ 8000b76:	4a0e      	ldr	r2, [pc, #56]	; (8000bb0 <main+0x64>)
  8000b78:	fba2 2303 	umull	r2, r3, r2, r3
  8000b7c:	0b5b      	lsrs	r3, r3, #13
  8000b7e:	4618      	mov	r0, r3
@@ -2172,321 +2172,316 @@ int main(void) {
     while (1)
 	{
 	if (BuffReady != 0){
- 8000b84:	4b0e      	ldr	r3, [pc, #56]	; (8000bc0 <main+0x74>)
+ 8000b84:	4b0b      	ldr	r3, [pc, #44]	; (8000bb4 <main+0x68>)
  8000b86:	781b      	ldrb	r3, [r3, #0]
  8000b88:	2b00      	cmp	r3, #0
  8000b8a:	d0fb      	beq.n	8000b84 <main+0x38>
 	check=1;
- 8000b8c:	4b0d      	ldr	r3, [pc, #52]	; (8000bc4 <main+0x78>)
+ 8000b8c:	4b0a      	ldr	r3, [pc, #40]	; (8000bb8 <main+0x6c>)
  8000b8e:	2201      	movs	r2, #1
  8000b90:	701a      	strb	r2, [r3, #0]
-	SD_WriteBlock_1(SDWriteOffset);
- 8000b92:	4b08      	ldr	r3, [pc, #32]	; (8000bb4 <main+0x68>)
- 8000b94:	681b      	ldr	r3, [r3, #0]
- 8000b96:	4618      	mov	r0, r3
- 8000b98:	f7ff ff52 	bl	8000a40 <SD_WriteBlock_1>
+//	SD_WriteBlock_1(SDWriteOffset);
         SDWriteOffset  = SDWriteOffset + SD_BUFSIZE;
- 8000b9c:	4b05      	ldr	r3, [pc, #20]	; (8000bb4 <main+0x68>)
- 8000b9e:	681b      	ldr	r3, [r3, #0]
- 8000ba0:	f503 7300 	add.w	r3, r3, #512	; 0x200
- 8000ba4:	4a03      	ldr	r2, [pc, #12]	; (8000bb4 <main+0x68>)
- 8000ba6:	6013      	str	r3, [r2, #0]
+ 8000b92:	4b05      	ldr	r3, [pc, #20]	; (8000ba8 <main+0x5c>)
+ 8000b94:	681b      	ldr	r3, [r3, #0]
+ 8000b96:	f503 7300 	add.w	r3, r3, #512	; 0x200
+ 8000b9a:	4a03      	ldr	r2, [pc, #12]	; (8000ba8 <main+0x5c>)
+ 8000b9c:	6013      	str	r3, [r2, #0]
 
 
 
 	}
 
     }
- 8000ba8:	e7ec      	b.n	8000b84 <main+0x38>
- 8000baa:	bf00      	nop
- 8000bac:	20000014 	.word	0x20000014
- 8000bb0:	20000226 	.word	0x20000226
- 8000bb4:	20000228 	.word	0x20000228
- 8000bb8:	20000000 	.word	0x20000000
- 8000bbc:	d1b71759 	.word	0xd1b71759
- 8000bc0:	20000630 	.word	0x20000630
- 8000bc4:	20000632 	.word	0x20000632
-
-08000bc8 <SysTick_Handler>:
+ 8000b9e:	e7f1      	b.n	8000b84 <main+0x38>
+ 8000ba0:	20000014 	.word	0x20000014
+ 8000ba4:	20000226 	.word	0x20000226
+ 8000ba8:	20000228 	.word	0x20000228
+ 8000bac:	20000000 	.word	0x20000000
+ 8000bb0:	d1b71759 	.word	0xd1b71759
+ 8000bb4:	20000630 	.word	0x20000630
+ 8000bb8:	20000632 	.word	0x20000632
+
+08000bbc <SysTick_Handler>:
 }
 
 void SysTick_Handler(void) {
- 8000bc8:	b480      	push	{r7}
- 8000bca:	af00      	add	r7, sp, #0
+ 8000bbc:	b480      	push	{r7}
+ 8000bbe:	af00      	add	r7, sp, #0
 
 if (Rstatus == 1 && Wstatus != 1){
- 8000bcc:	4b40      	ldr	r3, [pc, #256]	; (8000cd0 <SysTick_Handler+0x108>)
- 8000bce:	781b      	ldrb	r3, [r3, #0]
- 8000bd0:	2b01      	cmp	r3, #1
- 8000bd2:	d129      	bne.n	8000c28 <SysTick_Handler+0x60>
- 8000bd4:	4b3f      	ldr	r3, [pc, #252]	; (8000cd4 <SysTick_Handler+0x10c>)
- 8000bd6:	781b      	ldrb	r3, [r3, #0]
- 8000bd8:	2b01      	cmp	r3, #1
- 8000bda:	d025      	beq.n	8000c28 <SysTick_Handler+0x60>
+ 8000bc0:	4b40      	ldr	r3, [pc, #256]	; (8000cc4 <SysTick_Handler+0x108>)
+ 8000bc2:	781b      	ldrb	r3, [r3, #0]
+ 8000bc4:	2b01      	cmp	r3, #1
+ 8000bc6:	d129      	bne.n	8000c1c <SysTick_Handler+0x60>
+ 8000bc8:	4b3f      	ldr	r3, [pc, #252]	; (8000cc8 <SysTick_Handler+0x10c>)
+ 8000bca:	781b      	ldrb	r3, [r3, #0]
+ 8000bcc:	2b01      	cmp	r3, #1
+ 8000bce:	d025      	beq.n	8000c1c <SysTick_Handler+0x60>
 ADC1ConvertedValue = 0xB1;
- 8000bdc:	4b3e      	ldr	r3, [pc, #248]	; (8000cd8 <SysTick_Handler+0x110>)
- 8000bde:	22b1      	movs	r2, #177	; 0xb1
- 8000be0:	801a      	strh	r2, [r3, #0]
+ 8000bd0:	4b3e      	ldr	r3, [pc, #248]	; (8000ccc <SysTick_Handler+0x110>)
+ 8000bd2:	22b1      	movs	r2, #177	; 0xb1
+ 8000bd4:	801a      	strh	r2, [r3, #0]
 Buffer1[BuffCount] = TMSTP;
- 8000be2:	4b3e      	ldr	r3, [pc, #248]	; (8000cdc <SysTick_Handler+0x114>)
- 8000be4:	781b      	ldrb	r3, [r3, #0]
- 8000be6:	461a      	mov	r2, r3
- 8000be8:	4b3d      	ldr	r3, [pc, #244]	; (8000ce0 <SysTick_Handler+0x118>)
- 8000bea:	8819      	ldrh	r1, [r3, #0]
- 8000bec:	4b3d      	ldr	r3, [pc, #244]	; (8000ce4 <SysTick_Handler+0x11c>)
- 8000bee:	f823 1012 	strh.w	r1, [r3, r2, lsl #1]
+ 8000bd6:	4b3e      	ldr	r3, [pc, #248]	; (8000cd0 <SysTick_Handler+0x114>)
+ 8000bd8:	781b      	ldrb	r3, [r3, #0]
+ 8000bda:	461a      	mov	r2, r3
+ 8000bdc:	4b3d      	ldr	r3, [pc, #244]	; (8000cd4 <SysTick_Handler+0x118>)
+ 8000bde:	8819      	ldrh	r1, [r3, #0]
+ 8000be0:	4b3d      	ldr	r3, [pc, #244]	; (8000cd8 <SysTick_Handler+0x11c>)
+ 8000be2:	f823 1012 	strh.w	r1, [r3, r2, lsl #1]
 BuffCount++;
- 8000bf2:	4b3a      	ldr	r3, [pc, #232]	; (8000cdc <SysTick_Handler+0x114>)
- 8000bf4:	781b      	ldrb	r3, [r3, #0]
- 8000bf6:	3301      	adds	r3, #1
- 8000bf8:	b2da      	uxtb	r2, r3
- 8000bfa:	4b38      	ldr	r3, [pc, #224]	; (8000cdc <SysTick_Handler+0x114>)
- 8000bfc:	701a      	strb	r2, [r3, #0]
+ 8000be6:	4b3a      	ldr	r3, [pc, #232]	; (8000cd0 <SysTick_Handler+0x114>)
+ 8000be8:	781b      	ldrb	r3, [r3, #0]
+ 8000bea:	3301      	adds	r3, #1
+ 8000bec:	b2da      	uxtb	r2, r3
+ 8000bee:	4b38      	ldr	r3, [pc, #224]	; (8000cd0 <SysTick_Handler+0x114>)
+ 8000bf0:	701a      	strb	r2, [r3, #0]
 Buffer1[BuffCount] = ADC1ConvertedValue;
- 8000bfe:	4b37      	ldr	r3, [pc, #220]	; (8000cdc <SysTick_Handler+0x114>)
- 8000c00:	781b      	ldrb	r3, [r3, #0]
- 8000c02:	461a      	mov	r2, r3
- 8000c04:	4b34      	ldr	r3, [pc, #208]	; (8000cd8 <SysTick_Handler+0x110>)
- 8000c06:	881b      	ldrh	r3, [r3, #0]
- 8000c08:	b299      	uxth	r1, r3
- 8000c0a:	4b36      	ldr	r3, [pc, #216]	; (8000ce4 <SysTick_Handler+0x11c>)
- 8000c0c:	f823 1012 	strh.w	r1, [r3, r2, lsl #1]
+ 8000bf2:	4b37      	ldr	r3, [pc, #220]	; (8000cd0 <SysTick_Handler+0x114>)
+ 8000bf4:	781b      	ldrb	r3, [r3, #0]
+ 8000bf6:	461a      	mov	r2, r3
+ 8000bf8:	4b34      	ldr	r3, [pc, #208]	; (8000ccc <SysTick_Handler+0x110>)
+ 8000bfa:	881b      	ldrh	r3, [r3, #0]
+ 8000bfc:	b299      	uxth	r1, r3
+ 8000bfe:	4b36      	ldr	r3, [pc, #216]	; (8000cd8 <SysTick_Handler+0x11c>)
+ 8000c00:	f823 1012 	strh.w	r1, [r3, r2, lsl #1]
 BuffCount++;
- 8000c10:	4b32      	ldr	r3, [pc, #200]	; (8000cdc <SysTick_Handler+0x114>)
- 8000c12:	781b      	ldrb	r3, [r3, #0]
- 8000c14:	3301      	adds	r3, #1
- 8000c16:	b2da      	uxtb	r2, r3
- 8000c18:	4b30      	ldr	r3, [pc, #192]	; (8000cdc <SysTick_Handler+0x114>)
- 8000c1a:	701a      	strb	r2, [r3, #0]
+ 8000c04:	4b32      	ldr	r3, [pc, #200]	; (8000cd0 <SysTick_Handler+0x114>)
+ 8000c06:	781b      	ldrb	r3, [r3, #0]
+ 8000c08:	3301      	adds	r3, #1
+ 8000c0a:	b2da      	uxtb	r2, r3
+ 8000c0c:	4b30      	ldr	r3, [pc, #192]	; (8000cd0 <SysTick_Handler+0x114>)
+ 8000c0e:	701a      	strb	r2, [r3, #0]
 TMSTP++;
- 8000c1c:	4b30      	ldr	r3, [pc, #192]	; (8000ce0 <SysTick_Handler+0x118>)
- 8000c1e:	881b      	ldrh	r3, [r3, #0]
- 8000c20:	3301      	adds	r3, #1
- 8000c22:	b29a      	uxth	r2, r3
- 8000c24:	4b2e      	ldr	r3, [pc, #184]	; (8000ce0 <SysTick_Handler+0x118>)
- 8000c26:	801a      	strh	r2, [r3, #0]
+ 8000c10:	4b30      	ldr	r3, [pc, #192]	; (8000cd4 <SysTick_Handler+0x118>)
+ 8000c12:	881b      	ldrh	r3, [r3, #0]
+ 8000c14:	3301      	adds	r3, #1
+ 8000c16:	b29a      	uxth	r2, r3
+ 8000c18:	4b2e      	ldr	r3, [pc, #184]	; (8000cd4 <SysTick_Handler+0x118>)
+ 8000c1a:	801a      	strh	r2, [r3, #0]
 }
 
 if (Rstatus == 2 && Wstatus != 2){
- 8000c28:	4b29      	ldr	r3, [pc, #164]	; (8000cd0 <SysTick_Handler+0x108>)
- 8000c2a:	781b      	ldrb	r3, [r3, #0]
- 8000c2c:	2b02      	cmp	r3, #2
- 8000c2e:	d129      	bne.n	8000c84 <SysTick_Handler+0xbc>
- 8000c30:	4b28      	ldr	r3, [pc, #160]	; (8000cd4 <SysTick_Handler+0x10c>)
- 8000c32:	781b      	ldrb	r3, [r3, #0]
- 8000c34:	2b02      	cmp	r3, #2
- 8000c36:	d025      	beq.n	8000c84 <SysTick_Handler+0xbc>
+ 8000c1c:	4b29      	ldr	r3, [pc, #164]	; (8000cc4 <SysTick_Handler+0x108>)
+ 8000c1e:	781b      	ldrb	r3, [r3, #0]
+ 8000c20:	2b02      	cmp	r3, #2
+ 8000c22:	d129      	bne.n	8000c78 <SysTick_Handler+0xbc>
+ 8000c24:	4b28      	ldr	r3, [pc, #160]	; (8000cc8 <SysTick_Handler+0x10c>)
+ 8000c26:	781b      	ldrb	r3, [r3, #0]
+ 8000c28:	2b02      	cmp	r3, #2
+ 8000c2a:	d025      	beq.n	8000c78 <SysTick_Handler+0xbc>
 ADC1ConvertedValue = 0xB2;
- 8000c38:	4b27      	ldr	r3, [pc, #156]	; (8000cd8 <SysTick_Handler+0x110>)
- 8000c3a:	22b2      	movs	r2, #178	; 0xb2
- 8000c3c:	801a      	strh	r2, [r3, #0]
+ 8000c2c:	4b27      	ldr	r3, [pc, #156]	; (8000ccc <SysTick_Handler+0x110>)
+ 8000c2e:	22b2      	movs	r2, #178	; 0xb2
+ 8000c30:	801a      	strh	r2, [r3, #0]
 Buffer2[BuffCount] = TMSTP;
- 8000c3e:	4b27      	ldr	r3, [pc, #156]	; (8000cdc <SysTick_Handler+0x114>)
- 8000c40:	781b      	ldrb	r3, [r3, #0]
- 8000c42:	461a      	mov	r2, r3
- 8000c44:	4b26      	ldr	r3, [pc, #152]	; (8000ce0 <SysTick_Handler+0x118>)
- 8000c46:	8819      	ldrh	r1, [r3, #0]
- 8000c48:	4b27      	ldr	r3, [pc, #156]	; (8000ce8 <SysTick_Handler+0x120>)
- 8000c4a:	f823 1012 	strh.w	r1, [r3, r2, lsl #1]
+ 8000c32:	4b27      	ldr	r3, [pc, #156]	; (8000cd0 <SysTick_Handler+0x114>)
+ 8000c34:	781b      	ldrb	r3, [r3, #0]
+ 8000c36:	461a      	mov	r2, r3
+ 8000c38:	4b26      	ldr	r3, [pc, #152]	; (8000cd4 <SysTick_Handler+0x118>)
+ 8000c3a:	8819      	ldrh	r1, [r3, #0]
+ 8000c3c:	4b27      	ldr	r3, [pc, #156]	; (8000cdc <SysTick_Handler+0x120>)
+ 8000c3e:	f823 1012 	strh.w	r1, [r3, r2, lsl #1]
 BuffCount++;
- 8000c4e:	4b23      	ldr	r3, [pc, #140]	; (8000cdc <SysTick_Handler+0x114>)
- 8000c50:	781b      	ldrb	r3, [r3, #0]
- 8000c52:	3301      	adds	r3, #1
- 8000c54:	b2da      	uxtb	r2, r3
- 8000c56:	4b21      	ldr	r3, [pc, #132]	; (8000cdc <SysTick_Handler+0x114>)
- 8000c58:	701a      	strb	r2, [r3, #0]
+ 8000c42:	4b23      	ldr	r3, [pc, #140]	; (8000cd0 <SysTick_Handler+0x114>)
+ 8000c44:	781b      	ldrb	r3, [r3, #0]
+ 8000c46:	3301      	adds	r3, #1
+ 8000c48:	b2da      	uxtb	r2, r3
+ 8000c4a:	4b21      	ldr	r3, [pc, #132]	; (8000cd0 <SysTick_Handler+0x114>)
+ 8000c4c:	701a      	strb	r2, [r3, #0]
 Buffer2[BuffCount] = ADC1ConvertedValue;
- 8000c5a:	4b20      	ldr	r3, [pc, #128]	; (8000cdc <SysTick_Handler+0x114>)
- 8000c5c:	781b      	ldrb	r3, [r3, #0]
- 8000c5e:	461a      	mov	r2, r3
- 8000c60:	4b1d      	ldr	r3, [pc, #116]	; (8000cd8 <SysTick_Handler+0x110>)
- 8000c62:	881b      	ldrh	r3, [r3, #0]
- 8000c64:	b299      	uxth	r1, r3
- 8000c66:	4b20      	ldr	r3, [pc, #128]	; (8000ce8 <SysTick_Handler+0x120>)
- 8000c68:	f823 1012 	strh.w	r1, [r3, r2, lsl #1]
+ 8000c4e:	4b20      	ldr	r3, [pc, #128]	; (8000cd0 <SysTick_Handler+0x114>)
+ 8000c50:	781b      	ldrb	r3, [r3, #0]
+ 8000c52:	461a      	mov	r2, r3
+ 8000c54:	4b1d      	ldr	r3, [pc, #116]	; (8000ccc <SysTick_Handler+0x110>)
+ 8000c56:	881b      	ldrh	r3, [r3, #0]
+ 8000c58:	b299      	uxth	r1, r3
+ 8000c5a:	4b20      	ldr	r3, [pc, #128]	; (8000cdc <SysTick_Handler+0x120>)
+ 8000c5c:	f823 1012 	strh.w	r1, [r3, r2, lsl #1]
 BuffCount++;
- 8000c6c:	4b1b      	ldr	r3, [pc, #108]	; (8000cdc <SysTick_Handler+0x114>)
- 8000c6e:	781b      	ldrb	r3, [r3, #0]
- 8000c70:	3301      	adds	r3, #1
- 8000c72:	b2da      	uxtb	r2, r3
- 8000c74:	4b19      	ldr	r3, [pc, #100]	; (8000cdc <SysTick_Handler+0x114>)
- 8000c76:	701a      	strb	r2, [r3, #0]
+ 8000c60:	4b1b      	ldr	r3, [pc, #108]	; (8000cd0 <SysTick_Handler+0x114>)
+ 8000c62:	781b      	ldrb	r3, [r3, #0]
+ 8000c64:	3301      	adds	r3, #1
+ 8000c66:	b2da      	uxtb	r2, r3
+ 8000c68:	4b19      	ldr	r3, [pc, #100]	; (8000cd0 <SysTick_Handler+0x114>)
+ 8000c6a:	701a      	strb	r2, [r3, #0]
 TMSTP++;
- 8000c78:	4b19      	ldr	r3, [pc, #100]	; (8000ce0 <SysTick_Handler+0x118>)
- 8000c7a:	881b      	ldrh	r3, [r3, #0]
- 8000c7c:	3301      	adds	r3, #1
- 8000c7e:	b29a      	uxth	r2, r3
- 8000c80:	4b17      	ldr	r3, [pc, #92]	; (8000ce0 <SysTick_Handler+0x118>)
- 8000c82:	801a      	strh	r2, [r3, #0]
+ 8000c6c:	4b19      	ldr	r3, [pc, #100]	; (8000cd4 <SysTick_Handler+0x118>)
+ 8000c6e:	881b      	ldrh	r3, [r3, #0]
+ 8000c70:	3301      	adds	r3, #1
+ 8000c72:	b29a      	uxth	r2, r3
+ 8000c74:	4b17      	ldr	r3, [pc, #92]	; (8000cd4 <SysTick_Handler+0x118>)
+ 8000c76:	801a      	strh	r2, [r3, #0]
 }
 
 if ( BuffCount == 254 && Rstatus == 1 ){
- 8000c84:	4b15      	ldr	r3, [pc, #84]	; (8000cdc <SysTick_Handler+0x114>)
- 8000c86:	781b      	ldrb	r3, [r3, #0]
- 8000c88:	2bfe      	cmp	r3, #254	; 0xfe
- 8000c8a:	d10c      	bne.n	8000ca6 <SysTick_Handler+0xde>
- 8000c8c:	4b10      	ldr	r3, [pc, #64]	; (8000cd0 <SysTick_Handler+0x108>)
- 8000c8e:	781b      	ldrb	r3, [r3, #0]
- 8000c90:	2b01      	cmp	r3, #1
- 8000c92:	d108      	bne.n	8000ca6 <SysTick_Handler+0xde>
+ 8000c78:	4b15      	ldr	r3, [pc, #84]	; (8000cd0 <SysTick_Handler+0x114>)
+ 8000c7a:	781b      	ldrb	r3, [r3, #0]
+ 8000c7c:	2bfe      	cmp	r3, #254	; 0xfe
+ 8000c7e:	d10c      	bne.n	8000c9a <SysTick_Handler+0xde>
+ 8000c80:	4b10      	ldr	r3, [pc, #64]	; (8000cc4 <SysTick_Handler+0x108>)
+ 8000c82:	781b      	ldrb	r3, [r3, #0]
+ 8000c84:	2b01      	cmp	r3, #1
+ 8000c86:	d108      	bne.n	8000c9a <SysTick_Handler+0xde>
 	Rstatus = 2;
- 8000c94:	4b0e      	ldr	r3, [pc, #56]	; (8000cd0 <SysTick_Handler+0x108>)
- 8000c96:	2202      	movs	r2, #2
- 8000c98:	701a      	strb	r2, [r3, #0]
+ 8000c88:	4b0e      	ldr	r3, [pc, #56]	; (8000cc4 <SysTick_Handler+0x108>)
+ 8000c8a:	2202      	movs	r2, #2
+ 8000c8c:	701a      	strb	r2, [r3, #0]
 	BuffReady = 1;
- 8000c9a:	4b14      	ldr	r3, [pc, #80]	; (8000cec <SysTick_Handler+0x124>)
- 8000c9c:	2201      	movs	r2, #1
- 8000c9e:	701a      	strb	r2, [r3, #0]
+ 8000c8e:	4b14      	ldr	r3, [pc, #80]	; (8000ce0 <SysTick_Handler+0x124>)
+ 8000c90:	2201      	movs	r2, #1
+ 8000c92:	701a      	strb	r2, [r3, #0]
 	BuffCount = 0;
- 8000ca0:	4b0e      	ldr	r3, [pc, #56]	; (8000cdc <SysTick_Handler+0x114>)
- 8000ca2:	2200      	movs	r2, #0
- 8000ca4:	701a      	strb	r2, [r3, #0]
+ 8000c94:	4b0e      	ldr	r3, [pc, #56]	; (8000cd0 <SysTick_Handler+0x114>)
+ 8000c96:	2200      	movs	r2, #0
+ 8000c98:	701a      	strb	r2, [r3, #0]
 }
 
 if (BuffCount == 254 && Rstatus == 2){
- 8000ca6:	4b0d      	ldr	r3, [pc, #52]	; (8000cdc <SysTick_Handler+0x114>)
- 8000ca8:	781b      	ldrb	r3, [r3, #0]
- 8000caa:	2bfe      	cmp	r3, #254	; 0xfe
- 8000cac:	d10c      	bne.n	8000cc8 <SysTick_Handler+0x100>
- 8000cae:	4b08      	ldr	r3, [pc, #32]	; (8000cd0 <SysTick_Handler+0x108>)
- 8000cb0:	781b      	ldrb	r3, [r3, #0]
- 8000cb2:	2b02      	cmp	r3, #2
- 8000cb4:	d108      	bne.n	8000cc8 <SysTick_Handler+0x100>
+ 8000c9a:	4b0d      	ldr	r3, [pc, #52]	; (8000cd0 <SysTick_Handler+0x114>)
+ 8000c9c:	781b      	ldrb	r3, [r3, #0]
+ 8000c9e:	2bfe      	cmp	r3, #254	; 0xfe
+ 8000ca0:	d10c      	bne.n	8000cbc <SysTick_Handler+0x100>
+ 8000ca2:	4b08      	ldr	r3, [pc, #32]	; (8000cc4 <SysTick_Handler+0x108>)
+ 8000ca4:	781b      	ldrb	r3, [r3, #0]
+ 8000ca6:	2b02      	cmp	r3, #2
+ 8000ca8:	d108      	bne.n	8000cbc <SysTick_Handler+0x100>
 	Rstatus = 1;
- 8000cb6:	4b06      	ldr	r3, [pc, #24]	; (8000cd0 <SysTick_Handler+0x108>)
- 8000cb8:	2201      	movs	r2, #1
- 8000cba:	701a      	strb	r2, [r3, #0]
+ 8000caa:	4b06      	ldr	r3, [pc, #24]	; (8000cc4 <SysTick_Handler+0x108>)
+ 8000cac:	2201      	movs	r2, #1
+ 8000cae:	701a      	strb	r2, [r3, #0]
 	BuffReady = 2;
- 8000cbc:	4b0b      	ldr	r3, [pc, #44]	; (8000cec <SysTick_Handler+0x124>)
- 8000cbe:	2202      	movs	r2, #2
- 8000cc0:	701a      	strb	r2, [r3, #0]
+ 8000cb0:	4b0b      	ldr	r3, [pc, #44]	; (8000ce0 <SysTick_Handler+0x124>)
+ 8000cb2:	2202      	movs	r2, #2
+ 8000cb4:	701a      	strb	r2, [r3, #0]
 	BuffCount = 0;
- 8000cc2:	4b06      	ldr	r3, [pc, #24]	; (8000cdc <SysTick_Handler+0x114>)
- 8000cc4:	2200      	movs	r2, #0
- 8000cc6:	701a      	strb	r2, [r3, #0]
+ 8000cb6:	4b06      	ldr	r3, [pc, #24]	; (8000cd0 <SysTick_Handler+0x114>)
+ 8000cb8:	2200      	movs	r2, #0
+ 8000cba:	701a      	strb	r2, [r3, #0]
 }
 
 
 }
- 8000cc8:	bf00      	nop
- 8000cca:	46bd      	mov	sp, r7
- 8000ccc:	bc80      	pop	{r7}
- 8000cce:	4770      	bx	lr
- 8000cd0:	2000001a 	.word	0x2000001a
- 8000cd4:	2000001b 	.word	0x2000001b
- 8000cd8:	2000022c 	.word	0x2000022c
- 8000cdc:	20000631 	.word	0x20000631
- 8000ce0:	20000634 	.word	0x20000634
- 8000ce4:	20000230 	.word	0x20000230
- 8000ce8:	20000430 	.word	0x20000430
- 8000cec:	20000630 	.word	0x20000630
- 8000cf0:	08000d4c 	.word	0x08000d4c
- 8000cf4:	20000000 	.word	0x20000000
- 8000cf8:	2000001c 	.word	0x2000001c
- 8000cfc:	2000001c 	.word	0x2000001c
- 8000d00:	20000638 	.word	0x20000638
-
-08000d04 <Reset_Handler>:
+ 8000cbc:	bf00      	nop
+ 8000cbe:	46bd      	mov	sp, r7
+ 8000cc0:	bc80      	pop	{r7}
+ 8000cc2:	4770      	bx	lr
+ 8000cc4:	2000001a 	.word	0x2000001a
+ 8000cc8:	2000001b 	.word	0x2000001b
+ 8000ccc:	2000022c 	.word	0x2000022c
+ 8000cd0:	20000631 	.word	0x20000631
+ 8000cd4:	20000634 	.word	0x20000634
+ 8000cd8:	20000230 	.word	0x20000230
+ 8000cdc:	20000430 	.word	0x20000430
+ 8000ce0:	20000630 	.word	0x20000630
+ 8000ce4:	08000d40 	.word	0x08000d40
+ 8000ce8:	20000000 	.word	0x20000000
+ 8000cec:	2000001c 	.word	0x2000001c
+ 8000cf0:	2000001c 	.word	0x2000001c
+ 8000cf4:	20000638 	.word	0x20000638
+
+08000cf8 <Reset_Handler>:
 	.weak	Reset_Handler
 	.type	Reset_Handler, %function
 Reset_Handler:	
 
 /* Copy the data segment initializers from flash to SRAM */  
   movs	r1, #0
- 8000d04:	2100      	movs	r1, #0
+ 8000cf8:	2100      	movs	r1, #0
   b	LoopCopyDataInit
- 8000d06:	e003      	b.n	8000d10 <LoopCopyDataInit>
+ 8000cfa:	e003      	b.n	8000d04 <LoopCopyDataInit>
 
-08000d08 <CopyDataInit>:
+08000cfc <CopyDataInit>:
 
 CopyDataInit:
 	ldr	r3, =_sidata
- 8000d08:	4b0a      	ldr	r3, [pc, #40]	; (8000d34 <LoopFillZerobss+0x10>)
+ 8000cfc:	4b0a      	ldr	r3, [pc, #40]	; (8000d28 <LoopFillZerobss+0x10>)
 	ldr	r3, [r3, r1]
- 8000d0a:	585b      	ldr	r3, [r3, r1]
+ 8000cfe:	585b      	ldr	r3, [r3, r1]
 	str	r3, [r0, r1]
- 8000d0c:	5043      	str	r3, [r0, r1]
+ 8000d00:	5043      	str	r3, [r0, r1]
 	adds	r1, r1, #4
- 8000d0e:	3104      	adds	r1, #4
+ 8000d02:	3104      	adds	r1, #4
 
-08000d10 <LoopCopyDataInit>:
+08000d04 <LoopCopyDataInit>:
     
 LoopCopyDataInit:
 	ldr	r0, =_sdata
- 8000d10:	4809      	ldr	r0, [pc, #36]	; (8000d38 <LoopFillZerobss+0x14>)
+ 8000d04:	4809      	ldr	r0, [pc, #36]	; (8000d2c <LoopFillZerobss+0x14>)
 	ldr	r3, =_edata
- 8000d12:	4b0a      	ldr	r3, [pc, #40]	; (8000d3c <LoopFillZerobss+0x18>)
+ 8000d06:	4b0a      	ldr	r3, [pc, #40]	; (8000d30 <LoopFillZerobss+0x18>)
 	adds	r2, r0, r1
- 8000d14:	1842      	adds	r2, r0, r1
+ 8000d08:	1842      	adds	r2, r0, r1
 	cmp	r2, r3
- 8000d16:	429a      	cmp	r2, r3
+ 8000d0a:	429a      	cmp	r2, r3
 	bcc	CopyDataInit
- 8000d18:	d3f6      	bcc.n	8000d08 <CopyDataInit>
+ 8000d0c:	d3f6      	bcc.n	8000cfc <CopyDataInit>
 	ldr	r2, =_sbss
- 8000d1a:	4a09      	ldr	r2, [pc, #36]	; (8000d40 <LoopFillZerobss+0x1c>)
+ 8000d0e:	4a09      	ldr	r2, [pc, #36]	; (8000d34 <LoopFillZerobss+0x1c>)
 	b	LoopFillZerobss
- 8000d1c:	e002      	b.n	8000d24 <LoopFillZerobss>
+ 8000d10:	e002      	b.n	8000d18 <LoopFillZerobss>
 
-08000d1e <FillZerobss>:
+08000d12 <FillZerobss>:
 /* Zero fill the bss segment. */  
 FillZerobss:
 	movs	r3, #0
- 8000d1e:	2300      	movs	r3, #0
+ 8000d12:	2300      	movs	r3, #0
 	str	r3, [r2], #4
- 8000d20:	f842 3b04 	str.w	r3, [r2], #4
+ 8000d14:	f842 3b04 	str.w	r3, [r2], #4
 
-08000d24 <LoopFillZerobss>:
+08000d18 <LoopFillZerobss>:
     
 LoopFillZerobss:
 	ldr	r3, = _ebss
- 8000d24:	4b07      	ldr	r3, [pc, #28]	; (8000d44 <LoopFillZerobss+0x20>)
+ 8000d18:	4b07      	ldr	r3, [pc, #28]	; (8000d38 <LoopFillZerobss+0x20>)
 	cmp	r2, r3
- 8000d26:	429a      	cmp	r2, r3
+ 8000d1a:	429a      	cmp	r2, r3
 	bcc	FillZerobss
- 8000d28:	d3f9      	bcc.n	8000d1e <FillZerobss>
+ 8000d1c:	d3f9      	bcc.n	8000d12 <FillZerobss>
 /* Call the clock system intitialization function.*/
   bl  SystemInit  
- 8000d2a:	f7ff fa3b 	bl	80001a4 <SystemInit>
+ 8000d1e:	f7ff fa41 	bl	80001a4 <SystemInit>
 /* Call the application's entry point.*/
 	bl	main
- 8000d2e:	f7ff ff0d 	bl	8000b4c <main>
+ 8000d22:	f7ff ff13 	bl	8000b4c <main>
 	bx	lr    
- 8000d32:	4770      	bx	lr
+ 8000d26:	4770      	bx	lr
 /* Copy the data segment initializers from flash to SRAM */  
   movs	r1, #0
   b	LoopCopyDataInit
 
 CopyDataInit:
 	ldr	r3, =_sidata
- 8000d34:	08000d4c 	.word	0x08000d4c
+ 8000d28:	08000d40 	.word	0x08000d40
 	ldr	r3, [r3, r1]
 	str	r3, [r0, r1]
 	adds	r1, r1, #4
     
 LoopCopyDataInit:
 	ldr	r0, =_sdata
- 8000d38:	20000000 	.word	0x20000000
+ 8000d2c:	20000000 	.word	0x20000000
 	ldr	r3, =_edata
- 8000d3c:	2000001c 	.word	0x2000001c
+ 8000d30:	2000001c 	.word	0x2000001c
 	adds	r2, r0, r1
 	cmp	r2, r3
 	bcc	CopyDataInit
 	ldr	r2, =_sbss
- 8000d40:	2000001c 	.word	0x2000001c
+ 8000d34:	2000001c 	.word	0x2000001c
 FillZerobss:
 	movs	r3, #0
 	str	r3, [r2], #4
     
 LoopFillZerobss:
 	ldr	r3, = _ebss
- 8000d44:	20000638 	.word	0x20000638
+ 8000d38:	20000638 	.word	0x20000638
 
-08000d48 <ADC1_2_IRQHandler>:
+08000d3c <ADC1_2_IRQHandler>:
  * @retval None       
 */
     .section	.text.Default_Handler,"ax",%progbits
 Default_Handler:
 Infinite_Loop:
 	b	Infinite_Loop
- 8000d48:	e7fe      	b.n	8000d48 <ADC1_2_IRQHandler>
+ 8000d3c:	e7fe      	b.n	8000d3c <ADC1_2_IRQHandler>
 	...

BIN
stm32f1_03/build/main.o


BIN
stm32f1_03/build/startup_stm32f10x_ld.o


+ 59 - 470
stm32f1_03/main.c

@@ -112,8 +112,7 @@
 #define SD_CS_LOW()     GPIO_ResetBits(SD_CS_GPIO_PORT, SD_CS_PIN)
 #define SD_CS_HIGH()    GPIO_SetBits(SD_CS_GPIO_PORT, SD_CS_PIN)
 #define SD_DUMMY_BYTE   0xFF
-
-
+#define RCC_APB2Periph_ADC1              ((uint32_t)0x00000200)
 
 #define SPI_I2S_FLAG_RXNE               ((uint16_t)0x0001)
 #define SPI_I2S_FLAG_TXE                ((uint16_t)0x0002)
@@ -129,8 +128,10 @@
                                    ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
                                    ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))
 
-
-
+#define ADC_ExternalTrigConv_None                  ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_DataAlign_Right                        ((uint32_t)0x00000000)
+#define ADC_Channel_0                               ((uint8_t)0x00)
+#define ADC_Mode_Independent                       ((uint32_t)0x00000000)
 
 #ifdef  USE_FULL_ASSERT
   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
@@ -155,7 +156,28 @@ uint8_t  BuffReady = 0, BuffCount = 0, Rstatus = 1, Wstatus = 2, check = 0;
 
 uint16_t TMSTP = 0;
 
-
+                                                                                                                             
+typedef struct                                                                                                               
+{                                                                                                                            
+  uint32_t ADC_Mode;                      /*!< Configures the ADC to operate in independent or                               
+                                               dual mode.                                                                    
+                                               This parameter can be a value of @ref ADC_mode */                             
+                                                                                                                             
+  FunctionalState ADC_ScanConvMode;       /*!< Specifies whether the conversion is performed in                              
+                                               Scan (multichannels) or Single (one channel) mode.                            
+                                               This parameter can be set to ENABLE or DISABLE */                             
+  FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in                              
+                                               Continuous or Single mode.                                                    
+                                               This parameter can be set to ENABLE or DISABLE. */                            
+  uint32_t ADC_ExternalTrigConv;          /*!< Defines the external trigger used to start the analog                         
+                                               to digital conversion of regular channels. This parameter                     
+                                               can be a value of @ref ADC_external_trigger_sources_for_regular_channels_convers*/
+  uint32_t ADC_DataAlign;                 /*!< Specifies whether the ADC data alignment is left or right.                    
+                                               This parameter can be a value of @ref ADC_data_align */                       
+  uint8_t ADC_NbrOfChannel;               /*!< Specifies the number of ADC channels that will be converted                   
+                                               using the sequencer for regular channel group.                                
+                                               This parameter must range from 1 to 16. */                                    
+}ADC_InitTypeDef;                                                                                                            
 
 typedef struct
 {
@@ -296,78 +318,20 @@ SD_Error SD_GoIdleState(void);
 void SD_SendCmd(uint8_t Cmd, uint32_t Arg, uint8_t Crc);
 SD_Error SD_GetResponse(uint8_t Response);
 uint8_t SD_GetDataResponse(void);
+void ADC_DeInit(ADC_TypeDef* ADCx);
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ResetCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_StartCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
 
 
 
 
 
-
-
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
-  /* Check the status of the specified SPI/I2S flag */
-  if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
-  {
-    /* SPI_I2S_FLAG is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* SPI_I2S_FLAG is reset */
-    bitstatus = RESET;
-  }
-  /* Return the SPI_I2S_FLAG status */
-  return  bitstatus;
-}
-
-
-void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  
-  /* Write in the DR register the data to be sent */
-  SPIx->DR = Data;
-}
-
-
-
-uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  
-  /* Return the data in the DR register */
-  return SPIx->DR;
-}
-
-
-
-uint8_t SD_WriteByte(uint8_t Data)
-{
-  /*!< Wait until the transmit buffer is empty */
-  while(SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_TXE) == RESET)
-  {
-  }
-  
-  /*!< Send the byte */
-  SPI_I2S_SendData(SD_SPI, Data);
-  
-  /*!< Wait to receive a byte*/
-  while(SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
-  {
-  }
-  
-  /*!< Return the byte read from the SPI bus */ 
-  return SPI_I2S_ReceiveData(SD_SPI);
-}
-
-
-
 void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
 {
   uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
@@ -458,412 +422,37 @@ void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
 
 
 
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
-{
-  uint16_t tmpreg = 0;
-  
-  /* check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));   
-  
-  /* Check the SPI parameters */
-  assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
-  assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
-  assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
-  assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
-  assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
-  assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
-  assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
-  assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
-  assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
-
-/*---------------------------- SPIx CR1 Configuration ------------------------*/
-  /* Get the SPIx CR1 value */
-  tmpreg = SPIx->CR1;
-  /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
-  tmpreg &= CR1_CLEAR_Mask;
-  /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
-     master/salve mode, CPOL and CPHA */
-  /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
-  /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
-  /* Set LSBFirst bit according to SPI_FirstBit value */
-  /* Set BR bits according to SPI_BaudRatePrescaler value */
-  /* Set CPOL bit according to SPI_CPOL value */
-  /* Set CPHA bit according to SPI_CPHA value */
-  tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
-                  SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |  
-                  SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |  
-                  SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
-  /* Write to SPIx CR1 */
-  SPIx->CR1 = tmpreg;
-  
-  /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
-  SPIx->I2SCFGR &= SPI_Mode_Select;
-
-/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
-  /* Write to SPIx CRCPOLY */
-  SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
-}
-
-
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected SPI peripheral */
-    SPIx->CR1 |= CR1_SPE_Set;
-  }
-  else
-  {
-    /* Disable the selected SPI peripheral */
-    SPIx->CR1 &= CR1_SPE_Reset;
-  }
-}
-
-
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-  
-  GPIOx->BSRR = GPIO_Pin;
-}
-
-
-
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    RCC->APB2ENR |= RCC_APB2Periph;
-  }
-  else
-  {
-    RCC->APB2ENR &= ~RCC_APB2Periph;
-  }
-}
-
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-  
-  GPIOx->BRR = GPIO_Pin;
-}
-
-
-
-
-
-void SD_LowLevel_Init(void)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-  SPI_InitTypeDef   SPI_InitStructure;
-
-  /*!< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO 
-       and SD_SPI_SCK_GPIO Periph clock enable */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
-
-  /*!< SD_SPI Periph clock enable */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE); 
-
-  
-  /*!< Configure SD_SPI pins: SCK */
-  GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN |  SD_SPI_MOSI_PIN | SD_SPI_MISO_PIN;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */
-  GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-  GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< SD_SPI Config */
-  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
-  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
-  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
-  SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
-  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
-  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
-  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
-
-  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
-  SPI_InitStructure.SPI_CRCPolynomial = 7;
-  SPI_Init(SD_SPI, &SPI_InitStructure);
-  
-  SPI_Cmd(SD_SPI, ENABLE); /*!< SD_SPI enable */
-}
-
-
-
-SD_Error SD_GoIdleState(void)
-{
-  /*!< SD chip select low */
-  SD_CS_LOW();
-  
-  /*!< Send CMD0 (SD_CMD_GO_IDLE_STATE) to put SD in SPI mode */
-  SD_SendCmd(SD_CMD_GO_IDLE_STATE, 0, 0x95);
-  
-  /*!< Wait for In Idle State Response (R1 Format) equal to 0x01 */
-  if (SD_GetResponse(SD_IN_IDLE_STATE))
-  {
-    /*!< No Idle State Response: return response failue */
-    return SD_RESPONSE_FAILURE;
-  }
-  /*----------Activates the card initialization process-----------*/
-  do
-  {
-    /*!< SD chip select high */
-    SD_CS_HIGH();
-    
-    /*!< Send Dummy byte 0xFF */
-    SD_WriteByte(SD_DUMMY_BYTE);
-    
-    /*!< SD chip select low */
-    SD_CS_LOW();
-    
-    /*!< Send CMD1 (Activates the card process) until response equal to 0x0 */
-    SD_SendCmd(SD_CMD_SEND_OP_COND, 0, 0xFF);
-    /*!< Wait for no error Response (R1 Format) equal to 0x00 */
-  }
-  while (SD_GetResponse(SD_RESPONSE_NO_ERROR));
-  
-  /*!< SD chip select high */
-  SD_CS_HIGH();
-  
-  /*!< Send dummy byte 0xFF */
-  SD_WriteByte(SD_DUMMY_BYTE);
-  
-  return SD_RESPONSE_NO_ERROR;
-}
-
-
-void SD_SendCmd(uint8_t Cmd, uint32_t Arg, uint8_t Crc)
-{
-  uint32_t i = 0x00;
-  
-  uint8_t Frame[6];
-  
-  Frame[0] = (Cmd | 0x40); /*!< Construct byte 1 */
-  
-  Frame[1] = (uint8_t)(Arg >> 24); /*!< Construct byte 2 */
-  
-  Frame[2] = (uint8_t)(Arg >> 16); /*!< Construct byte 3 */
-  
-  Frame[3] = (uint8_t)(Arg >> 8); /*!< Construct byte 4 */
-  
-  Frame[4] = (uint8_t)(Arg); /*!< Construct byte 5 */
-  
-  Frame[5] = (Crc); /*!< Construct CRC: byte 6 */
-  
-  for (i = 0; i < 6; i++)
-  {
-    SD_WriteByte(Frame[i]); /*!< Send the Cmd bytes */
-  }
-}
-
-
-SD_Error SD_GetResponse(uint8_t Response)
-{
-  uint32_t Count = 0xFFF;
-
-  /*!< Check if response is got or a timeout is happen */
-  while ((SD_ReadByte() != Response) && Count)
-  {
-    Count--;
-  }
-  if (Count == 0)
-  {
-    /*!< After time out */
-    return SD_RESPONSE_FAILURE;
-  }
-  else
-  {
-    /*!< Right response got */
-    return SD_RESPONSE_NO_ERROR;
-  }
-}
-
-uint8_t SD_ReadByte(void)
-{
-  uint8_t Data = 0;
-  
-  /*!< Wait until the transmit buffer is empty */
-  while (SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_TXE) == RESET)
-  {
-  }
-  /*!< Send the byte */
-  SPI_I2S_SendData(SD_SPI, SD_DUMMY_BYTE);
-
-  /*!< Wait until a data is received */
-  while (SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
-  {
-  }
-  /*!< Get the received data */
-  Data = SPI_I2S_ReceiveData(SD_SPI);
-
-  /*!< Return the shifted data */
-  return Data;
-}
-
-uint8_t SD_GetDataResponse(void)
-{
-  uint32_t i = 0;
-  uint8_t response, rvalue;
-
-  while (i <= 64)
-  {
-    /*!< Read resonse */
-    response = SD_ReadByte();
-    /*!< Mask unused bits */
-    response &= 0x1F;
-    switch (response)
-    {
-      case SD_DATA_OK:
-      {
-        rvalue = SD_DATA_OK;
-        break;
-      }
-      case SD_DATA_CRC_ERROR:
-        return SD_DATA_CRC_ERROR;
-      case SD_DATA_WRITE_ERROR:
-        return SD_DATA_WRITE_ERROR;
-      default:
-      {
-        rvalue = SD_DATA_OTHER_ERROR;
-        break;
-      }
-    }
-    /*!< Exit loop in case of data ok */
-    if (rvalue == SD_DATA_OK)
-      break;
-    /*!< Increment loop counter */
-    i++;
-  }
-
-  /*!< Wait null data */
-  while (SD_ReadByte() == 0);
-
-  /*!< Return response */
-  return response;
-}
-
-
-SD_Error SD_Init(void)
-{
-  uint32_t i = 0;
-
-  /*!< Initialize SD_SPI */
-  SD_LowLevel_Init(); 
-
-  /*!< SD chip select high */
-  SD_CS_HIGH();
-
-  /*!< Send dummy byte 0xFF, 10 times with CS high */
-  /*!< Rise CS and MOSI for 80 clocks cycles */
-  for (i = 0; i <= 9; i++)
-  {
-    /*!< Send dummy byte 0xFF */
-    SD_WriteByte(SD_DUMMY_BYTE);
-  }
-  /*------------Put SD in SPI mode--------------*/
-  /*!< SD initialized and set to SPI mode properly */
-  return (SD_GoIdleState());
-}
-
-
-
-
-uint8_t _checkSDStatus() {
-if (SD_Status == SD_RESPONSE_NO_ERROR)
-return 0;
-
-do
-SD_Status = SD_Init();
-while (SD_Status != SD_RESPONSE_NO_ERROR);
-
-return 1;
-}
-
-void checkSDStatus() {
-while (_checkSDStatus()) { 
-//<----><------>writeBufFilled = 0;
-//<----><------>SDWriteOffset  = SD_WriteHeaders();
-}
-}
-
-
-SD_Error SD_WriteBlock_1(uint32_t WriteAddr)
-{
-  Wstatus = BuffReady;
-  BuffReady = 0;
-  uint32_t i = 0;
-  SD_Error rvalue = SD_RESPONSE_FAILURE;
-  SD_CS_LOW();
-  SD_SendCmd(SD_CMD_WRITE_SINGLE_BLOCK, WriteAddr, 0xFF);
-  if (!SD_GetResponse(SD_RESPONSE_NO_ERROR))
-  {
-    SD_WriteByte(SD_DUMMY_BYTE);
-    SD_WriteByte(0xFE);
-	if (Wstatus == 1){
-    for (i = 0; i < SD_BUFSIZE/2; i += 1)
-    {
-    SD_WriteByte(Buffer1[i]);
-    SD_WriteByte(Buffer1[i] >> 8);
-    }
-    }
-    
-    if (Wstatus == 2){
-    for (i = 0; i < SD_BUFSIZE/2; i += 1)
-    {
-    SD_WriteByte(Buffer2[i]);
-    SD_WriteByte(Buffer2[i] >> 8);
-    }
-    }
-    
-    SD_ReadByte();
-    SD_ReadByte();
-    if (SD_GetDataResponse() == SD_DATA_OK)
-    {
-      rvalue = SD_RESPONSE_NO_ERROR;
-    }
-  }
-  SD_CS_HIGH();
-  SD_WriteByte(SD_DUMMY_BYTE);
-    Wstatus = 0;
-  return rvalue;
-}
-
 
 int main(void) {
+        ADC_InitTypeDef     ADC_InitStructure;
+        GPIO_InitTypeDef    GPIO_InitStructure;
+        RCC_AHBPeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
+        RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 ;
+        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
+        GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz ;
+        GPIO_Init(GPIOA, &GPIO_InitStructure);
+        ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;                                                                         
+  ADC_InitStructure.ADC_ScanConvMode = ENABLE;                                                                               
+  ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;                                                                         
+  ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;                                                        
+  ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;                                                                     
+  ADC_InitStructure.ADC_NbrOfChannel = 0;                                                                                    
+  ADC_Init(ADC1, &ADC_InitStructure);     
+  ADC_Cmd(ADC1, ENABLE);                                                                                                     
+  ADC_ResetCalibration(ADC1);                                                                                                
+  while(ADC_GetResetCalibrationStatus(ADC1));                                                                                
+  ADC_StartCalibration(ADC1);                                                                                                
+  while(ADC_GetCalibrationStatus(ADC1));                                                                                     
+  ADC_SoftwareStartConvCmd(ADC1, ENABLE);                                                                                    
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1 | RCC_APB2Periph_GPIOA, ENABLE);                                                
 
-    status = SD_Init();
-    checkSDStatus();
-    writeBufFilled = 0;
-//    SD_WriteHeaders();
-    SDWriteOffset  = SD_BUFSIZE;
-    SystemCoreClockUpdate();
-    SysTick_Config(SystemCoreClock/10000);
     while (1)
 	{
-	if (BuffReady != 0){
-	check=1;
-//	SD_WriteBlock_1(SDWriteOffset);
-        SDWriteOffset  = SDWriteOffset + SD_BUFSIZE;
-
-
 
 	}
 
-    }
+
 }
 
 void SysTick_Handler(void) {

+ 31 - 0
stm32f1_04/Makefile

@@ -0,0 +1,31 @@
+CC      = arm-none-eabi-gcc
+LD      = arm-none-eabi-gcc -v
+CP      = arm-none-eabi-objcopy
+OD      = arm-none-eabi-objdump
+
+CFLAGS  =  -I./ -I./lib -I./inc -c -fno-common -O0 -g -mcpu=cortex-m3 -mthumb 
+LFLAGS  = -Tstm32_flash.ld -nostartfiles
+ODFLAGS = -S
+AR+= -rcs
+
+all: test
+
+clean: -rm build/main.lst build/startup_stm32f10x_ld.o build/main.o build/main.elf build/main.lst build/main.bin
+
+test: main.elf 
+	@ echo "...copying"
+	$(CP) -O binary build/main.elf build/main.bin
+	$(CP) -O ihex build/main.elf build/main.hex
+	$(OD) $(ODFLAGS) build/main.elf > build/main.lst
+
+main.elf: main.o startup.o stm32_flash.ld
+	@ echo "..linking"
+	$(LD) $(LFLAGS) -o build/main.elf build/main.o build/startup_stm32f10x_ld.o
+
+main.o: main.c
+	@ echo ".compiling"
+	$(CC) $(CFLAGS) main.c -o build/main.o
+
+startup.o: source/startup_stm32f10x_ld.s
+	@ echo ".compiling"
+	$(CC) $(CFLAGS) source/startup_stm32f10x_ld.s -o build/startup_stm32f10x_ld.o

+ 5 - 0
stm32f1_04/build/gdb.scr

@@ -0,0 +1,5 @@
+tar ext :4242
+load
+continue
+print ADC1ConvertedValue
+

BIN
stm32f1_04/build/main.bin


BIN
stm32f1_04/build/main.elf


+ 234 - 0
stm32f1_04/build/main.hex

@@ -0,0 +1,234 @@
+:020000040800F2
+:1000000000280020050E0008490E0008490E0008CF
+:10001000490E0008490E0008490E000800000000C3
+:10002000000000000000000000000000490E000871
+:10003000490E000800000000490E0008D10D00081C
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File diff suppressed because it is too large
+ 2793 - 0
stm32f1_04/build/main.lst


BIN
stm32f1_04/build/main.o


BIN
stm32f1_04/build/startup_stm32f10x_ld.o


+ 4 - 0
stm32f1_04/gdb.txt

@@ -0,0 +1,4 @@
+tar ext :4242
+load
+continue
+print SCNT

File diff suppressed because it is too large
+ 1818 - 0
stm32f1_04/inc/core_cm3.h


+ 220 - 0
stm32f1_04/inc/misc.h

@@ -0,0 +1,220 @@
+/**
+  ******************************************************************************
+  * @file    misc.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the miscellaneous
+  *          firmware library functions (add-on to CMSIS functions).
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MISC_H
+#define __MISC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup MISC
+  * @{
+  */
+
+/** @defgroup MISC_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  NVIC Init Structure definition  
+  */
+
+typedef struct
+{
+  uint8_t NVIC_IRQChannel;                    /*!< Specifies the IRQ channel to be enabled or disabled.
+                                                   This parameter can be a value of @ref IRQn_Type 
+                                                   (For the complete STM32 Devices IRQ Channels list, please
+                                                    refer to stm32f10x.h file) */
+
+  uint8_t NVIC_IRQChannelPreemptionPriority;  /*!< Specifies the pre-emption priority for the IRQ channel
+                                                   specified in NVIC_IRQChannel. This parameter can be a value
+                                                   between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+  uint8_t NVIC_IRQChannelSubPriority;         /*!< Specifies the subpriority level for the IRQ channel specified
+                                                   in NVIC_IRQChannel. This parameter can be a value
+                                                   between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+  FunctionalState NVIC_IRQChannelCmd;         /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+                                                   will be enabled or disabled. 
+                                                   This parameter can be set either to ENABLE or DISABLE */   
+} NVIC_InitTypeDef;
+ 
+/**
+  * @}
+  */
+
+/** @defgroup NVIC_Priority_Table 
+  * @{
+  */
+
+/**
+@code  
+ The table below gives the allowed values of the pre-emption priority and subpriority according
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+  ============================================================================================================================
+    NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  | Description
+  ============================================================================================================================
+   NVIC_PriorityGroup_0  |                0                  |            0-15             |   0 bits for pre-emption priority
+                         |                                   |                             |   4 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------
+   NVIC_PriorityGroup_1  |                0-1                |            0-7              |   1 bits for pre-emption priority
+                         |                                   |                             |   3 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------    
+   NVIC_PriorityGroup_2  |                0-3                |            0-3              |   2 bits for pre-emption priority
+                         |                                   |                             |   2 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------    
+   NVIC_PriorityGroup_3  |                0-7                |            0-1              |   3 bits for pre-emption priority
+                         |                                   |                             |   1 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------    
+   NVIC_PriorityGroup_4  |                0-15               |            0                |   4 bits for pre-emption priority
+                         |                                   |                             |   0 bits for subpriority                       
+  ============================================================================================================================
+@endcode
+*/
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup Vector_Table_Base 
+  * @{
+  */
+
+#define NVIC_VectTab_RAM             ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH           ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
+                                  ((VECTTAB) == NVIC_VectTab_FLASH))
+/**
+  * @}
+  */
+
+/** @defgroup System_Low_Power 
+  * @{
+  */
+
+#define NVIC_LP_SEVONPEND            ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP            ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT          ((uint8_t)0x02)
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
+                        ((LP) == NVIC_LP_SLEEPDEEP) || \
+                        ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+  * @}
+  */
+
+/** @defgroup Preemption_Priority_Group 
+  * @{
+  */
+
+#define NVIC_PriorityGroup_0         ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
+                                                            4 bits for subpriority */
+#define NVIC_PriorityGroup_1         ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
+                                                            3 bits for subpriority */
+#define NVIC_PriorityGroup_2         ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
+                                                            2 bits for subpriority */
+#define NVIC_PriorityGroup_3         ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
+                                                            1 bits for subpriority */
+#define NVIC_PriorityGroup_4         ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
+                                                            0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
+                                       ((GROUP) == NVIC_PriorityGroup_1) || \
+                                       ((GROUP) == NVIC_PriorityGroup_2) || \
+                                       ((GROUP) == NVIC_PriorityGroup_3) || \
+                                       ((GROUP) == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET(OFFSET)  ((OFFSET) < 0x000FFFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup SysTick_clock_source 
+  * @{
+  */
+
+#define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
+                                       ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Exported_Functions
+  * @{
+  */
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MISC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

+ 368 - 0
stm32f1_04/inc/stm32_eval.h

@@ -0,0 +1,368 @@
+/**
+  ******************************************************************************
+  * @file    stm32_eval.h
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   Header file for stm32_eval.c module.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+  
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_EVAL_H
+#define __STM32_EVAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Includes ------------------------------------------------------------------*/
+
+/** @addtogroup Utilities
+  * @{
+  */ 
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @defgroup STM32_EVAL_Abstraction_Layer
+  * @{
+  */
+  
+/** @defgroup STM32_EVAL_HARDWARE_RESOURCES
+  * @{
+  */
+
+/**
+@code  
+ The table below gives an overview of the hardware resources supported by each 
+ STM32 EVAL board.
+     - LCD: TFT Color LCD (Parallel (FSMC) and Serial (SPI))
+     - IOE: IO Expander on I2C
+     - sFLASH: serial SPI FLASH (M25Pxxx)
+     - sEE: serial I2C EEPROM (M24C08, M24C32, M24C64)
+     - TSENSOR: Temperature Sensor (LM75)
+     - SD: SD Card memory (SPI and SDIO (SD Card MODE)) 
+  =================================================================================================================+
+    STM32 EVAL     | LED | Buttons  | Com Ports |    LCD    | IOE  | sFLASH | sEE | TSENSOR | SD (SPI) | SD(SDIO)  |
+  =================================================================================================================+
+   STM3210B-EVAL   |  4  |    8     |     2     | YES (SPI) | NO   |  YES   | NO  |   YES   |    YES   |    NO     |
+  -----------------------------------------------------------------------------------------------------------------+
+   STM3210E-EVAL   |  4  |    8     |     2     | YES (FSMC)| NO   |  YES   | NO  |   YES   |    NO    |    YES    |
+  -----------------------------------------------------------------------------------------------------------------+
+   STM3210C-EVAL   |  4  |    3     |     1     | YES (SPI) | YES  |  NO    | YES |   NO    |    YES   |    NO     |
+  -----------------------------------------------------------------------------------------------------------------+
+   STM32100B-EVAL  |  4  |    8     |     2     | YES (SPI) | NO   |  YES   | NO  |   YES   |    YES   |    NO     |
+  -----------------------------------------------------------------------------------------------------------------+
+   STM32L152-EVAL  |  4  |    8     |     2     | YES (SPI) | NO   |  NO    | NO  |   YES   |    YES   |    NO     |
+  -----------------------------------------------------------------------------------------------------------------+
+   STM32100E-EVAL  |  4  |    8     |     2     | YES (FSMC)| YES  |  YES   | YES |   YES   |    YES   |    NO     |
+  =================================================================================================================+
+@endcode
+*/
+
+/**
+  * @}
+  */
+  
+/** @defgroup STM32_EVAL_Exported_Types
+  * @{
+  */
+typedef enum 
+{
+  LED1 = 0,
+  LED2 = 1,
+  LED3 = 2,
+  LED4 = 3
+} Led_TypeDef;
+
+typedef enum 
+{  
+  BUTTON_WAKEUP = 0,
+  BUTTON_TAMPER = 1,
+  BUTTON_KEY = 2,
+  BUTTON_RIGHT = 3,
+  BUTTON_LEFT = 4,
+  BUTTON_UP = 5,
+  BUTTON_DOWN = 6,
+  BUTTON_SEL = 7
+} Button_TypeDef;
+
+typedef enum 
+{  
+  BUTTON_MODE_GPIO = 0,
+  BUTTON_MODE_EXTI = 1
+} ButtonMode_TypeDef;
+
+typedef enum 
+{ 
+  JOY_NONE = 0,
+  JOY_SEL = 1,
+  JOY_DOWN = 2,
+  JOY_LEFT = 3,
+  JOY_RIGHT = 4,
+  JOY_UP = 5
+} JOYState_TypeDef
+;
+
+typedef enum 
+{
+  COM1 = 0,
+  COM2 = 1
+} COM_TypeDef;   
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM32_EVAL_Exported_Constants
+  * @{
+  */
+
+/** 
+  * @brief  Uncomment the line corresponding to the STMicroelectronics evaluation
+  *   board used in your application.
+  *   
+  *  Tip: To avoid modifying this file each time you need to switch between these
+  *       boards, you can define the board in your toolchain compiler preprocessor.    
+  */ 
+#if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL)\
+   &&  !defined (USE_STM3210C_EVAL) &&  !defined (USE_STM32L152_EVAL) &&  !defined (USE_STM32100E_EVAL)
+ //#define USE_STM32100B_EVAL
+ //#define USE_STM3210B_EVAL
+ //#define USE_STM3210E_EVAL
+ //#define USE_STM3210C_EVAL
+ //#define USE_STM32L152_EVAL
+ //#define USE_STM32100E_EVAL
+#endif
+
+#ifdef USE_STM32100B_EVAL
+ #include "stm32f10x.h"
+ #include "stm32100b_eval/stm32100b_eval.h"
+#elif defined USE_STM3210B_EVAL
+ #include "stm32f10x.h"
+ #include "stm3210b_eval/stm3210b_eval.h" 
+#elif defined USE_STM3210E_EVAL
+ #include "stm32f10x.h"
+ #include "stm3210e_eval/stm3210e_eval.h"
+#elif defined USE_STM3210C_EVAL
+ #include "stm32f10x.h"
+ #include "stm3210c_eval/stm3210c_eval.h"
+#elif defined USE_STM32L152_EVAL
+ #include "stm32l1xx.h"
+ #include "stm32l152_eval/stm32l152_eval.h" 
+#elif defined USE_STM32100E_EVAL
+ #include "stm32f10x.h"
+ #include "stm32100e_eval/stm32100e_eval.h"
+#else 
+ #error "Please select first the STM32 EVAL board to be used (in stm32_eval.h)"
+#endif                      
+
+
+/** 
+  * @brief  STM32 Button Defines Legacy  
+  */ 
+#define Button_WAKEUP        BUTTON_WAKEUP
+#define Button_TAMPER        BUTTON_TAMPER
+#define Button_KEY           BUTTON_KEY
+#define Button_RIGHT         BUTTON_RIGHT
+#define Button_LEFT          BUTTON_LEFT
+#define Button_UP            BUTTON_UP
+#define Button_DOWN          BUTTON_DOWN
+#define Button_SEL           BUTTON_SEL
+#define Mode_GPIO            BUTTON_MODE_GPIO
+#define Mode_EXTI            BUTTON_MODE_EXTI
+#define Button_Mode_TypeDef  ButtonMode_TypeDef
+#define JOY_CENTER           JOY_SEL
+#define JOY_State_TypeDef    JOYState_TypeDef 
+
+/** 
+  * @brief  LCD Defines Legacy  
+  */ 
+#define LCD_RSNWR_GPIO_CLK  LCD_NWR_GPIO_CLK
+#define LCD_SPI_GPIO_PORT   LCD_SPI_SCK_GPIO_PORT
+#define LCD_SPI_GPIO_CLK    LCD_SPI_SCK_GPIO_CLK
+#define R0                  LCD_REG_0
+#define R1                  LCD_REG_1
+#define R2                  LCD_REG_2
+#define R3                  LCD_REG_3
+#define R4                  LCD_REG_4
+#define R5                  LCD_REG_5
+#define R6                  LCD_REG_6
+#define R7                  LCD_REG_7
+#define R8                  LCD_REG_8
+#define R9                  LCD_REG_9
+#define R10                 LCD_REG_10
+#define R12                 LCD_REG_12
+#define R13                 LCD_REG_13
+#define R14                 LCD_REG_14
+#define R15                 LCD_REG_15
+#define R16                 LCD_REG_16
+#define R17                 LCD_REG_17
+#define R18                 LCD_REG_18
+#define R19                 LCD_REG_19
+#define R20                 LCD_REG_20
+#define R21                 LCD_REG_21
+#define R22                 LCD_REG_22
+#define R23                 LCD_REG_23
+#define R24                 LCD_REG_24
+#define R25                 LCD_REG_25
+#define R26                 LCD_REG_26
+#define R27                 LCD_REG_27
+#define R28                 LCD_REG_28
+#define R29                 LCD_REG_29
+#define R30                 LCD_REG_30
+#define R31                 LCD_REG_31
+#define R32                 LCD_REG_32
+#define R33                 LCD_REG_33
+#define R34                 LCD_REG_34
+#define R36                 LCD_REG_36
+#define R37                 LCD_REG_37
+#define R40                 LCD_REG_40
+#define R41                 LCD_REG_41
+#define R43                 LCD_REG_43
+#define R45                 LCD_REG_45
+#define R48                 LCD_REG_48
+#define R49                 LCD_REG_49
+#define R50                 LCD_REG_50
+#define R51                 LCD_REG_51
+#define R52                 LCD_REG_52
+#define R53                 LCD_REG_53
+#define R54                 LCD_REG_54
+#define R55                 LCD_REG_55
+#define R56                 LCD_REG_56
+#define R57                 LCD_REG_57
+#define R59                 LCD_REG_59
+#define R60                 LCD_REG_60
+#define R61                 LCD_REG_61
+#define R62                 LCD_REG_62
+#define R63                 LCD_REG_63
+#define R64                 LCD_REG_64
+#define R65                 LCD_REG_65
+#define R66                 LCD_REG_66
+#define R67                 LCD_REG_67
+#define R68                 LCD_REG_68
+#define R69                 LCD_REG_69
+#define R70                 LCD_REG_70
+#define R71                 LCD_REG_71
+#define R72                 LCD_REG_72
+#define R73                 LCD_REG_73
+#define R74                 LCD_REG_74
+#define R75                 LCD_REG_75
+#define R76                 LCD_REG_76
+#define R77                 LCD_REG_77
+#define R78                 LCD_REG_78
+#define R79                 LCD_REG_79
+#define R80                 LCD_REG_80
+#define R81                 LCD_REG_81
+#define R82                 LCD_REG_82
+#define R83                 LCD_REG_83
+#define R96                 LCD_REG_96
+#define R97                 LCD_REG_97
+#define R106                LCD_REG_106
+#define R118                LCD_REG_118
+#define R128                LCD_REG_128
+#define R129                LCD_REG_129
+#define R130                LCD_REG_130
+#define R131                LCD_REG_131
+#define R132                LCD_REG_132
+#define R133                LCD_REG_133
+#define R134                LCD_REG_134
+#define R135                LCD_REG_135
+#define R136                LCD_REG_136
+#define R137                LCD_REG_137
+#define R139                LCD_REG_139
+#define R140                LCD_REG_140
+#define R141                LCD_REG_141
+#define R143                LCD_REG_143
+#define R144                LCD_REG_144
+#define R145                LCD_REG_145
+#define R146                LCD_REG_146
+#define R147                LCD_REG_147
+#define R148                LCD_REG_148
+#define R149                LCD_REG_149
+#define R150                LCD_REG_150
+#define R151                LCD_REG_151
+#define R152                LCD_REG_152
+#define R153                LCD_REG_153
+#define R154                LCD_REG_154
+#define R157                LCD_REG_157
+#define R192                LCD_REG_192
+#define R193                LCD_REG_193
+#define R227                LCD_REG_227
+#define R229                LCD_REG_229
+#define R231                LCD_REG_231
+#define R239                LCD_REG_239
+#define White               LCD_COLOR_WHITE
+#define Black               LCD_COLOR_BLACK
+#define Grey                LCD_COLOR_GREY
+#define Blue                LCD_COLOR_BLUE
+#define Blue2               LCD_COLOR_BLUE2
+#define Red                 LCD_COLOR_RED
+#define Magenta             LCD_COLOR_MAGENTA
+#define Green               LCD_COLOR_GREEN
+#define Cyan                LCD_COLOR_CYAN
+#define Yellow              LCD_COLOR_YELLOW
+#define Line0               LCD_LINE_0
+#define Line1               LCD_LINE_1
+#define Line2               LCD_LINE_2
+#define Line3               LCD_LINE_3
+#define Line4               LCD_LINE_4
+#define Line5               LCD_LINE_5
+#define Line6               LCD_LINE_6
+#define Line7               LCD_LINE_7
+#define Line8               LCD_LINE_8
+#define Line9               LCD_LINE_9
+#define Horizontal          LCD_DIR_HORIZONTAL
+#define Vertical            LCD_DIR_VERTICAL
+
+
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32_EVAL_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32_EVAL_Exported_Functions
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32_EVAL_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */   
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

File diff suppressed because it is too large
+ 8336 - 0
stm32f1_04/inc/stm32f10x.h


+ 483 - 0
stm32f1_04/inc/stm32f10x_adc.h

@@ -0,0 +1,483 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_adc.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the ADC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_ADC_H
+#define __STM32F10x_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup ADC
+  * @{
+  */
+
+/** @defgroup ADC_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  ADC Init structure definition  
+  */
+
+typedef struct
+{
+  uint32_t ADC_Mode;                      /*!< Configures the ADC to operate in independent or
+                                               dual mode. 
+                                               This parameter can be a value of @ref ADC_mode */
+
+  FunctionalState ADC_ScanConvMode;       /*!< Specifies whether the conversion is performed in
+                                               Scan (multichannels) or Single (one channel) mode.
+                                               This parameter can be set to ENABLE or DISABLE */
+
+  FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
+                                               Continuous or Single mode.
+                                               This parameter can be set to ENABLE or DISABLE. */
+
+  uint32_t ADC_ExternalTrigConv;          /*!< Defines the external trigger used to start the analog
+                                               to digital conversion of regular channels. This parameter
+                                               can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
+
+  uint32_t ADC_DataAlign;                 /*!< Specifies whether the ADC data alignment is left or right.
+                                               This parameter can be a value of @ref ADC_data_align */
+
+  uint8_t ADC_NbrOfChannel;               /*!< Specifies the number of ADC channels that will be converted
+                                               using the sequencer for regular channel group.
+                                               This parameter must range from 1 to 16. */
+}ADC_InitTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Constants
+  * @{
+  */
+
+#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
+                                   ((PERIPH) == ADC2) || \
+                                   ((PERIPH) == ADC3))
+
+#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
+                                   ((PERIPH) == ADC3))
+
+/** @defgroup ADC_mode 
+  * @{
+  */
+
+#define ADC_Mode_Independent                       ((uint32_t)0x00000000)
+#define ADC_Mode_RegInjecSimult                    ((uint32_t)0x00010000)
+#define ADC_Mode_RegSimult_AlterTrig               ((uint32_t)0x00020000)
+#define ADC_Mode_InjecSimult_FastInterl            ((uint32_t)0x00030000)
+#define ADC_Mode_InjecSimult_SlowInterl            ((uint32_t)0x00040000)
+#define ADC_Mode_InjecSimult                       ((uint32_t)0x00050000)
+#define ADC_Mode_RegSimult                         ((uint32_t)0x00060000)
+#define ADC_Mode_FastInterl                        ((uint32_t)0x00070000)
+#define ADC_Mode_SlowInterl                        ((uint32_t)0x00080000)
+#define ADC_Mode_AlterTrig                         ((uint32_t)0x00090000)
+
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
+                           ((MODE) == ADC_Mode_RegInjecSimult) || \
+                           ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \
+                           ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \
+                           ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \
+                           ((MODE) == ADC_Mode_InjecSimult) || \
+                           ((MODE) == ADC_Mode_RegSimult) || \
+                           ((MODE) == ADC_Mode_FastInterl) || \
+                           ((MODE) == ADC_Mode_SlowInterl) || \
+                           ((MODE) == ADC_Mode_AlterTrig))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion 
+  * @{
+  */
+
+#define ADC_ExternalTrigConv_T1_CC1                ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T1_CC2                ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T2_CC2                ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T3_TRGO               ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T4_CC4                ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO    ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */
+
+#define ADC_ExternalTrigConv_T1_CC3                ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigConv_None                  ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */
+
+#define ADC_ExternalTrigConv_T3_CC1                ((uint32_t)0x00000000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T2_CC3                ((uint32_t)0x00020000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T8_CC1                ((uint32_t)0x00060000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T8_TRGO               ((uint32_t)0x00080000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T5_CC1                ((uint32_t)0x000A0000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T5_CC3                ((uint32_t)0x000C0000) /*!< For ADC3 only */
+
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_None) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_data_align 
+  * @{
+  */
+
+#define ADC_DataAlign_Right                        ((uint32_t)0x00000000)
+#define ADC_DataAlign_Left                         ((uint32_t)0x00000800)
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
+                                  ((ALIGN) == ADC_DataAlign_Left))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_channels 
+  * @{
+  */
+
+#define ADC_Channel_0                               ((uint8_t)0x00)
+#define ADC_Channel_1                               ((uint8_t)0x01)
+#define ADC_Channel_2                               ((uint8_t)0x02)
+#define ADC_Channel_3                               ((uint8_t)0x03)
+#define ADC_Channel_4                               ((uint8_t)0x04)
+#define ADC_Channel_5                               ((uint8_t)0x05)
+#define ADC_Channel_6                               ((uint8_t)0x06)
+#define ADC_Channel_7                               ((uint8_t)0x07)
+#define ADC_Channel_8                               ((uint8_t)0x08)
+#define ADC_Channel_9                               ((uint8_t)0x09)
+#define ADC_Channel_10                              ((uint8_t)0x0A)
+#define ADC_Channel_11                              ((uint8_t)0x0B)
+#define ADC_Channel_12                              ((uint8_t)0x0C)
+#define ADC_Channel_13                              ((uint8_t)0x0D)
+#define ADC_Channel_14                              ((uint8_t)0x0E)
+#define ADC_Channel_15                              ((uint8_t)0x0F)
+#define ADC_Channel_16                              ((uint8_t)0x10)
+#define ADC_Channel_17                              ((uint8_t)0x11)
+
+#define ADC_Channel_TempSensor                      ((uint8_t)ADC_Channel_16)
+#define ADC_Channel_Vrefint                         ((uint8_t)ADC_Channel_17)
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
+                                 ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
+                                 ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
+                                 ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
+                                 ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
+                                 ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
+                                 ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
+                                 ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
+                                 ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_sampling_time 
+  * @{
+  */
+
+#define ADC_SampleTime_1Cycles5                    ((uint8_t)0x00)
+#define ADC_SampleTime_7Cycles5                    ((uint8_t)0x01)
+#define ADC_SampleTime_13Cycles5                   ((uint8_t)0x02)
+#define ADC_SampleTime_28Cycles5                   ((uint8_t)0x03)
+#define ADC_SampleTime_41Cycles5                   ((uint8_t)0x04)
+#define ADC_SampleTime_55Cycles5                   ((uint8_t)0x05)
+#define ADC_SampleTime_71Cycles5                   ((uint8_t)0x06)
+#define ADC_SampleTime_239Cycles5                  ((uint8_t)0x07)
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_7Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_13Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_28Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_41Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_55Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_71Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_239Cycles5))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion 
+  * @{
+  */
+
+#define ADC_ExternalTrigInjecConv_T2_TRGO           ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_T2_CC1            ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_T3_CC4            ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_T4_TRGO           ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */
+
+#define ADC_ExternalTrigInjecConv_T1_TRGO           ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjecConv_T1_CC4            ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjecConv_None              ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */
+
+#define ADC_ExternalTrigInjecConv_T4_CC3            ((uint32_t)0x00002000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T8_CC2            ((uint32_t)0x00003000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T8_CC4            ((uint32_t)0x00004000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T5_TRGO           ((uint32_t)0x00005000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T5_CC4            ((uint32_t)0x00006000) /*!< For ADC3 only */
+
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_channel_selection 
+  * @{
+  */
+
+#define ADC_InjectedChannel_1                       ((uint8_t)0x14)
+#define ADC_InjectedChannel_2                       ((uint8_t)0x18)
+#define ADC_InjectedChannel_3                       ((uint8_t)0x1C)
+#define ADC_InjectedChannel_4                       ((uint8_t)0x20)
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_2) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_3) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_4))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_analog_watchdog_selection 
+  * @{
+  */
+
+#define ADC_AnalogWatchdog_SingleRegEnable         ((uint32_t)0x00800200)
+#define ADC_AnalogWatchdog_SingleInjecEnable       ((uint32_t)0x00400200)
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable  ((uint32_t)0x00C00200)
+#define ADC_AnalogWatchdog_AllRegEnable            ((uint32_t)0x00800000)
+#define ADC_AnalogWatchdog_AllInjecEnable          ((uint32_t)0x00400000)
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable    ((uint32_t)0x00C00000)
+#define ADC_AnalogWatchdog_None                    ((uint32_t)0x00000000)
+
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_None))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_interrupts_definition 
+  * @{
+  */
+
+#define ADC_IT_EOC                                 ((uint16_t)0x0220)
+#define ADC_IT_AWD                                 ((uint16_t)0x0140)
+#define ADC_IT_JEOC                                ((uint16_t)0x0480)
+
+#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))
+
+#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
+                           ((IT) == ADC_IT_JEOC))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_flags_definition 
+  * @{
+  */
+
+#define ADC_FLAG_AWD                               ((uint8_t)0x01)
+#define ADC_FLAG_EOC                               ((uint8_t)0x02)
+#define ADC_FLAG_JEOC                              ((uint8_t)0x04)
+#define ADC_FLAG_JSTRT                             ((uint8_t)0x08)
+#define ADC_FLAG_STRT                              ((uint8_t)0x10)
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
+                               ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
+                               ((FLAG) == ADC_FLAG_STRT))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_thresholds 
+  * @{
+  */
+
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_offset 
+  * @{
+  */
+
+#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_length 
+  * @{
+  */
+
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_rank 
+  * @{
+  */
+
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_regular_length 
+  * @{
+  */
+
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_rank 
+  * @{
+  */
+
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_discontinuous_mode_number 
+  * @{
+  */
+
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions
+  * @{
+  */
+
+void ADC_DeInit(ADC_TypeDef* ADCx);
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
+void ADC_ResetCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_StartCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
+uint32_t ADC_GetDualModeConversionValue(void);
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_ADC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

+ 195 - 0
stm32f1_04/inc/stm32f10x_bkp.h

@@ -0,0 +1,195 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_bkp.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the BKP firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_BKP_H
+#define __STM32F10x_BKP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup BKP
+  * @{
+  */
+
+/** @defgroup BKP_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Exported_Constants
+  * @{
+  */
+
+/** @defgroup Tamper_Pin_active_level 
+  * @{
+  */
+
+#define BKP_TamperPinLevel_High           ((uint16_t)0x0000)
+#define BKP_TamperPinLevel_Low            ((uint16_t)0x0001)
+#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \
+                                        ((LEVEL) == BKP_TamperPinLevel_Low))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin 
+  * @{
+  */
+
+#define BKP_RTCOutputSource_None          ((uint16_t)0x0000)
+#define BKP_RTCOutputSource_CalibClock    ((uint16_t)0x0080)
+#define BKP_RTCOutputSource_Alarm         ((uint16_t)0x0100)
+#define BKP_RTCOutputSource_Second        ((uint16_t)0x0300)
+#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \
+                                          ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \
+                                          ((SOURCE) == BKP_RTCOutputSource_Alarm) || \
+                                          ((SOURCE) == BKP_RTCOutputSource_Second))
+/**
+  * @}
+  */
+
+/** @defgroup Data_Backup_Register 
+  * @{
+  */
+
+#define BKP_DR1                           ((uint16_t)0x0004)
+#define BKP_DR2                           ((uint16_t)0x0008)
+#define BKP_DR3                           ((uint16_t)0x000C)
+#define BKP_DR4                           ((uint16_t)0x0010)
+#define BKP_DR5                           ((uint16_t)0x0014)
+#define BKP_DR6                           ((uint16_t)0x0018)
+#define BKP_DR7                           ((uint16_t)0x001C)
+#define BKP_DR8                           ((uint16_t)0x0020)
+#define BKP_DR9                           ((uint16_t)0x0024)
+#define BKP_DR10                          ((uint16_t)0x0028)