build/main.elf: file format elf32-littlearm Disassembly of section .text: 0800010c : * interrupt, or negative to specify an internal (core) interrupt. * * Note: The priority cannot be set for every core interrupt. */ static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 800010c: b480 push {r7} 800010e: b083 sub sp, #12 8000110: af00 add r7, sp, #0 8000112: 4603 mov r3, r0 8000114: 6039 str r1, [r7, #0] 8000116: 71fb strb r3, [r7, #7] if(IRQn < 0) { 8000118: f997 3007 ldrsb.w r3, [r7, #7] 800011c: 2b00 cmp r3, #0 800011e: da0b bge.n 8000138 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ 8000120: 490d ldr r1, [pc, #52] ; (8000158 ) 8000122: 79fb ldrb r3, [r7, #7] 8000124: f003 030f and.w r3, r3, #15 8000128: 3b04 subs r3, #4 800012a: 683a ldr r2, [r7, #0] 800012c: b2d2 uxtb r2, r2 800012e: 0112 lsls r2, r2, #4 8000130: b2d2 uxtb r2, r2 8000132: 440b add r3, r1 8000134: 761a strb r2, [r3, #24] else { NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ } 8000136: e009 b.n 800014c static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if(IRQn < 0) { SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ else { NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ 8000138: 4908 ldr r1, [pc, #32] ; (800015c ) 800013a: f997 3007 ldrsb.w r3, [r7, #7] 800013e: 683a ldr r2, [r7, #0] 8000140: b2d2 uxtb r2, r2 8000142: 0112 lsls r2, r2, #4 8000144: b2d2 uxtb r2, r2 8000146: 440b add r3, r1 8000148: f883 2300 strb.w r2, [r3, #768] ; 0x300 } 800014c: bf00 nop 800014e: 370c adds r7, #12 8000150: 46bd mov sp, r7 8000152: bc80 pop {r7} 8000154: 4770 bx lr 8000156: bf00 nop 8000158: e000ed00 .word 0xe000ed00 800015c: e000e100 .word 0xe000e100 08000160 : * Initialise the system tick timer and its interrupt and start the * system tick timer / counter in free running mode to generate * periodical interrupts. */ static __INLINE uint32_t SysTick_Config(uint32_t ticks) { 8000160: b580 push {r7, lr} 8000162: b082 sub sp, #8 8000164: af00 add r7, sp, #0 8000166: 6078 str r0, [r7, #4] if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ 8000168: 687b ldr r3, [r7, #4] 800016a: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 800016e: d301 bcc.n 8000174 8000170: 2301 movs r3, #1 8000172: e011 b.n 8000198 SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ 8000174: 4a0a ldr r2, [pc, #40] ; (80001a0 ) 8000176: 687b ldr r3, [r7, #4] 8000178: f023 437f bic.w r3, r3, #4278190080 ; 0xff000000 800017c: 3b01 subs r3, #1 800017e: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ 8000180: 210f movs r1, #15 8000182: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8000186: f7ff ffc1 bl 800010c SysTick->VAL = 0; /* Load the SysTick Counter Value */ 800018a: 4b05 ldr r3, [pc, #20] ; (80001a0 ) 800018c: 2200 movs r2, #0 800018e: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8000190: 4b03 ldr r3, [pc, #12] ; (80001a0 ) 8000192: 2207 movs r2, #7 8000194: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0); /* Function successful */ 8000196: 2300 movs r3, #0 } 8000198: 4618 mov r0, r3 800019a: 3708 adds r7, #8 800019c: 46bd mov sp, r7 800019e: bd80 pop {r7, pc} 80001a0: e000e010 .word 0xe000e010 080001a4 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 80001a4: b580 push {r7, lr} 80001a6: af00 add r7, sp, #0 /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ /* Set HSION bit */ RCC->CR |= (uint32_t)0x00000001; 80001a8: 4a15 ldr r2, [pc, #84] ; (8000200 ) 80001aa: 4b15 ldr r3, [pc, #84] ; (8000200 ) 80001ac: 681b ldr r3, [r3, #0] 80001ae: f043 0301 orr.w r3, r3, #1 80001b2: 6013 str r3, [r2, #0] /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ #ifndef STM32F10X_CL RCC->CFGR &= (uint32_t)0xF8FF0000; 80001b4: 4912 ldr r1, [pc, #72] ; (8000200 ) 80001b6: 4b12 ldr r3, [pc, #72] ; (8000200 ) 80001b8: 685a ldr r2, [r3, #4] 80001ba: 4b12 ldr r3, [pc, #72] ; (8000204 ) 80001bc: 4013 ands r3, r2 80001be: 604b str r3, [r1, #4] #else RCC->CFGR &= (uint32_t)0xF0FF0000; #endif /* STM32F10X_CL */ /* Reset HSEON, CSSON and PLLON bits */ RCC->CR &= (uint32_t)0xFEF6FFFF; 80001c0: 4a0f ldr r2, [pc, #60] ; (8000200 ) 80001c2: 4b0f ldr r3, [pc, #60] ; (8000200 ) 80001c4: 681b ldr r3, [r3, #0] 80001c6: f023 7384 bic.w r3, r3, #17301504 ; 0x1080000 80001ca: f423 3380 bic.w r3, r3, #65536 ; 0x10000 80001ce: 6013 str r3, [r2, #0] /* Reset HSEBYP bit */ RCC->CR &= (uint32_t)0xFFFBFFFF; 80001d0: 4a0b ldr r2, [pc, #44] ; (8000200 ) 80001d2: 4b0b ldr r3, [pc, #44] ; (8000200 ) 80001d4: 681b ldr r3, [r3, #0] 80001d6: f423 2380 bic.w r3, r3, #262144 ; 0x40000 80001da: 6013 str r3, [r2, #0] /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ RCC->CFGR &= (uint32_t)0xFF80FFFF; 80001dc: 4a08 ldr r2, [pc, #32] ; (8000200 ) 80001de: 4b08 ldr r3, [pc, #32] ; (8000200 ) 80001e0: 685b ldr r3, [r3, #4] 80001e2: f423 03fe bic.w r3, r3, #8323072 ; 0x7f0000 80001e6: 6053 str r3, [r2, #4] /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000; #else /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x009F0000; 80001e8: 4b05 ldr r3, [pc, #20] ; (8000200 ) 80001ea: f44f 021f mov.w r2, #10420224 ; 0x9f0000 80001ee: 609a str r2, [r3, #8] #endif /* DATA_IN_ExtSRAM */ #endif /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ /* Configure the Flash Latency cycles and enable prefetch buffer */ SetSysClock(); 80001f0: f000 f878 bl 80002e4 #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ 80001f4: 4b04 ldr r3, [pc, #16] ; (8000208 ) 80001f6: f04f 6200 mov.w r2, #134217728 ; 0x8000000 80001fa: 609a str r2, [r3, #8] #endif } 80001fc: bf00 nop 80001fe: bd80 pop {r7, pc} 8000200: 40021000 .word 0x40021000 8000204: f8ff0000 .word 0xf8ff0000 8000208: e000ed00 .word 0xe000ed00 0800020c : * value for HSE crystal. * @param None * @retval None */ void SystemCoreClockUpdate (void) { 800020c: b480 push {r7} 800020e: b085 sub sp, #20 8000210: af00 add r7, sp, #0 uint32_t tmp = 0, pllmull = 0, pllsource = 0; 8000212: 2300 movs r3, #0 8000214: 60fb str r3, [r7, #12] 8000216: 2300 movs r3, #0 8000218: 60bb str r3, [r7, #8] 800021a: 2300 movs r3, #0 800021c: 607b str r3, [r7, #4] #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) uint32_t prediv1factor = 0; #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; 800021e: 4b2c ldr r3, [pc, #176] ; (80002d0 ) 8000220: 685b ldr r3, [r3, #4] 8000222: f003 030c and.w r3, r3, #12 8000226: 60fb str r3, [r7, #12] switch (tmp) 8000228: 68fb ldr r3, [r7, #12] 800022a: 2b04 cmp r3, #4 800022c: d007 beq.n 800023e 800022e: 2b08 cmp r3, #8 8000230: d009 beq.n 8000246 8000232: 2b00 cmp r3, #0 8000234: d133 bne.n 800029e { case 0x00: /* HSI used as system clock */ SystemCoreClock = HSI_VALUE; 8000236: 4b27 ldr r3, [pc, #156] ; (80002d4 ) 8000238: 4a27 ldr r2, [pc, #156] ; (80002d8 ) 800023a: 601a str r2, [r3, #0] break; 800023c: e033 b.n 80002a6 case 0x04: /* HSE used as system clock */ SystemCoreClock = HSE_VALUE; 800023e: 4b25 ldr r3, [pc, #148] ; (80002d4 ) 8000240: 4a25 ldr r2, [pc, #148] ; (80002d8 ) 8000242: 601a str r2, [r3, #0] break; 8000244: e02f b.n 80002a6 case 0x08: /* PLL used as system clock */ /* Get PLL clock source and multiplication factor ----------------------*/ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; 8000246: 4b22 ldr r3, [pc, #136] ; (80002d0 ) 8000248: 685b ldr r3, [r3, #4] 800024a: f403 1370 and.w r3, r3, #3932160 ; 0x3c0000 800024e: 60bb str r3, [r7, #8] pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; 8000250: 4b1f ldr r3, [pc, #124] ; (80002d0 ) 8000252: 685b ldr r3, [r3, #4] 8000254: f403 3380 and.w r3, r3, #65536 ; 0x10000 8000258: 607b str r3, [r7, #4] #ifndef STM32F10X_CL pllmull = ( pllmull >> 18) + 2; 800025a: 68bb ldr r3, [r7, #8] 800025c: 0c9b lsrs r3, r3, #18 800025e: 3302 adds r3, #2 8000260: 60bb str r3, [r7, #8] if (pllsource == 0x00) 8000262: 687b ldr r3, [r7, #4] 8000264: 2b00 cmp r3, #0 8000266: d106 bne.n 8000276 { /* HSI oscillator clock divided by 2 selected as PLL clock entry */ SystemCoreClock = (HSI_VALUE >> 1) * pllmull; 8000268: 68bb ldr r3, [r7, #8] 800026a: 4a1c ldr r2, [pc, #112] ; (80002dc ) 800026c: fb02 f303 mul.w r3, r2, r3 8000270: 4a18 ldr r2, [pc, #96] ; (80002d4 ) 8000272: 6013 str r3, [r2, #0] pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; } } #endif /* STM32F10X_CL */ break; 8000274: e017 b.n 80002a6 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; /* HSE oscillator clock selected as PREDIV1 clock entry */ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; #else /* HSE selected as PLL clock entry */ if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) 8000276: 4b16 ldr r3, [pc, #88] ; (80002d0 ) 8000278: 685b ldr r3, [r3, #4] 800027a: f403 3300 and.w r3, r3, #131072 ; 0x20000 800027e: 2b00 cmp r3, #0 8000280: d006 beq.n 8000290 {/* HSE oscillator clock divided by 2 */ SystemCoreClock = (HSE_VALUE >> 1) * pllmull; 8000282: 68bb ldr r3, [r7, #8] 8000284: 4a15 ldr r2, [pc, #84] ; (80002dc ) 8000286: fb02 f303 mul.w r3, r2, r3 800028a: 4a12 ldr r2, [pc, #72] ; (80002d4 ) 800028c: 6013 str r3, [r2, #0] pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; } } #endif /* STM32F10X_CL */ break; 800028e: e00a b.n 80002a6 {/* HSE oscillator clock divided by 2 */ SystemCoreClock = (HSE_VALUE >> 1) * pllmull; } else { SystemCoreClock = HSE_VALUE * pllmull; 8000290: 68bb ldr r3, [r7, #8] 8000292: 4a11 ldr r2, [pc, #68] ; (80002d8 ) 8000294: fb02 f303 mul.w r3, r2, r3 8000298: 4a0e ldr r2, [pc, #56] ; (80002d4 ) 800029a: 6013 str r3, [r2, #0] pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; } } #endif /* STM32F10X_CL */ break; 800029c: e003 b.n 80002a6 default: SystemCoreClock = HSI_VALUE; 800029e: 4b0d ldr r3, [pc, #52] ; (80002d4 ) 80002a0: 4a0d ldr r2, [pc, #52] ; (80002d8 ) 80002a2: 601a str r2, [r3, #0] break; 80002a4: bf00 nop } /* Compute HCLK clock frequency ----------------*/ /* Get HCLK prescaler */ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; 80002a6: 4b0a ldr r3, [pc, #40] ; (80002d0 ) 80002a8: 685b ldr r3, [r3, #4] 80002aa: f003 03f0 and.w r3, r3, #240 ; 0xf0 80002ae: 091b lsrs r3, r3, #4 80002b0: 4a0b ldr r2, [pc, #44] ; (80002e0 ) 80002b2: 5cd3 ldrb r3, [r2, r3] 80002b4: b2db uxtb r3, r3 80002b6: 60fb str r3, [r7, #12] /* HCLK clock frequency */ SystemCoreClock >>= tmp; 80002b8: 4b06 ldr r3, [pc, #24] ; (80002d4 ) 80002ba: 681a ldr r2, [r3, #0] 80002bc: 68fb ldr r3, [r7, #12] 80002be: fa22 f303 lsr.w r3, r2, r3 80002c2: 4a04 ldr r2, [pc, #16] ; (80002d4 ) 80002c4: 6013 str r3, [r2, #0] } 80002c6: bf00 nop 80002c8: 3714 adds r7, #20 80002ca: 46bd mov sp, r7 80002cc: bc80 pop {r7} 80002ce: 4770 bx lr 80002d0: 40021000 .word 0x40021000 80002d4: 20000000 .word 0x20000000 80002d8: 007a1200 .word 0x007a1200 80002dc: 003d0900 .word 0x003d0900 80002e0: 20000004 .word 0x20000004 080002e4 : * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. * @param None * @retval None */ static void SetSysClock(void) { 80002e4: b580 push {r7, lr} 80002e6: af00 add r7, sp, #0 #elif defined SYSCLK_FREQ_48MHz SetSysClockTo48(); #elif defined SYSCLK_FREQ_56MHz SetSysClockTo56(); #elif defined SYSCLK_FREQ_72MHz SetSysClockTo72(); 80002e8: f000 f802 bl 80002f0 #endif /* If none of the define above is enabled, the HSI is used as System clock source (default after reset) */ } 80002ec: bf00 nop 80002ee: bd80 pop {r7, pc} 080002f0 : * @note This function should be used only after reset. * @param None * @retval None */ static void SetSysClockTo72(void) { 80002f0: b480 push {r7} 80002f2: b083 sub sp, #12 80002f4: af00 add r7, sp, #0 __IO uint32_t StartUpCounter = 0, HSEStatus = 0; 80002f6: 2300 movs r3, #0 80002f8: 607b str r3, [r7, #4] 80002fa: 2300 movs r3, #0 80002fc: 603b str r3, [r7, #0] /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ /* Enable HSE */ RCC->CR |= ((uint32_t)RCC_CR_HSEON); 80002fe: 4a3a ldr r2, [pc, #232] ; (80003e8 ) 8000300: 4b39 ldr r3, [pc, #228] ; (80003e8 ) 8000302: 681b ldr r3, [r3, #0] 8000304: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8000308: 6013 str r3, [r2, #0] /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CR & RCC_CR_HSERDY; 800030a: 4b37 ldr r3, [pc, #220] ; (80003e8 ) 800030c: 681b ldr r3, [r3, #0] 800030e: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000312: 603b str r3, [r7, #0] StartUpCounter++; 8000314: 687b ldr r3, [r7, #4] 8000316: 3301 adds r3, #1 8000318: 607b str r3, [r7, #4] } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); 800031a: 683b ldr r3, [r7, #0] 800031c: 2b00 cmp r3, #0 800031e: d103 bne.n 8000328 8000320: 687b ldr r3, [r7, #4] 8000322: f5b3 6fa0 cmp.w r3, #1280 ; 0x500 8000326: d1f0 bne.n 800030a if ((RCC->CR & RCC_CR_HSERDY) != RESET) 8000328: 4b2f ldr r3, [pc, #188] ; (80003e8 ) 800032a: 681b ldr r3, [r3, #0] 800032c: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000330: 2b00 cmp r3, #0 8000332: d002 beq.n 800033a { HSEStatus = (uint32_t)0x01; 8000334: 2301 movs r3, #1 8000336: 603b str r3, [r7, #0] 8000338: e001 b.n 800033e } else { HSEStatus = (uint32_t)0x00; 800033a: 2300 movs r3, #0 800033c: 603b str r3, [r7, #0] } if (HSEStatus == (uint32_t)0x01) 800033e: 683b ldr r3, [r7, #0] 8000340: 2b01 cmp r3, #1 8000342: d14b bne.n 80003dc { /* Enable Prefetch Buffer */ FLASH->ACR |= FLASH_ACR_PRFTBE; 8000344: 4a29 ldr r2, [pc, #164] ; (80003ec ) 8000346: 4b29 ldr r3, [pc, #164] ; (80003ec ) 8000348: 681b ldr r3, [r3, #0] 800034a: f043 0310 orr.w r3, r3, #16 800034e: 6013 str r3, [r2, #0] /* Flash 2 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); 8000350: 4a26 ldr r2, [pc, #152] ; (80003ec ) 8000352: 4b26 ldr r3, [pc, #152] ; (80003ec ) 8000354: 681b ldr r3, [r3, #0] 8000356: f023 0303 bic.w r3, r3, #3 800035a: 6013 str r3, [r2, #0] FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; 800035c: 4a23 ldr r2, [pc, #140] ; (80003ec ) 800035e: 4b23 ldr r3, [pc, #140] ; (80003ec ) 8000360: 681b ldr r3, [r3, #0] 8000362: f043 0302 orr.w r3, r3, #2 8000366: 6013 str r3, [r2, #0] /* HCLK = SYSCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; 8000368: 4a1f ldr r2, [pc, #124] ; (80003e8 ) 800036a: 4b1f ldr r3, [pc, #124] ; (80003e8 ) 800036c: 685b ldr r3, [r3, #4] 800036e: 6053 str r3, [r2, #4] /* PCLK2 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; 8000370: 4a1d ldr r2, [pc, #116] ; (80003e8 ) 8000372: 4b1d ldr r3, [pc, #116] ; (80003e8 ) 8000374: 685b ldr r3, [r3, #4] 8000376: 6053 str r3, [r2, #4] /* PCLK1 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; 8000378: 4a1b ldr r2, [pc, #108] ; (80003e8 ) 800037a: 4b1b ldr r3, [pc, #108] ; (80003e8 ) 800037c: 685b ldr r3, [r3, #4] 800037e: f443 6380 orr.w r3, r3, #1024 ; 0x400 8000382: 6053 str r3, [r2, #4] RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLMULL9); #else /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | 8000384: 4a18 ldr r2, [pc, #96] ; (80003e8 ) 8000386: 4b18 ldr r3, [pc, #96] ; (80003e8 ) 8000388: 685b ldr r3, [r3, #4] 800038a: f423 137c bic.w r3, r3, #4128768 ; 0x3f0000 800038e: 6053 str r3, [r2, #4] RCC_CFGR_PLLMULL)); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); 8000390: 4a15 ldr r2, [pc, #84] ; (80003e8 ) 8000392: 4b15 ldr r3, [pc, #84] ; (80003e8 ) 8000394: 685b ldr r3, [r3, #4] 8000396: f443 13e8 orr.w r3, r3, #1900544 ; 0x1d0000 800039a: 6053 str r3, [r2, #4] #endif /* STM32F10X_CL */ /* Enable PLL */ RCC->CR |= RCC_CR_PLLON; 800039c: 4a12 ldr r2, [pc, #72] ; (80003e8 ) 800039e: 4b12 ldr r3, [pc, #72] ; (80003e8 ) 80003a0: 681b ldr r3, [r3, #0] 80003a2: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 80003a6: 6013 str r3, [r2, #0] /* Wait till PLL is ready */ while((RCC->CR & RCC_CR_PLLRDY) == 0) 80003a8: bf00 nop 80003aa: 4b0f ldr r3, [pc, #60] ; (80003e8 ) 80003ac: 681b ldr r3, [r3, #0] 80003ae: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80003b2: 2b00 cmp r3, #0 80003b4: d0f9 beq.n 80003aa { } /* Select PLL as system clock source */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); 80003b6: 4a0c ldr r2, [pc, #48] ; (80003e8 ) 80003b8: 4b0b ldr r3, [pc, #44] ; (80003e8 ) 80003ba: 685b ldr r3, [r3, #4] 80003bc: f023 0303 bic.w r3, r3, #3 80003c0: 6053 str r3, [r2, #4] RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; 80003c2: 4a09 ldr r2, [pc, #36] ; (80003e8 ) 80003c4: 4b08 ldr r3, [pc, #32] ; (80003e8 ) 80003c6: 685b ldr r3, [r3, #4] 80003c8: f043 0302 orr.w r3, r3, #2 80003cc: 6053 str r3, [r2, #4] /* Wait till PLL is used as system clock source */ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) 80003ce: bf00 nop 80003d0: 4b05 ldr r3, [pc, #20] ; (80003e8 ) 80003d2: 685b ldr r3, [r3, #4] 80003d4: f003 030c and.w r3, r3, #12 80003d8: 2b08 cmp r3, #8 80003da: d1f9 bne.n 80003d0 } else { /* If HSE fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */ } } 80003dc: bf00 nop 80003de: 370c adds r7, #12 80003e0: 46bd mov sp, r7 80003e2: bc80 pop {r7} 80003e4: 4770 bx lr 80003e6: bf00 nop 80003e8: 40021000 .word 0x40021000 80003ec: 40022000 .word 0x40022000 080003f0 : FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx); void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) { 80003f0: b480 push {r7} 80003f2: b083 sub sp, #12 80003f4: af00 add r7, sp, #0 80003f6: 6078 str r0, [r7, #4] 80003f8: 460b mov r3, r1 80003fa: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 80003fc: 78fb ldrb r3, [r7, #3] 80003fe: 2b00 cmp r3, #0 8000400: d006 beq.n 8000410 { /* Set the ADON bit to wake up the ADC from power down mode */ ADCx->CR2 |= CR2_ADON_Set; 8000402: 687b ldr r3, [r7, #4] 8000404: 689b ldr r3, [r3, #8] 8000406: f043 0201 orr.w r2, r3, #1 800040a: 687b ldr r3, [r7, #4] 800040c: 609a str r2, [r3, #8] else { /* Disable the selected ADC peripheral */ ADCx->CR2 &= CR2_ADON_Reset; } } 800040e: e005 b.n 800041c ADCx->CR2 |= CR2_ADON_Set; } else { /* Disable the selected ADC peripheral */ ADCx->CR2 &= CR2_ADON_Reset; 8000410: 687b ldr r3, [r7, #4] 8000412: 689b ldr r3, [r3, #8] 8000414: f023 0201 bic.w r2, r3, #1 8000418: 687b ldr r3, [r7, #4] 800041a: 609a str r2, [r3, #8] } } 800041c: bf00 nop 800041e: 370c adds r7, #12 8000420: 46bd mov sp, r7 8000422: bc80 pop {r7} 8000424: 4770 bx lr 8000426: bf00 nop 08000428 : FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) { 8000428: b480 push {r7} 800042a: b085 sub sp, #20 800042c: af00 add r7, sp, #0 800042e: 6078 str r0, [r7, #4] 8000430: 460b mov r3, r1 8000432: 807b strh r3, [r7, #2] FlagStatus bitstatus = RESET; 8000434: 2300 movs r3, #0 8000436: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); /* Check the status of the specified SPI/I2S flag */ if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) 8000438: 687b ldr r3, [r7, #4] 800043a: 891b ldrh r3, [r3, #8] 800043c: b29a uxth r2, r3 800043e: 887b ldrh r3, [r7, #2] 8000440: 4013 ands r3, r2 8000442: b29b uxth r3, r3 8000444: 2b00 cmp r3, #0 8000446: d002 beq.n 800044e { /* SPI_I2S_FLAG is set */ bitstatus = SET; 8000448: 2301 movs r3, #1 800044a: 73fb strb r3, [r7, #15] 800044c: e001 b.n 8000452 } else { /* SPI_I2S_FLAG is reset */ bitstatus = RESET; 800044e: 2300 movs r3, #0 8000450: 73fb strb r3, [r7, #15] } /* Return the SPI_I2S_FLAG status */ return bitstatus; 8000452: 7bfb ldrb r3, [r7, #15] } 8000454: 4618 mov r0, r3 8000456: 3714 adds r7, #20 8000458: 46bd mov sp, r7 800045a: bc80 pop {r7} 800045c: 4770 bx lr 800045e: bf00 nop 08000460 : void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) { 8000460: b480 push {r7} 8000462: b083 sub sp, #12 8000464: af00 add r7, sp, #0 8000466: 6078 str r0, [r7, #4] 8000468: 460b mov r3, r1 800046a: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); /* Write in the DR register the data to be sent */ SPIx->DR = Data; 800046c: 687b ldr r3, [r7, #4] 800046e: 887a ldrh r2, [r7, #2] 8000470: 819a strh r2, [r3, #12] } 8000472: bf00 nop 8000474: 370c adds r7, #12 8000476: 46bd mov sp, r7 8000478: bc80 pop {r7} 800047a: 4770 bx lr 0800047c : void ADC_ResetCalibration(ADC_TypeDef* ADCx) { 800047c: b480 push {r7} 800047e: b083 sub sp, #12 8000480: af00 add r7, sp, #0 8000482: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Resets the selected ADC calibration registers */ ADCx->CR2 |= CR2_RSTCAL_Set; 8000484: 687b ldr r3, [r7, #4] 8000486: 689b ldr r3, [r3, #8] 8000488: f043 0208 orr.w r2, r3, #8 800048c: 687b ldr r3, [r7, #4] 800048e: 609a str r2, [r3, #8] } 8000490: bf00 nop 8000492: 370c adds r7, #12 8000494: 46bd mov sp, r7 8000496: bc80 pop {r7} 8000498: 4770 bx lr 800049a: bf00 nop 0800049c : FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx) { 800049c: b480 push {r7} 800049e: b085 sub sp, #20 80004a0: af00 add r7, sp, #0 80004a2: 6078 str r0, [r7, #4] FlagStatus bitstatus = RESET; 80004a4: 2300 movs r3, #0 80004a6: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Check the status of RSTCAL bit */ if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET) 80004a8: 687b ldr r3, [r7, #4] 80004aa: 689b ldr r3, [r3, #8] 80004ac: f003 0308 and.w r3, r3, #8 80004b0: 2b00 cmp r3, #0 80004b2: d002 beq.n 80004ba { /* RSTCAL bit is set */ bitstatus = SET; 80004b4: 2301 movs r3, #1 80004b6: 73fb strb r3, [r7, #15] 80004b8: e001 b.n 80004be } else { /* RSTCAL bit is reset */ bitstatus = RESET; 80004ba: 2300 movs r3, #0 80004bc: 73fb strb r3, [r7, #15] } /* Return the RSTCAL bit status */ return bitstatus; 80004be: 7bfb ldrb r3, [r7, #15] } 80004c0: 4618 mov r0, r3 80004c2: 3714 adds r7, #20 80004c4: 46bd mov sp, r7 80004c6: bc80 pop {r7} 80004c8: 4770 bx lr 80004ca: bf00 nop 080004cc : void ADC_StartCalibration(ADC_TypeDef* ADCx) { 80004cc: b480 push {r7} 80004ce: b083 sub sp, #12 80004d0: af00 add r7, sp, #0 80004d2: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Enable the selected ADC calibration process */ ADCx->CR2 |= CR2_CAL_Set; 80004d4: 687b ldr r3, [r7, #4] 80004d6: 689b ldr r3, [r3, #8] 80004d8: f043 0204 orr.w r2, r3, #4 80004dc: 687b ldr r3, [r7, #4] 80004de: 609a str r2, [r3, #8] } 80004e0: bf00 nop 80004e2: 370c adds r7, #12 80004e4: 46bd mov sp, r7 80004e6: bc80 pop {r7} 80004e8: 4770 bx lr 80004ea: bf00 nop 080004ec : FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx) { 80004ec: b480 push {r7} 80004ee: b085 sub sp, #20 80004f0: af00 add r7, sp, #0 80004f2: 6078 str r0, [r7, #4] FlagStatus bitstatus = RESET; 80004f4: 2300 movs r3, #0 80004f6: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Check the status of CAL bit */ if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET) 80004f8: 687b ldr r3, [r7, #4] 80004fa: 689b ldr r3, [r3, #8] 80004fc: f003 0304 and.w r3, r3, #4 8000500: 2b00 cmp r3, #0 8000502: d002 beq.n 800050a { /* CAL bit is set: calibration on going */ bitstatus = SET; 8000504: 2301 movs r3, #1 8000506: 73fb strb r3, [r7, #15] 8000508: e001 b.n 800050e } else { /* CAL bit is reset: end of calibration */ bitstatus = RESET; 800050a: 2300 movs r3, #0 800050c: 73fb strb r3, [r7, #15] } /* Return the CAL bit status */ return bitstatus; 800050e: 7bfb ldrb r3, [r7, #15] } 8000510: 4618 mov r0, r3 8000512: 3714 adds r7, #20 8000514: 46bd mov sp, r7 8000516: bc80 pop {r7} 8000518: 4770 bx lr 800051a: bf00 nop 0800051c : void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) { 800051c: b480 push {r7} 800051e: b083 sub sp, #12 8000520: af00 add r7, sp, #0 8000522: 6078 str r0, [r7, #4] 8000524: 460b mov r3, r1 8000526: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 8000528: 78fb ldrb r3, [r7, #3] 800052a: 2b00 cmp r3, #0 800052c: d006 beq.n 800053c { /* Enable the selected ADC conversion on external event and start the selected ADC conversion */ ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set; 800052e: 687b ldr r3, [r7, #4] 8000530: 689b ldr r3, [r3, #8] 8000532: f443 02a0 orr.w r2, r3, #5242880 ; 0x500000 8000536: 687b ldr r3, [r7, #4] 8000538: 609a str r2, [r3, #8] { /* Disable the selected ADC conversion on external event and stop the selected ADC conversion */ ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset; } } 800053a: e005 b.n 8000548 } else { /* Disable the selected ADC conversion on external event and stop the selected ADC conversion */ ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset; 800053c: 687b ldr r3, [r7, #4] 800053e: 689b ldr r3, [r3, #8] 8000540: f423 02a0 bic.w r2, r3, #5242880 ; 0x500000 8000544: 687b ldr r3, [r7, #4] 8000546: 609a str r2, [r3, #8] } } 8000548: bf00 nop 800054a: 370c adds r7, #12 800054c: 46bd mov sp, r7 800054e: bc80 pop {r7} 8000550: 4770 bx lr 8000552: bf00 nop 08000554 : uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) { 8000554: b480 push {r7} 8000556: b083 sub sp, #12 8000558: af00 add r7, sp, #0 800055a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); /* Return the data in the DR register */ return SPIx->DR; 800055c: 687b ldr r3, [r7, #4] 800055e: 899b ldrh r3, [r3, #12] 8000560: b29b uxth r3, r3 } 8000562: 4618 mov r0, r3 8000564: 370c adds r7, #12 8000566: 46bd mov sp, r7 8000568: bc80 pop {r7} 800056a: 4770 bx lr 0800056c : uint8_t SD_WriteByte(uint8_t Data) { 800056c: b580 push {r7, lr} 800056e: b082 sub sp, #8 8000570: af00 add r7, sp, #0 8000572: 4603 mov r3, r0 8000574: 71fb strb r3, [r7, #7] /*!< Wait until the transmit buffer is empty */ while(SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_TXE) == RESET) 8000576: bf00 nop 8000578: 2102 movs r1, #2 800057a: 480e ldr r0, [pc, #56] ; (80005b4 ) 800057c: f7ff ff54 bl 8000428 8000580: 4603 mov r3, r0 8000582: 2b00 cmp r3, #0 8000584: d0f8 beq.n 8000578 { } /*!< Send the byte */ SPI_I2S_SendData(SD_SPI, Data); 8000586: 79fb ldrb r3, [r7, #7] 8000588: b29b uxth r3, r3 800058a: 4619 mov r1, r3 800058c: 4809 ldr r0, [pc, #36] ; (80005b4 ) 800058e: f7ff ff67 bl 8000460 /*!< Wait to receive a byte*/ while(SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_RXNE) == RESET) 8000592: bf00 nop 8000594: 2101 movs r1, #1 8000596: 4807 ldr r0, [pc, #28] ; (80005b4 ) 8000598: f7ff ff46 bl 8000428 800059c: 4603 mov r3, r0 800059e: 2b00 cmp r3, #0 80005a0: d0f8 beq.n 8000594 { } /*!< Return the byte read from the SPI bus */ return SPI_I2S_ReceiveData(SD_SPI); 80005a2: 4804 ldr r0, [pc, #16] ; (80005b4 ) 80005a4: f7ff ffd6 bl 8000554 80005a8: 4603 mov r3, r0 80005aa: b2db uxtb r3, r3 } 80005ac: 4618 mov r0, r3 80005ae: 3708 adds r7, #8 80005b0: 46bd mov sp, r7 80005b2: bd80 pop {r7, pc} 80005b4: 40013000 .word 0x40013000 080005b8 : void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) { 80005b8: b480 push {r7} 80005ba: b089 sub sp, #36 ; 0x24 80005bc: af00 add r7, sp, #0 80005be: 6078 str r0, [r7, #4] 80005c0: 6039 str r1, [r7, #0] uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; 80005c2: 2300 movs r3, #0 80005c4: 61fb str r3, [r7, #28] 80005c6: 2300 movs r3, #0 80005c8: 613b str r3, [r7, #16] 80005ca: 2300 movs r3, #0 80005cc: 61bb str r3, [r7, #24] 80005ce: 2300 movs r3, #0 80005d0: 60fb str r3, [r7, #12] uint32_t tmpreg = 0x00, pinmask = 0x00; 80005d2: 2300 movs r3, #0 80005d4: 617b str r3, [r7, #20] 80005d6: 2300 movs r3, #0 80005d8: 60bb str r3, [r7, #8] assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); /*---------------------------- GPIO Mode Configuration -----------------------*/ currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); 80005da: 683b ldr r3, [r7, #0] 80005dc: 78db ldrb r3, [r3, #3] 80005de: f003 030f and.w r3, r3, #15 80005e2: 61fb str r3, [r7, #28] if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) 80005e4: 683b ldr r3, [r7, #0] 80005e6: 78db ldrb r3, [r3, #3] 80005e8: f003 0310 and.w r3, r3, #16 80005ec: 2b00 cmp r3, #0 80005ee: d005 beq.n 80005fc { /* Check the parameters */ assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); /* Output mode */ currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; 80005f0: 683b ldr r3, [r7, #0] 80005f2: 789b ldrb r3, [r3, #2] 80005f4: 461a mov r2, r3 80005f6: 69fb ldr r3, [r7, #28] 80005f8: 4313 orrs r3, r2 80005fa: 61fb str r3, [r7, #28] } /*---------------------------- GPIO CRL Configuration ------------------------*/ /* Configure the eight low port pins */ if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) 80005fc: 683b ldr r3, [r7, #0] 80005fe: 881b ldrh r3, [r3, #0] 8000600: b2db uxtb r3, r3 8000602: 2b00 cmp r3, #0 8000604: d044 beq.n 8000690 { tmpreg = GPIOx->CRL; 8000606: 687b ldr r3, [r7, #4] 8000608: 681b ldr r3, [r3, #0] 800060a: 617b str r3, [r7, #20] for (pinpos = 0x00; pinpos < 0x08; pinpos++) 800060c: 2300 movs r3, #0 800060e: 61bb str r3, [r7, #24] 8000610: e038 b.n 8000684 { pos = ((uint32_t)0x01) << pinpos; 8000612: 2201 movs r2, #1 8000614: 69bb ldr r3, [r7, #24] 8000616: fa02 f303 lsl.w r3, r2, r3 800061a: 60fb str r3, [r7, #12] /* Get the port pins position */ currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; 800061c: 683b ldr r3, [r7, #0] 800061e: 881b ldrh r3, [r3, #0] 8000620: 461a mov r2, r3 8000622: 68fb ldr r3, [r7, #12] 8000624: 4013 ands r3, r2 8000626: 613b str r3, [r7, #16] if (currentpin == pos) 8000628: 693a ldr r2, [r7, #16] 800062a: 68fb ldr r3, [r7, #12] 800062c: 429a cmp r2, r3 800062e: d126 bne.n 800067e { pos = pinpos << 2; 8000630: 69bb ldr r3, [r7, #24] 8000632: 009b lsls r3, r3, #2 8000634: 60fb str r3, [r7, #12] /* Clear the corresponding low control register bits */ pinmask = ((uint32_t)0x0F) << pos; 8000636: 220f movs r2, #15 8000638: 68fb ldr r3, [r7, #12] 800063a: fa02 f303 lsl.w r3, r2, r3 800063e: 60bb str r3, [r7, #8] tmpreg &= ~pinmask; 8000640: 68bb ldr r3, [r7, #8] 8000642: 43db mvns r3, r3 8000644: 697a ldr r2, [r7, #20] 8000646: 4013 ands r3, r2 8000648: 617b str r3, [r7, #20] /* Write the mode configuration in the corresponding bits */ tmpreg |= (currentmode << pos); 800064a: 69fa ldr r2, [r7, #28] 800064c: 68fb ldr r3, [r7, #12] 800064e: fa02 f303 lsl.w r3, r2, r3 8000652: 697a ldr r2, [r7, #20] 8000654: 4313 orrs r3, r2 8000656: 617b str r3, [r7, #20] /* Reset the corresponding ODR bit */ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) 8000658: 683b ldr r3, [r7, #0] 800065a: 78db ldrb r3, [r3, #3] 800065c: 2b28 cmp r3, #40 ; 0x28 800065e: d105 bne.n 800066c { GPIOx->BRR = (((uint32_t)0x01) << pinpos); 8000660: 2201 movs r2, #1 8000662: 69bb ldr r3, [r7, #24] 8000664: 409a lsls r2, r3 8000666: 687b ldr r3, [r7, #4] 8000668: 615a str r2, [r3, #20] 800066a: e008 b.n 800067e } else { /* Set the corresponding ODR bit */ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) 800066c: 683b ldr r3, [r7, #0] 800066e: 78db ldrb r3, [r3, #3] 8000670: 2b48 cmp r3, #72 ; 0x48 8000672: d104 bne.n 800067e { GPIOx->BSRR = (((uint32_t)0x01) << pinpos); 8000674: 2201 movs r2, #1 8000676: 69bb ldr r3, [r7, #24] 8000678: 409a lsls r2, r3 800067a: 687b ldr r3, [r7, #4] 800067c: 611a str r2, [r3, #16] /*---------------------------- GPIO CRL Configuration ------------------------*/ /* Configure the eight low port pins */ if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) { tmpreg = GPIOx->CRL; for (pinpos = 0x00; pinpos < 0x08; pinpos++) 800067e: 69bb ldr r3, [r7, #24] 8000680: 3301 adds r3, #1 8000682: 61bb str r3, [r7, #24] 8000684: 69bb ldr r3, [r7, #24] 8000686: 2b07 cmp r3, #7 8000688: d9c3 bls.n 8000612 GPIOx->BSRR = (((uint32_t)0x01) << pinpos); } } } } GPIOx->CRL = tmpreg; 800068a: 687b ldr r3, [r7, #4] 800068c: 697a ldr r2, [r7, #20] 800068e: 601a str r2, [r3, #0] } /*---------------------------- GPIO CRH Configuration ------------------------*/ /* Configure the eight high port pins */ if (GPIO_InitStruct->GPIO_Pin > 0x00FF) 8000690: 683b ldr r3, [r7, #0] 8000692: 881b ldrh r3, [r3, #0] 8000694: 2bff cmp r3, #255 ; 0xff 8000696: d946 bls.n 8000726 { tmpreg = GPIOx->CRH; 8000698: 687b ldr r3, [r7, #4] 800069a: 685b ldr r3, [r3, #4] 800069c: 617b str r3, [r7, #20] for (pinpos = 0x00; pinpos < 0x08; pinpos++) 800069e: 2300 movs r3, #0 80006a0: 61bb str r3, [r7, #24] 80006a2: e03a b.n 800071a { pos = (((uint32_t)0x01) << (pinpos + 0x08)); 80006a4: 69bb ldr r3, [r7, #24] 80006a6: 3308 adds r3, #8 80006a8: 2201 movs r2, #1 80006aa: fa02 f303 lsl.w r3, r2, r3 80006ae: 60fb str r3, [r7, #12] /* Get the port pins position */ currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); 80006b0: 683b ldr r3, [r7, #0] 80006b2: 881b ldrh r3, [r3, #0] 80006b4: 461a mov r2, r3 80006b6: 68fb ldr r3, [r7, #12] 80006b8: 4013 ands r3, r2 80006ba: 613b str r3, [r7, #16] if (currentpin == pos) 80006bc: 693a ldr r2, [r7, #16] 80006be: 68fb ldr r3, [r7, #12] 80006c0: 429a cmp r2, r3 80006c2: d127 bne.n 8000714 { pos = pinpos << 2; 80006c4: 69bb ldr r3, [r7, #24] 80006c6: 009b lsls r3, r3, #2 80006c8: 60fb str r3, [r7, #12] /* Clear the corresponding high control register bits */ pinmask = ((uint32_t)0x0F) << pos; 80006ca: 220f movs r2, #15 80006cc: 68fb ldr r3, [r7, #12] 80006ce: fa02 f303 lsl.w r3, r2, r3 80006d2: 60bb str r3, [r7, #8] tmpreg &= ~pinmask; 80006d4: 68bb ldr r3, [r7, #8] 80006d6: 43db mvns r3, r3 80006d8: 697a ldr r2, [r7, #20] 80006da: 4013 ands r3, r2 80006dc: 617b str r3, [r7, #20] /* Write the mode configuration in the corresponding bits */ tmpreg |= (currentmode << pos); 80006de: 69fa ldr r2, [r7, #28] 80006e0: 68fb ldr r3, [r7, #12] 80006e2: fa02 f303 lsl.w r3, r2, r3 80006e6: 697a ldr r2, [r7, #20] 80006e8: 4313 orrs r3, r2 80006ea: 617b str r3, [r7, #20] /* Reset the corresponding ODR bit */ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) 80006ec: 683b ldr r3, [r7, #0] 80006ee: 78db ldrb r3, [r3, #3] 80006f0: 2b28 cmp r3, #40 ; 0x28 80006f2: d105 bne.n 8000700 { GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08)); 80006f4: 69bb ldr r3, [r7, #24] 80006f6: 3308 adds r3, #8 80006f8: 2201 movs r2, #1 80006fa: 409a lsls r2, r3 80006fc: 687b ldr r3, [r7, #4] 80006fe: 615a str r2, [r3, #20] } /* Set the corresponding ODR bit */ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) 8000700: 683b ldr r3, [r7, #0] 8000702: 78db ldrb r3, [r3, #3] 8000704: 2b48 cmp r3, #72 ; 0x48 8000706: d105 bne.n 8000714 { GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08)); 8000708: 69bb ldr r3, [r7, #24] 800070a: 3308 adds r3, #8 800070c: 2201 movs r2, #1 800070e: 409a lsls r2, r3 8000710: 687b ldr r3, [r7, #4] 8000712: 611a str r2, [r3, #16] /*---------------------------- GPIO CRH Configuration ------------------------*/ /* Configure the eight high port pins */ if (GPIO_InitStruct->GPIO_Pin > 0x00FF) { tmpreg = GPIOx->CRH; for (pinpos = 0x00; pinpos < 0x08; pinpos++) 8000714: 69bb ldr r3, [r7, #24] 8000716: 3301 adds r3, #1 8000718: 61bb str r3, [r7, #24] 800071a: 69bb ldr r3, [r7, #24] 800071c: 2b07 cmp r3, #7 800071e: d9c1 bls.n 80006a4 { GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08)); } } } GPIOx->CRH = tmpreg; 8000720: 687b ldr r3, [r7, #4] 8000722: 697a ldr r2, [r7, #20] 8000724: 605a str r2, [r3, #4] } } 8000726: bf00 nop 8000728: 3724 adds r7, #36 ; 0x24 800072a: 46bd mov sp, r7 800072c: bc80 pop {r7} 800072e: 4770 bx lr 08000730 : void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) { 8000730: b480 push {r7} 8000732: b085 sub sp, #20 8000734: af00 add r7, sp, #0 8000736: 6078 str r0, [r7, #4] 8000738: 6039 str r1, [r7, #0] uint16_t tmpreg = 0; 800073a: 2300 movs r3, #0 800073c: 81fb strh r3, [r7, #14] assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); /*---------------------------- SPIx CR1 Configuration ------------------------*/ /* Get the SPIx CR1 value */ tmpreg = SPIx->CR1; 800073e: 687b ldr r3, [r7, #4] 8000740: 881b ldrh r3, [r3, #0] 8000742: 81fb strh r3, [r7, #14] /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ tmpreg &= CR1_CLEAR_Mask; 8000744: 89fb ldrh r3, [r7, #14] 8000746: f403 5341 and.w r3, r3, #12352 ; 0x3040 800074a: 81fb strh r3, [r7, #14] /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ /* Set LSBFirst bit according to SPI_FirstBit value */ /* Set BR bits according to SPI_BaudRatePrescaler value */ /* Set CPOL bit according to SPI_CPOL value */ /* Set CPHA bit according to SPI_CPHA value */ tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | 800074c: 683b ldr r3, [r7, #0] 800074e: 881a ldrh r2, [r3, #0] 8000750: 683b ldr r3, [r7, #0] 8000752: 885b ldrh r3, [r3, #2] 8000754: 4313 orrs r3, r2 8000756: b29a uxth r2, r3 SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | 8000758: 683b ldr r3, [r7, #0] 800075a: 889b ldrh r3, [r3, #4] /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ /* Set LSBFirst bit according to SPI_FirstBit value */ /* Set BR bits according to SPI_BaudRatePrescaler value */ /* Set CPOL bit according to SPI_CPOL value */ /* Set CPHA bit according to SPI_CPHA value */ tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | 800075c: 4313 orrs r3, r2 800075e: b29a uxth r2, r3 SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | 8000760: 683b ldr r3, [r7, #0] 8000762: 88db ldrh r3, [r3, #6] /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ /* Set LSBFirst bit according to SPI_FirstBit value */ /* Set BR bits according to SPI_BaudRatePrescaler value */ /* Set CPOL bit according to SPI_CPOL value */ /* Set CPHA bit according to SPI_CPHA value */ tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | 8000764: 4313 orrs r3, r2 8000766: b29a uxth r2, r3 SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | 8000768: 683b ldr r3, [r7, #0] 800076a: 891b ldrh r3, [r3, #8] /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ /* Set LSBFirst bit according to SPI_FirstBit value */ /* Set BR bits according to SPI_BaudRatePrescaler value */ /* Set CPOL bit according to SPI_CPOL value */ /* Set CPHA bit according to SPI_CPHA value */ tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | 800076c: 4313 orrs r3, r2 800076e: b29a uxth r2, r3 SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | 8000770: 683b ldr r3, [r7, #0] 8000772: 895b ldrh r3, [r3, #10] /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ /* Set LSBFirst bit according to SPI_FirstBit value */ /* Set BR bits according to SPI_BaudRatePrescaler value */ /* Set CPOL bit according to SPI_CPOL value */ /* Set CPHA bit according to SPI_CPHA value */ tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | 8000774: 4313 orrs r3, r2 8000776: b29a uxth r2, r3 SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); 8000778: 683b ldr r3, [r7, #0] 800077a: 899b ldrh r3, [r3, #12] /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ /* Set LSBFirst bit according to SPI_FirstBit value */ /* Set BR bits according to SPI_BaudRatePrescaler value */ /* Set CPOL bit according to SPI_CPOL value */ /* Set CPHA bit according to SPI_CPHA value */ tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | 800077c: 4313 orrs r3, r2 800077e: b29a uxth r2, r3 SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); 8000780: 683b ldr r3, [r7, #0] 8000782: 89db ldrh r3, [r3, #14] /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ /* Set LSBFirst bit according to SPI_FirstBit value */ /* Set BR bits according to SPI_BaudRatePrescaler value */ /* Set CPOL bit according to SPI_CPOL value */ /* Set CPHA bit according to SPI_CPHA value */ tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | 8000784: 4313 orrs r3, r2 8000786: b29a uxth r2, r3 8000788: 89fb ldrh r3, [r7, #14] 800078a: 4313 orrs r3, r2 800078c: 81fb strh r3, [r7, #14] SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); /* Write to SPIx CR1 */ SPIx->CR1 = tmpreg; 800078e: 687b ldr r3, [r7, #4] 8000790: 89fa ldrh r2, [r7, #14] 8000792: 801a strh r2, [r3, #0] /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ SPIx->I2SCFGR &= SPI_Mode_Select; 8000794: 687b ldr r3, [r7, #4] 8000796: 8b9b ldrh r3, [r3, #28] 8000798: b29b uxth r3, r3 800079a: f423 6300 bic.w r3, r3, #2048 ; 0x800 800079e: b29a uxth r2, r3 80007a0: 687b ldr r3, [r7, #4] 80007a2: 839a strh r2, [r3, #28] /*---------------------------- SPIx CRCPOLY Configuration --------------------*/ /* Write to SPIx CRCPOLY */ SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; 80007a4: 683b ldr r3, [r7, #0] 80007a6: 8a1a ldrh r2, [r3, #16] 80007a8: 687b ldr r3, [r7, #4] 80007aa: 821a strh r2, [r3, #16] } 80007ac: bf00 nop 80007ae: 3714 adds r7, #20 80007b0: 46bd mov sp, r7 80007b2: bc80 pop {r7} 80007b4: 4770 bx lr 80007b6: bf00 nop 080007b8 : void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) { 80007b8: b480 push {r7} 80007ba: b083 sub sp, #12 80007bc: af00 add r7, sp, #0 80007be: 6078 str r0, [r7, #4] 80007c0: 460b mov r3, r1 80007c2: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 80007c4: 78fb ldrb r3, [r7, #3] 80007c6: 2b00 cmp r3, #0 80007c8: d008 beq.n 80007dc { /* Enable the selected SPI peripheral */ SPIx->CR1 |= CR1_SPE_Set; 80007ca: 687b ldr r3, [r7, #4] 80007cc: 881b ldrh r3, [r3, #0] 80007ce: b29b uxth r3, r3 80007d0: f043 0340 orr.w r3, r3, #64 ; 0x40 80007d4: b29a uxth r2, r3 80007d6: 687b ldr r3, [r7, #4] 80007d8: 801a strh r2, [r3, #0] else { /* Disable the selected SPI peripheral */ SPIx->CR1 &= CR1_SPE_Reset; } } 80007da: e007 b.n 80007ec SPIx->CR1 |= CR1_SPE_Set; } else { /* Disable the selected SPI peripheral */ SPIx->CR1 &= CR1_SPE_Reset; 80007dc: 687b ldr r3, [r7, #4] 80007de: 881b ldrh r3, [r3, #0] 80007e0: b29b uxth r3, r3 80007e2: f023 0340 bic.w r3, r3, #64 ; 0x40 80007e6: b29a uxth r2, r3 80007e8: 687b ldr r3, [r7, #4] 80007ea: 801a strh r2, [r3, #0] } } 80007ec: bf00 nop 80007ee: 370c adds r7, #12 80007f0: 46bd mov sp, r7 80007f2: bc80 pop {r7} 80007f4: 4770 bx lr 80007f6: bf00 nop 080007f8 : void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 80007f8: b480 push {r7} 80007fa: b083 sub sp, #12 80007fc: af00 add r7, sp, #0 80007fe: 6078 str r0, [r7, #4] 8000800: 460b mov r3, r1 8000802: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); GPIOx->BSRR = GPIO_Pin; 8000804: 887a ldrh r2, [r7, #2] 8000806: 687b ldr r3, [r7, #4] 8000808: 611a str r2, [r3, #16] } 800080a: bf00 nop 800080c: 370c adds r7, #12 800080e: 46bd mov sp, r7 8000810: bc80 pop {r7} 8000812: 4770 bx lr 08000814 : void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) { 8000814: b480 push {r7} 8000816: b083 sub sp, #12 8000818: af00 add r7, sp, #0 800081a: 6078 str r0, [r7, #4] 800081c: 460b mov r3, r1 800081e: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 8000820: 78fb ldrb r3, [r7, #3] 8000822: 2b00 cmp r3, #0 8000824: d006 beq.n 8000834 { RCC->APB2ENR |= RCC_APB2Periph; 8000826: 4909 ldr r1, [pc, #36] ; (800084c ) 8000828: 4b08 ldr r3, [pc, #32] ; (800084c ) 800082a: 699a ldr r2, [r3, #24] 800082c: 687b ldr r3, [r7, #4] 800082e: 4313 orrs r3, r2 8000830: 618b str r3, [r1, #24] } else { RCC->APB2ENR &= ~RCC_APB2Periph; } } 8000832: e006 b.n 8000842 { RCC->APB2ENR |= RCC_APB2Periph; } else { RCC->APB2ENR &= ~RCC_APB2Periph; 8000834: 4905 ldr r1, [pc, #20] ; (800084c ) 8000836: 4b05 ldr r3, [pc, #20] ; (800084c ) 8000838: 699a ldr r2, [r3, #24] 800083a: 687b ldr r3, [r7, #4] 800083c: 43db mvns r3, r3 800083e: 4013 ands r3, r2 8000840: 618b str r3, [r1, #24] } } 8000842: bf00 nop 8000844: 370c adds r7, #12 8000846: 46bd mov sp, r7 8000848: bc80 pop {r7} 800084a: 4770 bx lr 800084c: 40021000 .word 0x40021000 08000850 : void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 8000850: b480 push {r7} 8000852: b083 sub sp, #12 8000854: af00 add r7, sp, #0 8000856: 6078 str r0, [r7, #4] 8000858: 460b mov r3, r1 800085a: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); GPIOx->BRR = GPIO_Pin; 800085c: 887a ldrh r2, [r7, #2] 800085e: 687b ldr r3, [r7, #4] 8000860: 615a str r2, [r3, #20] } 8000862: bf00 nop 8000864: 370c adds r7, #12 8000866: 46bd mov sp, r7 8000868: bc80 pop {r7} 800086a: 4770 bx lr 0800086c : void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) { 800086c: b480 push {r7} 800086e: b085 sub sp, #20 8000870: af00 add r7, sp, #0 8000872: 6078 str r0, [r7, #4] 8000874: 6039 str r1, [r7, #0] uint32_t tmpreg1 = 0; 8000876: 2300 movs r3, #0 8000878: 60fb str r3, [r7, #12] uint8_t tmpreg2 = 0; 800087a: 2300 movs r3, #0 800087c: 72fb strb r3, [r7, #11] assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel)); /*---------------------------- ADCx CR1 Configuration -----------------*/ /* Get the ADCx CR1 value */ tmpreg1 = ADCx->CR1; 800087e: 687b ldr r3, [r7, #4] 8000880: 685b ldr r3, [r3, #4] 8000882: 60fb str r3, [r7, #12] /* Clear DUALMOD and SCAN bits */ tmpreg1 &= CR1_CLEAR_Mask; 8000884: 68fb ldr r3, [r7, #12] 8000886: f403 5341 and.w r3, r3, #12352 ; 0x3040 800088a: 60fb str r3, [r7, #12] /* Configure ADCx: Dual mode and scan conversion mode */ /* Set DUALMOD bits according to ADC_Mode value */ /* Set SCAN bit according to ADC_ScanConvMode value */ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); 800088c: 683b ldr r3, [r7, #0] 800088e: 681a ldr r2, [r3, #0] 8000890: 683b ldr r3, [r7, #0] 8000892: 791b ldrb r3, [r3, #4] 8000894: 021b lsls r3, r3, #8 8000896: 4313 orrs r3, r2 8000898: 68fa ldr r2, [r7, #12] 800089a: 4313 orrs r3, r2 800089c: 60fb str r3, [r7, #12] /* Write to ADCx CR1 */ ADCx->CR1 = tmpreg1; 800089e: 687b ldr r3, [r7, #4] 80008a0: 68fa ldr r2, [r7, #12] 80008a2: 605a str r2, [r3, #4] /*---------------------------- ADCx CR2 Configuration -----------------*/ /* Get the ADCx CR2 value */ tmpreg1 = ADCx->CR2; 80008a4: 687b ldr r3, [r7, #4] 80008a6: 689b ldr r3, [r3, #8] 80008a8: 60fb str r3, [r7, #12] /* Clear CONT, ALIGN and EXTSEL bits */ tmpreg1 &= CR2_CLEAR_Mask; 80008aa: 68fa ldr r2, [r7, #12] 80008ac: 4b16 ldr r3, [pc, #88] ; (8000908 ) 80008ae: 4013 ands r3, r2 80008b0: 60fb str r3, [r7, #12] /* Configure ADCx: external trigger event and continuous conversion mode */ /* Set ALIGN bit according to ADC_DataAlign value */ /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ /* Set CONT bit according to ADC_ContinuousConvMode value */ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | 80008b2: 683b ldr r3, [r7, #0] 80008b4: 68da ldr r2, [r3, #12] 80008b6: 683b ldr r3, [r7, #0] 80008b8: 689b ldr r3, [r3, #8] 80008ba: 431a orrs r2, r3 ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); 80008bc: 683b ldr r3, [r7, #0] 80008be: 795b ldrb r3, [r3, #5] 80008c0: 005b lsls r3, r3, #1 tmpreg1 &= CR2_CLEAR_Mask; /* Configure ADCx: external trigger event and continuous conversion mode */ /* Set ALIGN bit according to ADC_DataAlign value */ /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ /* Set CONT bit according to ADC_ContinuousConvMode value */ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | 80008c2: 4313 orrs r3, r2 80008c4: 68fa ldr r2, [r7, #12] 80008c6: 4313 orrs r3, r2 80008c8: 60fb str r3, [r7, #12] ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); /* Write to ADCx CR2 */ ADCx->CR2 = tmpreg1; 80008ca: 687b ldr r3, [r7, #4] 80008cc: 68fa ldr r2, [r7, #12] 80008ce: 609a str r2, [r3, #8] /*---------------------------- ADCx SQR1 Configuration -----------------*/ /* Get the ADCx SQR1 value */ tmpreg1 = ADCx->SQR1; 80008d0: 687b ldr r3, [r7, #4] 80008d2: 6adb ldr r3, [r3, #44] ; 0x2c 80008d4: 60fb str r3, [r7, #12] /* Clear L bits */ tmpreg1 &= SQR1_CLEAR_Mask; 80008d6: 68fb ldr r3, [r7, #12] 80008d8: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000 80008dc: 60fb str r3, [r7, #12] /* Configure ADCx: regular channel sequence length */ /* Set L bits according to ADC_NbrOfChannel value */ tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); 80008de: 683b ldr r3, [r7, #0] 80008e0: 7c1b ldrb r3, [r3, #16] 80008e2: 3b01 subs r3, #1 80008e4: b2da uxtb r2, r3 80008e6: 7afb ldrb r3, [r7, #11] 80008e8: 4313 orrs r3, r2 80008ea: 72fb strb r3, [r7, #11] tmpreg1 |= (uint32_t)tmpreg2 << 20; 80008ec: 7afb ldrb r3, [r7, #11] 80008ee: 051b lsls r3, r3, #20 80008f0: 68fa ldr r2, [r7, #12] 80008f2: 4313 orrs r3, r2 80008f4: 60fb str r3, [r7, #12] /* Write to ADCx SQR1 */ ADCx->SQR1 = tmpreg1; 80008f6: 687b ldr r3, [r7, #4] 80008f8: 68fa ldr r2, [r7, #12] 80008fa: 62da str r2, [r3, #44] ; 0x2c } 80008fc: bf00 nop 80008fe: 3714 adds r7, #20 8000900: 46bd mov sp, r7 8000902: bc80 pop {r7} 8000904: 4770 bx lr 8000906: bf00 nop 8000908: fff1f7fd .word 0xfff1f7fd 0800090c : void SD_LowLevel_Init(void) { 800090c: b580 push {r7, lr} 800090e: b086 sub sp, #24 8000910: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStructure; SPI_InitTypeDef SPI_InitStructure; /*!< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO and SD_SPI_SCK_GPIO Periph clock enable */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); 8000912: 2101 movs r1, #1 8000914: 2004 movs r0, #4 8000916: f7ff ff7d bl 8000814 /*!< SD_SPI Periph clock enable */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE); 800091a: 2101 movs r1, #1 800091c: f44f 5080 mov.w r0, #4096 ; 0x1000 8000920: f7ff ff78 bl 8000814 /*!< Configure SD_SPI pins: SCK */ GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN | SD_SPI_MOSI_PIN | SD_SPI_MISO_PIN; 8000924: 23e0 movs r3, #224 ; 0xe0 8000926: 82bb strh r3, [r7, #20] GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 8000928: 2303 movs r3, #3 800092a: 75bb strb r3, [r7, #22] GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; 800092c: 2318 movs r3, #24 800092e: 75fb strb r3, [r7, #23] GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); 8000930: f107 0314 add.w r3, r7, #20 8000934: 4619 mov r1, r3 8000936: 4817 ldr r0, [pc, #92] ; (8000994 ) 8000938: f7ff fe3e bl 80005b8 /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */ GPIO_InitStructure.GPIO_Pin = SD_CS_PIN; 800093c: 2310 movs r3, #16 800093e: 82bb strh r3, [r7, #20] GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; 8000940: 2310 movs r3, #16 8000942: 75fb strb r3, [r7, #23] GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure); 8000944: f107 0314 add.w r3, r7, #20 8000948: 4619 mov r1, r3 800094a: 4812 ldr r0, [pc, #72] ; (8000994 ) 800094c: f7ff fe34 bl 80005b8 /*!< SD_SPI Config */ SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; 8000950: 2300 movs r3, #0 8000952: 803b strh r3, [r7, #0] SPI_InitStructure.SPI_Mode = SPI_Mode_Master; 8000954: f44f 7382 mov.w r3, #260 ; 0x104 8000958: 807b strh r3, [r7, #2] SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; 800095a: 2300 movs r3, #0 800095c: 80bb strh r3, [r7, #4] SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; 800095e: 2302 movs r3, #2 8000960: 80fb strh r3, [r7, #6] SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; 8000962: 2301 movs r3, #1 8000964: 813b strh r3, [r7, #8] SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; 8000966: f44f 7300 mov.w r3, #512 ; 0x200 800096a: 817b strh r3, [r7, #10] SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4; 800096c: 2308 movs r3, #8 800096e: 81bb strh r3, [r7, #12] SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; 8000970: 2300 movs r3, #0 8000972: 81fb strh r3, [r7, #14] SPI_InitStructure.SPI_CRCPolynomial = 7; 8000974: 2307 movs r3, #7 8000976: 823b strh r3, [r7, #16] SPI_Init(SD_SPI, &SPI_InitStructure); 8000978: 463b mov r3, r7 800097a: 4619 mov r1, r3 800097c: 4806 ldr r0, [pc, #24] ; (8000998 ) 800097e: f7ff fed7 bl 8000730 SPI_Cmd(SD_SPI, ENABLE); /*!< SD_SPI enable */ 8000982: 2101 movs r1, #1 8000984: 4804 ldr r0, [pc, #16] ; (8000998 ) 8000986: f7ff ff17 bl 80007b8 } 800098a: bf00 nop 800098c: 3718 adds r7, #24 800098e: 46bd mov sp, r7 8000990: bd80 pop {r7, pc} 8000992: bf00 nop 8000994: 40010800 .word 0x40010800 8000998: 40013000 .word 0x40013000 0800099c : SD_Error SD_GoIdleState(void) { 800099c: b580 push {r7, lr} 800099e: af00 add r7, sp, #0 /*!< SD chip select low */ SD_CS_LOW(); 80009a0: 2110 movs r1, #16 80009a2: 4818 ldr r0, [pc, #96] ; (8000a04 ) 80009a4: f7ff ff54 bl 8000850 /*!< Send CMD0 (SD_CMD_GO_IDLE_STATE) to put SD in SPI mode */ SD_SendCmd(SD_CMD_GO_IDLE_STATE, 0, 0x95); 80009a8: 2295 movs r2, #149 ; 0x95 80009aa: 2100 movs r1, #0 80009ac: 2000 movs r0, #0 80009ae: f000 f82b bl 8000a08 /*!< Wait for In Idle State Response (R1 Format) equal to 0x01 */ if (SD_GetResponse(SD_IN_IDLE_STATE)) 80009b2: 2001 movs r0, #1 80009b4: f000 f85e bl 8000a74 80009b8: 4603 mov r3, r0 80009ba: 2b00 cmp r3, #0 80009bc: d001 beq.n 80009c2 { /*!< No Idle State Response: return response failue */ return SD_RESPONSE_FAILURE; 80009be: 23ff movs r3, #255 ; 0xff 80009c0: e01d b.n 80009fe } /*----------Activates the card initialization process-----------*/ do { /*!< SD chip select high */ SD_CS_HIGH(); 80009c2: 2110 movs r1, #16 80009c4: 480f ldr r0, [pc, #60] ; (8000a04 ) 80009c6: f7ff ff17 bl 80007f8 /*!< Send Dummy byte 0xFF */ SD_WriteByte(SD_DUMMY_BYTE); 80009ca: 20ff movs r0, #255 ; 0xff 80009cc: f7ff fdce bl 800056c /*!< SD chip select low */ SD_CS_LOW(); 80009d0: 2110 movs r1, #16 80009d2: 480c ldr r0, [pc, #48] ; (8000a04 ) 80009d4: f7ff ff3c bl 8000850 /*!< Send CMD1 (Activates the card process) until response equal to 0x0 */ SD_SendCmd(SD_CMD_SEND_OP_COND, 0, 0xFF); 80009d8: 22ff movs r2, #255 ; 0xff 80009da: 2100 movs r1, #0 80009dc: 2001 movs r0, #1 80009de: f000 f813 bl 8000a08 /*!< Wait for no error Response (R1 Format) equal to 0x00 */ } while (SD_GetResponse(SD_RESPONSE_NO_ERROR)); 80009e2: 2000 movs r0, #0 80009e4: f000 f846 bl 8000a74 80009e8: 4603 mov r3, r0 80009ea: 2b00 cmp r3, #0 80009ec: d1e9 bne.n 80009c2 /*!< SD chip select high */ SD_CS_HIGH(); 80009ee: 2110 movs r1, #16 80009f0: 4804 ldr r0, [pc, #16] ; (8000a04 ) 80009f2: f7ff ff01 bl 80007f8 /*!< Send dummy byte 0xFF */ SD_WriteByte(SD_DUMMY_BYTE); 80009f6: 20ff movs r0, #255 ; 0xff 80009f8: f7ff fdb8 bl 800056c return SD_RESPONSE_NO_ERROR; 80009fc: 2300 movs r3, #0 } 80009fe: 4618 mov r0, r3 8000a00: bd80 pop {r7, pc} 8000a02: bf00 nop 8000a04: 40010800 .word 0x40010800 08000a08 : void SD_SendCmd(uint8_t Cmd, uint32_t Arg, uint8_t Crc) { 8000a08: b580 push {r7, lr} 8000a0a: b086 sub sp, #24 8000a0c: af00 add r7, sp, #0 8000a0e: 4603 mov r3, r0 8000a10: 6039 str r1, [r7, #0] 8000a12: 71fb strb r3, [r7, #7] 8000a14: 4613 mov r3, r2 8000a16: 71bb strb r3, [r7, #6] uint32_t i = 0x00; 8000a18: 2300 movs r3, #0 8000a1a: 617b str r3, [r7, #20] uint8_t Frame[6]; Frame[0] = (Cmd | 0x40); /*!< Construct byte 1 */ 8000a1c: 79fb ldrb r3, [r7, #7] 8000a1e: f043 0340 orr.w r3, r3, #64 ; 0x40 8000a22: b2db uxtb r3, r3 8000a24: 733b strb r3, [r7, #12] Frame[1] = (uint8_t)(Arg >> 24); /*!< Construct byte 2 */ 8000a26: 683b ldr r3, [r7, #0] 8000a28: 0e1b lsrs r3, r3, #24 8000a2a: b2db uxtb r3, r3 8000a2c: 737b strb r3, [r7, #13] Frame[2] = (uint8_t)(Arg >> 16); /*!< Construct byte 3 */ 8000a2e: 683b ldr r3, [r7, #0] 8000a30: 0c1b lsrs r3, r3, #16 8000a32: b2db uxtb r3, r3 8000a34: 73bb strb r3, [r7, #14] Frame[3] = (uint8_t)(Arg >> 8); /*!< Construct byte 4 */ 8000a36: 683b ldr r3, [r7, #0] 8000a38: 0a1b lsrs r3, r3, #8 8000a3a: b2db uxtb r3, r3 8000a3c: 73fb strb r3, [r7, #15] Frame[4] = (uint8_t)(Arg); /*!< Construct byte 5 */ 8000a3e: 683b ldr r3, [r7, #0] 8000a40: b2db uxtb r3, r3 8000a42: 743b strb r3, [r7, #16] Frame[5] = (Crc); /*!< Construct CRC: byte 6 */ 8000a44: 79bb ldrb r3, [r7, #6] 8000a46: 747b strb r3, [r7, #17] for (i = 0; i < 6; i++) 8000a48: 2300 movs r3, #0 8000a4a: 617b str r3, [r7, #20] 8000a4c: e00a b.n 8000a64 { SD_WriteByte(Frame[i]); /*!< Send the Cmd bytes */ 8000a4e: f107 020c add.w r2, r7, #12 8000a52: 697b ldr r3, [r7, #20] 8000a54: 4413 add r3, r2 8000a56: 781b ldrb r3, [r3, #0] 8000a58: 4618 mov r0, r3 8000a5a: f7ff fd87 bl 800056c Frame[4] = (uint8_t)(Arg); /*!< Construct byte 5 */ Frame[5] = (Crc); /*!< Construct CRC: byte 6 */ for (i = 0; i < 6; i++) 8000a5e: 697b ldr r3, [r7, #20] 8000a60: 3301 adds r3, #1 8000a62: 617b str r3, [r7, #20] 8000a64: 697b ldr r3, [r7, #20] 8000a66: 2b05 cmp r3, #5 8000a68: d9f1 bls.n 8000a4e { SD_WriteByte(Frame[i]); /*!< Send the Cmd bytes */ } } 8000a6a: bf00 nop 8000a6c: 3718 adds r7, #24 8000a6e: 46bd mov sp, r7 8000a70: bd80 pop {r7, pc} 8000a72: bf00 nop 08000a74 : SD_Error SD_GetResponse(uint8_t Response) { 8000a74: b580 push {r7, lr} 8000a76: b084 sub sp, #16 8000a78: af00 add r7, sp, #0 8000a7a: 4603 mov r3, r0 8000a7c: 71fb strb r3, [r7, #7] uint32_t Count = 0xFFF; 8000a7e: f640 73ff movw r3, #4095 ; 0xfff 8000a82: 60fb str r3, [r7, #12] /*!< Check if response is got or a timeout is happen */ while ((SD_ReadByte() != Response) && Count) 8000a84: e002 b.n 8000a8c { Count--; 8000a86: 68fb ldr r3, [r7, #12] 8000a88: 3b01 subs r3, #1 8000a8a: 60fb str r3, [r7, #12] SD_Error SD_GetResponse(uint8_t Response) { uint32_t Count = 0xFFF; /*!< Check if response is got or a timeout is happen */ while ((SD_ReadByte() != Response) && Count) 8000a8c: f000 f812 bl 8000ab4 8000a90: 4603 mov r3, r0 8000a92: 461a mov r2, r3 8000a94: 79fb ldrb r3, [r7, #7] 8000a96: 4293 cmp r3, r2 8000a98: d002 beq.n 8000aa0 8000a9a: 68fb ldr r3, [r7, #12] 8000a9c: 2b00 cmp r3, #0 8000a9e: d1f2 bne.n 8000a86 { Count--; } if (Count == 0) 8000aa0: 68fb ldr r3, [r7, #12] 8000aa2: 2b00 cmp r3, #0 8000aa4: d101 bne.n 8000aaa { /*!< After time out */ return SD_RESPONSE_FAILURE; 8000aa6: 23ff movs r3, #255 ; 0xff 8000aa8: e000 b.n 8000aac } else { /*!< Right response got */ return SD_RESPONSE_NO_ERROR; 8000aaa: 2300 movs r3, #0 } } 8000aac: 4618 mov r0, r3 8000aae: 3710 adds r7, #16 8000ab0: 46bd mov sp, r7 8000ab2: bd80 pop {r7, pc} 08000ab4 : uint8_t SD_ReadByte(void) { 8000ab4: b580 push {r7, lr} 8000ab6: b082 sub sp, #8 8000ab8: af00 add r7, sp, #0 uint8_t Data = 0; 8000aba: 2300 movs r3, #0 8000abc: 71fb strb r3, [r7, #7] /*!< Wait until the transmit buffer is empty */ while (SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_TXE) == RESET) 8000abe: bf00 nop 8000ac0: 2102 movs r1, #2 8000ac2: 480e ldr r0, [pc, #56] ; (8000afc ) 8000ac4: f7ff fcb0 bl 8000428 8000ac8: 4603 mov r3, r0 8000aca: 2b00 cmp r3, #0 8000acc: d0f8 beq.n 8000ac0 { } /*!< Send the byte */ SPI_I2S_SendData(SD_SPI, SD_DUMMY_BYTE); 8000ace: 21ff movs r1, #255 ; 0xff 8000ad0: 480a ldr r0, [pc, #40] ; (8000afc ) 8000ad2: f7ff fcc5 bl 8000460 /*!< Wait until a data is received */ while (SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_RXNE) == RESET) 8000ad6: bf00 nop 8000ad8: 2101 movs r1, #1 8000ada: 4808 ldr r0, [pc, #32] ; (8000afc ) 8000adc: f7ff fca4 bl 8000428 8000ae0: 4603 mov r3, r0 8000ae2: 2b00 cmp r3, #0 8000ae4: d0f8 beq.n 8000ad8 { } /*!< Get the received data */ Data = SPI_I2S_ReceiveData(SD_SPI); 8000ae6: 4805 ldr r0, [pc, #20] ; (8000afc ) 8000ae8: f7ff fd34 bl 8000554 8000aec: 4603 mov r3, r0 8000aee: 71fb strb r3, [r7, #7] /*!< Return the shifted data */ return Data; 8000af0: 79fb ldrb r3, [r7, #7] } 8000af2: 4618 mov r0, r3 8000af4: 3708 adds r7, #8 8000af6: 46bd mov sp, r7 8000af8: bd80 pop {r7, pc} 8000afa: bf00 nop 8000afc: 40013000 .word 0x40013000 08000b00 : uint8_t SD_GetDataResponse(void) { 8000b00: b580 push {r7, lr} 8000b02: b082 sub sp, #8 8000b04: af00 add r7, sp, #0 uint32_t i = 0; 8000b06: 2300 movs r3, #0 8000b08: 607b str r3, [r7, #4] uint8_t response, rvalue; while (i <= 64) 8000b0a: e01e b.n 8000b4a { /*!< Read resonse */ response = SD_ReadByte(); 8000b0c: f7ff ffd2 bl 8000ab4 8000b10: 4603 mov r3, r0 8000b12: 70fb strb r3, [r7, #3] /*!< Mask unused bits */ response &= 0x1F; 8000b14: 78fb ldrb r3, [r7, #3] 8000b16: f003 031f and.w r3, r3, #31 8000b1a: 70fb strb r3, [r7, #3] switch (response) 8000b1c: 78fb ldrb r3, [r7, #3] 8000b1e: 2b0b cmp r3, #11 8000b20: d006 beq.n 8000b30 8000b22: 2b0d cmp r3, #13 8000b24: d006 beq.n 8000b34 8000b26: 2b05 cmp r3, #5 8000b28: d106 bne.n 8000b38 { case SD_DATA_OK: { rvalue = SD_DATA_OK; 8000b2a: 2305 movs r3, #5 8000b2c: 70bb strb r3, [r7, #2] break; 8000b2e: e006 b.n 8000b3e } case SD_DATA_CRC_ERROR: return SD_DATA_CRC_ERROR; 8000b30: 230b movs r3, #11 8000b32: e016 b.n 8000b62 case SD_DATA_WRITE_ERROR: return SD_DATA_WRITE_ERROR; 8000b34: 230d movs r3, #13 8000b36: e014 b.n 8000b62 default: { rvalue = SD_DATA_OTHER_ERROR; 8000b38: 23ff movs r3, #255 ; 0xff 8000b3a: 70bb strb r3, [r7, #2] break; 8000b3c: bf00 nop } } /*!< Exit loop in case of data ok */ if (rvalue == SD_DATA_OK) 8000b3e: 78bb ldrb r3, [r7, #2] 8000b40: 2b05 cmp r3, #5 8000b42: d006 beq.n 8000b52 break; /*!< Increment loop counter */ i++; 8000b44: 687b ldr r3, [r7, #4] 8000b46: 3301 adds r3, #1 8000b48: 607b str r3, [r7, #4] uint8_t SD_GetDataResponse(void) { uint32_t i = 0; uint8_t response, rvalue; while (i <= 64) 8000b4a: 687b ldr r3, [r7, #4] 8000b4c: 2b40 cmp r3, #64 ; 0x40 8000b4e: d9dd bls.n 8000b0c 8000b50: e000 b.n 8000b54 break; } } /*!< Exit loop in case of data ok */ if (rvalue == SD_DATA_OK) break; 8000b52: bf00 nop /*!< Increment loop counter */ i++; } /*!< Wait null data */ while (SD_ReadByte() == 0); 8000b54: bf00 nop 8000b56: f7ff ffad bl 8000ab4 8000b5a: 4603 mov r3, r0 8000b5c: 2b00 cmp r3, #0 8000b5e: d0fa beq.n 8000b56 /*!< Return response */ return response; 8000b60: 78fb ldrb r3, [r7, #3] } 8000b62: 4618 mov r0, r3 8000b64: 3708 adds r7, #8 8000b66: 46bd mov sp, r7 8000b68: bd80 pop {r7, pc} 8000b6a: bf00 nop 08000b6c : SD_Error SD_Init(void) { 8000b6c: b580 push {r7, lr} 8000b6e: b082 sub sp, #8 8000b70: af00 add r7, sp, #0 uint32_t i = 0; 8000b72: 2300 movs r3, #0 8000b74: 607b str r3, [r7, #4] /*!< Initialize SD_SPI */ SD_LowLevel_Init(); 8000b76: f7ff fec9 bl 800090c /*!< SD chip select high */ SD_CS_HIGH(); 8000b7a: 2110 movs r1, #16 8000b7c: 480a ldr r0, [pc, #40] ; (8000ba8 ) 8000b7e: f7ff fe3b bl 80007f8 /*!< Send dummy byte 0xFF, 10 times with CS high */ /*!< Rise CS and MOSI for 80 clocks cycles */ for (i = 0; i <= 9; i++) 8000b82: 2300 movs r3, #0 8000b84: 607b str r3, [r7, #4] 8000b86: e005 b.n 8000b94 { /*!< Send dummy byte 0xFF */ SD_WriteByte(SD_DUMMY_BYTE); 8000b88: 20ff movs r0, #255 ; 0xff 8000b8a: f7ff fcef bl 800056c /*!< SD chip select high */ SD_CS_HIGH(); /*!< Send dummy byte 0xFF, 10 times with CS high */ /*!< Rise CS and MOSI for 80 clocks cycles */ for (i = 0; i <= 9; i++) 8000b8e: 687b ldr r3, [r7, #4] 8000b90: 3301 adds r3, #1 8000b92: 607b str r3, [r7, #4] 8000b94: 687b ldr r3, [r7, #4] 8000b96: 2b09 cmp r3, #9 8000b98: d9f6 bls.n 8000b88 /*!< Send dummy byte 0xFF */ SD_WriteByte(SD_DUMMY_BYTE); } /*------------Put SD in SPI mode--------------*/ /*!< SD initialized and set to SPI mode properly */ return (SD_GoIdleState()); 8000b9a: f7ff feff bl 800099c 8000b9e: 4603 mov r3, r0 } 8000ba0: 4618 mov r0, r3 8000ba2: 3708 adds r7, #8 8000ba4: 46bd mov sp, r7 8000ba6: bd80 pop {r7, pc} 8000ba8: 40010800 .word 0x40010800 08000bac <_checkSDStatus>: uint8_t _checkSDStatus() { 8000bac: b580 push {r7, lr} 8000bae: af00 add r7, sp, #0 if (SD_Status == SD_RESPONSE_NO_ERROR) 8000bb0: 4b09 ldr r3, [pc, #36] ; (8000bd8 <_checkSDStatus+0x2c>) 8000bb2: 881b ldrh r3, [r3, #0] 8000bb4: 2b00 cmp r3, #0 8000bb6: d101 bne.n 8000bbc <_checkSDStatus+0x10> return 0; 8000bb8: 2300 movs r3, #0 8000bba: e00a b.n 8000bd2 <_checkSDStatus+0x26> do SD_Status = SD_Init(); 8000bbc: f7ff ffd6 bl 8000b6c 8000bc0: 4603 mov r3, r0 8000bc2: b29a uxth r2, r3 8000bc4: 4b04 ldr r3, [pc, #16] ; (8000bd8 <_checkSDStatus+0x2c>) 8000bc6: 801a strh r2, [r3, #0] while (SD_Status != SD_RESPONSE_NO_ERROR); 8000bc8: 4b03 ldr r3, [pc, #12] ; (8000bd8 <_checkSDStatus+0x2c>) 8000bca: 881b ldrh r3, [r3, #0] 8000bcc: 2b00 cmp r3, #0 8000bce: d1f5 bne.n 8000bbc <_checkSDStatus+0x10> return 1; 8000bd0: 2301 movs r3, #1 } 8000bd2: 4618 mov r0, r3 8000bd4: bd80 pop {r7, pc} 8000bd6: bf00 nop 8000bd8: 20000018 .word 0x20000018 08000bdc : void checkSDStatus() { 8000bdc: b580 push {r7, lr} 8000bde: af00 add r7, sp, #0 while (_checkSDStatus()) { 8000be0: bf00 nop 8000be2: f7ff ffe3 bl 8000bac <_checkSDStatus> 8000be6: 4603 mov r3, r0 8000be8: 2b00 cmp r3, #0 8000bea: d1fa bne.n 8000be2 //<----><------>writeBufFilled = 0; //<----><------>SDWriteOffset = SD_WriteHeaders(); } } 8000bec: bf00 nop 8000bee: bd80 pop {r7, pc} 08000bf0 : uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) { 8000bf0: b480 push {r7} 8000bf2: b083 sub sp, #12 8000bf4: af00 add r7, sp, #0 8000bf6: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Return the selected ADC conversion value */ return (uint16_t) ADCx->DR; 8000bf8: 687b ldr r3, [r7, #4] 8000bfa: 6cdb ldr r3, [r3, #76] ; 0x4c 8000bfc: b29b uxth r3, r3 } 8000bfe: 4618 mov r0, r3 8000c00: 370c adds r7, #12 8000c02: 46bd mov sp, r7 8000c04: bc80 pop {r7} 8000c06: 4770 bx lr 08000c08 : SD_Error SD_WriteBlock_1(uint32_t WriteAddr) { 8000c08: b580 push {r7, lr} 8000c0a: b084 sub sp, #16 8000c0c: af00 add r7, sp, #0 8000c0e: 6078 str r0, [r7, #4] Wstatus = BuffReady; 8000c10: 4b3b ldr r3, [pc, #236] ; (8000d00 ) 8000c12: 781a ldrb r2, [r3, #0] 8000c14: 4b3b ldr r3, [pc, #236] ; (8000d04 ) 8000c16: 701a strb r2, [r3, #0] BuffReady = 0; 8000c18: 4b39 ldr r3, [pc, #228] ; (8000d00 ) 8000c1a: 2200 movs r2, #0 8000c1c: 701a strb r2, [r3, #0] uint32_t i = 0; 8000c1e: 2300 movs r3, #0 8000c20: 60fb str r3, [r7, #12] SD_Error rvalue = SD_RESPONSE_FAILURE; 8000c22: 23ff movs r3, #255 ; 0xff 8000c24: 72fb strb r3, [r7, #11] SD_CS_LOW(); 8000c26: 2110 movs r1, #16 8000c28: 4837 ldr r0, [pc, #220] ; (8000d08 ) 8000c2a: f7ff fe11 bl 8000850 SD_SendCmd(SD_CMD_WRITE_SINGLE_BLOCK, WriteAddr, 0xFF); 8000c2e: 22ff movs r2, #255 ; 0xff 8000c30: 6879 ldr r1, [r7, #4] 8000c32: 2018 movs r0, #24 8000c34: f7ff fee8 bl 8000a08 if (!SD_GetResponse(SD_RESPONSE_NO_ERROR)) 8000c38: 2000 movs r0, #0 8000c3a: f7ff ff1b bl 8000a74 8000c3e: 4603 mov r3, r0 8000c40: 2b00 cmp r3, #0 8000c42: d14e bne.n 8000ce2 { SD_WriteByte(SD_DUMMY_BYTE); 8000c44: 20ff movs r0, #255 ; 0xff 8000c46: f7ff fc91 bl 800056c SD_WriteByte(0xFE); 8000c4a: 20fe movs r0, #254 ; 0xfe 8000c4c: f7ff fc8e bl 800056c if (Wstatus == 1){ 8000c50: 4b2c ldr r3, [pc, #176] ; (8000d04 ) 8000c52: 781b ldrb r3, [r3, #0] 8000c54: 2b01 cmp r3, #1 8000c56: d11a bne.n 8000c8e for (i = 0; i < SD_BUFSIZE/2; i += 1) 8000c58: 2300 movs r3, #0 8000c5a: 60fb str r3, [r7, #12] 8000c5c: e014 b.n 8000c88 { SD_WriteByte(Buffer1[i]); 8000c5e: 4a2b ldr r2, [pc, #172] ; (8000d0c ) 8000c60: 68fb ldr r3, [r7, #12] 8000c62: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8000c66: b2db uxtb r3, r3 8000c68: 4618 mov r0, r3 8000c6a: f7ff fc7f bl 800056c SD_WriteByte(Buffer1[i] >> 8); 8000c6e: 4a27 ldr r2, [pc, #156] ; (8000d0c ) 8000c70: 68fb ldr r3, [r7, #12] 8000c72: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8000c76: 0a1b lsrs r3, r3, #8 8000c78: b29b uxth r3, r3 8000c7a: b2db uxtb r3, r3 8000c7c: 4618 mov r0, r3 8000c7e: f7ff fc75 bl 800056c if (!SD_GetResponse(SD_RESPONSE_NO_ERROR)) { SD_WriteByte(SD_DUMMY_BYTE); SD_WriteByte(0xFE); if (Wstatus == 1){ for (i = 0; i < SD_BUFSIZE/2; i += 1) 8000c82: 68fb ldr r3, [r7, #12] 8000c84: 3301 adds r3, #1 8000c86: 60fb str r3, [r7, #12] 8000c88: 68fb ldr r3, [r7, #12] 8000c8a: 2bff cmp r3, #255 ; 0xff 8000c8c: d9e7 bls.n 8000c5e SD_WriteByte(Buffer1[i]); SD_WriteByte(Buffer1[i] >> 8); } } if (Wstatus == 2){ 8000c8e: 4b1d ldr r3, [pc, #116] ; (8000d04 ) 8000c90: 781b ldrb r3, [r3, #0] 8000c92: 2b02 cmp r3, #2 8000c94: d11a bne.n 8000ccc for (i = 0; i < SD_BUFSIZE/2; i += 1) 8000c96: 2300 movs r3, #0 8000c98: 60fb str r3, [r7, #12] 8000c9a: e014 b.n 8000cc6 { SD_WriteByte(Buffer2[i]); 8000c9c: 4a1c ldr r2, [pc, #112] ; (8000d10 ) 8000c9e: 68fb ldr r3, [r7, #12] 8000ca0: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8000ca4: b2db uxtb r3, r3 8000ca6: 4618 mov r0, r3 8000ca8: f7ff fc60 bl 800056c SD_WriteByte(Buffer2[i] >> 8); 8000cac: 4a18 ldr r2, [pc, #96] ; (8000d10 ) 8000cae: 68fb ldr r3, [r7, #12] 8000cb0: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8000cb4: 0a1b lsrs r3, r3, #8 8000cb6: b29b uxth r3, r3 8000cb8: b2db uxtb r3, r3 8000cba: 4618 mov r0, r3 8000cbc: f7ff fc56 bl 800056c SD_WriteByte(Buffer1[i] >> 8); } } if (Wstatus == 2){ for (i = 0; i < SD_BUFSIZE/2; i += 1) 8000cc0: 68fb ldr r3, [r7, #12] 8000cc2: 3301 adds r3, #1 8000cc4: 60fb str r3, [r7, #12] 8000cc6: 68fb ldr r3, [r7, #12] 8000cc8: 2bff cmp r3, #255 ; 0xff 8000cca: d9e7 bls.n 8000c9c SD_WriteByte(Buffer2[i]); SD_WriteByte(Buffer2[i] >> 8); } } SD_ReadByte(); 8000ccc: f7ff fef2 bl 8000ab4 SD_ReadByte(); 8000cd0: f7ff fef0 bl 8000ab4 if (SD_GetDataResponse() == SD_DATA_OK) 8000cd4: f7ff ff14 bl 8000b00 8000cd8: 4603 mov r3, r0 8000cda: 2b05 cmp r3, #5 8000cdc: d101 bne.n 8000ce2 { rvalue = SD_RESPONSE_NO_ERROR; 8000cde: 2300 movs r3, #0 8000ce0: 72fb strb r3, [r7, #11] } } SD_CS_HIGH(); 8000ce2: 2110 movs r1, #16 8000ce4: 4808 ldr r0, [pc, #32] ; (8000d08 ) 8000ce6: f7ff fd87 bl 80007f8 SD_WriteByte(SD_DUMMY_BYTE); 8000cea: 20ff movs r0, #255 ; 0xff 8000cec: f7ff fc3e bl 800056c Wstatus = 0; 8000cf0: 4b04 ldr r3, [pc, #16] ; (8000d04 ) 8000cf2: 2200 movs r2, #0 8000cf4: 701a strb r2, [r3, #0] return rvalue; 8000cf6: 7afb ldrb r3, [r7, #11] } 8000cf8: 4618 mov r0, r3 8000cfa: 3710 adds r7, #16 8000cfc: 46bd mov sp, r7 8000cfe: bd80 pop {r7, pc} 8000d00: 20000630 .word 0x20000630 8000d04: 2000001b .word 0x2000001b 8000d08: 40010800 .word 0x40010800 8000d0c: 20000230 .word 0x20000230 8000d10: 20000430 .word 0x20000430 08000d14 : void ADC_Start (void){ 8000d14: b580 push {r7, lr} 8000d16: b086 sub sp, #24 8000d18: af00 add r7, sp, #0 ADC_InitTypeDef ADC_InitStructure; GPIO_InitTypeDef GPIO_InitStructure; RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE); 8000d1a: 2101 movs r1, #1 8000d1c: f44f 7000 mov.w r0, #512 ; 0x200 8000d20: f7ff fd78 bl 8000814 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 ; 8000d24: 2301 movs r3, #1 8000d26: 803b strh r3, [r7, #0] GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN; 8000d28: 2300 movs r3, #0 8000d2a: 70fb strb r3, [r7, #3] GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz ; 8000d2c: 2302 movs r3, #2 8000d2e: 70bb strb r3, [r7, #2] GPIO_Init(GPIOA, &GPIO_InitStructure); 8000d30: 463b mov r3, r7 8000d32: 4619 mov r1, r3 8000d34: 481a ldr r0, [pc, #104] ; (8000da0 ) 8000d36: f7ff fc3f bl 80005b8 ADC_InitStructure.ADC_Mode = ADC_Mode_Independent; 8000d3a: 2300 movs r3, #0 8000d3c: 607b str r3, [r7, #4] ADC_InitStructure.ADC_ScanConvMode = ENABLE; 8000d3e: 2301 movs r3, #1 8000d40: 723b strb r3, [r7, #8] ADC_InitStructure.ADC_ContinuousConvMode = ENABLE; 8000d42: 2301 movs r3, #1 8000d44: 727b strb r3, [r7, #9] ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None; 8000d46: f44f 2360 mov.w r3, #917504 ; 0xe0000 8000d4a: 60fb str r3, [r7, #12] ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; 8000d4c: 2300 movs r3, #0 8000d4e: 613b str r3, [r7, #16] ADC_InitStructure.ADC_NbrOfChannel = 0; 8000d50: 2300 movs r3, #0 8000d52: 753b strb r3, [r7, #20] ADC_Init(ADC1, &ADC_InitStructure); 8000d54: 1d3b adds r3, r7, #4 8000d56: 4619 mov r1, r3 8000d58: 4812 ldr r0, [pc, #72] ; (8000da4 ) 8000d5a: f7ff fd87 bl 800086c ADC_Cmd(ADC1, ENABLE); 8000d5e: 2101 movs r1, #1 8000d60: 4810 ldr r0, [pc, #64] ; (8000da4 ) 8000d62: f7ff fb45 bl 80003f0 ADC_ResetCalibration(ADC1); 8000d66: 480f ldr r0, [pc, #60] ; (8000da4 ) 8000d68: f7ff fb88 bl 800047c while(ADC_GetResetCalibrationStatus(ADC1)); 8000d6c: bf00 nop 8000d6e: 480d ldr r0, [pc, #52] ; (8000da4 ) 8000d70: f7ff fb94 bl 800049c 8000d74: 4603 mov r3, r0 8000d76: 2b00 cmp r3, #0 8000d78: d1f9 bne.n 8000d6e ADC_StartCalibration(ADC1); 8000d7a: 480a ldr r0, [pc, #40] ; (8000da4 ) 8000d7c: f7ff fba6 bl 80004cc while(ADC_GetCalibrationStatus(ADC1)); 8000d80: bf00 nop 8000d82: 4808 ldr r0, [pc, #32] ; (8000da4 ) 8000d84: f7ff fbb2 bl 80004ec 8000d88: 4603 mov r3, r0 8000d8a: 2b00 cmp r3, #0 8000d8c: d1f9 bne.n 8000d82 ADC_SoftwareStartConvCmd(ADC1, ENABLE); 8000d8e: 2101 movs r1, #1 8000d90: 4804 ldr r0, [pc, #16] ; (8000da4 ) 8000d92: f7ff fbc3 bl 800051c } 8000d96: bf00 nop 8000d98: 3718 adds r7, #24 8000d9a: 46bd mov sp, r7 8000d9c: bd80 pop {r7, pc} 8000d9e: bf00 nop 8000da0: 40010800 .word 0x40010800 8000da4: 40012400 .word 0x40012400 08000da8
: int main(void) { 8000da8: b580 push {r7, lr} 8000daa: af00 add r7, sp, #0 // status = SD_Init(); // checkSDStatus(); // writeBufFilled = 0; //// SD_WriteHeaders(); // SDWriteOffset = SD_BUFSIZE; SystemCoreClockUpdate(); 8000dac: f7ff fa2e bl 800020c SysTick_Config(SystemCoreClock/10); 8000db0: 4b05 ldr r3, [pc, #20] ; (8000dc8 ) 8000db2: 681b ldr r3, [r3, #0] 8000db4: 4a05 ldr r2, [pc, #20] ; (8000dcc ) 8000db6: fba2 2303 umull r2, r3, r2, r3 8000dba: 08db lsrs r3, r3, #3 8000dbc: 4618 mov r0, r3 8000dbe: f7ff f9cf bl 8000160 ADC_Start(); 8000dc2: f7ff ffa7 bl 8000d14 // SDWriteOffset = SDWriteOffset + SD_BUFSIZE; // } } 8000dc6: e7fe b.n 8000dc6 8000dc8: 20000000 .word 0x20000000 8000dcc: cccccccd .word 0xcccccccd 08000dd0 : } void SysTick_Handler(void) { 8000dd0: b580 push {r7, lr} 8000dd2: af00 add r7, sp, #0 ADC1ConvertedValue = ADC_GetConversionValue(ADC1); 8000dd4: 4804 ldr r0, [pc, #16] ; (8000de8 ) 8000dd6: f7ff ff0b bl 8000bf0 8000dda: 4603 mov r3, r0 8000ddc: 461a mov r2, r3 8000dde: 4b03 ldr r3, [pc, #12] ; (8000dec ) 8000de0: 801a strh r2, [r3, #0] BuffReady = 2; BuffCount = 0; } */ } 8000de2: bf00 nop 8000de4: bd80 pop {r7, pc} 8000de6: bf00 nop 8000de8: 40012400 .word 0x40012400 8000dec: 2000022c .word 0x2000022c 8000df0: 08000e4c .word 0x08000e4c 8000df4: 20000000 .word 0x20000000 8000df8: 2000001c .word 0x2000001c 8000dfc: 2000001c .word 0x2000001c 8000e00: 20000638 .word 0x20000638 08000e04 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 8000e04: 2100 movs r1, #0 b LoopCopyDataInit 8000e06: e003 b.n 8000e10 08000e08 : CopyDataInit: ldr r3, =_sidata 8000e08: 4b0a ldr r3, [pc, #40] ; (8000e34 ) ldr r3, [r3, r1] 8000e0a: 585b ldr r3, [r3, r1] str r3, [r0, r1] 8000e0c: 5043 str r3, [r0, r1] adds r1, r1, #4 8000e0e: 3104 adds r1, #4 08000e10 : LoopCopyDataInit: ldr r0, =_sdata 8000e10: 4809 ldr r0, [pc, #36] ; (8000e38 ) ldr r3, =_edata 8000e12: 4b0a ldr r3, [pc, #40] ; (8000e3c ) adds r2, r0, r1 8000e14: 1842 adds r2, r0, r1 cmp r2, r3 8000e16: 429a cmp r2, r3 bcc CopyDataInit 8000e18: d3f6 bcc.n 8000e08 ldr r2, =_sbss 8000e1a: 4a09 ldr r2, [pc, #36] ; (8000e40 ) b LoopFillZerobss 8000e1c: e002 b.n 8000e24 08000e1e : /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 8000e1e: 2300 movs r3, #0 str r3, [r2], #4 8000e20: f842 3b04 str.w r3, [r2], #4 08000e24 : LoopFillZerobss: ldr r3, = _ebss 8000e24: 4b07 ldr r3, [pc, #28] ; (8000e44 ) cmp r2, r3 8000e26: 429a cmp r2, r3 bcc FillZerobss 8000e28: d3f9 bcc.n 8000e1e /* Call the clock system intitialization function.*/ bl SystemInit 8000e2a: f7ff f9bb bl 80001a4 /* Call the application's entry point.*/ bl main 8000e2e: f7ff ffbb bl 8000da8
bx lr 8000e32: 4770 bx lr /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 b LoopCopyDataInit CopyDataInit: ldr r3, =_sidata 8000e34: 08000e4c .word 0x08000e4c ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: ldr r0, =_sdata 8000e38: 20000000 .word 0x20000000 ldr r3, =_edata 8000e3c: 2000001c .word 0x2000001c adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit ldr r2, =_sbss 8000e40: 2000001c .word 0x2000001c FillZerobss: movs r3, #0 str r3, [r2], #4 LoopFillZerobss: ldr r3, = _ebss 8000e44: 20000638 .word 0x20000638 08000e48 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8000e48: e7fe b.n 8000e48 ...