Sine_logger/eagle/Sine_Logger/cpu.s#1

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<wire x1="5.08" y1="-10.16" x2="-5.08" y2="-10.16" width="0.254" layer="94"/>
<text x="-5.08" y="12.7" size="1.27" layer="95">&gt;NAME</text>
<pin name="PB0" x="10.16" y="10.16" length="middle" rot="R180"/>
<pin name="PB1" x="10.16" y="7.62" length="middle" rot="R180"/>
<pin name="PB2" x="10.16" y="5.08" length="middle" rot="R180"/>
<pin name="PB3" x="10.16" y="2.54" length="middle" rot="R180"/>
<pin name="PB4" x="10.16" y="0" length="middle" rot="R180"/>
<pin name="PB5" x="10.16" y="-2.54" length="middle" rot="R180"/>
<pin name="PB6" x="10.16" y="-5.08" length="middle" rot="R180"/>
<pin name="PB7" x="10.16" y="-7.62" length="middle" rot="R180"/>
</symbol>
<symbol name="PORT_B_H">
<wire x1="-5.08" y1="10.16" x2="5.08" y2="10.16" width="0.254" layer="94"/>
<wire x1="5.08" y1="10.16" x2="5.08" y2="-12.7" width="0.254" layer="94"/>
<wire x1="5.08" y1="-12.7" x2="-5.08" y2="-12.7" width="0.254" layer="94"/>
<text x="-5.08" y="10.16" size="1.27" layer="95">&gt;NAME</text>
<pin name="PB8" x="10.16" y="7.62" length="middle" rot="R180"/>
<pin name="PB9" x="10.16" y="5.08" length="middle" rot="R180"/>
<pin name="PB10" x="10.16" y="2.54" length="middle" rot="R180"/>
<pin name="PB11" x="10.16" y="0" length="middle" rot="R180"/>
<pin name="PB12" x="10.16" y="-2.54" length="middle" rot="R180"/>
<pin name="PB13" x="10.16" y="-5.08" length="middle" rot="R180"/>
<pin name="PB14" x="10.16" y="-7.62" length="middle" rot="R180"/>
<pin name="PB15" x="10.16" y="-10.16" length="middle" rot="R180"/>
</symbol>
<symbol name="PORT_C_L">
<wire x1="5.08" y1="12.7" x2="-5.08" y2="12.7" width="0.254" layer="94"/>
<wire x1="-5.08" y1="12.7" x2="-5.08" y2="-10.16" width="0.254" layer="94"/>
<wire x1="-5.08" y1="-10.16" x2="5.08" y2="-10.16" width="0.254" layer="94"/>
<text x="-5.08" y="12.7" size="1.27" layer="95">&gt;NAME</text>
<pin name="PC0" x="-10.16" y="10.16" length="middle"/>
<pin name="PC1" x="-10.16" y="7.62" length="middle"/>
<pin name="PC2" x="-10.16" y="5.08" length="middle"/>
<pin name="PC3" x="-10.16" y="2.54" length="middle"/>
<pin name="PC4" x="-10.16" y="0" length="middle"/>
<pin name="PC5" x="-10.16" y="-2.54" length="middle"/>
<pin name="PC6" x="-10.16" y="-5.08" length="middle"/>
<pin name="PC7" x="-10.16" y="-7.62" length="middle"/>
</symbol>
<symbol name="PORT_C_H">
<wire x1="5.08" y1="10.16" x2="-5.08" y2="10.16" width="0.254" layer="94"/>
<wire x1="-5.08" y1="10.16" x2="-5.08" y2="-12.7" width="0.254" layer="94"/>
<wire x1="-5.08" y1="-12.7" x2="5.08" y2="-12.7" width="0.254" layer="94"/>
<text x="-5.08" y="10.16" size="1.27" layer="95">&gt;NAME</text>
<pin name="PC13" x="-10.16" y="-5.08" length="middle"/>
<pin name="PC14" x="-10.16" y="-7.62" length="middle"/>
<pin name="PC15" x="-10.16" y="-10.16" length="middle"/>
<pin name="PC8" x="-10.16" y="7.62" length="middle"/>
<pin name="PC9" x="-10.16" y="5.08" length="middle"/>
<pin name="PC10" x="-10.16" y="2.54" length="middle"/>
<pin name="PC11" x="-10.16" y="0" length="middle"/>
<pin name="PC12" x="-10.16" y="-2.54" length="middle"/>
</symbol>
<symbol name="VCC_VDD_M">
<wire x1="5.08" y1="22.86" x2="-5.08" y2="22.86" width="0.254" layer="94"/>
<wire x1="-5.08" y1="-22.86" x2="5.08" y2="-22.86" width="0.254" layer="94"/>
<wire x1="-5.08" y1="22.86" x2="-5.08" y2="-22.86" width="0.254" layer="94"/>
<text x="-5.08" y="22.86" size="1.27" layer="95">&gt;NAME</text>
<pin name="VDD_1" x="-10.16" y="20.32" length="middle" direction="pwr"/>
<pin name="VDD_2" x="-10.16" y="15.24" length="middle" direction="pwr"/>
<pin name="VDD_3" x="-10.16" y="10.16" length="middle" direction="pwr"/>
<pin name="VSS_1" x="-10.16" y="-5.08" length="middle" direction="pwr"/>
<pin name="VSS_2" x="-10.16" y="-10.16" length="middle" direction="pwr"/>
<pin name="VSS_3" x="-10.16" y="-15.24" length="middle" direction="pwr"/>
<pin name="VDD_4" x="-10.16" y="5.08" length="middle" direction="pwr"/>
<pin name="VSS_4" x="-10.16" y="-20.32" length="middle" direction="pwr"/>
</symbol>
<symbol name="PORT_D_3">
<wire x1="-5.08" y1="5.08" x2="5.08" y2="5.08" width="0.254" layer="94"/>
<wire x1="5.08" y1="5.08" x2="5.08" y2="-5.08" width="0.254" layer="94"/>
<wire x1="5.08" y1="-5.08" x2="-5.08" y2="-5.08" width="0.254" layer="94"/>
<text x="-5.08" y="5.08" size="1.27" layer="95">&gt;NAME</text>
<pin name="PD0/OSC&lt;=" x="10.16" y="2.54" length="middle" rot="R180"/>
<pin name="PD1/OSC=&gt;" x="10.16" y="0" length="middle" rot="R180"/>
<pin name="PD2" x="10.16" y="-2.54" length="middle" rot="R180"/>
</symbol>
<symbol name="BAT_AN_M">
<wire x1="-5.08" y1="7.62" x2="5.08" y2="7.62" width="0.254" layer="94"/>
<wire x1="5.08" y1="7.62" x2="5.08" y2="-7.62" width="0.254" layer="94"/>
<wire x1="5.08" y1="-7.62" x2="-5.08" y2="-7.62" width="0.254" layer="94"/>
<text x="-5.08" y="7.62" size="1.27" layer="95">&gt;NAME</text>
<pin name="VBAT" x="10.16" y="5.08" length="middle" direction="pwr" rot="R180"/>
<pin name="VSSA" x="10.16" y="0" length="middle" direction="pwr" rot="R180"/>
<pin name="VDDA" x="10.16" y="-5.08" length="middle" direction="pwr" rot="R180"/>
</symbol>
<symbol name="BOOT_RST">
<wire x1="-5.08" y1="5.08" x2="5.08" y2="5.08" width="0.254" layer="94"/>
<wire x1="5.08" y1="5.08" x2="5.08" y2="-5.08" width="0.254" layer="94"/>
<wire x1="5.08" y1="-5.08" x2="-5.08" y2="-5.08" width="0.254" layer="94"/>
<text x="-5.08" y="-7.62" size="1.27" layer="95">&gt;VALUE</text>
<text x="-5.08" y="5.08" size="1.27" layer="95">&gt;NAME</text>
<pin name="NRST" x="10.16" y="2.54" length="middle" direction="in" function="dot" rot="R180"/>
<pin name="BOOT0" x="10.16" y="-2.54" length="middle" direction="in" rot="R180"/>
</symbol>
</symbols>
<devicesets>
<deviceset name="STM32F10XRXT6" prefix="U">
<description>STM32F101/103 64pin LQFP</description>
<gates>
<gate name="PORTA_L" symbol="PORT_A_L" x="-15.24" y="45.72"/>
<gate name="PORTA_H" symbol="PORT_A_H" x="-15.24" y="17.78"/>
<gate name="PORTB_L" symbol="PORT_B_L" x="7.62" y="43.18"/>
<gate name="PORTB_H" symbol="PORT_B_H" x="7.62" y="20.32"/>
<gate name="PORTC_L" symbol="PORT_C_L" x="-12.7" y="-7.62"/>
<gate name="PORTC_H" symbol="PORT_C_H" x="-12.7" y="-30.48"/>
<gate name="POWER" symbol="VCC_VDD_M" x="-12.7" y="-68.58"/>
<gate name="PORTD/OSC" symbol="PORT_D_3" x="7.62" y="0"/>
<gate name="AN_POWER" symbol="BAT_AN_M" x="7.62" y="-15.24"/>
<gate name="RESET" symbol="BOOT_RST" x="7.62" y="-30.48"/>
</gates>
<devices>
<device name="" package="TQFP64">
<connects>
<connect gate="AN_POWER" pin="VBAT" pad="1"/>
<connect gate="AN_POWER" pin="VDDA" pad="13"/>
<connect gate="AN_POWER" pin="VSSA" pad="12"/>
<connect gate="PORTA_H" pin="PA10" pad="43"/>
<connect gate="PORTA_H" pin="PA11" pad="44"/>
<connect gate="PORTA_H" pin="PA12" pad="45"/>
<connect gate="PORTA_H" pin="PA13" pad="46"/>
<connect gate="PORTA_H" pin="PA14" pad="49"/>
<connect gate="PORTA_H" pin="PA15" pad="50"/>
<connect gate="PORTA_H" pin="PA8" pad="41"/>
<connect gate="PORTA_H" pin="PA9" pad="42"/>
<connect gate="PORTA_L" pin="PA0" pad="14"/>
<connect gate="PORTA_L" pin="PA1" pad="15"/>
<connect gate="PORTA_L" pin="PA2" pad="16"/>
<connect gate="PORTA_L" pin="PA3" pad="17"/>
<connect gate="PORTA_L" pin="PA4" pad="20"/>
<connect gate="PORTA_L" pin="PA5" pad="21"/>
<connect gate="PORTA_L" pin="PA6" pad="22"/>
<connect gate="PORTA_L" pin="PA7" pad="23"/>
<connect gate="PORTB_H" pin="PB10" pad="29"/>
<connect gate="PORTB_H" pin="PB11" pad="30"/>
<connect gate="PORTB_H" pin="PB12" pad="33"/>
<connect gate="PORTB_H" pin="PB13" pad="34"/>
<connect gate="PORTB_H" pin="PB14" pad="35"/>
<connect gate="PORTB_H" pin="PB15" pad="36"/>
<connect gate="PORTB_H" pin="PB8" pad="61"/>
<connect gate="PORTB_H" pin="PB9" pad="62"/>
<connect gate="PORTB_L" pin="PB0" pad="26"/>
<connect gate="PORTB_L" pin="PB1" pad="27"/>
<connect gate="PORTB_L" pin="PB2" pad="28"/>
<connect gate="PORTB_L" pin="PB3" pad="55"/>
<connect gate="PORTB_L" pin="PB4" pad="56"/>
<connect gate="PORTB_L" pin="PB5" pad="57"/>
<connect gate="PORTB_L" pin="PB6" pad="58"/>
<connect gate="PORTB_L" pin="PB7" pad="59"/>
<connect gate="PORTC_H" pin="PC10" pad="51"/>
<connect gate="PORTC_H" pin="PC11" pad="52"/>
<connect gate="PORTC_H" pin="PC12" pad="53"/>
<connect gate="PORTC_H" pin="PC13" pad="2"/>
<connect gate="PORTC_H" pin="PC14" pad="3"/>
<connect gate="PORTC_H" pin="PC15" pad="4"/>
<connect gate="PORTC_H" pin="PC8" pad="39"/>
<connect gate="PORTC_H" pin="PC9" pad="40"/>
<connect gate="PORTC_L" pin="PC0" pad="8"/>
<connect gate="PORTC_L" pin="PC1" pad="9"/>
<connect gate="PORTC_L" pin="PC2" pad="10"/>
<connect gate="PORTC_L" pin="PC3" pad="11"/>
<connect gate="PORTC_L" pin="PC4" pad="24"/>
<connect gate="PORTC_L" pin="PC5" pad="25"/>
<connect gate="PORTC_L" pin="PC6" pad="37"/>
<connect gate="PORTC_L" pin="PC7" pad="38"/>
<connect gate="PORTD/OSC" pin="PD0/OSC&lt;=" pad="5"/>
<connect gate="PORTD/OSC" pin="PD1/OSC=&gt;" pad="6"/>
<connect gate="PORTD/OSC" pin="PD2" pad="54"/>
<connect gate="POWER" pin="VDD_1" pad="32"/>
<connect gate="POWER" pin="VDD_2" pad="48"/>
<connect gate="POWER" pin="VDD_3" pad="64"/>
<connect gate="POWER" pin="VDD_4" pad="19"/>
<connect gate="POWER" pin="VSS_1" pad="31"/>
<connect gate="POWER" pin="VSS_2" pad="47"/>
<connect gate="POWER" pin="VSS_3" pad="63"/>
<connect gate="POWER" pin="VSS_4" pad="18"/>
<connect gate="RESET" pin="BOOT0" pad="60"/>
<connect gate="RESET" pin="NRST" pad="7"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
<library name="wirepad">
<description>&lt;b&gt;Single Pads&lt;/b&gt;&lt;p&gt;
&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
<packages>
<package name="SMD1,27-2,54">
<description>&lt;b&gt;SMD PAD&lt;/b&gt;</description>
<smd name="1" x="0" y="0" dx="1.27" dy="2.54" layer="1"/>
<text x="0" y="0" size="0.0254" layer="27">&gt;VALUE</text>
<text x="-0.8" y="-2.4" size="1.27" layer="25" rot="R90">&gt;NAME</text>
</package>
</packages>
<symbols>
<symbol name="PAD">
<wire x1="-1.016" y1="1.016" x2="1.016" y2="-1.016" width="0.254" layer="94"/>
<wire x1="-1.016" y1="-1.016" x2="1.016" y2="1.016" width="0.254" layer="94"/>
<text x="-1.143" y="1.8542" size="1.778" layer="95">&gt;NAME</text>
<text x="-1.143" y="-3.302" size="1.778" layer="96">&gt;VALUE</text>
<pin name="P" x="2.54" y="0" visible="off" length="short" direction="pas" rot="R180"/>
</symbol>
</symbols>
<devicesets>
<deviceset name="SMD2" prefix="PAD" uservalue="yes">
<description>&lt;b&gt;SMD PAD&lt;/b&gt;</description>
<gates>
<gate name="1" symbol="PAD" x="0" y="0"/>
</gates>
<devices>
<device name="" package="SMD1,27-2,54">
<connects>
<connect gate="1" pin="P" pad="1"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
</libraries>
<attributes>
</attributes>
<variantdefs>
</variantdefs>
<classes>
<class number="0" name="default" width="0" drill="0">
</class>
</classes>
<parts>
<part name="U1" library="stm32" deviceset="STM32F10XRXT6" device=""/>
<part name="PAD1" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD2" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD3" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD4" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD5" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD6" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD7" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD8" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD9" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD10" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD11" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD12" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD13" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD14" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD15" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD16" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD17" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD18" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD19" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD20" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD21" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD22" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD23" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD24" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD25" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD26" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD27" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD28" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD29" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD30" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD31" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD32" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD33" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD34" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD35" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD36" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD37" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD38" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD39" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD40" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD41" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD42" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD43" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD44" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD45" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD46" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD47" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD48" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD49" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD50" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD51" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD52" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD53" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD54" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD55" library="wirepad" deviceset="SMD2" device=""/>
<part name="PAD56" library="wirepad" deviceset="SMD2" device=""/>
</parts>
<sheets>
<sheet>
<plain>
</plain>
<instances>
<instance part="U1" gate="PORTA_L" x="68.58" y="60.96"/>
<instance part="U1" gate="PORTA_H" x="121.92" y="60.96"/>
<instance part="U1" gate="PORTB_L" x="99.06" y="25.4"/>
<instance part="U1" gate="PORTB_H" x="134.62" y="25.4"/>
<instance part="U1" gate="PORTC_L" x="38.1" y="33.02"/>
<instance part="U1" gate="PORTC_H" x="20.32" y="60.96"/>
<instance part="U1" gate="POWER" x="-5.08" y="50.8"/>
<instance part="U1" gate="PORTD/OSC" x="99.06" y="83.82"/>
<instance part="U1" gate="AN_POWER" x="-25.4" y="12.7"/>
<instance part="U1" gate="RESET" x="160.02" y="58.42"/>
<instance part="PAD1" gate="1" x="-20.32" y="71.12"/>
<instance part="PAD2" gate="1" x="-20.32" y="66.04"/>
<instance part="PAD3" gate="1" x="-20.32" y="60.96"/>
<instance part="PAD4" gate="1" x="-20.32" y="55.88"/>
<instance part="PAD5" gate="1" x="-20.32" y="45.72"/>
<instance part="PAD6" gate="1" x="-20.32" y="40.64"/>
<instance part="PAD7" gate="1" x="-20.32" y="35.56"/>
<instance part="PAD8" gate="1" x="-20.32" y="30.48"/>
<instance part="PAD9" gate="1" x="7.62" y="68.58"/>
<instance part="PAD10" gate="1" x="7.62" y="66.04"/>
<instance part="PAD11" gate="1" x="7.62" y="63.5"/>
<instance part="PAD12" gate="1" x="7.62" y="60.96"/>
<instance part="PAD13" gate="1" x="7.62" y="58.42"/>
<instance part="PAD14" gate="1" x="7.62" y="55.88"/>
<instance part="PAD15" gate="1" x="7.62" y="53.34"/>
<instance part="PAD16" gate="1" x="7.62" y="50.8"/>
<instance part="PAD17" gate="1" x="25.4" y="43.18"/>
<instance part="PAD18" gate="1" x="25.4" y="40.64"/>
<instance part="PAD19" gate="1" x="25.4" y="38.1"/>
<instance part="PAD20" gate="1" x="25.4" y="35.56"/>
<instance part="PAD21" gate="1" x="25.4" y="33.02"/>
<instance part="PAD22" gate="1" x="25.4" y="30.48"/>
<instance part="PAD23" gate="1" x="25.4" y="27.94"/>
<instance part="PAD24" gate="1" x="25.4" y="25.4"/>
<instance part="PAD25" gate="1" x="58.42" y="68.58"/>
<instance part="PAD26" gate="1" x="58.42" y="66.04"/>
<instance part="PAD27" gate="1" x="58.42" y="63.5"/>
<instance part="PAD28" gate="1" x="58.42" y="60.96"/>
<instance part="PAD29" gate="1" x="58.42" y="58.42"/>
<instance part="PAD30" gate="1" x="58.42" y="55.88"/>
<instance part="PAD31" gate="1" x="58.42" y="53.34"/>
<instance part="PAD32" gate="1" x="58.42" y="50.8"/>
<instance part="PAD33" gate="1" x="111.76" y="86.36" rot="R180"/>
<instance part="PAD34" gate="1" x="111.76" y="83.82" rot="R180"/>
<instance part="PAD35" gate="1" x="111.76" y="81.28" rot="R180"/>
<instance part="PAD36" gate="1" x="111.76" y="35.56" rot="R180"/>
<instance part="PAD37" gate="1" x="111.76" y="33.02" rot="R180"/>
<instance part="PAD38" gate="1" x="111.76" y="30.48" rot="R180"/>
<instance part="PAD39" gate="1" x="111.76" y="27.94" rot="R180"/>
<instance part="PAD40" gate="1" x="111.76" y="25.4" rot="R180"/>
<instance part="PAD41" gate="1" x="111.76" y="22.86" rot="R180"/>
<instance part="PAD42" gate="1" x="111.76" y="20.32" rot="R180"/>
<instance part="PAD43" gate="1" x="111.76" y="17.78" rot="R180"/>
<instance part="PAD44" gate="1" x="147.32" y="33.02" rot="R180"/>
<instance part="PAD45" gate="1" x="147.32" y="30.48" rot="R180"/>
<instance part="PAD46" gate="1" x="147.32" y="27.94" rot="R180"/>
<instance part="PAD47" gate="1" x="147.32" y="25.4" rot="R180"/>
<instance part="PAD48" gate="1" x="147.32" y="22.86" rot="R180"/>
<instance part="PAD49" gate="1" x="147.32" y="20.32" rot="R180"/>
<instance part="PAD50" gate="1" x="147.32" y="17.78" rot="R180"/>
<instance part="PAD51" gate="1" x="147.32" y="15.24" rot="R180"/>
<instance part="PAD52" gate="1" x="-5.08" y="17.78" rot="R180"/>
<instance part="PAD53" gate="1" x="-5.08" y="12.7" rot="R180"/>
<instance part="PAD54" gate="1" x="-7.62" y="7.62" rot="R180"/>
<instance part="PAD55" gate="1" x="172.72" y="60.96" rot="R180"/>
<instance part="PAD56" gate="1" x="172.72" y="55.88" rot="R180"/>
</instances>
<busses>
</busses>
<nets>
<net name="N$1" class="0">
<segment>
<pinref part="U1" gate="POWER" pin="VDD_1"/>
<pinref part="PAD1" gate="1" pin="P"/>
<pinref part="U1" gate="POWER" pin="VDD_2"/>
<pinref part="PAD2" gate="1" pin="P"/>
<wire x1="-17.78" y1="66.04" x2="-15.24" y2="66.04" width="0.1524" layer="91"/>
<wire x1="-17.78" y1="71.12" x2="-15.24" y2="71.12" width="0.1524" layer="91"/>
<wire x1="-15.24" y1="71.12" x2="-15.24" y2="66.04" width="0.1524" layer="91"/>
<junction x="-15.24" y="66.04"/>
<pinref part="U1" gate="POWER" pin="VDD_3"/>
<pinref part="PAD3" gate="1" pin="P"/>
<wire x1="-17.78" y1="60.96" x2="-15.24" y2="60.96" width="0.1524" layer="91"/>
<wire x1="-15.24" y1="66.04" x2="-15.24" y2="60.96" width="0.1524" layer="91"/>
<junction x="-15.24" y="60.96"/>
<pinref part="U1" gate="POWER" pin="VDD_4"/>
<pinref part="PAD4" gate="1" pin="P"/>
<wire x1="-17.78" y1="55.88" x2="-15.24" y2="55.88" width="0.1524" layer="91"/>
<wire x1="-15.24" y1="60.96" x2="-15.24" y2="55.88" width="0.1524" layer="91"/>
<junction x="-15.24" y="55.88"/>
<wire x1="-15.24" y1="55.88" x2="-15.24" y2="50.8" width="0.1524" layer="91"/>
<wire x1="-15.24" y1="50.8" x2="-22.86" y2="50.8" width="0.1524" layer="91"/>
<wire x1="-22.86" y1="50.8" x2="-22.86" y2="22.86" width="0.1524" layer="91"/>
<wire x1="-22.86" y1="22.86" x2="-10.16" y2="22.86" width="0.1524" layer="91"/>
<pinref part="U1" gate="AN_POWER" pin="VDDA"/>
<pinref part="PAD54" gate="1" pin="P"/>
<wire x1="-10.16" y1="7.62" x2="-15.24" y2="7.62" width="0.1524" layer="91"/>
<wire x1="-10.16" y1="22.86" x2="-10.16" y2="7.62" width="0.1524" layer="91"/>
<junction x="-10.16" y="7.62"/>
</segment>
</net>
<net name="N$5" class="0">
<segment>
<pinref part="U1" gate="POWER" pin="VSS_1"/>
<pinref part="PAD5" gate="1" pin="P"/>
<wire x1="-17.78" y1="45.72" x2="-15.24" y2="45.72" width="0.1524" layer="91"/>
<pinref part="U1" gate="POWER" pin="VSS_2"/>
<pinref part="PAD6" gate="1" pin="P"/>
<wire x1="-17.78" y1="40.64" x2="-15.24" y2="40.64" width="0.1524" layer="91"/>
<wire x1="-15.24" y1="45.72" x2="-15.24" y2="40.64" width="0.1524" layer="91"/>
<junction x="-15.24" y="45.72"/>
<junction x="-15.24" y="40.64"/>
<pinref part="U1" gate="POWER" pin="VSS_3"/>
<pinref part="PAD7" gate="1" pin="P"/>
<wire x1="-17.78" y1="35.56" x2="-15.24" y2="35.56" width="0.1524" layer="91"/>
<wire x1="-15.24" y1="40.64" x2="-15.24" y2="35.56" width="0.1524" layer="91"/>
<junction x="-15.24" y="35.56"/>
<pinref part="U1" gate="POWER" pin="VSS_4"/>
<pinref part="PAD8" gate="1" pin="P"/>
<wire x1="-17.78" y1="30.48" x2="-15.24" y2="30.48" width="0.1524" layer="91"/>
<wire x1="-15.24" y1="35.56" x2="-15.24" y2="30.48" width="0.1524" layer="91"/>
<junction x="-15.24" y="30.48"/>
<pinref part="U1" gate="AN_POWER" pin="VSSA"/>
<pinref part="PAD53" gate="1" pin="P"/>
<wire x1="-7.62" y1="12.7" x2="-15.24" y2="12.7" width="0.1524" layer="91"/>
<wire x1="-15.24" y1="30.48" x2="-15.24" y2="12.7" width="0.1524" layer="91"/>
<junction x="-15.24" y="12.7"/>
</segment>
</net>
<net name="N$9" class="0">
<segment>
<pinref part="U1" gate="PORTC_H" pin="PC8"/>
<pinref part="PAD9" gate="1" pin="P"/>
</segment>
</net>
<net name="N$10" class="0">
<segment>
<pinref part="U1" gate="PORTC_H" pin="PC9"/>
<pinref part="PAD10" gate="1" pin="P"/>
</segment>
</net>
<net name="N$11" class="0">
<segment>
<pinref part="U1" gate="PORTC_H" pin="PC10"/>
<pinref part="PAD11" gate="1" pin="P"/>
</segment>
</net>
<net name="N$12" class="0">
<segment>
<pinref part="U1" gate="PORTC_H" pin="PC11"/>
<pinref part="PAD12" gate="1" pin="P"/>
</segment>
</net>
<net name="N$13" class="0">
<segment>
<pinref part="U1" gate="PORTC_H" pin="PC12"/>
<pinref part="PAD13" gate="1" pin="P"/>
</segment>
</net>
<net name="N$14" class="0">
<segment>
<pinref part="U1" gate="PORTC_H" pin="PC13"/>
<pinref part="PAD14" gate="1" pin="P"/>
</segment>
</net>
<net name="N$15" class="0">
<segment>
<pinref part="U1" gate="PORTC_H" pin="PC14"/>
<pinref part="PAD15" gate="1" pin="P"/>
</segment>
</net>
<net name="N$16" class="0">
<segment>
<pinref part="U1" gate="PORTC_H" pin="PC15"/>
<pinref part="PAD16" gate="1" pin="P"/>
</segment>
</net>
<net name="N$17" class="0">
<segment>
<pinref part="U1" gate="PORTC_L" pin="PC0"/>
<pinref part="PAD17" gate="1" pin="P"/>
</segment>
</net>
<net name="N$18" class="0">
<segment>
<pinref part="U1" gate="PORTC_L" pin="PC1"/>
<pinref part="PAD18" gate="1" pin="P"/>
</segment>
</net>
<net name="N$19" class="0">
<segment>
<pinref part="U1" gate="PORTC_L" pin="PC2"/>
<pinref part="PAD19" gate="1" pin="P"/>
</segment>
</net>
<net name="N$20" class="0">
<segment>
<pinref part="U1" gate="PORTC_L" pin="PC3"/>
<pinref part="PAD20" gate="1" pin="P"/>
</segment>
</net>
<net name="N$21" class="0">
<segment>
<pinref part="U1" gate="PORTC_L" pin="PC4"/>
<pinref part="PAD21" gate="1" pin="P"/>
</segment>
</net>
<net name="N$22" class="0">
<segment>
<pinref part="U1" gate="PORTC_L" pin="PC5"/>
<pinref part="PAD22" gate="1" pin="P"/>
</segment>
</net>
<net name="N$23" class="0">
<segment>
<pinref part="U1" gate="PORTC_L" pin="PC6"/>
<pinref part="PAD23" gate="1" pin="P"/>
</segment>
</net>
<net name="N$24" class="0">
<segment>
<pinref part="U1" gate="PORTC_L" pin="PC7"/>
<pinref part="PAD24" gate="1" pin="P"/>
</segment>
</net>
<net name="N$25" class="0">
<segment>
<pinref part="U1" gate="PORTA_L" pin="PA0"/>
<pinref part="PAD25" gate="1" pin="P"/>
</segment>
</net>
<net name="N$26" class="0">
<segment>
<pinref part="U1" gate="PORTA_L" pin="PA1"/>
<pinref part="PAD26" gate="1" pin="P"/>
</segment>
</net>
<net name="N$27" class="0">
<segment>
<pinref part="U1" gate="PORTA_L" pin="PA2"/>
<pinref part="PAD27" gate="1" pin="P"/>
</segment>
</net>
<net name="N$28" class="0">
<segment>
<pinref part="U1" gate="PORTA_L" pin="PA3"/>
<pinref part="PAD28" gate="1" pin="P"/>
</segment>
</net>
<net name="N$29" class="0">
<segment>
<pinref part="U1" gate="PORTA_L" pin="PA4"/>
<pinref part="PAD29" gate="1" pin="P"/>
</segment>
</net>
<net name="N$30" class="0">
<segment>
<pinref part="U1" gate="PORTA_L" pin="PA5"/>
<pinref part="PAD30" gate="1" pin="P"/>
</segment>
</net>
<net name="N$31" class="0">
<segment>
<pinref part="U1" gate="PORTA_L" pin="PA6"/>
<pinref part="PAD31" gate="1" pin="P"/>
</segment>
</net>
<net name="N$32" class="0">
<segment>
<pinref part="U1" gate="PORTA_L" pin="PA7"/>
<pinref part="PAD32" gate="1" pin="P"/>
</segment>
</net>
<net name="N$33" class="0">
<segment>
<pinref part="U1" gate="PORTD/OSC" pin="PD0/OSC&lt;="/>
<pinref part="PAD33" gate="1" pin="P"/>
</segment>
</net>
<net name="N$34" class="0">
<segment>
<pinref part="U1" gate="PORTD/OSC" pin="PD1/OSC=&gt;"/>
<pinref part="PAD34" gate="1" pin="P"/>
</segment>
</net>
<net name="N$35" class="0">
<segment>
<pinref part="U1" gate="PORTD/OSC" pin="PD2"/>
<pinref part="PAD35" gate="1" pin="P"/>
</segment>
</net>
<net name="N$36" class="0">
<segment>
<pinref part="U1" gate="PORTB_L" pin="PB0"/>
<pinref part="PAD36" gate="1" pin="P"/>
</segment>
</net>
<net name="N$37" class="0">
<segment>
<pinref part="U1" gate="PORTB_L" pin="PB1"/>
<pinref part="PAD37" gate="1" pin="P"/>
</segment>
</net>
<net name="N$38" class="0">
<segment>
<pinref part="U1" gate="PORTB_L" pin="PB2"/>
<pinref part="PAD38" gate="1" pin="P"/>
</segment>
</net>
<net name="N$39" class="0">
<segment>
<pinref part="U1" gate="PORTB_L" pin="PB3"/>
<pinref part="PAD39" gate="1" pin="P"/>
</segment>
</net>
<net name="N$40" class="0">
<segment>
<pinref part="U1" gate="PORTB_L" pin="PB4"/>
<pinref part="PAD40" gate="1" pin="P"/>
</segment>
</net>
<net name="N$41" class="0">
<segment>
<pinref part="U1" gate="PORTB_L" pin="PB5"/>
<pinref part="PAD41" gate="1" pin="P"/>
</segment>
</net>
<net name="N$42" class="0">
<segment>
<pinref part="U1" gate="PORTB_L" pin="PB6"/>
<pinref part="PAD42" gate="1" pin="P"/>
</segment>
</net>
<net name="N$43" class="0">
<segment>
<pinref part="U1" gate="PORTB_L" pin="PB7"/>
<pinref part="PAD43" gate="1" pin="P"/>
</segment>
</net>
<net name="N$44" class="0">
<segment>
<pinref part="U1" gate="PORTB_H" pin="PB8"/>
<pinref part="PAD44" gate="1" pin="P"/>
</segment>
</net>
<net name="N$45" class="0">
<segment>
<pinref part="U1" gate="PORTB_H" pin="PB9"/>
<pinref part="PAD45" gate="1" pin="P"/>
</segment>
</net>
<net name="N$46" class="0">
<segment>
<pinref part="U1" gate="PORTB_H" pin="PB10"/>
<pinref part="PAD46" gate="1" pin="P"/>
</segment>
</net>
<net name="N$47" class="0">
<segment>
<pinref part="U1" gate="PORTB_H" pin="PB11"/>
<pinref part="PAD47" gate="1" pin="P"/>
</segment>
</net>
<net name="N$48" class="0">
<segment>
<pinref part="U1" gate="PORTB_H" pin="PB12"/>
<pinref part="PAD48" gate="1" pin="P"/>
</segment>
</net>
<net name="N$49" class="0">
<segment>
<pinref part="U1" gate="PORTB_H" pin="PB13"/>
<pinref part="PAD49" gate="1" pin="P"/>
</segment>
</net>
<net name="N$50" class="0">
<segment>
<pinref part="U1" gate="PORTB_H" pin="PB14"/>
<pinref part="PAD50" gate="1" pin="P"/>
</segment>
</net>
<net name="N$51" class="0">
<segment>
<pinref part="U1" gate="PORTB_H" pin="PB15"/>
<pinref part="PAD51" gate="1" pin="P"/>
</segment>
</net>
<net name="N$52" class="0">
<segment>
<pinref part="U1" gate="AN_POWER" pin="VBAT"/>
<pinref part="PAD52" gate="1" pin="P"/>
<wire x1="-7.62" y1="17.78" x2="-15.24" y2="17.78" width="0.1524" layer="91"/>
</segment>
</net>
<net name="N$55" class="0">
<segment>
<pinref part="U1" gate="RESET" pin="NRST"/>
<pinref part="PAD55" gate="1" pin="P"/>
</segment>
</net>
<net name="N$56" class="0">
<segment>
<pinref part="U1" gate="RESET" pin="BOOT0"/>
<pinref part="PAD56" gate="1" pin="P"/>
</segment>
</net>
</nets>
</sheet>
</sheets>
</schematic>
</drawing>
</eagle>