stm32f4xx_hash.c 25 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f4xx_hash.c
  4. * @author MCD Application Team
  5. * @version V1.0.0
  6. * @date 30-September-2011
  7. * @brief This file provides firmware functions to manage the following
  8. * functionalities of the HASH / HMAC Processor (HASH) peripheral:
  9. * - Initialization and Configuration functions
  10. * - Message Digest generation functions
  11. * - context swapping functions
  12. * - DMA interface function
  13. * - Interrupts and flags management
  14. *
  15. * @verbatim
  16. *
  17. * ===================================================================
  18. * How to use this driver
  19. * ===================================================================
  20. * HASH operation :
  21. * ----------------
  22. * 1. Enable the HASH controller clock using
  23. * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE) function.
  24. *
  25. * 2. Initialise the HASH using HASH_Init() function.
  26. *
  27. * 3 . Reset the HASH processor core, so that the HASH will be ready
  28. * to compute he message digest of a new message by using
  29. * HASH_Reset() function.
  30. *
  31. * 4. Enable the HASH controller using the HASH_Cmd() function.
  32. *
  33. * 5. if using DMA for Data input transfer, Activate the DMA Request
  34. * using HASH_DMACmd() function
  35. *
  36. * 6. if DMA is not used for data transfer, use HASH_DataIn() function
  37. * to enter data to IN FIFO.
  38. *
  39. *
  40. * 7. Configure the Number of valid bits in last word of the message
  41. * using HASH_SetLastWordValidBitsNbr() function.
  42. *
  43. * 8. if the message length is not an exact multiple of 512 bits,
  44. * then the function HASH_StartDigest() must be called to
  45. * launch the computation of the final digest.
  46. *
  47. * 9. Once computed, the digest can be read using HASH_GetDigest()
  48. * function.
  49. *
  50. * 10. To control HASH events you can use one of the following
  51. * two methods:
  52. * a- Check on HASH flags using the HASH_GetFlagStatus() function.
  53. * b- Use HASH interrupts through the function HASH_ITConfig() at
  54. * initialization phase and HASH_GetITStatus() function into
  55. * interrupt routines in hashing phase.
  56. * After checking on a flag you should clear it using HASH_ClearFlag()
  57. * function. And after checking on an interrupt event you should
  58. * clear it using HASH_ClearITPendingBit() function.
  59. *
  60. * 11. Save and restore hash processor context using
  61. * HASH_SaveContext() and HASH_RestoreContext() functions.
  62. *
  63. *
  64. *
  65. * HMAC operation :
  66. * ----------------
  67. * The HMAC algorithm is used for message authentication, by
  68. * irreversibly binding the message being processed to a key chosen
  69. * by the user.
  70. * For HMAC specifications, refer to "HMAC: keyed-hashing for message
  71. * authentication, H. Krawczyk, M. Bellare, R. Canetti, February 1997"
  72. *
  73. * Basically, the HMAC algorithm consists of two nested hash operations:
  74. * HMAC(message) = Hash[((key | pad) XOR 0x5C) | Hash(((key | pad) XOR 0x36) | message)]
  75. * where:
  76. * - "pad" is a sequence of zeroes needed to extend the key to the
  77. * length of the underlying hash function data block (that is
  78. * 512 bits for both the SHA-1 and MD5 hash algorithms)
  79. * - "|" represents the concatenation operator
  80. *
  81. *
  82. * To compute the HMAC, four different phases are required:
  83. *
  84. * 1. Initialise the HASH using HASH_Init() function to do HMAC
  85. * operation.
  86. *
  87. * 2. The key (to be used for the inner hash function) is then given
  88. * to the core. This operation follows the same mechanism as the
  89. * one used to send the message in the hash operation (that is,
  90. * by HASH_DataIn() function and, finally,
  91. * HASH_StartDigest() function.
  92. *
  93. * 3. Once the last word has been entered and computation has started,
  94. * the hash processor elaborates the key. It is then ready to
  95. * accept the message text using the same mechanism as the one
  96. * used to send the message in the hash operation.
  97. *
  98. * 4. After the first hash round, the hash processor returns "ready"
  99. * to indicate that it is ready to receive the key to be used for
  100. * the outer hash function (normally, this key is the same as the
  101. * one used for the inner hash function). When the last word of
  102. * the key is entered and computation starts, the HMAC result is
  103. * made available using HASH_GetDigest() function.
  104. *
  105. *
  106. * @endverbatim
  107. *
  108. ******************************************************************************
  109. * @attention
  110. *
  111. * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  112. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  113. * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  114. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  115. * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  116. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  117. *
  118. * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
  119. ******************************************************************************
  120. */
  121. /* Includes ------------------------------------------------------------------*/
  122. #include "stm32f4xx_hash.h"
  123. #include "stm32f4xx_rcc.h"
  124. /** @addtogroup STM32F4xx_StdPeriph_Driver
  125. * @{
  126. */
  127. /** @defgroup HASH
  128. * @brief HASH driver modules
  129. * @{
  130. */
  131. /* Private typedef -----------------------------------------------------------*/
  132. /* Private define ------------------------------------------------------------*/
  133. /* Private macro -------------------------------------------------------------*/
  134. /* Private variables ---------------------------------------------------------*/
  135. /* Private function prototypes -----------------------------------------------*/
  136. /* Private functions ---------------------------------------------------------*/
  137. /** @defgroup HASH_Private_Functions
  138. * @{
  139. */
  140. /** @defgroup HASH_Group1 Initialization and Configuration functions
  141. * @brief Initialization and Configuration functions
  142. *
  143. @verbatim
  144. ===============================================================================
  145. Initialization and Configuration functions
  146. ===============================================================================
  147. This section provides functions allowing to
  148. - Initialize the HASH peripheral
  149. - Configure the HASH Processor
  150. - MD5/SHA1,
  151. - HASH/HMAC,
  152. - datatype
  153. - HMAC Key (if mode = HMAC)
  154. - Reset the HASH Processor
  155. @endverbatim
  156. * @{
  157. */
  158. /**
  159. * @brief Deinitializes the HASH peripheral registers to their default reset values
  160. * @param None
  161. * @retval None
  162. */
  163. void HASH_DeInit(void)
  164. {
  165. /* Enable HASH reset state */
  166. RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, ENABLE);
  167. /* Release HASH from reset state */
  168. RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, DISABLE);
  169. }
  170. /**
  171. * @brief Initializes the HASH peripheral according to the specified parameters
  172. * in the HASH_InitStruct structure.
  173. * @note the hash processor is reset when calling this function so that the
  174. * HASH will be ready to compute the message digest of a new message.
  175. * There is no need to call HASH_Reset() function.
  176. * @param HASH_InitStruct: pointer to a HASH_InitTypeDef structure that contains
  177. * the configuration information for the HASH peripheral.
  178. * @note The field HASH_HMACKeyType in HASH_InitTypeDef must be filled only
  179. * if the algorithm mode is HMAC.
  180. * @retval None
  181. */
  182. void HASH_Init(HASH_InitTypeDef* HASH_InitStruct)
  183. {
  184. /* Check the parameters */
  185. assert_param(IS_HASH_ALGOSELECTION(HASH_InitStruct->HASH_AlgoSelection));
  186. assert_param(IS_HASH_DATATYPE(HASH_InitStruct->HASH_DataType));
  187. assert_param(IS_HASH_ALGOMODE(HASH_InitStruct->HASH_AlgoMode));
  188. /* Configure the Algorithm used, algorithm mode and the datatype */
  189. HASH->CR &= ~ (HASH_CR_ALGO | HASH_CR_DATATYPE | HASH_CR_MODE);
  190. HASH->CR |= (HASH_InitStruct->HASH_AlgoSelection | \
  191. HASH_InitStruct->HASH_DataType | \
  192. HASH_InitStruct->HASH_AlgoMode);
  193. /* if algorithm mode is HMAC, set the Key */
  194. if(HASH_InitStruct->HASH_AlgoMode == HASH_AlgoMode_HMAC)
  195. {
  196. assert_param(IS_HASH_HMAC_KEYTYPE(HASH_InitStruct->HASH_HMACKeyType));
  197. HASH->CR &= ~HASH_CR_LKEY;
  198. HASH->CR |= HASH_InitStruct->HASH_HMACKeyType;
  199. }
  200. /* Reset the HASH processor core, so that the HASH will be ready to compute
  201. the message digest of a new message */
  202. HASH->CR |= HASH_CR_INIT;
  203. }
  204. /**
  205. * @brief Fills each HASH_InitStruct member with its default value.
  206. * @param HASH_InitStruct : pointer to a HASH_InitTypeDef structure which will
  207. * be initialized.
  208. * @note The default values set are : Processor mode is HASH, Algorithm selected is SHA1,
  209. * Data type selected is 32b and HMAC Key Type is short key.
  210. * @retval None
  211. */
  212. void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct)
  213. {
  214. /* Initialize the HASH_AlgoSelection member */
  215. HASH_InitStruct->HASH_AlgoSelection = HASH_AlgoSelection_SHA1;
  216. /* Initialize the HASH_AlgoMode member */
  217. HASH_InitStruct->HASH_AlgoMode = HASH_AlgoMode_HASH;
  218. /* Initialize the HASH_DataType member */
  219. HASH_InitStruct->HASH_DataType = HASH_DataType_32b;
  220. /* Initialize the HASH_HMACKeyType member */
  221. HASH_InitStruct->HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;
  222. }
  223. /**
  224. * @brief Resets the HASH processor core, so that the HASH will be ready
  225. * to compute the message digest of a new message.
  226. * @note Calling this function will clear the HASH_SR_DCIS (Digest calculation
  227. * completion interrupt status) bit corresponding to HASH_IT_DCI
  228. * interrupt and HASH_FLAG_DCIS flag.
  229. * @param None
  230. * @retval None
  231. */
  232. void HASH_Reset(void)
  233. {
  234. /* Reset the HASH processor core */
  235. HASH->CR |= HASH_CR_INIT;
  236. }
  237. /**
  238. * @}
  239. */
  240. /** @defgroup HASH_Group2 Message Digest generation functions
  241. * @brief Message Digest generation functions
  242. *
  243. @verbatim
  244. ===============================================================================
  245. Message Digest generation functions
  246. ===============================================================================
  247. This section provides functions allowing the generation of message digest:
  248. - Push data in the IN FIFO : using HASH_DataIn()
  249. - Get the number of words set in IN FIFO, use HASH_GetInFIFOWordsNbr()
  250. - set the last word valid bits number using HASH_SetLastWordValidBitsNbr()
  251. - start digest calculation : using HASH_StartDigest()
  252. - Get the Digest message : using HASH_GetDigest()
  253. @endverbatim
  254. * @{
  255. */
  256. /**
  257. * @brief Configure the Number of valid bits in last word of the message
  258. * @param ValidNumber: Number of valid bits in last word of the message.
  259. * This parameter must be a number between 0 and 0x1F.
  260. * - 0x00: All 32 bits of the last data written are valid
  261. * - 0x01: Only bit [0] of the last data written is valid
  262. * - 0x02: Only bits[1:0] of the last data written are valid
  263. * - 0x03: Only bits[2:0] of the last data written are valid
  264. * - ...
  265. * - 0x1F: Only bits[30:0] of the last data written are valid
  266. * @note The Number of valid bits must be set before to start the message
  267. * digest competition (in Hash and HMAC) and key treatment(in HMAC).
  268. * @retval None
  269. */
  270. void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber)
  271. {
  272. /* Check the parameters */
  273. assert_param(IS_HASH_VALIDBITSNUMBER(ValidNumber));
  274. /* Configure the Number of valid bits in last word of the message */
  275. HASH->STR &= ~(HASH_STR_NBW);
  276. HASH->STR |= ValidNumber;
  277. }
  278. /**
  279. * @brief Writes data in the Data Input FIFO
  280. * @param Data: new data of the message to be processed.
  281. * @retval None
  282. */
  283. void HASH_DataIn(uint32_t Data)
  284. {
  285. /* Write in the DIN register a new data */
  286. HASH->DIN = Data;
  287. }
  288. /**
  289. * @brief Returns the number of words already pushed into the IN FIFO.
  290. * @param None
  291. * @retval The value of words already pushed into the IN FIFO.
  292. */
  293. uint8_t HASH_GetInFIFOWordsNbr(void)
  294. {
  295. /* Return the value of NBW bits */
  296. return ((HASH->CR & HASH_CR_NBW) >> 8);
  297. }
  298. /**
  299. * @brief Provides the message digest result.
  300. * @note In MD5 mode, Data[4] filed of HASH_MsgDigest structure is not used
  301. * and is read as zero.
  302. * @param HASH_MessageDigest: pointer to a HASH_MsgDigest structure which will
  303. * hold the message digest result
  304. * @retval None
  305. */
  306. void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest)
  307. {
  308. /* Get the data field */
  309. HASH_MessageDigest->Data[0] = HASH->HR[0];
  310. HASH_MessageDigest->Data[1] = HASH->HR[1];
  311. HASH_MessageDigest->Data[2] = HASH->HR[2];
  312. HASH_MessageDigest->Data[3] = HASH->HR[3];
  313. HASH_MessageDigest->Data[4] = HASH->HR[4];
  314. }
  315. /**
  316. * @brief Starts the message padding and calculation of the final message
  317. * @param None
  318. * @retval None
  319. */
  320. void HASH_StartDigest(void)
  321. {
  322. /* Start the Digest calculation */
  323. HASH->STR |= HASH_STR_DCAL;
  324. }
  325. /**
  326. * @}
  327. */
  328. /** @defgroup HASH_Group3 Context swapping functions
  329. * @brief Context swapping functions
  330. *
  331. @verbatim
  332. ===============================================================================
  333. Context swapping functions
  334. ===============================================================================
  335. This section provides functions allowing to save and store HASH Context
  336. It is possible to interrupt a HASH/HMAC process to perform another processing
  337. with a higher priority, and to complete the interrupted process later on, when
  338. the higher priority task is complete. To do so, the context of the interrupted
  339. task must be saved from the HASH registers to memory, and then be restored
  340. from memory to the HASH registers.
  341. 1. To save the current context, use HASH_SaveContext() function
  342. 2. To restore the saved context, use HASH_RestoreContext() function
  343. @endverbatim
  344. * @{
  345. */
  346. /**
  347. * @brief Save the Hash peripheral Context.
  348. * @note The context can be saved only when no block is currently being
  349. * processed. So user must wait for DINIS = 1 (the last block has been
  350. * processed and the input FIFO is empty) or NBW != 0 (the FIFO is not
  351. * full and no processing is ongoing).
  352. * @param HASH_ContextSave: pointer to a HASH_Context structure that contains
  353. * the repository for current context.
  354. * @retval None
  355. */
  356. void HASH_SaveContext(HASH_Context* HASH_ContextSave)
  357. {
  358. uint8_t i = 0;
  359. /* save context registers */
  360. HASH_ContextSave->HASH_IMR = HASH->IMR;
  361. HASH_ContextSave->HASH_STR = HASH->STR;
  362. HASH_ContextSave->HASH_CR = HASH->CR;
  363. for(i=0; i<=50;i++)
  364. {
  365. HASH_ContextSave->HASH_CSR[i] = HASH->CSR[i];
  366. }
  367. }
  368. /**
  369. * @brief Restore the Hash peripheral Context.
  370. * @note After calling this function, user can restart the processing from the
  371. * point where it has been interrupted.
  372. * @param HASH_ContextRestore: pointer to a HASH_Context structure that contains
  373. * the repository for saved context.
  374. * @retval None
  375. */
  376. void HASH_RestoreContext(HASH_Context* HASH_ContextRestore)
  377. {
  378. uint8_t i = 0;
  379. /* restore context registers */
  380. HASH->IMR = HASH_ContextRestore->HASH_IMR;
  381. HASH->STR = HASH_ContextRestore->HASH_STR;
  382. HASH->CR = HASH_ContextRestore->HASH_CR;
  383. /* Initialize the hash processor */
  384. HASH->CR |= HASH_CR_INIT;
  385. /* continue restoring context registers */
  386. for(i=0; i<=50;i++)
  387. {
  388. HASH->CSR[i] = HASH_ContextRestore->HASH_CSR[i];
  389. }
  390. }
  391. /**
  392. * @}
  393. */
  394. /** @defgroup HASH_Group4 HASH's DMA interface Configuration function
  395. * @brief HASH's DMA interface Configuration function
  396. *
  397. @verbatim
  398. ===============================================================================
  399. HASH's DMA interface Configuration function
  400. ===============================================================================
  401. This section provides functions allowing to configure the DMA interface for
  402. HASH/ HMAC data input transfer.
  403. When the DMA mode is enabled (using the HASH_DMACmd() function), data can be
  404. sent to the IN FIFO using the DMA peripheral.
  405. @endverbatim
  406. * @{
  407. */
  408. /**
  409. * @brief Enables or disables the HASH DMA interface.
  410. * @note The DMA is disabled by hardware after the end of transfer.
  411. * @param NewState: new state of the selected HASH DMA transfer request.
  412. * This parameter can be: ENABLE or DISABLE.
  413. * @retval None
  414. */
  415. void HASH_DMACmd(FunctionalState NewState)
  416. {
  417. /* Check the parameters */
  418. assert_param(IS_FUNCTIONAL_STATE(NewState));
  419. if (NewState != DISABLE)
  420. {
  421. /* Enable the HASH DMA request */
  422. HASH->CR |= HASH_CR_DMAE;
  423. }
  424. else
  425. {
  426. /* Disable the HASH DMA request */
  427. HASH->CR &= ~HASH_CR_DMAE;
  428. }
  429. }
  430. /**
  431. * @}
  432. */
  433. /** @defgroup HASH_Group5 Interrupts and flags management functions
  434. * @brief Interrupts and flags management functions
  435. *
  436. @verbatim
  437. ===============================================================================
  438. Interrupts and flags management functions
  439. ===============================================================================
  440. This section provides functions allowing to configure the HASH Interrupts and
  441. to get the status and clear flags and Interrupts pending bits.
  442. The HASH provides 2 Interrupts sources and 5 Flags:
  443. Flags :
  444. ----------
  445. 1. HASH_FLAG_DINIS : set when 16 locations are free in the Data IN FIFO
  446. which means that a new block (512 bit) can be entered
  447. into the input buffer.
  448. 2. HASH_FLAG_DCIS : set when Digest calculation is complete
  449. 3. HASH_FLAG_DMAS : set when HASH's DMA interface is enabled (DMAE=1) or
  450. a transfer is ongoing.
  451. This Flag is cleared only by hardware.
  452. 4. HASH_FLAG_BUSY : set when The hash core is processing a block of data
  453. This Flag is cleared only by hardware.
  454. 5. HASH_FLAG_DINNE : set when Data IN FIFO is not empty which means that
  455. the Data IN FIFO contains at least one word of data.
  456. This Flag is cleared only by hardware.
  457. Interrupts :
  458. ------------
  459. 1. HASH_IT_DINI : if enabled, this interrupt source is pending when 16
  460. locations are free in the Data IN FIFO which means that
  461. a new block (512 bit) can be entered into the input buffer.
  462. This interrupt source is cleared using
  463. HASH_ClearITPendingBit(HASH_IT_DINI) function.
  464. 2. HASH_IT_DCI : if enabled, this interrupt source is pending when Digest
  465. calculation is complete.
  466. This interrupt source is cleared using
  467. HASH_ClearITPendingBit(HASH_IT_DCI) function.
  468. Managing the HASH controller events :
  469. ------------------------------------
  470. The user should identify which mode will be used in his application to manage
  471. the HASH controller events: Polling mode or Interrupt mode.
  472. 1. In the Polling Mode it is advised to use the following functions:
  473. - HASH_GetFlagStatus() : to check if flags events occur.
  474. - HASH_ClearFlag() : to clear the flags events.
  475. 2. In the Interrupt Mode it is advised to use the following functions:
  476. - HASH_ITConfig() : to enable or disable the interrupt source.
  477. - HASH_GetITStatus() : to check if Interrupt occurs.
  478. - HASH_ClearITPendingBit() : to clear the Interrupt pending Bit
  479. (corresponding Flag).
  480. @endverbatim
  481. * @{
  482. */
  483. /**
  484. * @brief Enables or disables the specified HASH interrupts.
  485. * @param HASH_IT: specifies the HASH interrupt source to be enabled or disabled.
  486. * This parameter can be any combination of the following values:
  487. * @arg HASH_IT_DINI: Data Input interrupt
  488. * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
  489. * @param NewState: new state of the specified HASH interrupt.
  490. * This parameter can be: ENABLE or DISABLE.
  491. * @retval None
  492. */
  493. void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState)
  494. {
  495. /* Check the parameters */
  496. assert_param(IS_HASH_IT(HASH_IT));
  497. assert_param(IS_FUNCTIONAL_STATE(NewState));
  498. if (NewState != DISABLE)
  499. {
  500. /* Enable the selected HASH interrupt */
  501. HASH->IMR |= HASH_IT;
  502. }
  503. else
  504. {
  505. /* Disable the selected HASH interrupt */
  506. HASH->IMR &= (uint8_t) ~HASH_IT;
  507. }
  508. }
  509. /**
  510. * @brief Checks whether the specified HASH flag is set or not.
  511. * @param HASH_FLAG: specifies the HASH flag to check.
  512. * This parameter can be one of the following values:
  513. * @arg HASH_FLAG_DINIS: Data input interrupt status flag
  514. * @arg HASH_FLAG_DCIS: Digest calculation completion interrupt status flag
  515. * @arg HASH_FLAG_BUSY: Busy flag
  516. * @arg HASH_FLAG_DMAS: DMAS Status flag
  517. * @arg HASH_FLAG_DINNE: Data Input register (DIN) not empty status flag
  518. * @retval The new state of HASH_FLAG (SET or RESET)
  519. */
  520. FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG)
  521. {
  522. FlagStatus bitstatus = RESET;
  523. uint32_t tempreg = 0;
  524. /* Check the parameters */
  525. assert_param(IS_HASH_GET_FLAG(HASH_FLAG));
  526. /* check if the FLAG is in CR register */
  527. if ((HASH_FLAG & HASH_FLAG_DINNE) != (uint16_t)RESET )
  528. {
  529. tempreg = HASH->CR;
  530. }
  531. else /* The FLAG is in SR register */
  532. {
  533. tempreg = HASH->SR;
  534. }
  535. /* Check the status of the specified HASH flag */
  536. if ((tempreg & HASH_FLAG) != (uint16_t)RESET)
  537. {
  538. /* HASH is set */
  539. bitstatus = SET;
  540. }
  541. else
  542. {
  543. /* HASH_FLAG is reset */
  544. bitstatus = RESET;
  545. }
  546. /* Return the HASH_FLAG status */
  547. return bitstatus;
  548. }
  549. /**
  550. * @brief Clears the HASH flags.
  551. * @param HASH_FLAG: specifies the flag to clear.
  552. * This parameter can be any combination of the following values:
  553. * @arg HASH_FLAG_DINIS: Data Input Flag
  554. * @arg HASH_FLAG_DCIS: Digest Calculation Completion Flag
  555. * @retval None
  556. */
  557. void HASH_ClearFlag(uint16_t HASH_FLAG)
  558. {
  559. /* Check the parameters */
  560. assert_param(IS_HASH_CLEAR_FLAG(HASH_FLAG));
  561. /* Clear the selected HASH flags */
  562. HASH->SR = ~(uint32_t)HASH_FLAG;
  563. }
  564. /**
  565. * @brief Checks whether the specified HASH interrupt has occurred or not.
  566. * @param HASH_IT: specifies the HASH interrupt source to check.
  567. * This parameter can be one of the following values:
  568. * @arg HASH_IT_DINI: Data Input interrupt
  569. * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
  570. * @retval The new state of HASH_IT (SET or RESET).
  571. */
  572. ITStatus HASH_GetITStatus(uint8_t HASH_IT)
  573. {
  574. ITStatus bitstatus = RESET;
  575. uint32_t tmpreg = 0;
  576. /* Check the parameters */
  577. assert_param(IS_HASH_GET_IT(HASH_IT));
  578. /* Check the status of the specified HASH interrupt */
  579. tmpreg = HASH->SR;
  580. if (((HASH->IMR & tmpreg) & HASH_IT) != RESET)
  581. {
  582. /* HASH_IT is set */
  583. bitstatus = SET;
  584. }
  585. else
  586. {
  587. /* HASH_IT is reset */
  588. bitstatus = RESET;
  589. }
  590. /* Return the HASH_IT status */
  591. return bitstatus;
  592. }
  593. /**
  594. * @brief Clears the HASH interrupt pending bit(s).
  595. * @param HASH_IT: specifies the HASH interrupt pending bit(s) to clear.
  596. * This parameter can be any combination of the following values:
  597. * @arg HASH_IT_DINI: Data Input interrupt
  598. * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
  599. * @retval None
  600. */
  601. void HASH_ClearITPendingBit(uint8_t HASH_IT)
  602. {
  603. /* Check the parameters */
  604. assert_param(IS_HASH_IT(HASH_IT));
  605. /* Clear the selected HASH interrupt pending bit */
  606. HASH->SR = (uint8_t)~HASH_IT;
  607. }
  608. /**
  609. * @}
  610. */
  611. /**
  612. * @}
  613. */
  614. /**
  615. * @}
  616. */
  617. /**
  618. * @}
  619. */
  620. /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/