startup_stm32f0xx.s 8.5 KB

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  1. /**
  2. ******************************************************************************
  3. * @file startup_stm32f0xx.s
  4. * @author MCD Application Team
  5. * @version V1.0.1
  6. * @date 20-April-2012
  7. * @brief STM32F0xx Devices vector table for Atollic toolchain.
  8. * This module performs:
  9. * - Set the initial SP
  10. * - Set the initial PC == Reset_Handler,
  11. * - Set the vector table entries with the exceptions ISR address
  12. * - Configure the clock system
  13. * - Branches to main in the C library (which eventually
  14. * calls main()).
  15. * After Reset the Cortex-M0 processor is in Thread mode,
  16. * priority is Privileged, and the Stack is set to Main.
  17. ******************************************************************************
  18. * @attention
  19. *
  20. * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
  21. *
  22. * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
  23. * You may not use this file except in compliance with the License.
  24. * You may obtain a copy of the License at:
  25. *
  26. * http://www.st.com/software_license_agreement_liberty_v2
  27. *
  28. * Unless required by applicable law or agreed to in writing, software
  29. * distributed under the License is distributed on an "AS IS" BASIS,
  30. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  31. * See the License for the specific language governing permissions and
  32. * limitations under the License.
  33. *
  34. ******************************************************************************
  35. */
  36. .syntax unified
  37. .cpu cortex-m0
  38. .fpu softvfp
  39. .thumb
  40. .global g_pfnVectors
  41. .global Default_Handler
  42. /* start address for the initialization values of the .data section.
  43. defined in linker script */
  44. .word _sidata
  45. /* start address for the .data section. defined in linker script */
  46. .word _sdata
  47. /* end address for the .data section. defined in linker script */
  48. .word _edata
  49. /* start address for the .bss section. defined in linker script */
  50. .word _sbss
  51. /* end address for the .bss section. defined in linker script */
  52. .word _ebss
  53. .equ BootRAM, 0xF108F85F
  54. /**
  55. * @brief This is the code that gets called when the processor first
  56. * starts execution following a reset event. Only the absolutely
  57. * necessary set is performed, after which the application
  58. * supplied main() routine is called.
  59. * @param None
  60. * @retval : None
  61. */
  62. .section .text.Reset_Handler
  63. .weak Reset_Handler
  64. .type Reset_Handler, %function
  65. Reset_Handler:
  66. ldr r0, =_estack
  67. mov sp, r0 /* set stack pointer */
  68. /* Copy the data segment initializers from flash to SRAM */
  69. movs r1, #0
  70. b LoopCopyDataInit
  71. CopyDataInit:
  72. ldr r3, =_sidata
  73. ldr r3, [r3, r1]
  74. str r3, [r0, r1]
  75. adds r1, r1, #4
  76. LoopCopyDataInit:
  77. ldr r0, =_sdata
  78. ldr r3, =_edata
  79. adds r2, r0, r1
  80. cmp r2, r3
  81. bcc CopyDataInit
  82. ldr r2, =_sbss
  83. b LoopFillZerobss
  84. /* Zero fill the bss segment. */
  85. FillZerobss:
  86. movs r3, #0
  87. str r3, [r2]
  88. adds r2, r2, #4
  89. LoopFillZerobss:
  90. ldr r3, = _ebss
  91. cmp r2, r3
  92. bcc FillZerobss
  93. /* Call the clock system intitialization function.*/
  94. bl SystemInit
  95. /* Call static constructors */
  96. bl __libc_init_array
  97. /* Call the application's entry point.*/
  98. bl main
  99. LoopForever:
  100. b LoopForever
  101. .size Reset_Handler, .-Reset_Handler
  102. /**
  103. * @brief This is the code that gets called when the processor receives an
  104. * unexpected interrupt. This simply enters an infinite loop, preserving
  105. * the system state for examination by a debugger.
  106. *
  107. * @param None
  108. * @retval : None
  109. */
  110. .section .text.Default_Handler,"ax",%progbits
  111. Default_Handler:
  112. Infinite_Loop:
  113. b Infinite_Loop
  114. .size Default_Handler, .-Default_Handler
  115. /******************************************************************************
  116. *
  117. * The minimal vector table for a Cortex M0. Note that the proper constructs
  118. * must be placed on this to ensure that it ends up at physical address
  119. * 0x0000.0000.
  120. *
  121. ******************************************************************************/
  122. .section .isr_vector,"a",%progbits
  123. .type g_pfnVectors, %object
  124. .size g_pfnVectors, .-g_pfnVectors
  125. g_pfnVectors:
  126. .word _estack
  127. .word Reset_Handler
  128. .word NMI_Handler
  129. .word HardFault_Handler
  130. .word 0
  131. .word 0
  132. .word 0
  133. .word 0
  134. .word 0
  135. .word 0
  136. .word 0
  137. .word SVC_Handler
  138. .word 0
  139. .word 0
  140. .word PendSV_Handler
  141. .word SysTick_Handler
  142. .word WWDG_IRQHandler
  143. .word PVD_IRQHandler
  144. .word RTC_IRQHandler
  145. .word FLASH_IRQHandler
  146. .word RCC_IRQHandler
  147. .word EXTI0_1_IRQHandler
  148. .word EXTI2_3_IRQHandler
  149. .word EXTI4_15_IRQHandler
  150. .word TS_IRQHandler
  151. .word DMA1_Channel1_IRQHandler
  152. .word DMA1_Channel2_3_IRQHandler
  153. .word DMA1_Channel4_5_IRQHandler
  154. .word ADC1_COMP_IRQHandler
  155. .word TIM1_BRK_UP_TRG_COM_IRQHandler
  156. .word TIM1_CC_IRQHandler
  157. .word TIM2_IRQHandler
  158. .word TIM3_IRQHandler
  159. .word TIM6_DAC_IRQHandler
  160. .word 0
  161. .word TIM14_IRQHandler
  162. .word TIM15_IRQHandler
  163. .word TIM16_IRQHandler
  164. .word TIM17_IRQHandler
  165. .word I2C1_IRQHandler
  166. .word I2C2_IRQHandler
  167. .word SPI1_IRQHandler
  168. .word SPI2_IRQHandler
  169. .word USART1_IRQHandler
  170. .word USART2_IRQHandler
  171. .word 0
  172. .word CEC_IRQHandler
  173. .word 0
  174. .word BootRAM /* @0x108. This is for boot in RAM mode for
  175. STM32F0xx devices. */
  176. /*******************************************************************************
  177. *
  178. * Provide weak aliases for each Exception handler to the Default_Handler.
  179. * As they are weak aliases, any function with the same name will override
  180. * this definition.
  181. *
  182. *******************************************************************************/
  183. .weak NMI_Handler
  184. .thumb_set NMI_Handler,Default_Handler
  185. .weak HardFault_Handler
  186. .thumb_set HardFault_Handler,Default_Handler
  187. .weak SVC_Handler
  188. .thumb_set SVC_Handler,Default_Handler
  189. .weak PendSV_Handler
  190. .thumb_set PendSV_Handler,Default_Handler
  191. .weak SysTick_Handler
  192. .thumb_set SysTick_Handler,Default_Handler
  193. .weak WWDG_IRQHandler
  194. .thumb_set WWDG_IRQHandler,Default_Handler
  195. .weak PVD_IRQHandler
  196. .thumb_set PVD_IRQHandler,Default_Handler
  197. .weak RTC_IRQHandler
  198. .thumb_set RTC_IRQHandler,Default_Handler
  199. .weak FLASH_IRQHandler
  200. .thumb_set FLASH_IRQHandler,Default_Handler
  201. .weak RCC_IRQHandler
  202. .thumb_set RCC_IRQHandler,Default_Handler
  203. .weak EXTI0_1_IRQHandler
  204. .thumb_set EXTI0_1_IRQHandler,Default_Handler
  205. .weak EXTI2_3_IRQHandler
  206. .thumb_set EXTI2_3_IRQHandler,Default_Handler
  207. .weak EXTI4_15_IRQHandler
  208. .thumb_set EXTI4_15_IRQHandler,Default_Handler
  209. .weak TS_IRQHandler
  210. .thumb_set TS_IRQHandler,Default_Handler
  211. .weak DMA1_Channel1_IRQHandler
  212. .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
  213. .weak DMA1_Channel2_3_IRQHandler
  214. .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
  215. .weak DMA1_Channel4_5_IRQHandler
  216. .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
  217. .weak ADC1_COMP_IRQHandler
  218. .thumb_set ADC1_COMP_IRQHandler,Default_Handler
  219. .weak TIM1_BRK_UP_TRG_COM_IRQHandler
  220. .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
  221. .weak TIM1_CC_IRQHandler
  222. .thumb_set TIM1_CC_IRQHandler,Default_Handler
  223. .weak TIM2_IRQHandler
  224. .thumb_set TIM2_IRQHandler,Default_Handler
  225. .weak TIM3_IRQHandler
  226. .thumb_set TIM3_IRQHandler,Default_Handler
  227. .weak TIM6_DAC_IRQHandler
  228. .thumb_set TIM6_DAC_IRQHandler,Default_Handler
  229. .weak TIM14_IRQHandler
  230. .thumb_set TIM14_IRQHandler,Default_Handler
  231. .weak TIM15_IRQHandler
  232. .thumb_set TIM15_IRQHandler,Default_Handler
  233. .weak TIM16_IRQHandler
  234. .thumb_set TIM16_IRQHandler,Default_Handler
  235. .weak TIM17_IRQHandler
  236. .thumb_set TIM17_IRQHandler,Default_Handler
  237. .weak I2C1_IRQHandler
  238. .thumb_set I2C1_IRQHandler,Default_Handler
  239. .weak I2C2_IRQHandler
  240. .thumb_set I2C2_IRQHandler,Default_Handler
  241. .weak SPI1_IRQHandler
  242. .thumb_set SPI1_IRQHandler,Default_Handler
  243. .weak SPI2_IRQHandler
  244. .thumb_set SPI2_IRQHandler,Default_Handler
  245. .weak USART1_IRQHandler
  246. .thumb_set USART1_IRQHandler,Default_Handler
  247. .weak USART2_IRQHandler
  248. .thumb_set USART2_IRQHandler,Default_Handler
  249. .weak CEC_IRQHandler
  250. .thumb_set CEC_IRQHandler,Default_Handler
  251. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/