stm32f0xx_pwr.c 20 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f0xx_pwr.c
  4. * @author MCD Application Team
  5. * @version V1.5.0
  6. * @date 05-December-2014
  7. * @brief This file provides firmware functions to manage the following
  8. * functionalities of the Power Controller (PWR) peripheral:
  9. * + Backup Domain Access
  10. * + PVD configuration
  11. * + WakeUp pins configuration
  12. * + Low Power modes configuration
  13. * + Flags management
  14. *
  15. ******************************************************************************
  16. * @attention
  17. *
  18. * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
  19. *
  20. * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
  21. * You may not use this file except in compliance with the License.
  22. * You may obtain a copy of the License at:
  23. *
  24. * http://www.st.com/software_license_agreement_liberty_v2
  25. *
  26. * Unless required by applicable law or agreed to in writing, software
  27. * distributed under the License is distributed on an "AS IS" BASIS,
  28. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  29. * See the License for the specific language governing permissions and
  30. * limitations under the License.
  31. *
  32. ******************************************************************************
  33. */
  34. /* Includes ------------------------------------------------------------------*/
  35. #include "stm32f0xx_pwr.h"
  36. #include "stm32f0xx_rcc.h"
  37. /** @addtogroup STM32F0xx_StdPeriph_Driver
  38. * @{
  39. */
  40. /** @defgroup PWR
  41. * @brief PWR driver modules
  42. * @{
  43. */
  44. /* Private typedef -----------------------------------------------------------*/
  45. /* Private define ------------------------------------------------------------*/
  46. /* ------------------ PWR registers bit mask ------------------------ */
  47. /* CR register bit mask */
  48. #define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
  49. #define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
  50. /* Private macro -------------------------------------------------------------*/
  51. /* Private variables ---------------------------------------------------------*/
  52. /* Private function prototypes -----------------------------------------------*/
  53. /* Private functions ---------------------------------------------------------*/
  54. /** @defgroup PWR_Private_Functions
  55. * @{
  56. */
  57. /** @defgroup PWR_Group1 Backup Domain Access function
  58. * @brief Backup Domain Access function
  59. *
  60. @verbatim
  61. ==============================================================================
  62. ##### Backup Domain Access function #####
  63. ==============================================================================
  64. [..] After reset, the Backup Domain Registers (RCC BDCR Register, RTC registers
  65. and RTC backup registers) are protected against possible stray write accesses.
  66. [..] To enable access to Backup domain use the PWR_BackupAccessCmd(ENABLE) function.
  67. @endverbatim
  68. * @{
  69. */
  70. /**
  71. * @brief Deinitializes the PWR peripheral registers to their default reset values.
  72. * @param None
  73. * @retval None
  74. */
  75. void PWR_DeInit(void)
  76. {
  77. RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
  78. RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
  79. }
  80. /**
  81. * @brief Enables or disables access to the Backup domain registers.
  82. * @note If the HSE divided by 32 is used as the RTC clock, the
  83. * Backup Domain Access should be kept enabled.
  84. * @param NewState: new state of the access to the Backup domain registers.
  85. * This parameter can be: ENABLE or DISABLE.
  86. * @retval None
  87. */
  88. void PWR_BackupAccessCmd(FunctionalState NewState)
  89. {
  90. /* Check the parameters */
  91. assert_param(IS_FUNCTIONAL_STATE(NewState));
  92. if (NewState != DISABLE)
  93. {
  94. /* Enable the Backup Domain Access */
  95. PWR->CR |= PWR_CR_DBP;
  96. }
  97. else
  98. {
  99. /* Disable the Backup Domain Access */
  100. PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_DBP);
  101. }
  102. }
  103. /**
  104. * @}
  105. */
  106. /** @defgroup PWR_Group2 PVD configuration functions
  107. * @brief PVD configuration functions
  108. *
  109. @verbatim
  110. ==============================================================================
  111. ##### PVD configuration functions #####
  112. ==============================================================================
  113. [..]
  114. (+) The PVD is used to monitor the VDD power supply by comparing it to a threshold
  115. selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
  116. (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the
  117. PVD threshold. This event is internally connected to the EXTI line16
  118. and can generate an interrupt if enabled through the EXTI registers.
  119. (+) The PVD is stopped in Standby mode.
  120. @endverbatim
  121. * @{
  122. */
  123. /**
  124. * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
  125. * @note This function is not applicable for STM32F030 devices.
  126. * @param PWR_PVDLevel: specifies the PVD detection level
  127. * This parameter can be one of the following values:
  128. * @arg PWR_PVDLevel_0
  129. * @arg PWR_PVDLevel_1
  130. * @arg PWR_PVDLevel_2
  131. * @arg PWR_PVDLevel_3
  132. * @arg PWR_PVDLevel_4
  133. * @arg PWR_PVDLevel_5
  134. * @arg PWR_PVDLevel_6
  135. * @arg PWR_PVDLevel_7
  136. * @note Refer to the electrical characteristics of your device datasheet for
  137. * more details about the voltage threshold corresponding to each
  138. * detection level.
  139. * @retval None
  140. */
  141. void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
  142. {
  143. uint32_t tmpreg = 0;
  144. /* Check the parameters */
  145. assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
  146. tmpreg = PWR->CR;
  147. /* Clear PLS[7:5] bits */
  148. tmpreg &= CR_PLS_MASK;
  149. /* Set PLS[7:5] bits according to PWR_PVDLevel value */
  150. tmpreg |= PWR_PVDLevel;
  151. /* Store the new value */
  152. PWR->CR = tmpreg;
  153. }
  154. /**
  155. * @brief Enables or disables the Power Voltage Detector(PVD).
  156. * @note This function is not applicable for STM32F030 devices.
  157. * @param NewState: new state of the PVD.
  158. * This parameter can be: ENABLE or DISABLE.
  159. * @retval None
  160. */
  161. void PWR_PVDCmd(FunctionalState NewState)
  162. {
  163. /* Check the parameters */
  164. assert_param(IS_FUNCTIONAL_STATE(NewState));
  165. if (NewState != DISABLE)
  166. {
  167. /* Enable the PVD */
  168. PWR->CR |= PWR_CR_PVDE;
  169. }
  170. else
  171. {
  172. /* Disable the PVD */
  173. PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_PVDE);
  174. }
  175. }
  176. /**
  177. * @}
  178. */
  179. /** @defgroup PWR_Group3 WakeUp pins configuration functions
  180. * @brief WakeUp pins configuration functions
  181. *
  182. @verbatim
  183. ==============================================================================
  184. ##### WakeUp pin configuration functions #####
  185. ==============================================================================
  186. (+) WakeUp pins are used to wakeup the system from Standby mode. These pins are
  187. forced in input pull down configuration and are active on rising edges.
  188. (+) There are eight WakeUp pins: WakeUp Pin 1 on PA.00 and WakeUp Pin 2 on PC.13.
  189. The following WakeUp pins are only applicable for STM32F072 dvices:
  190. WakeUp Pin 3 on PE.06, WakeUp Pin 4 on PA.02, WakeUp Pin 5 on PC.05,
  191. WakeUp Pin 6 on PB.05, WakeUp Pin 7 on PB.15 and WakeUp Pin 8 on PF.02.
  192. @endverbatim
  193. * @{
  194. */
  195. /**
  196. * @brief Enables or disables the WakeUp Pin functionality.
  197. * @param PWR_WakeUpPin: specifies the WakeUpPin.
  198. * This parameter can be one of the following values
  199. * @arg PWR_WakeUpPin_1
  200. * @arg PWR_WakeUpPin_2
  201. * @arg PWR_WakeUpPin_3, only applicable for STM32F072 devices
  202. * @arg PWR_WakeUpPin_4, only applicable for STM32F072 devices
  203. * @arg PWR_WakeUpPin_5, only applicable for STM32F072 devices
  204. * @arg PWR_WakeUpPin_6, only applicable for STM32F072 devices
  205. * @arg PWR_WakeUpPin_7, only applicable for STM32F072 devices
  206. * @arg PWR_WakeUpPin_8, only applicable for STM32F072 devices
  207. * @param NewState: new state of the WakeUp Pin functionality.
  208. * This parameter can be: ENABLE or DISABLE.
  209. * @retval None
  210. */
  211. void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)
  212. {
  213. /* Check the parameters */
  214. assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin));
  215. assert_param(IS_FUNCTIONAL_STATE(NewState));
  216. if (NewState != DISABLE)
  217. {
  218. /* Enable the EWUPx pin */
  219. PWR->CSR |= PWR_WakeUpPin;
  220. }
  221. else
  222. {
  223. /* Disable the EWUPx pin */
  224. PWR->CSR &= ~PWR_WakeUpPin;
  225. }
  226. }
  227. /**
  228. * @}
  229. */
  230. /** @defgroup PWR_Group4 Low Power modes configuration functions
  231. * @brief Low Power modes configuration functions
  232. *
  233. @verbatim
  234. ==============================================================================
  235. ##### Low Power modes configuration functions #####
  236. ==============================================================================
  237. [..] The devices feature three low-power modes:
  238. (+) Sleep mode: Cortex-M0 core stopped, peripherals kept running.
  239. (+) Stop mode: all clocks are stopped, regulator running, regulator in low power mode
  240. (+) Standby mode: VCORE domain powered off
  241. *** Sleep mode ***
  242. ==================
  243. [..]
  244. (+) Entry:
  245. (++) The Sleep mode is entered by executing the WFE() or WFI() instructions.
  246. (+) Exit:
  247. (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
  248. controller (NVIC) can wake up the device from Sleep mode.
  249. *** Stop mode ***
  250. =================
  251. [..] In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the HSI,
  252. the HSI14 and the HSE RC oscillators are disabled. Internal SRAM and register
  253. contents are preserved.
  254. The voltage regulator can be configured either in normal or low-power mode.
  255. (+) Entry:
  256. (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,)
  257. function with regulator in LowPower or with Regulator ON.
  258. (+) Exit:
  259. (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode
  260. or any internal IPs (I2C, UASRT or CEC) wakeup event.
  261. *** Standby mode ***
  262. ====================
  263. [..] The Standby mode allows to achieve the lowest power consumption. It is based
  264. on the Cortex-M0 deepsleep mode, with the voltage regulator disabled.
  265. The VCORE domain is consequently powered off. The PLL, the HSI, the HSI14
  266. oscillator and the HSE oscillator are also switched off. SRAM and register
  267. contents are lost except for the Backup domain (RTC registers, RTC backup
  268. registers and Standby circuitry).
  269. [..] The voltage regulator is OFF.
  270. (+) Entry:
  271. (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
  272. (+) Exit:
  273. (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
  274. tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
  275. *** Auto-wakeup (AWU) from low-power mode ***
  276. =============================================
  277. [..] The MCU can be woken up from low-power mode by an RTC Alarm event, a tamper
  278. event, a time-stamp event, or a comparator event, without depending on an
  279. external interrupt (Auto-wakeup mode).
  280. (+) RTC auto-wakeup (AWU) from the Stop mode
  281. (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
  282. (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
  283. or Event modes) using the EXTI_Init() function.
  284. (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
  285. (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
  286. and RTC_AlarmCmd() functions.
  287. (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
  288. is necessary to:
  289. (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt
  290. or Event modes) using the EXTI_Init() function.
  291. (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
  292. function.
  293. (+++) Configure the RTC to detect the tamper or time stamp event using the
  294. RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
  295. functions.
  296. (+) RTC auto-wakeup (AWU) from the Standby mode
  297. (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
  298. (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function.
  299. (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
  300. and RTC_AlarmCmd() functions.
  301. (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it
  302. is necessary to:
  303. (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
  304. function.
  305. (+++) Configure the RTC to detect the tamper or time stamp event using the
  306. RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
  307. functions.
  308. (+) Comparator auto-wakeup (AWU) from the Stop mode
  309. (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup
  310. event, it is necessary to:
  311. (+++) Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2
  312. to be sensitive to to the selected edges (falling, rising or falling
  313. and rising) (Interrupt or Event modes) using the EXTI_Init() function.
  314. (+++) Configure the comparator to generate the event.
  315. @endverbatim
  316. * @{
  317. */
  318. /**
  319. * @brief Enters Sleep mode.
  320. * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
  321. * @param PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
  322. * This parameter can be one of the following values:
  323. * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
  324. * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
  325. * @retval None
  326. */
  327. void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry)
  328. {
  329. /* Check the parameters */
  330. assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));
  331. /* Clear SLEEPDEEP bit of Cortex-M0 System Control Register */
  332. SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
  333. /* Select SLEEP mode entry -------------------------------------------------*/
  334. if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)
  335. {
  336. /* Request Wait For Interrupt */
  337. __WFI();
  338. }
  339. else
  340. {
  341. /* Request Wait For Event */
  342. __SEV();
  343. __WFE();
  344. __WFE();
  345. }
  346. }
  347. /**
  348. * @brief Enters STOP mode.
  349. * @note In Stop mode, all I/O pins keep the same state as in Run mode.
  350. * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
  351. * the HSI RC oscillator is selected as system clock.
  352. * @note When the voltage regulator operates in low power mode, an additional
  353. * startup delay is incurred when waking up from Stop mode.
  354. * By keeping the internal regulator ON during Stop mode, the consumption
  355. * is higher although the startup time is reduced.
  356. * @param PWR_Regulator: specifies the regulator state in STOP mode.
  357. * This parameter can be one of the following values:
  358. * @arg PWR_Regulator_ON: STOP mode with regulator ON
  359. * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
  360. * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
  361. * This parameter can be one of the following values:
  362. * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
  363. * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
  364. @arg PWR_STOPEntry_SLEEPONEXIT: enter STOP mode with SLEEPONEXIT instruction
  365. * @retval None
  366. */
  367. void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
  368. {
  369. uint32_t tmpreg = 0;
  370. /* Check the parameters */
  371. assert_param(IS_PWR_REGULATOR(PWR_Regulator));
  372. assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
  373. /* Select the regulator state in STOP mode ---------------------------------*/
  374. tmpreg = PWR->CR;
  375. /* Clear PDDS and LPDSR bits */
  376. tmpreg &= CR_DS_MASK;
  377. /* Set LPDSR bit according to PWR_Regulator value */
  378. tmpreg |= PWR_Regulator;
  379. /* Store the new value */
  380. PWR->CR = tmpreg;
  381. /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */
  382. SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
  383. /* Select STOP mode entry --------------------------------------------------*/
  384. if(PWR_STOPEntry == PWR_STOPEntry_WFI)
  385. {
  386. /* Request Wait For Interrupt */
  387. __WFI();
  388. /* Reset SLEEPDEEP bit of Cortex System Control Register */
  389. SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
  390. }
  391. else if (PWR_STOPEntry == PWR_STOPEntry_WFE)
  392. {
  393. /* Request Wait For Event */
  394. __WFE();
  395. /* Reset SLEEPDEEP bit of Cortex System Control Register */
  396. SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
  397. }
  398. else
  399. {
  400. /* Set SLEEP on exit bit of Cortex-M0 System Control Register */
  401. SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk;
  402. }
  403. }
  404. /**
  405. * @brief Enters STANDBY mode.
  406. * @note In Standby mode, all I/O pins are high impedance except for:
  407. * - Reset pad (still available)
  408. * - RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper,
  409. * time-stamp, RTC Alarm out, or RTC clock calibration out.
  410. * - WKUP pin 1 (PA0) if enabled.
  411. * @note The Wakeup flag (WUF) need to be cleared at application level before to call this function
  412. * @param None
  413. * @retval None
  414. */
  415. void PWR_EnterSTANDBYMode(void)
  416. {
  417. /* Select STANDBY mode */
  418. PWR->CR |= PWR_CR_PDDS;
  419. /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */
  420. SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
  421. /* Request Wait For Interrupt */
  422. __WFI();
  423. }
  424. /**
  425. * @}
  426. */
  427. /** @defgroup PWR_Group5 Flags management functions
  428. * @brief Flags management functions
  429. *
  430. @verbatim
  431. ==============================================================================
  432. ##### Flags management functions #####
  433. ==============================================================================
  434. @endverbatim
  435. * @{
  436. */
  437. /**
  438. * @brief Checks whether the specified PWR flag is set or not.
  439. * @param PWR_FLAG: specifies the flag to check.
  440. * This parameter can be one of the following values:
  441. * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup
  442. * event was received from the WKUP pin or from the RTC alarm
  443. * (Alarm A or Alarm B), RTC Tamper event or RTC TimeStamp event.
  444. * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the
  445. * system was resumed from StandBy mode.
  446. * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD
  447. * is enabled by the PWR_PVDCmd() function.
  448. * @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag.
  449. * This flag indicates the state of the internal voltage
  450. * reference, VREFINT.
  451. * @retval The new state of PWR_FLAG (SET or RESET).
  452. */
  453. FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
  454. {
  455. FlagStatus bitstatus = RESET;
  456. /* Check the parameters */
  457. assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
  458. if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
  459. {
  460. bitstatus = SET;
  461. }
  462. else
  463. {
  464. bitstatus = RESET;
  465. }
  466. /* Return the flag status */
  467. return bitstatus;
  468. }
  469. /**
  470. * @brief Clears the PWR's pending flags.
  471. * @param PWR_FLAG: specifies the flag to clear.
  472. * This parameter can be one of the following values:
  473. * @arg PWR_FLAG_WU: Wake Up flag
  474. * @arg PWR_FLAG_SB: StandBy flag
  475. * @retval None
  476. */
  477. void PWR_ClearFlag(uint32_t PWR_FLAG)
  478. {
  479. /* Check the parameters */
  480. assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
  481. PWR->CR |= PWR_FLAG << 2;
  482. }
  483. /**
  484. * @}
  485. */
  486. /**
  487. * @}
  488. */
  489. /**
  490. * @}
  491. */
  492. /**
  493. * @}
  494. */
  495. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/