stm32f10x_can.c 44 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f10x_can.c
  4. * @author MCD Application Team
  5. * @version V3.5.0
  6. * @date 11-March-2011
  7. * @brief This file provides all the CAN firmware functions.
  8. ******************************************************************************
  9. * @attention
  10. *
  11. * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  12. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  13. * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  14. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  15. * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  16. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  17. *
  18. * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
  19. ******************************************************************************
  20. */
  21. /* Includes ------------------------------------------------------------------*/
  22. #include "stm32f10x_can.h"
  23. #include "stm32f10x_rcc.h"
  24. /** @addtogroup STM32F10x_StdPeriph_Driver
  25. * @{
  26. */
  27. /** @defgroup CAN
  28. * @brief CAN driver modules
  29. * @{
  30. */
  31. /** @defgroup CAN_Private_TypesDefinitions
  32. * @{
  33. */
  34. /**
  35. * @}
  36. */
  37. /** @defgroup CAN_Private_Defines
  38. * @{
  39. */
  40. /* CAN Master Control Register bits */
  41. #define MCR_DBF ((uint32_t)0x00010000) /* software master reset */
  42. /* CAN Mailbox Transmit Request */
  43. #define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */
  44. /* CAN Filter Master Register bits */
  45. #define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */
  46. /* Time out for INAK bit */
  47. #define INAK_TIMEOUT ((uint32_t)0x0000FFFF)
  48. /* Time out for SLAK bit */
  49. #define SLAK_TIMEOUT ((uint32_t)0x0000FFFF)
  50. /* Flags in TSR register */
  51. #define CAN_FLAGS_TSR ((uint32_t)0x08000000)
  52. /* Flags in RF1R register */
  53. #define CAN_FLAGS_RF1R ((uint32_t)0x04000000)
  54. /* Flags in RF0R register */
  55. #define CAN_FLAGS_RF0R ((uint32_t)0x02000000)
  56. /* Flags in MSR register */
  57. #define CAN_FLAGS_MSR ((uint32_t)0x01000000)
  58. /* Flags in ESR register */
  59. #define CAN_FLAGS_ESR ((uint32_t)0x00F00000)
  60. /* Mailboxes definition */
  61. #define CAN_TXMAILBOX_0 ((uint8_t)0x00)
  62. #define CAN_TXMAILBOX_1 ((uint8_t)0x01)
  63. #define CAN_TXMAILBOX_2 ((uint8_t)0x02)
  64. #define CAN_MODE_MASK ((uint32_t) 0x00000003)
  65. /**
  66. * @}
  67. */
  68. /** @defgroup CAN_Private_Macros
  69. * @{
  70. */
  71. /**
  72. * @}
  73. */
  74. /** @defgroup CAN_Private_Variables
  75. * @{
  76. */
  77. /**
  78. * @}
  79. */
  80. /** @defgroup CAN_Private_FunctionPrototypes
  81. * @{
  82. */
  83. static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
  84. /**
  85. * @}
  86. */
  87. /** @defgroup CAN_Private_Functions
  88. * @{
  89. */
  90. /**
  91. * @brief Deinitializes the CAN peripheral registers to their default reset values.
  92. * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
  93. * @retval None.
  94. */
  95. void CAN_DeInit(CAN_TypeDef* CANx)
  96. {
  97. /* Check the parameters */
  98. assert_param(IS_CAN_ALL_PERIPH(CANx));
  99. if (CANx == CAN1)
  100. {
  101. /* Enable CAN1 reset state */
  102. RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE);
  103. /* Release CAN1 from reset state */
  104. RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);
  105. }
  106. else
  107. {
  108. /* Enable CAN2 reset state */
  109. RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE);
  110. /* Release CAN2 from reset state */
  111. RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE);
  112. }
  113. }
  114. /**
  115. * @brief Initializes the CAN peripheral according to the specified
  116. * parameters in the CAN_InitStruct.
  117. * @param CANx: where x can be 1 or 2 to to select the CAN
  118. * peripheral.
  119. * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that
  120. * contains the configuration information for the
  121. * CAN peripheral.
  122. * @retval Constant indicates initialization succeed which will be
  123. * CAN_InitStatus_Failed or CAN_InitStatus_Success.
  124. */
  125. uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
  126. {
  127. uint8_t InitStatus = CAN_InitStatus_Failed;
  128. uint32_t wait_ack = 0x00000000;
  129. /* Check the parameters */
  130. assert_param(IS_CAN_ALL_PERIPH(CANx));
  131. assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
  132. assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
  133. assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
  134. assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
  135. assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
  136. assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
  137. assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
  138. assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
  139. assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
  140. assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
  141. assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
  142. /* Exit from sleep mode */
  143. CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
  144. /* Request initialisation */
  145. CANx->MCR |= CAN_MCR_INRQ ;
  146. /* Wait the acknowledge */
  147. while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
  148. {
  149. wait_ack++;
  150. }
  151. /* Check acknowledge */
  152. if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
  153. {
  154. InitStatus = CAN_InitStatus_Failed;
  155. }
  156. else
  157. {
  158. /* Set the time triggered communication mode */
  159. if (CAN_InitStruct->CAN_TTCM == ENABLE)
  160. {
  161. CANx->MCR |= CAN_MCR_TTCM;
  162. }
  163. else
  164. {
  165. CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM;
  166. }
  167. /* Set the automatic bus-off management */
  168. if (CAN_InitStruct->CAN_ABOM == ENABLE)
  169. {
  170. CANx->MCR |= CAN_MCR_ABOM;
  171. }
  172. else
  173. {
  174. CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM;
  175. }
  176. /* Set the automatic wake-up mode */
  177. if (CAN_InitStruct->CAN_AWUM == ENABLE)
  178. {
  179. CANx->MCR |= CAN_MCR_AWUM;
  180. }
  181. else
  182. {
  183. CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM;
  184. }
  185. /* Set the no automatic retransmission */
  186. if (CAN_InitStruct->CAN_NART == ENABLE)
  187. {
  188. CANx->MCR |= CAN_MCR_NART;
  189. }
  190. else
  191. {
  192. CANx->MCR &= ~(uint32_t)CAN_MCR_NART;
  193. }
  194. /* Set the receive FIFO locked mode */
  195. if (CAN_InitStruct->CAN_RFLM == ENABLE)
  196. {
  197. CANx->MCR |= CAN_MCR_RFLM;
  198. }
  199. else
  200. {
  201. CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM;
  202. }
  203. /* Set the transmit FIFO priority */
  204. if (CAN_InitStruct->CAN_TXFP == ENABLE)
  205. {
  206. CANx->MCR |= CAN_MCR_TXFP;
  207. }
  208. else
  209. {
  210. CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP;
  211. }
  212. /* Set the bit timing register */
  213. CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \
  214. ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \
  215. ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \
  216. ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \
  217. ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
  218. /* Request leave initialisation */
  219. CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ;
  220. /* Wait the acknowledge */
  221. wait_ack = 0;
  222. while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
  223. {
  224. wait_ack++;
  225. }
  226. /* ...and check acknowledged */
  227. if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
  228. {
  229. InitStatus = CAN_InitStatus_Failed;
  230. }
  231. else
  232. {
  233. InitStatus = CAN_InitStatus_Success ;
  234. }
  235. }
  236. /* At this step, return the status of initialization */
  237. return InitStatus;
  238. }
  239. /**
  240. * @brief Initializes the CAN peripheral according to the specified
  241. * parameters in the CAN_FilterInitStruct.
  242. * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef
  243. * structure that contains the configuration
  244. * information.
  245. * @retval None.
  246. */
  247. void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
  248. {
  249. uint32_t filter_number_bit_pos = 0;
  250. /* Check the parameters */
  251. assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
  252. assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
  253. assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
  254. assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
  255. assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
  256. filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber;
  257. /* Initialisation mode for the filter */
  258. CAN1->FMR |= FMR_FINIT;
  259. /* Filter Deactivation */
  260. CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos;
  261. /* Filter Scale */
  262. if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
  263. {
  264. /* 16-bit scale for the filter */
  265. CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos;
  266. /* First 16-bit identifier and First 16-bit mask */
  267. /* Or First 16-bit identifier and Second 16-bit identifier */
  268. CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
  269. ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
  270. (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
  271. /* Second 16-bit identifier and Second 16-bit mask */
  272. /* Or Third 16-bit identifier and Fourth 16-bit identifier */
  273. CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
  274. ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
  275. (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
  276. }
  277. if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
  278. {
  279. /* 32-bit scale for the filter */
  280. CAN1->FS1R |= filter_number_bit_pos;
  281. /* 32-bit identifier or First 32-bit identifier */
  282. CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
  283. ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
  284. (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
  285. /* 32-bit mask or Second 32-bit identifier */
  286. CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
  287. ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
  288. (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
  289. }
  290. /* Filter Mode */
  291. if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
  292. {
  293. /*Id/Mask mode for the filter*/
  294. CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos;
  295. }
  296. else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
  297. {
  298. /*Identifier list mode for the filter*/
  299. CAN1->FM1R |= (uint32_t)filter_number_bit_pos;
  300. }
  301. /* Filter FIFO assignment */
  302. if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0)
  303. {
  304. /* FIFO 0 assignation for the filter */
  305. CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos;
  306. }
  307. if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1)
  308. {
  309. /* FIFO 1 assignation for the filter */
  310. CAN1->FFA1R |= (uint32_t)filter_number_bit_pos;
  311. }
  312. /* Filter activation */
  313. if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
  314. {
  315. CAN1->FA1R |= filter_number_bit_pos;
  316. }
  317. /* Leave the initialisation mode for the filter */
  318. CAN1->FMR &= ~FMR_FINIT;
  319. }
  320. /**
  321. * @brief Fills each CAN_InitStruct member with its default value.
  322. * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which
  323. * will be initialized.
  324. * @retval None.
  325. */
  326. void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
  327. {
  328. /* Reset CAN init structure parameters values */
  329. /* Initialize the time triggered communication mode */
  330. CAN_InitStruct->CAN_TTCM = DISABLE;
  331. /* Initialize the automatic bus-off management */
  332. CAN_InitStruct->CAN_ABOM = DISABLE;
  333. /* Initialize the automatic wake-up mode */
  334. CAN_InitStruct->CAN_AWUM = DISABLE;
  335. /* Initialize the no automatic retransmission */
  336. CAN_InitStruct->CAN_NART = DISABLE;
  337. /* Initialize the receive FIFO locked mode */
  338. CAN_InitStruct->CAN_RFLM = DISABLE;
  339. /* Initialize the transmit FIFO priority */
  340. CAN_InitStruct->CAN_TXFP = DISABLE;
  341. /* Initialize the CAN_Mode member */
  342. CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
  343. /* Initialize the CAN_SJW member */
  344. CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
  345. /* Initialize the CAN_BS1 member */
  346. CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
  347. /* Initialize the CAN_BS2 member */
  348. CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
  349. /* Initialize the CAN_Prescaler member */
  350. CAN_InitStruct->CAN_Prescaler = 1;
  351. }
  352. /**
  353. * @brief Select the start bank filter for slave CAN.
  354. * @note This function applies only to STM32 Connectivity line devices.
  355. * @param CAN_BankNumber: Select the start slave bank filter from 1..27.
  356. * @retval None.
  357. */
  358. void CAN_SlaveStartBank(uint8_t CAN_BankNumber)
  359. {
  360. /* Check the parameters */
  361. assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));
  362. /* Enter Initialisation mode for the filter */
  363. CAN1->FMR |= FMR_FINIT;
  364. /* Select the start slave bank */
  365. CAN1->FMR &= (uint32_t)0xFFFFC0F1 ;
  366. CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8;
  367. /* Leave Initialisation mode for the filter */
  368. CAN1->FMR &= ~FMR_FINIT;
  369. }
  370. /**
  371. * @brief Enables or disables the DBG Freeze for CAN.
  372. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
  373. * @param NewState: new state of the CAN peripheral. This parameter can
  374. * be: ENABLE or DISABLE.
  375. * @retval None.
  376. */
  377. void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)
  378. {
  379. /* Check the parameters */
  380. assert_param(IS_CAN_ALL_PERIPH(CANx));
  381. assert_param(IS_FUNCTIONAL_STATE(NewState));
  382. if (NewState != DISABLE)
  383. {
  384. /* Enable Debug Freeze */
  385. CANx->MCR |= MCR_DBF;
  386. }
  387. else
  388. {
  389. /* Disable Debug Freeze */
  390. CANx->MCR &= ~MCR_DBF;
  391. }
  392. }
  393. /**
  394. * @brief Enables or disabes the CAN Time TriggerOperation communication mode.
  395. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
  396. * @param NewState : Mode new state , can be one of @ref FunctionalState.
  397. * @note when enabled, Time stamp (TIME[15:0]) value is sent in the last
  398. * two data bytes of the 8-byte message: TIME[7:0] in data byte 6
  399. * and TIME[15:8] in data byte 7
  400. * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be
  401. * sent over the CAN bus.
  402. * @retval None
  403. */
  404. void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState)
  405. {
  406. /* Check the parameters */
  407. assert_param(IS_CAN_ALL_PERIPH(CANx));
  408. assert_param(IS_FUNCTIONAL_STATE(NewState));
  409. if (NewState != DISABLE)
  410. {
  411. /* Enable the TTCM mode */
  412. CANx->MCR |= CAN_MCR_TTCM;
  413. /* Set TGT bits */
  414. CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT);
  415. CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT);
  416. CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT);
  417. }
  418. else
  419. {
  420. /* Disable the TTCM mode */
  421. CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM);
  422. /* Reset TGT bits */
  423. CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT);
  424. CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT);
  425. CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT);
  426. }
  427. }
  428. /**
  429. * @brief Initiates the transmission of a message.
  430. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
  431. * @param TxMessage: pointer to a structure which contains CAN Id, CAN
  432. * DLC and CAN data.
  433. * @retval The number of the mailbox that is used for transmission
  434. * or CAN_TxStatus_NoMailBox if there is no empty mailbox.
  435. */
  436. uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)
  437. {
  438. uint8_t transmit_mailbox = 0;
  439. /* Check the parameters */
  440. assert_param(IS_CAN_ALL_PERIPH(CANx));
  441. assert_param(IS_CAN_IDTYPE(TxMessage->IDE));
  442. assert_param(IS_CAN_RTR(TxMessage->RTR));
  443. assert_param(IS_CAN_DLC(TxMessage->DLC));
  444. /* Select one empty transmit mailbox */
  445. if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
  446. {
  447. transmit_mailbox = 0;
  448. }
  449. else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
  450. {
  451. transmit_mailbox = 1;
  452. }
  453. else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
  454. {
  455. transmit_mailbox = 2;
  456. }
  457. else
  458. {
  459. transmit_mailbox = CAN_TxStatus_NoMailBox;
  460. }
  461. if (transmit_mailbox != CAN_TxStatus_NoMailBox)
  462. {
  463. /* Set up the Id */
  464. CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;
  465. if (TxMessage->IDE == CAN_Id_Standard)
  466. {
  467. assert_param(IS_CAN_STDID(TxMessage->StdId));
  468. CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \
  469. TxMessage->RTR);
  470. }
  471. else
  472. {
  473. assert_param(IS_CAN_EXTID(TxMessage->ExtId));
  474. CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \
  475. TxMessage->IDE | \
  476. TxMessage->RTR);
  477. }
  478. /* Set up the DLC */
  479. TxMessage->DLC &= (uint8_t)0x0000000F;
  480. CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;
  481. CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;
  482. /* Set up the data field */
  483. CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) |
  484. ((uint32_t)TxMessage->Data[2] << 16) |
  485. ((uint32_t)TxMessage->Data[1] << 8) |
  486. ((uint32_t)TxMessage->Data[0]));
  487. CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) |
  488. ((uint32_t)TxMessage->Data[6] << 16) |
  489. ((uint32_t)TxMessage->Data[5] << 8) |
  490. ((uint32_t)TxMessage->Data[4]));
  491. /* Request transmission */
  492. CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;
  493. }
  494. return transmit_mailbox;
  495. }
  496. /**
  497. * @brief Checks the transmission of a message.
  498. * @param CANx: where x can be 1 or 2 to to select the
  499. * CAN peripheral.
  500. * @param TransmitMailbox: the number of the mailbox that is used for
  501. * transmission.
  502. * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, CAN_TxStatus_Failed
  503. * in an other case.
  504. */
  505. uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)
  506. {
  507. uint32_t state = 0;
  508. /* Check the parameters */
  509. assert_param(IS_CAN_ALL_PERIPH(CANx));
  510. assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
  511. switch (TransmitMailbox)
  512. {
  513. case (CAN_TXMAILBOX_0):
  514. state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0);
  515. break;
  516. case (CAN_TXMAILBOX_1):
  517. state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1);
  518. break;
  519. case (CAN_TXMAILBOX_2):
  520. state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2);
  521. break;
  522. default:
  523. state = CAN_TxStatus_Failed;
  524. break;
  525. }
  526. switch (state)
  527. {
  528. /* transmit pending */
  529. case (0x0): state = CAN_TxStatus_Pending;
  530. break;
  531. /* transmit failed */
  532. case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed;
  533. break;
  534. case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed;
  535. break;
  536. case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed;
  537. break;
  538. /* transmit succeeded */
  539. case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok;
  540. break;
  541. case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok;
  542. break;
  543. case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok;
  544. break;
  545. default: state = CAN_TxStatus_Failed;
  546. break;
  547. }
  548. return (uint8_t) state;
  549. }
  550. /**
  551. * @brief Cancels a transmit request.
  552. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
  553. * @param Mailbox: Mailbox number.
  554. * @retval None.
  555. */
  556. void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
  557. {
  558. /* Check the parameters */
  559. assert_param(IS_CAN_ALL_PERIPH(CANx));
  560. assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
  561. /* abort transmission */
  562. switch (Mailbox)
  563. {
  564. case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0;
  565. break;
  566. case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1;
  567. break;
  568. case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2;
  569. break;
  570. default:
  571. break;
  572. }
  573. }
  574. /**
  575. * @brief Receives a message.
  576. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
  577. * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
  578. * @param RxMessage: pointer to a structure receive message which contains
  579. * CAN Id, CAN DLC, CAN datas and FMI number.
  580. * @retval None.
  581. */
  582. void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
  583. {
  584. /* Check the parameters */
  585. assert_param(IS_CAN_ALL_PERIPH(CANx));
  586. assert_param(IS_CAN_FIFO(FIFONumber));
  587. /* Get the Id */
  588. RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;
  589. if (RxMessage->IDE == CAN_Id_Standard)
  590. {
  591. RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);
  592. }
  593. else
  594. {
  595. RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);
  596. }
  597. RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;
  598. /* Get the DLC */
  599. RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;
  600. /* Get the FMI */
  601. RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);
  602. /* Get the data field */
  603. RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;
  604. RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);
  605. RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);
  606. RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);
  607. RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;
  608. RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);
  609. RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);
  610. RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);
  611. /* Release the FIFO */
  612. /* Release FIFO0 */
  613. if (FIFONumber == CAN_FIFO0)
  614. {
  615. CANx->RF0R |= CAN_RF0R_RFOM0;
  616. }
  617. /* Release FIFO1 */
  618. else /* FIFONumber == CAN_FIFO1 */
  619. {
  620. CANx->RF1R |= CAN_RF1R_RFOM1;
  621. }
  622. }
  623. /**
  624. * @brief Releases the specified FIFO.
  625. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
  626. * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
  627. * @retval None.
  628. */
  629. void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)
  630. {
  631. /* Check the parameters */
  632. assert_param(IS_CAN_ALL_PERIPH(CANx));
  633. assert_param(IS_CAN_FIFO(FIFONumber));
  634. /* Release FIFO0 */
  635. if (FIFONumber == CAN_FIFO0)
  636. {
  637. CANx->RF0R |= CAN_RF0R_RFOM0;
  638. }
  639. /* Release FIFO1 */
  640. else /* FIFONumber == CAN_FIFO1 */
  641. {
  642. CANx->RF1R |= CAN_RF1R_RFOM1;
  643. }
  644. }
  645. /**
  646. * @brief Returns the number of pending messages.
  647. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
  648. * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
  649. * @retval NbMessage : which is the number of pending message.
  650. */
  651. uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)
  652. {
  653. uint8_t message_pending=0;
  654. /* Check the parameters */
  655. assert_param(IS_CAN_ALL_PERIPH(CANx));
  656. assert_param(IS_CAN_FIFO(FIFONumber));
  657. if (FIFONumber == CAN_FIFO0)
  658. {
  659. message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);
  660. }
  661. else if (FIFONumber == CAN_FIFO1)
  662. {
  663. message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);
  664. }
  665. else
  666. {
  667. message_pending = 0;
  668. }
  669. return message_pending;
  670. }
  671. /**
  672. * @brief Select the CAN Operation mode.
  673. * @param CAN_OperatingMode : CAN Operating Mode. This parameter can be one
  674. * of @ref CAN_OperatingMode_TypeDef enumeration.
  675. * @retval status of the requested mode which can be
  676. * - CAN_ModeStatus_Failed CAN failed entering the specific mode
  677. * - CAN_ModeStatus_Success CAN Succeed entering the specific mode
  678. */
  679. uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode)
  680. {
  681. uint8_t status = CAN_ModeStatus_Failed;
  682. /* Timeout for INAK or also for SLAK bits*/
  683. uint32_t timeout = INAK_TIMEOUT;
  684. /* Check the parameters */
  685. assert_param(IS_CAN_ALL_PERIPH(CANx));
  686. assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode));
  687. if (CAN_OperatingMode == CAN_OperatingMode_Initialization)
  688. {
  689. /* Request initialisation */
  690. CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ);
  691. /* Wait the acknowledge */
  692. while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0))
  693. {
  694. timeout--;
  695. }
  696. if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK)
  697. {
  698. status = CAN_ModeStatus_Failed;
  699. }
  700. else
  701. {
  702. status = CAN_ModeStatus_Success;
  703. }
  704. }
  705. else if (CAN_OperatingMode == CAN_OperatingMode_Normal)
  706. {
  707. /* Request leave initialisation and sleep mode and enter Normal mode */
  708. CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ));
  709. /* Wait the acknowledge */
  710. while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0))
  711. {
  712. timeout--;
  713. }
  714. if ((CANx->MSR & CAN_MODE_MASK) != 0)
  715. {
  716. status = CAN_ModeStatus_Failed;
  717. }
  718. else
  719. {
  720. status = CAN_ModeStatus_Success;
  721. }
  722. }
  723. else if (CAN_OperatingMode == CAN_OperatingMode_Sleep)
  724. {
  725. /* Request Sleep mode */
  726. CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
  727. /* Wait the acknowledge */
  728. while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0))
  729. {
  730. timeout--;
  731. }
  732. if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK)
  733. {
  734. status = CAN_ModeStatus_Failed;
  735. }
  736. else
  737. {
  738. status = CAN_ModeStatus_Success;
  739. }
  740. }
  741. else
  742. {
  743. status = CAN_ModeStatus_Failed;
  744. }
  745. return (uint8_t) status;
  746. }
  747. /**
  748. * @brief Enters the low power mode.
  749. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
  750. * @retval status: CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed in an
  751. * other case.
  752. */
  753. uint8_t CAN_Sleep(CAN_TypeDef* CANx)
  754. {
  755. uint8_t sleepstatus = CAN_Sleep_Failed;
  756. /* Check the parameters */
  757. assert_param(IS_CAN_ALL_PERIPH(CANx));
  758. /* Request Sleep mode */
  759. CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
  760. /* Sleep mode status */
  761. if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)
  762. {
  763. /* Sleep mode not entered */
  764. sleepstatus = CAN_Sleep_Ok;
  765. }
  766. /* return sleep mode status */
  767. return (uint8_t)sleepstatus;
  768. }
  769. /**
  770. * @brief Wakes the CAN up.
  771. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
  772. * @retval status: CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed in an
  773. * other case.
  774. */
  775. uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
  776. {
  777. uint32_t wait_slak = SLAK_TIMEOUT;
  778. uint8_t wakeupstatus = CAN_WakeUp_Failed;
  779. /* Check the parameters */
  780. assert_param(IS_CAN_ALL_PERIPH(CANx));
  781. /* Wake up request */
  782. CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
  783. /* Sleep mode status */
  784. while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))
  785. {
  786. wait_slak--;
  787. }
  788. if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)
  789. {
  790. /* wake up done : Sleep mode exited */
  791. wakeupstatus = CAN_WakeUp_Ok;
  792. }
  793. /* return wakeup status */
  794. return (uint8_t)wakeupstatus;
  795. }
  796. /**
  797. * @brief Returns the CANx's last error code (LEC).
  798. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
  799. * @retval CAN_ErrorCode: specifies the Error code :
  800. * - CAN_ERRORCODE_NoErr No Error
  801. * - CAN_ERRORCODE_StuffErr Stuff Error
  802. * - CAN_ERRORCODE_FormErr Form Error
  803. * - CAN_ERRORCODE_ACKErr Acknowledgment Error
  804. * - CAN_ERRORCODE_BitRecessiveErr Bit Recessive Error
  805. * - CAN_ERRORCODE_BitDominantErr Bit Dominant Error
  806. * - CAN_ERRORCODE_CRCErr CRC Error
  807. * - CAN_ERRORCODE_SoftwareSetErr Software Set Error
  808. */
  809. uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx)
  810. {
  811. uint8_t errorcode=0;
  812. /* Check the parameters */
  813. assert_param(IS_CAN_ALL_PERIPH(CANx));
  814. /* Get the error code*/
  815. errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC);
  816. /* Return the error code*/
  817. return errorcode;
  818. }
  819. /**
  820. * @brief Returns the CANx Receive Error Counter (REC).
  821. * @note In case of an error during reception, this counter is incremented
  822. * by 1 or by 8 depending on the error condition as defined by the CAN
  823. * standard. After every successful reception, the counter is
  824. * decremented by 1 or reset to 120 if its value was higher than 128.
  825. * When the counter value exceeds 127, the CAN controller enters the
  826. * error passive state.
  827. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
  828. * @retval CAN Receive Error Counter.
  829. */
  830. uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx)
  831. {
  832. uint8_t counter=0;
  833. /* Check the parameters */
  834. assert_param(IS_CAN_ALL_PERIPH(CANx));
  835. /* Get the Receive Error Counter*/
  836. counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24);
  837. /* Return the Receive Error Counter*/
  838. return counter;
  839. }
  840. /**
  841. * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
  842. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
  843. * @retval LSB of the 9-bit CAN Transmit Error Counter.
  844. */
  845. uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx)
  846. {
  847. uint8_t counter=0;
  848. /* Check the parameters */
  849. assert_param(IS_CAN_ALL_PERIPH(CANx));
  850. /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
  851. counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16);
  852. /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
  853. return counter;
  854. }
  855. /**
  856. * @brief Enables or disables the specified CANx interrupts.
  857. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
  858. * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
  859. * This parameter can be:
  860. * - CAN_IT_TME,
  861. * - CAN_IT_FMP0,
  862. * - CAN_IT_FF0,
  863. * - CAN_IT_FOV0,
  864. * - CAN_IT_FMP1,
  865. * - CAN_IT_FF1,
  866. * - CAN_IT_FOV1,
  867. * - CAN_IT_EWG,
  868. * - CAN_IT_EPV,
  869. * - CAN_IT_LEC,
  870. * - CAN_IT_ERR,
  871. * - CAN_IT_WKU or
  872. * - CAN_IT_SLK.
  873. * @param NewState: new state of the CAN interrupts.
  874. * This parameter can be: ENABLE or DISABLE.
  875. * @retval None.
  876. */
  877. void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
  878. {
  879. /* Check the parameters */
  880. assert_param(IS_CAN_ALL_PERIPH(CANx));
  881. assert_param(IS_CAN_IT(CAN_IT));
  882. assert_param(IS_FUNCTIONAL_STATE(NewState));
  883. if (NewState != DISABLE)
  884. {
  885. /* Enable the selected CANx interrupt */
  886. CANx->IER |= CAN_IT;
  887. }
  888. else
  889. {
  890. /* Disable the selected CANx interrupt */
  891. CANx->IER &= ~CAN_IT;
  892. }
  893. }
  894. /**
  895. * @brief Checks whether the specified CAN flag is set or not.
  896. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
  897. * @param CAN_FLAG: specifies the flag to check.
  898. * This parameter can be one of the following flags:
  899. * - CAN_FLAG_EWG
  900. * - CAN_FLAG_EPV
  901. * - CAN_FLAG_BOF
  902. * - CAN_FLAG_RQCP0
  903. * - CAN_FLAG_RQCP1
  904. * - CAN_FLAG_RQCP2
  905. * - CAN_FLAG_FMP1
  906. * - CAN_FLAG_FF1
  907. * - CAN_FLAG_FOV1
  908. * - CAN_FLAG_FMP0
  909. * - CAN_FLAG_FF0
  910. * - CAN_FLAG_FOV0
  911. * - CAN_FLAG_WKU
  912. * - CAN_FLAG_SLAK
  913. * - CAN_FLAG_LEC
  914. * @retval The new state of CAN_FLAG (SET or RESET).
  915. */
  916. FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
  917. {
  918. FlagStatus bitstatus = RESET;
  919. /* Check the parameters */
  920. assert_param(IS_CAN_ALL_PERIPH(CANx));
  921. assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
  922. if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET)
  923. {
  924. /* Check the status of the specified CAN flag */
  925. if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
  926. {
  927. /* CAN_FLAG is set */
  928. bitstatus = SET;
  929. }
  930. else
  931. {
  932. /* CAN_FLAG is reset */
  933. bitstatus = RESET;
  934. }
  935. }
  936. else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET)
  937. {
  938. /* Check the status of the specified CAN flag */
  939. if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
  940. {
  941. /* CAN_FLAG is set */
  942. bitstatus = SET;
  943. }
  944. else
  945. {
  946. /* CAN_FLAG is reset */
  947. bitstatus = RESET;
  948. }
  949. }
  950. else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET)
  951. {
  952. /* Check the status of the specified CAN flag */
  953. if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
  954. {
  955. /* CAN_FLAG is set */
  956. bitstatus = SET;
  957. }
  958. else
  959. {
  960. /* CAN_FLAG is reset */
  961. bitstatus = RESET;
  962. }
  963. }
  964. else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET)
  965. {
  966. /* Check the status of the specified CAN flag */
  967. if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
  968. {
  969. /* CAN_FLAG is set */
  970. bitstatus = SET;
  971. }
  972. else
  973. {
  974. /* CAN_FLAG is reset */
  975. bitstatus = RESET;
  976. }
  977. }
  978. else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */
  979. {
  980. /* Check the status of the specified CAN flag */
  981. if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
  982. {
  983. /* CAN_FLAG is set */
  984. bitstatus = SET;
  985. }
  986. else
  987. {
  988. /* CAN_FLAG is reset */
  989. bitstatus = RESET;
  990. }
  991. }
  992. /* Return the CAN_FLAG status */
  993. return bitstatus;
  994. }
  995. /**
  996. * @brief Clears the CAN's pending flags.
  997. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
  998. * @param CAN_FLAG: specifies the flag to clear.
  999. * This parameter can be one of the following flags:
  1000. * - CAN_FLAG_RQCP0
  1001. * - CAN_FLAG_RQCP1
  1002. * - CAN_FLAG_RQCP2
  1003. * - CAN_FLAG_FF1
  1004. * - CAN_FLAG_FOV1
  1005. * - CAN_FLAG_FF0
  1006. * - CAN_FLAG_FOV0
  1007. * - CAN_FLAG_WKU
  1008. * - CAN_FLAG_SLAK
  1009. * - CAN_FLAG_LEC
  1010. * @retval None.
  1011. */
  1012. void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
  1013. {
  1014. uint32_t flagtmp=0;
  1015. /* Check the parameters */
  1016. assert_param(IS_CAN_ALL_PERIPH(CANx));
  1017. assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));
  1018. if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */
  1019. {
  1020. /* Clear the selected CAN flags */
  1021. CANx->ESR = (uint32_t)RESET;
  1022. }
  1023. else /* MSR or TSR or RF0R or RF1R */
  1024. {
  1025. flagtmp = CAN_FLAG & 0x000FFFFF;
  1026. if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET)
  1027. {
  1028. /* Receive Flags */
  1029. CANx->RF0R = (uint32_t)(flagtmp);
  1030. }
  1031. else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET)
  1032. {
  1033. /* Receive Flags */
  1034. CANx->RF1R = (uint32_t)(flagtmp);
  1035. }
  1036. else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET)
  1037. {
  1038. /* Transmit Flags */
  1039. CANx->TSR = (uint32_t)(flagtmp);
  1040. }
  1041. else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */
  1042. {
  1043. /* Operating mode Flags */
  1044. CANx->MSR = (uint32_t)(flagtmp);
  1045. }
  1046. }
  1047. }
  1048. /**
  1049. * @brief Checks whether the specified CANx interrupt has occurred or not.
  1050. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
  1051. * @param CAN_IT: specifies the CAN interrupt source to check.
  1052. * This parameter can be one of the following flags:
  1053. * - CAN_IT_TME
  1054. * - CAN_IT_FMP0
  1055. * - CAN_IT_FF0
  1056. * - CAN_IT_FOV0
  1057. * - CAN_IT_FMP1
  1058. * - CAN_IT_FF1
  1059. * - CAN_IT_FOV1
  1060. * - CAN_IT_WKU
  1061. * - CAN_IT_SLK
  1062. * - CAN_IT_EWG
  1063. * - CAN_IT_EPV
  1064. * - CAN_IT_BOF
  1065. * - CAN_IT_LEC
  1066. * - CAN_IT_ERR
  1067. * @retval The current state of CAN_IT (SET or RESET).
  1068. */
  1069. ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
  1070. {
  1071. ITStatus itstatus = RESET;
  1072. /* Check the parameters */
  1073. assert_param(IS_CAN_ALL_PERIPH(CANx));
  1074. assert_param(IS_CAN_IT(CAN_IT));
  1075. /* check the enable interrupt bit */
  1076. if((CANx->IER & CAN_IT) != RESET)
  1077. {
  1078. /* in case the Interrupt is enabled, .... */
  1079. switch (CAN_IT)
  1080. {
  1081. case CAN_IT_TME:
  1082. /* Check CAN_TSR_RQCPx bits */
  1083. itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2);
  1084. break;
  1085. case CAN_IT_FMP0:
  1086. /* Check CAN_RF0R_FMP0 bit */
  1087. itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0);
  1088. break;
  1089. case CAN_IT_FF0:
  1090. /* Check CAN_RF0R_FULL0 bit */
  1091. itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0);
  1092. break;
  1093. case CAN_IT_FOV0:
  1094. /* Check CAN_RF0R_FOVR0 bit */
  1095. itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0);
  1096. break;
  1097. case CAN_IT_FMP1:
  1098. /* Check CAN_RF1R_FMP1 bit */
  1099. itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1);
  1100. break;
  1101. case CAN_IT_FF1:
  1102. /* Check CAN_RF1R_FULL1 bit */
  1103. itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1);
  1104. break;
  1105. case CAN_IT_FOV1:
  1106. /* Check CAN_RF1R_FOVR1 bit */
  1107. itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1);
  1108. break;
  1109. case CAN_IT_WKU:
  1110. /* Check CAN_MSR_WKUI bit */
  1111. itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI);
  1112. break;
  1113. case CAN_IT_SLK:
  1114. /* Check CAN_MSR_SLAKI bit */
  1115. itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI);
  1116. break;
  1117. case CAN_IT_EWG:
  1118. /* Check CAN_ESR_EWGF bit */
  1119. itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF);
  1120. break;
  1121. case CAN_IT_EPV:
  1122. /* Check CAN_ESR_EPVF bit */
  1123. itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF);
  1124. break;
  1125. case CAN_IT_BOF:
  1126. /* Check CAN_ESR_BOFF bit */
  1127. itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF);
  1128. break;
  1129. case CAN_IT_LEC:
  1130. /* Check CAN_ESR_LEC bit */
  1131. itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC);
  1132. break;
  1133. case CAN_IT_ERR:
  1134. /* Check CAN_MSR_ERRI bit */
  1135. itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI);
  1136. break;
  1137. default :
  1138. /* in case of error, return RESET */
  1139. itstatus = RESET;
  1140. break;
  1141. }
  1142. }
  1143. else
  1144. {
  1145. /* in case the Interrupt is not enabled, return RESET */
  1146. itstatus = RESET;
  1147. }
  1148. /* Return the CAN_IT status */
  1149. return itstatus;
  1150. }
  1151. /**
  1152. * @brief Clears the CANx's interrupt pending bits.
  1153. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
  1154. * @param CAN_IT: specifies the interrupt pending bit to clear.
  1155. * - CAN_IT_TME
  1156. * - CAN_IT_FF0
  1157. * - CAN_IT_FOV0
  1158. * - CAN_IT_FF1
  1159. * - CAN_IT_FOV1
  1160. * - CAN_IT_WKU
  1161. * - CAN_IT_SLK
  1162. * - CAN_IT_EWG
  1163. * - CAN_IT_EPV
  1164. * - CAN_IT_BOF
  1165. * - CAN_IT_LEC
  1166. * - CAN_IT_ERR
  1167. * @retval None.
  1168. */
  1169. void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)
  1170. {
  1171. /* Check the parameters */
  1172. assert_param(IS_CAN_ALL_PERIPH(CANx));
  1173. assert_param(IS_CAN_CLEAR_IT(CAN_IT));
  1174. switch (CAN_IT)
  1175. {
  1176. case CAN_IT_TME:
  1177. /* Clear CAN_TSR_RQCPx (rc_w1)*/
  1178. CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2;
  1179. break;
  1180. case CAN_IT_FF0:
  1181. /* Clear CAN_RF0R_FULL0 (rc_w1)*/
  1182. CANx->RF0R = CAN_RF0R_FULL0;
  1183. break;
  1184. case CAN_IT_FOV0:
  1185. /* Clear CAN_RF0R_FOVR0 (rc_w1)*/
  1186. CANx->RF0R = CAN_RF0R_FOVR0;
  1187. break;
  1188. case CAN_IT_FF1:
  1189. /* Clear CAN_RF1R_FULL1 (rc_w1)*/
  1190. CANx->RF1R = CAN_RF1R_FULL1;
  1191. break;
  1192. case CAN_IT_FOV1:
  1193. /* Clear CAN_RF1R_FOVR1 (rc_w1)*/
  1194. CANx->RF1R = CAN_RF1R_FOVR1;
  1195. break;
  1196. case CAN_IT_WKU:
  1197. /* Clear CAN_MSR_WKUI (rc_w1)*/
  1198. CANx->MSR = CAN_MSR_WKUI;
  1199. break;
  1200. case CAN_IT_SLK:
  1201. /* Clear CAN_MSR_SLAKI (rc_w1)*/
  1202. CANx->MSR = CAN_MSR_SLAKI;
  1203. break;
  1204. case CAN_IT_EWG:
  1205. /* Clear CAN_MSR_ERRI (rc_w1) */
  1206. CANx->MSR = CAN_MSR_ERRI;
  1207. /* Note : the corresponding Flag is cleared by hardware depending
  1208. of the CAN Bus status*/
  1209. break;
  1210. case CAN_IT_EPV:
  1211. /* Clear CAN_MSR_ERRI (rc_w1) */
  1212. CANx->MSR = CAN_MSR_ERRI;
  1213. /* Note : the corresponding Flag is cleared by hardware depending
  1214. of the CAN Bus status*/
  1215. break;
  1216. case CAN_IT_BOF:
  1217. /* Clear CAN_MSR_ERRI (rc_w1) */
  1218. CANx->MSR = CAN_MSR_ERRI;
  1219. /* Note : the corresponding Flag is cleared by hardware depending
  1220. of the CAN Bus status*/
  1221. break;
  1222. case CAN_IT_LEC:
  1223. /* Clear LEC bits */
  1224. CANx->ESR = RESET;
  1225. /* Clear CAN_MSR_ERRI (rc_w1) */
  1226. CANx->MSR = CAN_MSR_ERRI;
  1227. break;
  1228. case CAN_IT_ERR:
  1229. /*Clear LEC bits */
  1230. CANx->ESR = RESET;
  1231. /* Clear CAN_MSR_ERRI (rc_w1) */
  1232. CANx->MSR = CAN_MSR_ERRI;
  1233. /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending
  1234. of the CAN Bus status*/
  1235. break;
  1236. default :
  1237. break;
  1238. }
  1239. }
  1240. /**
  1241. * @brief Checks whether the CAN interrupt has occurred or not.
  1242. * @param CAN_Reg: specifies the CAN interrupt register to check.
  1243. * @param It_Bit: specifies the interrupt source bit to check.
  1244. * @retval The new state of the CAN Interrupt (SET or RESET).
  1245. */
  1246. static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
  1247. {
  1248. ITStatus pendingbitstatus = RESET;
  1249. if ((CAN_Reg & It_Bit) != (uint32_t)RESET)
  1250. {
  1251. /* CAN_IT is set */
  1252. pendingbitstatus = SET;
  1253. }
  1254. else
  1255. {
  1256. /* CAN_IT is reset */
  1257. pendingbitstatus = RESET;
  1258. }
  1259. return pendingbitstatus;
  1260. }
  1261. /**
  1262. * @}
  1263. */
  1264. /**
  1265. * @}
  1266. */
  1267. /**
  1268. * @}
  1269. */
  1270. /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/