Protel Design System Design Rule Check
PCB File : C:\Users\vladi\OneDrive\Рабочий стол\BIAS_TGA2237-SM\PCB1.PcbDoc
Date     : 16.09.2024
Time     : 18:45:08

Processing Rule : Clearance Constraint (Gap=15.748mil) (All),(All)
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=15.748mil) (InNet('GND')),(All)
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
Rule Violations :0

Processing Rule : Width Constraint (Min=10mil) (Max=50mil) (Preferred=25mil) (All)
Rule Violations :0

Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
Rule Violations :0

Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (All)
Rule Violations :0

Processing Rule : Hole To Hole Clearance (Gap=10mil) (All),(All)
Rule Violations :0

Processing Rule : Minimum Solder Mask Sliver (Gap=7.874mil) (All),(All)
Rule Violations :0

Processing Rule : Silk To Solder Mask (Clearance=7.874mil) (Disabled)(IsPad),(All)
Rule Violations :0

Processing Rule : Silk to Silk (Clearance=10mil) (Disabled)(All),(All)
Rule Violations :0

Processing Rule : Net Antennae (Tolerance=0mil) (All)
Rule Violations :0

Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
Rule Violations :0


Violations Detected : 0
Waived Violations : 0
Time Elapsed        : 00:00:01