Protel Design System Design Rule Check
PCB File : C:\Users\Vlad\Documents\BIAS_TGA2237-SM\PCB1.PcbDoc
Date     : 05.09.2024
Time     : 15:27:09

Processing Rule : Clearance Constraint (Gap=0.3mm) (All),(All)
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=0.381mm) (InNet('GND')),(All)
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
Rule Violations :0

Processing Rule : Width Constraint (Min=0.254mm) (Max=1.27mm) (Preferred=0.635mm) (All)
Rule Violations :0

Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0

Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
Rule Violations :0

Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
Rule Violations :0

Processing Rule : Minimum Solder Mask Sliver (Gap=0.2mm) (All),(All)
Rule Violations :0

Processing Rule : Silk To Solder Mask (Clearance=0.2mm) (Disabled)(IsPad),(All)
Rule Violations :0

Processing Rule : Silk to Silk (Clearance=0.254mm) (Disabled)(All),(All)
Rule Violations :0

Processing Rule : Net Antennae (Tolerance=0mm) (All)
Rule Violations :0

Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0


Violations Detected : 0
Waived Violations : 0
Time Elapsed        : 00:00:01