# Design Rule Verification Report

Date: |  | 27.07.2024
Time: |  | 16:24:11
Elapsed Time: |  | 00:00:01
Filename: |  | C:\Users\Vlad\Documents\BIAS_TGA2237-SM\PCB1.PcbDoc

Warnings: |  | 0
Rule Violations: |  | 3

## Summary

Warnings | Count
--- | ---
Total | 0

Rule Violations | Count
--- | ---
Clearance Constraint (Gap=0.254mm) (All),(All) | 0
Short-Circuit Constraint (Allowed=No) (All),(All) | 0
Un-Routed Net Constraint ( (All) ) | 1
Modified Polygon (Allow modified: No), (Allow shelved: No) | 0
Width Constraint (Min=0.254mm) (Max=1.27mm) (Preferred=0.508mm) (All) | 0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) | 0
Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All) | 0
Hole To Hole Clearance (Gap=0.254mm) (All),(All) | 0
Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All) | 2
Silk To Solder Mask (Clearance=0.254mm) (Disabled)(IsPad),(All) | 0
Silk to Silk (Clearance=0.254mm) (Disabled)(All),(All) | 0
Net Antennae (Tolerance=0mm) (All) | 0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) | 0
Total | 3

Un-Routed Net Constraint ( (All) )
Un-Routed Net Constraint: Net GND Between Track (16.768mm,15.688mm)(17.335mm,16.256mm) on Top Layer And Pad C8-1(17.074mm,11.605mm) on Top Layer [Unplated]

Back to top

Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
Minimum Solder Mask Sliver Constraint: (0.25mm < 0.254mm) Between Pad DD1-1(5.364mm,8.802mm) on Top Layer And Pad DD1-2(5.364mm,9.752mm) on Top Layer [Top Solder] Mask Sliver [0.25mm]
Minimum Solder Mask Sliver Constraint: (0.25mm < 0.254mm) Between Pad DD1-2(5.364mm,9.752mm) on Top Layer And Pad DD1-3(5.364mm,10.702mm) on Top Layer [Top Solder] Mask Sliver [0.25mm]

Back to top