Design Rule Verification Report
Date:
16.09.2024
Time:
18:45:08
Elapsed Time:
00:00:01
Filename:
C:\Users\vladi\OneDrive\Рабочий стол\BIAS_TGA2237-SM\PCB1.PcbDoc
Warnings:
0
Rule Violations:
0
Summary
Warnings
Count
Total
0
Rule Violations
Count
Clearance Constraint (Gap=15.748mil) (All),(All)
0
Clearance Constraint (Gap=15.748mil) (InNet('GND')),(All)
0
Short-Circuit Constraint (Allowed=No) (All),(All)
0
Un-Routed Net Constraint ( (All) )
0
Modified Polygon (Allow modified: No), (Allow shelved: No)
0
Width Constraint (Min=10mil) (Max=50mil) (Preferred=25mil) (All)
0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
0
Hole Size Constraint (Min=1mil) (Max=100mil) (All)
0
Hole To Hole Clearance (Gap=10mil) (All),(All)
0
Minimum Solder Mask Sliver (Gap=7.874mil) (All),(All)
0
Silk To Solder Mask (Clearance=7.874mil) (Disabled)(IsPad),(All)
0
Silk to Silk (Clearance=10mil) (Disabled)(All),(All)
0
Net Antennae (Tolerance=0mil) (All)
0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
0
Total
0