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@@ -1,10 +1,7 @@
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Protel Design System Design Rule Check
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PCB File : C:\Users\Vlad\Documents\BIAS_TGA2237-SM\PCB1.PcbDoc
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-Date : 24.07.2024
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-Time : 8:18:32
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-
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-WARNING: Design contains shelved or modified (but not repoured) polygons. The result of DRC is not correct. Recommended to restore/repour all polygons and proceed with DRC again
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- Polygon named: NONET_L01_P000 In net GND On Top Layer
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+Date : 27.07.2024
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+Time : 16:24:11
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Processing Rule : Clearance Constraint (Gap=0.254mm) (All),(All)
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Rule Violations :0
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@@ -13,11 +10,11 @@ Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
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Rule Violations :0
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Processing Rule : Un-Routed Net Constraint ( (All) )
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-Rule Violations :0
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+ Violation between Un-Routed Net Constraint: Net GND Between Track (16.768mm,15.688mm)(17.335mm,16.256mm) on Top Layer And Pad C8-1(17.074mm,11.605mm) on Top Layer [Unplated]
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+Rule Violations :1
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Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
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- Violation between Modified Polygon: Polygon Shelved (NONET_L01_P000) on Top Layer
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-Rule Violations :1
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+Rule Violations :0
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Processing Rule : Width Constraint (Min=0.254mm) (Max=1.27mm) (Preferred=0.508mm) (All)
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Rule Violations :0
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@@ -32,109 +29,15 @@ Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
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Rule Violations :0
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Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
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- Violation between Minimum Solder Mask Sliver Constraint: (0.25mm < 0.254mm) Between Pad DD1-1(41.295mm,11.248mm) on Top Layer And Pad DD1-2(41.295mm,10.298mm) on Top Layer [Top Solder] Mask Sliver [0.25mm]
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- Violation between Minimum Solder Mask Sliver Constraint: (0.25mm < 0.254mm) Between Pad DD1-2(41.295mm,10.298mm) on Top Layer And Pad DD1-3(41.295mm,9.348mm) on Top Layer [Top Solder] Mask Sliver [0.25mm]
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+ Violation between Minimum Solder Mask Sliver Constraint: (0.25mm < 0.254mm) Between Pad DD1-1(5.364mm,8.802mm) on Top Layer And Pad DD1-2(5.364mm,9.752mm) on Top Layer [Top Solder] Mask Sliver [0.25mm]
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+ Violation between Minimum Solder Mask Sliver Constraint: (0.25mm < 0.254mm) Between Pad DD1-2(5.364mm,9.752mm) on Top Layer And Pad DD1-3(5.364mm,10.702mm) on Top Layer [Top Solder] Mask Sliver [0.25mm]
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Rule Violations :2
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-Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C10-1(37.852mm,9.319mm) on Top Layer And Track (37.09mm,9.827mm)(37.09mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C10-1(37.852mm,9.319mm) on Top Layer And Track (37.09mm,9.827mm)(37.09mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.203mm < 0.254mm) Between Pad C10-1(37.852mm,9.319mm) on Top Layer And Track (38.608mm,9.89mm)(38.608mm,10.398mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.203mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C10-1(37.852mm,9.319mm) on Top Layer And Track (38.614mm,9.827mm)(38.614mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C10-2(37.852mm,10.906mm) on Top Layer And Track (37.09mm,9.827mm)(37.09mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C10-2(37.852mm,10.906mm) on Top Layer And Track (37.09mm,9.827mm)(37.09mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.185mm < 0.254mm) Between Pad C10-2(37.852mm,10.906mm) on Top Layer And Track (38.608mm,9.89mm)(38.608mm,10.398mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.185mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C10-2(37.852mm,10.906mm) on Top Layer And Track (38.614mm,9.827mm)(38.614mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C3-1(32.512mm,3.8mm) on Top Layer And Track (31.496mm,3.038mm)(32.004mm,3.038mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C3-1(32.512mm,3.8mm) on Top Layer And Track (31.496mm,4.562mm)(32.004mm,4.562mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C3-2(30.924mm,3.8mm) on Top Layer And Track (31.496mm,3.038mm)(32.004mm,3.038mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C3-2(30.924mm,3.8mm) on Top Layer And Track (31.496mm,4.562mm)(32.004mm,4.562mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C4-1(16.51mm,10.404mm) on Top Layer And Track (15.748mm,9.388mm)(15.748mm,9.896mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C4-1(16.51mm,10.404mm) on Top Layer And Track (17.272mm,9.388mm)(17.272mm,9.896mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C4-2(16.51mm,8.816mm) on Top Layer And Track (15.748mm,9.388mm)(15.748mm,9.896mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C4-2(16.51mm,8.816mm) on Top Layer And Track (17.272mm,9.388mm)(17.272mm,9.896mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C7-1(19.558mm,5.07mm) on Top Layer And Track (18.796mm,4.054mm)(18.796mm,4.562mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C7-1(19.558mm,5.07mm) on Top Layer And Track (20.32mm,4.054mm)(20.32mm,4.562mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C7-2(19.558mm,3.482mm) on Top Layer And Track (18.796mm,4.054mm)(18.796mm,4.562mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C7-2(19.558mm,3.482mm) on Top Layer And Track (20.32mm,4.054mm)(20.32mm,4.562mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C8-1(34.804mm,9.319mm) on Top Layer And Track (34.042mm,9.827mm)(34.042mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C8-1(34.804mm,9.319mm) on Top Layer And Track (35.566mm,9.827mm)(35.566mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C8-1(34.804mm,9.319mm) on Top Layer And Track (35.566mm,9.827mm)(35.566mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C8-2(34.804mm,10.906mm) on Top Layer And Track (34.042mm,9.827mm)(34.042mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C8-2(34.804mm,10.906mm) on Top Layer And Track (35.566mm,9.827mm)(35.566mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C8-2(34.804mm,10.906mm) on Top Layer And Track (35.566mm,9.827mm)(35.566mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C9-1(36.328mm,9.319mm) on Top Layer And Track (35.566mm,9.827mm)(35.566mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C9-1(36.328mm,9.319mm) on Top Layer And Track (35.566mm,9.827mm)(35.566mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C9-1(36.328mm,9.319mm) on Top Layer And Track (37.09mm,9.827mm)(37.09mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C9-1(36.328mm,9.319mm) on Top Layer And Track (37.09mm,9.827mm)(37.09mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C9-2(36.328mm,10.906mm) on Top Layer And Track (35.566mm,9.827mm)(35.566mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C9-2(36.328mm,10.906mm) on Top Layer And Track (35.566mm,9.827mm)(35.566mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C9-2(36.328mm,10.906mm) on Top Layer And Track (37.09mm,9.827mm)(37.09mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C9-2(36.328mm,10.906mm) on Top Layer And Track (37.09mm,9.827mm)(37.09mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-1(9.226mm,7.229mm) on Top Layer And Track (10.338mm,2.874mm)(10.338mm,7.774mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-1(9.226mm,7.229mm) on Top Layer And Track (8.463mm,7.904mm)(9.988mm,7.904mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-2(9.226mm,5.959mm) on Top Layer And Track (10.338mm,2.874mm)(10.338mm,7.774mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-3(9.226mm,4.689mm) on Top Layer And Track (10.338mm,2.874mm)(10.338mm,7.774mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-4(9.226mm,3.419mm) on Top Layer And Track (10.338mm,2.874mm)(10.338mm,7.774mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-5(14.65mm,3.419mm) on Top Layer And Track (13.538mm,2.874mm)(13.538mm,7.774mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-6(14.65mm,4.689mm) on Top Layer And Track (13.538mm,2.874mm)(13.538mm,7.774mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-7(14.65mm,5.959mm) on Top Layer And Track (13.538mm,2.874mm)(13.538mm,7.774mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-8(14.65mm,7.229mm) on Top Layer And Track (13.538mm,2.874mm)(13.538mm,7.774mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.229mm < 0.254mm) Between Pad DA2-1(23.45mm,7.483mm) on Top Layer And Track (22.352mm,6.53mm)(22.352mm,7.038mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.229mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA2-1(23.45mm,7.483mm) on Top Layer And Track (22.687mm,8.158mm)(24.212mm,8.158mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA2-1(23.45mm,7.483mm) on Top Layer And Track (24.562mm,3.128mm)(24.562mm,8.028mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad DA2-2(23.45mm,6.213mm) on Top Layer And Track (22.352mm,6.53mm)(22.352mm,7.038mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA2-2(23.45mm,6.213mm) on Top Layer And Track (24.562mm,3.128mm)(24.562mm,8.028mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA2-3(23.45mm,4.943mm) on Top Layer And Track (24.562mm,3.128mm)(24.562mm,8.028mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA2-4(23.45mm,3.673mm) on Top Layer And Track (24.562mm,3.128mm)(24.562mm,8.028mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA2-5(28.874mm,3.673mm) on Top Layer And Track (27.762mm,3.128mm)(27.762mm,8.028mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA2-6(28.874mm,4.943mm) on Top Layer And Track (27.762mm,3.128mm)(27.762mm,8.028mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA2-7(28.874mm,6.213mm) on Top Layer And Track (27.762mm,3.128mm)(27.762mm,8.028mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA2-8(28.874mm,7.483mm) on Top Layer And Track (27.762mm,3.128mm)(27.762mm,8.028mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R1-1(39.37mm,9.382mm) on Top Layer And Track (38.608mm,9.89mm)(38.608mm,10.398mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.179mm < 0.254mm) Between Pad R1-1(39.37mm,9.382mm) on Top Layer And Track (38.614mm,9.827mm)(38.614mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.179mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R1-1(39.37mm,9.382mm) on Top Layer And Track (40.132mm,9.89mm)(40.132mm,10.398mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R1-2(39.37mm,10.97mm) on Top Layer And Track (38.608mm,9.89mm)(38.608mm,10.398mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.231mm < 0.254mm) Between Pad R1-2(39.37mm,10.97mm) on Top Layer And Track (38.614mm,9.827mm)(38.614mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.231mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R1-2(39.37mm,10.97mm) on Top Layer And Track (40.132mm,9.89mm)(40.132mm,10.398mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R2-1(30.861mm,10.023mm) on Top Layer And Track (31.369mm,10.785mm)(31.877mm,10.785mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R2-1(30.861mm,10.023mm) on Top Layer And Track (31.369mm,9.261mm)(31.877mm,9.261mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R2-2(32.449mm,10.023mm) on Top Layer And Track (31.369mm,10.785mm)(31.877mm,10.785mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R2-2(32.449mm,10.023mm) on Top Layer And Track (31.369mm,9.261mm)(31.877mm,9.261mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R3-1(7.303mm,9.388mm) on Top Layer And Track (7.811mm,10.15mm)(8.319mm,10.15mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R3-1(7.303mm,9.388mm) on Top Layer And Track (7.811mm,8.626mm)(8.319mm,8.626mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R3-2(8.89mm,9.388mm) on Top Layer And Track (7.811mm,10.15mm)(8.319mm,10.15mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R3-2(8.89mm,9.388mm) on Top Layer And Track (7.811mm,8.626mm)(8.319mm,8.626mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R4-1(27.178mm,10.023mm) on Top Layer And Track (27.686mm,10.785mm)(28.194mm,10.785mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R4-1(27.178mm,10.023mm) on Top Layer And Track (27.686mm,9.261mm)(28.194mm,9.261mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R4-2(28.765mm,10.023mm) on Top Layer And Track (27.686mm,10.785mm)(28.194mm,10.785mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R4-2(28.765mm,10.023mm) on Top Layer And Track (27.686mm,9.261mm)(28.194mm,9.261mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R5-1(18.542mm,8.816mm) on Top Layer And Track (17.78mm,9.324mm)(17.78mm,9.832mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R5-1(18.542mm,8.816mm) on Top Layer And Track (19.304mm,9.324mm)(19.304mm,9.832mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R5-2(18.542mm,10.404mm) on Top Layer And Track (17.78mm,9.324mm)(17.78mm,9.832mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R5-2(18.542mm,10.404mm) on Top Layer And Track (19.304mm,9.324mm)(19.304mm,9.832mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R6-1(30.988mm,6.34mm) on Top Layer And Track (30.226mm,6.848mm)(30.226mm,7.356mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R6-1(30.988mm,6.34mm) on Top Layer And Track (31.75mm,6.848mm)(31.75mm,7.356mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R6-2(30.988mm,7.927mm) on Top Layer And Track (30.226mm,6.848mm)(30.226mm,7.356mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R6-2(30.988mm,7.927mm) on Top Layer And Track (31.75mm,6.848mm)(31.75mm,7.356mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R7-1(21.59mm,6.022mm) on Top Layer And Track (20.828mm,6.53mm)(20.828mm,7.038mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R7-1(21.59mm,6.022mm) on Top Layer And Track (22.352mm,6.53mm)(22.352mm,7.038mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R7-2(21.59mm,7.61mm) on Top Layer And Track (20.828mm,6.53mm)(20.828mm,7.038mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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- Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R7-2(21.59mm,7.61mm) on Top Layer And Track (22.352mm,6.53mm)(22.352mm,7.038mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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-Rule Violations :84
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+Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (Disabled)(IsPad),(All)
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+Rule Violations :0
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-Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All)
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- Violation between Silk To Silk Clearance Constraint: (0.216mm < 0.254mm) Between Text "C10" (37.473mm,8.143mm) on Top Overlay And Track (33.528mm,7.8mm)(38.608mm,7.8mm) on Top Overlay Silk Text to Silk Clearance [0.216mm]
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- Violation between Silk To Silk Clearance Constraint: (0.158mm < 0.254mm) Between Text "C7" (20.605mm,4.57mm) on Top Overlay And Track (20.32mm,4.054mm)(20.32mm,4.562mm) on Top Overlay Silk Text to Silk Clearance [0.158mm]
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- Violation between Silk To Silk Clearance Constraint: (0.216mm < 0.254mm) Between Text "C8" (34.53mm,8.143mm) on Top Overlay And Track (33.528mm,7.8mm)(38.608mm,7.8mm) on Top Overlay Silk Text to Silk Clearance [0.216mm]
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- Violation between Silk To Silk Clearance Constraint: (0.216mm < 0.254mm) Between Text "C9" (36.06mm,8.143mm) on Top Overlay And Track (33.528mm,7.8mm)(38.608mm,7.8mm) on Top Overlay Silk Text to Silk Clearance [0.216mm]
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- Violation between Silk To Silk Clearance Constraint: (0.221mm < 0.254mm) Between Text "R1" (39.125mm,8.143mm) on Top Overlay And Track (39.37mm,2.397mm)(39.37mm,7.795mm) on Top Overlay Silk Text to Silk Clearance [0.221mm]
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- Violation between Silk To Silk Clearance Constraint: (0.221mm < 0.254mm) Between Text "R1" (39.125mm,8.143mm) on Top Overlay And Track (39.37mm,7.795mm)(44.45mm,7.795mm) on Top Overlay Silk Text to Silk Clearance [0.221mm]
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- Violation between Silk To Silk Clearance Constraint: (0.158mm < 0.254mm) Between Text "R6" (32.035mm,7.392mm) on Top Overlay And Track (31.75mm,6.848mm)(31.75mm,7.356mm) on Top Overlay Silk Text to Silk Clearance [0.158mm]
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- Violation between Silk To Silk Clearance Constraint: (0.158mm < 0.254mm) Between Text "R7" (20.543mm,6.557mm) on Top Overlay And Track (20.828mm,6.53mm)(20.828mm,7.038mm) on Top Overlay Silk Text to Silk Clearance [0.158mm]
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- Violation between Silk To Silk Clearance Constraint: (0.235mm < 0.254mm) Between Text "XP2" (25.685mm,10.64mm) on Top Overlay And Track (25.4mm,8.626mm)(25.4mm,11.166mm) on Top Overlay Silk Text to Silk Clearance [0.235mm]
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- Violation between Silk To Silk Clearance Constraint: (0.235mm < 0.254mm) Between Text "XP3" (0.539mm,10.386mm) on Top Overlay And Track (1.27mm,8.626mm)(1.27mm,11.166mm) on Top Overlay Silk Text to Silk Clearance [0.235mm]
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-Rule Violations :10
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+Processing Rule : Silk to Silk (Clearance=0.254mm) (Disabled)(All),(All)
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+Rule Violations :0
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Processing Rule : Net Antennae (Tolerance=0mm) (All)
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Rule Violations :0
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@@ -143,6 +46,6 @@ Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (Al
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Rule Violations :0
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-Violations Detected : 97
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+Violations Detected : 3
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Waived Violations : 0
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Time Elapsed : 00:00:01
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