норм версия

BIAS_TGA2237-SM.PrjPcb

@@ -99,6 +99,10 @@ DItemRevisionGUID=
 GenerateClassCluster=0
 DocumentUniqueId=
 
+[GeneratedDocument1]
+DocumentPath=Project Outputs for BIAS_TGA2237-SM\Design Rule Check - PCB1.html
+DItemRevisionGUID=
+
 [Configuration1]
 Name=Sources
 ParameterCount=0

Project Logs for BIAS_TGA2237-SM/PCB1 PCB ECO 23.07.2024 4-31-11.LOG

@@ -0,0 +1,125 @@
+Added Component: Designator=C1(C1206)
+Add component (AddParameter): Name = "Value"; Value = "0,1 ???"; VariantName = "[No Variations]"
+Added Component: Designator=C2(C1206)
+Add component (AddParameter): Name = "Value"; Value = "0,1 ???"; VariantName = "[No Variations]"
+Added Component: Designator=C3(C0603)
+Add component (AddParameter): Name = "Value"; Value = "0,1 ???"; VariantName = "[No Variations]"
+Added Component: Designator=C4(C0603)
+Add component (AddParameter): Name = "Value"; Value = "0,1 ???"; VariantName = "[No Variations]"
+Added Component: Designator=C5(C1206)
+Add component (AddParameter): Name = "Value"; Value = "0,1 ???"; VariantName = "[No Variations]"
+Added Component: Designator=C6(C1206)
+Add component (AddParameter): Name = "Value"; Value = "0,1 ???"; VariantName = "[No Variations]"
+Added Component: Designator=C7(C0603)
+Add component (AddParameter): Name = "Value"; Value = "0,1 ???"; VariantName = "[No Variations]"
+Added Component: Designator=C8(C0603)
+Add component (AddParameter): Name = "Value"; Value = "0,1 ???"; VariantName = "[No Variations]"
+Added Component: Designator=C9(C0603)
+Add component (AddParameter): Name = "Value"; Value = "0,1 ???"; VariantName = "[No Variations]"
+Added Component: Designator=C10(C0603)
+Add component (AddParameter): Name = "Value"; Value = "0,1 ???"; VariantName = "[No Variations]"
+Added Component: Designator=DA1(SOIC127P600X175-8N)
+Add component (AddParameter): Name = "Arrow Part Number"; Value = "LM2662MX/NOPB"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Arrow Price/Stock"; Value = "null?region=nac"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Datasheet Link"; Value = "http://www.ti.com/lit/ds/symlink/lm2662.pdf"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Height"; Value = "1.75mm"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Manufacturer_Name"; Value = "Texas Instruments"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Manufacturer_Part_Number"; Value = "LM2662MX/NOPB"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Mouser Part Number"; Value = "926-LM2662MX/NOPB"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Mouser Price/Stock"; Value = "https://www.mouser.co.uk/ProductDetail/Texas-Instruments/LM2662MX-NOPB?qs=X1J7HmVL2ZEhDibOuMUl7w%3D%3D"; VariantName = "[No Variations]"
+Added Component: Designator=DA2(SOIC127P600X175-8N)
+Add component (AddParameter): Name = "Arrow Part Number"; Value = "TL072CDT"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Arrow Price/Stock"; Value = "https://www.arrow.com/en/products/tl072cdt/stmicroelectronics?region=europe"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Datasheet Link"; Value = "http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/CD00000490.pdf"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Height"; Value = "1.75mm"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Manufacturer_Name"; Value = "STMicroelectronics"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Manufacturer_Part_Number"; Value = "TL072CDT"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Mouser Part Number"; Value = "511-TL072CDT"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Mouser Price/Stock"; Value = "https://www.mouser.co.uk/ProductDetail/STMicroelectronics/TL072CDT?qs=6fffrORWf5pLFxBvwrMMAA%3D%3D"; VariantName = "[No Variations]"
+Added Component: Designator=R1(R0603)
+Add component (AddParameter): Name = "Value"; Value = "1???"; VariantName = "[No Variations]"
+Added Component: Designator=R2(R0603)
+Add component (AddParameter): Name = "Value"; Value = "1???"; VariantName = "[No Variations]"
+Added Component: Designator=R3(R0603)
+Add component (AddParameter): Name = "Value"; Value = "1???"; VariantName = "[No Variations]"
+Added Component: Designator=R4(R0603)
+Add component (AddParameter): Name = "Value"; Value = "1???"; VariantName = "[No Variations]"
+Added Component: Designator=R5(R0603)
+Add component (AddParameter): Name = "Value"; Value = "1???"; VariantName = "[No Variations]"
+Added Component: Designator=R6(R0603)
+Add component (AddParameter): Name = "Value"; Value = "1???"; VariantName = "[No Variations]"
+Added Component: Designator=RP1(3224W)
+Add component (AddParameter): Name = "Value"; Value = "1???"; VariantName = "[No Variations]"
+Added Component: Designator=XP1(PLS-2)
+Added Component: Designator=XP2(PLS-2)
+Added Component: Designator=XP3(PLS-2)
+Added Pin To Net: NetName=+5V Pin=C4-2
+Added Pin To Net: NetName=+5V Pin=C5-2
+Added Pin To Net: NetName=+5V Pin=DA1-8
+Added Pin To Net: NetName=+5V Pin=DA2-8
+Added Pin To Net: NetName=+5V Pin=R2-1
+Added Pin To Net: NetName=+5V Pin=RP1-1
+Added Pin To Net: NetName=+5V Pin=XP2-1
+Added Net: Name=+5V
+Added Pin To Net: NetName=-5V Pin=C6-2
+Added Pin To Net: NetName=-5V Pin=C7-2
+Added Pin To Net: NetName=-5V Pin=DA1-5
+Added Pin To Net: NetName=-5V Pin=DA2-4
+Added Net: Name=-5V
+Added Pin To Net: NetName=GATE Pin=C8-2
+Added Pin To Net: NetName=GATE Pin=C9-2
+Added Pin To Net: NetName=GATE Pin=C10-2
+Added Pin To Net: NetName=GATE Pin=DA2-1
+Added Pin To Net: NetName=GATE Pin=R6-2
+Added Pin To Net: NetName=GATE Pin=XP3-1
+Added Net: Name=GATE
+Added Pin To Net: NetName=GND Pin=C3-1
+Added Pin To Net: NetName=GND Pin=C4-1
+Added Pin To Net: NetName=GND Pin=C5-1
+Added Pin To Net: NetName=GND Pin=C6-1
+Added Pin To Net: NetName=GND Pin=C7-1
+Added Pin To Net: NetName=GND Pin=C8-1
+Added Pin To Net: NetName=GND Pin=C9-1
+Added Pin To Net: NetName=GND Pin=C10-1
+Added Pin To Net: NetName=GND Pin=DA1-3
+Added Pin To Net: NetName=GND Pin=DA2-3
+Added Pin To Net: NetName=GND Pin=R4-2
+Added Pin To Net: NetName=GND Pin=RP1-3
+Added Pin To Net: NetName=GND Pin=XP1-2
+Added Pin To Net: NetName=GND Pin=XP2-2
+Added Pin To Net: NetName=GND Pin=XP3-2
+Added Net: Name=GND
+Added Pin To Net: NetName=IN+ Pin=R1-1
+Added Pin To Net: NetName=IN+ Pin=R3-1
+Added Pin To Net: NetName=IN+ Pin=XP1-1
+Added Net: Name=IN+
+Added Pin To Net: NetName=NetC1_1 Pin=C1-1
+Added Pin To Net: NetName=NetC1_1 Pin=C2-1
+Added Pin To Net: NetName=NetC1_1 Pin=DA1-4
+Added Net: Name=NetC1_1
+Added Pin To Net: NetName=NetC1_2 Pin=C1-2
+Added Pin To Net: NetName=NetC1_2 Pin=C2-2
+Added Pin To Net: NetName=NetC1_2 Pin=DA1-2
+Added Net: Name=NetC1_2
+Added Pin To Net: NetName=NetC3_2 Pin=C3-2
+Added Pin To Net: NetName=NetC3_2 Pin=DA2-5
+Added Pin To Net: NetName=NetC3_2 Pin=R3-2
+Added Net: Name=NetC3_2
+Added Pin To Net: NetName=NetDA1_1 Pin=DA1-1
+Added Pin To Net: NetName=NetDA1_1 Pin=R2-2
+Added Net: Name=NetDA1_1
+Added Pin To Net: NetName=NetDA1_6 Pin=DA1-6
+Added Pin To Net: NetName=NetDA1_6 Pin=R4-1
+Added Net: Name=NetDA1_6
+Added Pin To Net: NetName=NetDA2_2 Pin=DA2-2
+Added Pin To Net: NetName=NetDA2_2 Pin=R5-2
+Added Pin To Net: NetName=NetDA2_2 Pin=R6-1
+Added Net: Name=NetDA2_2
+Added Pin To Net: NetName=NetDA2_6 Pin=DA2-6
+Added Pin To Net: NetName=NetDA2_6 Pin=DA2-7
+Added Pin To Net: NetName=NetDA2_6 Pin=R5-1
+Added Net: Name=NetDA2_6
+Added Pin To Net: NetName=NetR1_2 Pin=R1-2
+Added Pin To Net: NetName=NetR1_2 Pin=RP1-2
+Added Net: Name=NetR1_2
+Added Class: Name=Sheet1

Project Logs for BIAS_TGA2237-SM/Sheet1 SCH ECO 22.07.2024 12-39-21.LOG

@@ -0,0 +1,19 @@
+Change Component Designator: Old Designator=C1 New Designator=C?
+Change Component Designator: Old Designator=C2 New Designator=C?
+Change Component Designator: Old Designator=C3 New Designator=C?
+Change Component Designator: Old Designator=C4 New Designator=C?
+Change Component Designator: Old Designator=C5 New Designator=C?
+Change Component Designator: Old Designator=C6 New Designator=C?
+Change Component Designator: Old Designator=C7 New Designator=C?
+Change Component Designator: Old Designator=C8 New Designator=C?
+Change Component Designator: Old Designator=DA1 New Designator=DA?
+Change Component Designator: Old Designator=DA2 New Designator=DA?
+Change Component Designator: Old Designator=DA2 New Designator=DA?
+Change Component Designator: Old Designator=DA2 New Designator=DA?
+Change Component Designator: Old Designator=R1 New Designator=R?
+Change Component Designator: Old Designator=R2 New Designator=R?
+Change Component Designator: Old Designator=R3 New Designator=R?
+Change Component Designator: Old Designator=R4 New Designator=R?
+Change Component Designator: Old Designator=R5 New Designator=R?
+Change Component Designator: Old Designator=R6 New Designator=R?
+Change Component Designator: Old Designator=RP1 New Designator=RP?

Project Logs for BIAS_TGA2237-SM/Sheet1 SCH ECO 22.07.2024 12-39-31.LOG

@@ -0,0 +1,23 @@
+Change Component Designator: Old Designator=C? New Designator=C1
+Change Component Designator: Old Designator=C? New Designator=C2
+Change Component Designator: Old Designator=C? New Designator=C3
+Change Component Designator: Old Designator=C? New Designator=C4
+Change Component Designator: Old Designator=C? New Designator=C5
+Change Component Designator: Old Designator=C? New Designator=C6
+Change Component Designator: Old Designator=C? New Designator=C7
+Change Component Designator: Old Designator=C? New Designator=C8
+Change Component Designator: Old Designator=DA? New Designator=DA2
+Change Component Designator: Old Designator=DA? New Designator=DA2
+Change Component Designator: Old Designator=DA? New Designator=DA2
+Change Component Designator: Old Designator=DA? New Designator=DA1
+Change Component Designator: Old Designator=R? New Designator=R1
+Change Component Designator: Old Designator=R? New Designator=R2
+Change Component Designator: Old Designator=R? New Designator=R3
+Change Component Designator: Old Designator=R? New Designator=R4
+Change Component Designator: Old Designator=R? New Designator=R5
+Change Component Designator: Old Designator=R? New Designator=R6
+Change Component Designator: Old Designator=RP? New Designator=RP1
+Change Component Designator: Old Designator=XP? New Designator=XP1
+Change Component Designator: Old Designator=XP? New Designator=XP2
+Change Component Designator: Old Designator=XP? New Designator=XP3
+Change Component Designator: Old Designator=XP? New Designator=XP4

Project Logs for BIAS_TGA2237-SM/Sheet1 SCH ECO 22.07.2024 13-21-11.LOG

@@ -0,0 +1,23 @@
+Change Component Designator: Old Designator=C1 New Designator=C?
+Change Component Designator: Old Designator=C2 New Designator=C?
+Change Component Designator: Old Designator=C3 New Designator=C?
+Change Component Designator: Old Designator=C4 New Designator=C?
+Change Component Designator: Old Designator=C5 New Designator=C?
+Change Component Designator: Old Designator=C6 New Designator=C?
+Change Component Designator: Old Designator=C7 New Designator=C?
+Change Component Designator: Old Designator=C8 New Designator=C?
+Change Component Designator: Old Designator=DA1 New Designator=DA?
+Change Component Designator: Old Designator=DA2 New Designator=DA?
+Change Component Designator: Old Designator=DA2 New Designator=DA?
+Change Component Designator: Old Designator=DA2 New Designator=DA?
+Change Component Designator: Old Designator=R1 New Designator=R?
+Change Component Designator: Old Designator=R2 New Designator=R?
+Change Component Designator: Old Designator=R3 New Designator=R?
+Change Component Designator: Old Designator=R4 New Designator=R?
+Change Component Designator: Old Designator=R5 New Designator=R?
+Change Component Designator: Old Designator=R6 New Designator=R?
+Change Component Designator: Old Designator=RP1 New Designator=RP?
+Change Component Designator: Old Designator=XP1 New Designator=XP?
+Change Component Designator: Old Designator=XP2 New Designator=XP?
+Change Component Designator: Old Designator=XP3 New Designator=XP?
+Change Component Designator: Old Designator=XP4 New Designator=XP?

Project Logs for BIAS_TGA2237-SM/Sheet1 SCH ECO 22.07.2024 13-21-21.LOG

@@ -0,0 +1,26 @@
+Change Component Designator: Old Designator=C? New Designator=C1
+Change Component Designator: Old Designator=C? New Designator=C2
+Change Component Designator: Old Designator=C? New Designator=C3
+Change Component Designator: Old Designator=C? New Designator=C4
+Change Component Designator: Old Designator=C? New Designator=C5
+Change Component Designator: Old Designator=C? New Designator=C6
+Change Component Designator: Old Designator=C? New Designator=C7
+Change Component Designator: Old Designator=C? New Designator=C8
+Change Component Designator: Old Designator=DA? New Designator=DA2
+Change Component Designator: Old Designator=DA? New Designator=DA2
+Change Component Designator: Old Designator=DA? New Designator=DA2
+Change Component Designator: Old Designator=DA? New Designator=DA1
+Change Component Designator: Old Designator=R? New Designator=R1
+Change Component Designator: Old Designator=R? New Designator=R2
+Change Component Designator: Old Designator=R? New Designator=R3
+Change Component Designator: Old Designator=R? New Designator=R4
+Change Component Designator: Old Designator=R? New Designator=R5
+Change Component Designator: Old Designator=R? New Designator=R6
+Change Component Designator: Old Designator=R? New Designator=R7
+Change Component Designator: Old Designator=RP? New Designator=RP1
+Change Component Designator: Old Designator=U? New Designator=U1
+Change Component Designator: Old Designator=U? New Designator=U1
+Change Component Designator: Old Designator=XP? New Designator=XP1
+Change Component Designator: Old Designator=XP? New Designator=XP2
+Change Component Designator: Old Designator=XP? New Designator=XP3
+Change Component Designator: Old Designator=XP? New Designator=XP4

Project Logs for BIAS_TGA2237-SM/Sheet1 SCH ECO 23.07.2024 4-30-05.LOG

@@ -0,0 +1,22 @@
+Change Component Designator: Old Designator=C1 New Designator=C?
+Change Component Designator: Old Designator=C2 New Designator=C?
+Change Component Designator: Old Designator=C3 New Designator=C?
+Change Component Designator: Old Designator=C4 New Designator=C?
+Change Component Designator: Old Designator=C5 New Designator=C?
+Change Component Designator: Old Designator=C6 New Designator=C?
+Change Component Designator: Old Designator=C7 New Designator=C?
+Change Component Designator: Old Designator=C8 New Designator=C?
+Change Component Designator: Old Designator=DA1 New Designator=DA?
+Change Component Designator: Old Designator=DA2 New Designator=DA?
+Change Component Designator: Old Designator=DA2 New Designator=DA?
+Change Component Designator: Old Designator=DA2 New Designator=DA?
+Change Component Designator: Old Designator=R1 New Designator=R?
+Change Component Designator: Old Designator=R2 New Designator=R?
+Change Component Designator: Old Designator=R3 New Designator=R?
+Change Component Designator: Old Designator=R4 New Designator=R?
+Change Component Designator: Old Designator=R6 New Designator=R?
+Change Component Designator: Old Designator=R7 New Designator=R?
+Change Component Designator: Old Designator=RP1 New Designator=RP?
+Change Component Designator: Old Designator=XP1 New Designator=XP?
+Change Component Designator: Old Designator=XP3 New Designator=XP?
+Change Component Designator: Old Designator=XP4 New Designator=XP?

Project Logs for BIAS_TGA2237-SM/Sheet1 SCH ECO 23.07.2024 4-30-27.LOG

@@ -0,0 +1,24 @@
+Change Component Designator: Old Designator=C? New Designator=C1
+Change Component Designator: Old Designator=C? New Designator=C2
+Change Component Designator: Old Designator=C? New Designator=C3
+Change Component Designator: Old Designator=C? New Designator=C4
+Change Component Designator: Old Designator=C? New Designator=C5
+Change Component Designator: Old Designator=C? New Designator=C6
+Change Component Designator: Old Designator=C? New Designator=C7
+Change Component Designator: Old Designator=C? New Designator=C8
+Change Component Designator: Old Designator=C? New Designator=C9
+Change Component Designator: Old Designator=C? New Designator=C10
+Change Component Designator: Old Designator=DA? New Designator=DA2
+Change Component Designator: Old Designator=DA? New Designator=DA2
+Change Component Designator: Old Designator=DA? New Designator=DA2
+Change Component Designator: Old Designator=DA? New Designator=DA1
+Change Component Designator: Old Designator=R? New Designator=R1
+Change Component Designator: Old Designator=R? New Designator=R2
+Change Component Designator: Old Designator=R? New Designator=R3
+Change Component Designator: Old Designator=R? New Designator=R4
+Change Component Designator: Old Designator=R? New Designator=R5
+Change Component Designator: Old Designator=R? New Designator=R6
+Change Component Designator: Old Designator=RP? New Designator=RP1
+Change Component Designator: Old Designator=XP? New Designator=XP1
+Change Component Designator: Old Designator=XP? New Designator=XP2
+Change Component Designator: Old Designator=XP? New Designator=XP3

Project Outputs for BIAS_TGA2237-SM/Design Rule Check - PCB1.drc

@@ -0,0 +1,132 @@
+Protel Design System Design Rule Check
+PCB File : C:\Users\Vlad\Documents\BIAS_TGA2237-SM\PCB1.PcbDoc
+Date     : 23.07.2024
+Time     : 6:43:50
+
+Processing Rule : Clearance Constraint (Gap=10mil) (All),(All)
+Rule Violations :0
+
+Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
+Rule Violations :0
+
+Processing Rule : Un-Routed Net Constraint ( (All) )
+Rule Violations :0
+
+Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
+Rule Violations :0
+
+Processing Rule : Width Constraint (Min=10mil) (Max=50mil) (Preferred=20mil) (All)
+Rule Violations :0
+
+Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
+Rule Violations :0
+
+Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (All)
+Rule Violations :0
+
+Processing Rule : Hole To Hole Clearance (Gap=10mil) (All),(All)
+Rule Violations :0
+
+Processing Rule : Minimum Solder Mask Sliver (Gap=10mil) (All),(All)
+Rule Violations :0
+
+Processing Rule : Silk To Solder Mask (Clearance=10mil) (IsPad),(All)
+   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C10-1(1490.217mil,327.5mil) on Top Layer And Track (1460.217mil,347.5mil)(1460.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C10-1(1490.217mil,327.5mil) on Top Layer And Track (1460.217mil,347.5mil)(1460.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C10-1(1490.217mil,327.5mil) on Top Layer And Track (1520.217mil,347.5mil)(1520.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C10-2(1490.217mil,390mil) on Top Layer And Track (1460.217mil,347.5mil)(1460.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C10-2(1490.217mil,390mil) on Top Layer And Track (1460.217mil,347.5mil)(1460.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C10-2(1490.217mil,390mil) on Top Layer And Track (1520.217mil,347.5mil)(1520.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C3-1(1280mil,110.217mil) on Top Layer And Track (1240mil,140.217mil)(1260mil,140.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C3-1(1280mil,110.217mil) on Top Layer And Track (1240mil,80.217mil)(1260mil,80.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C3-2(1217.5mil,110.217mil) on Top Layer And Track (1240mil,140.217mil)(1260mil,140.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C3-2(1217.5mil,110.217mil) on Top Layer And Track (1240mil,80.217mil)(1260mil,80.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C4-1(650mil,370.217mil) on Top Layer And Track (620mil,330.217mil)(620mil,350.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C4-1(650mil,370.217mil) on Top Layer And Track (680mil,330.217mil)(680mil,350.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C4-2(650mil,307.717mil) on Top Layer And Track (620mil,330.217mil)(620mil,350.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C4-2(650mil,307.717mil) on Top Layer And Track (680mil,330.217mil)(680mil,350.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C7-1(770mil,160.217mil) on Top Layer And Track (740mil,120.217mil)(740mil,140.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C7-1(770mil,160.217mil) on Top Layer And Track (800mil,120.217mil)(800mil,140.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C7-2(770mil,97.717mil) on Top Layer And Track (740mil,120.217mil)(740mil,140.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C7-2(770mil,97.717mil) on Top Layer And Track (800mil,120.217mil)(800mil,140.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C8-1(1370.217mil,327.5mil) on Top Layer And Track (1340.217mil,347.5mil)(1340.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C8-1(1370.217mil,327.5mil) on Top Layer And Track (1400.217mil,347.5mil)(1400.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C8-1(1370.217mil,327.5mil) on Top Layer And Track (1400.217mil,347.5mil)(1400.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C8-2(1370.217mil,390mil) on Top Layer And Track (1340.217mil,347.5mil)(1340.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C8-2(1370.217mil,390mil) on Top Layer And Track (1400.217mil,347.5mil)(1400.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C8-2(1370.217mil,390mil) on Top Layer And Track (1400.217mil,347.5mil)(1400.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C9-1(1430.217mil,327.5mil) on Top Layer And Track (1400.217mil,347.5mil)(1400.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C9-1(1430.217mil,327.5mil) on Top Layer And Track (1400.217mil,347.5mil)(1400.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C9-1(1430.217mil,327.5mil) on Top Layer And Track (1460.217mil,347.5mil)(1460.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C9-1(1430.217mil,327.5mil) on Top Layer And Track (1460.217mil,347.5mil)(1460.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C9-2(1430.217mil,390mil) on Top Layer And Track (1400.217mil,347.5mil)(1400.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C9-2(1430.217mil,390mil) on Top Layer And Track (1400.217mil,347.5mil)(1400.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C9-2(1430.217mil,390mil) on Top Layer And Track (1460.217mil,347.5mil)(1460.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C9-2(1430.217mil,390mil) on Top Layer And Track (1460.217mil,347.5mil)(1460.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (9.842mil < 10mil) Between Pad DA1-1(363.228mil,245.217mil) on Top Layer And Track (333.189mil,271.791mil)(393.228mil,271.791mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.842mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA1-1(363.228mil,245.217mil) on Top Layer And Track (407.008mil,73.76mil)(407.008mil,266.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA1-2(363.228mil,195.217mil) on Top Layer And Track (407.008mil,73.76mil)(407.008mil,266.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA1-3(363.228mil,145.217mil) on Top Layer And Track (407.008mil,73.76mil)(407.008mil,266.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA1-4(363.228mil,95.217mil) on Top Layer And Track (407.008mil,73.76mil)(407.008mil,266.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA1-5(576.772mil,95.217mil) on Top Layer And Track (532.992mil,73.76mil)(532.992mil,266.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA1-6(576.772mil,145.217mil) on Top Layer And Track (532.992mil,73.76mil)(532.992mil,266.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA1-7(576.772mil,195.217mil) on Top Layer And Track (532.992mil,73.76mil)(532.992mil,266.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA1-8(576.772mil,245.217mil) on Top Layer And Track (532.992mil,73.76mil)(532.992mil,266.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (9.021mil < 10mil) Between Pad DA2-1(923.228mil,255.217mil) on Top Layer And Track (880mil,217.717mil)(880mil,237.717mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.021mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (9.842mil < 10mil) Between Pad DA2-1(923.228mil,255.217mil) on Top Layer And Track (893.189mil,281.791mil)(953.228mil,281.791mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.842mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA2-1(923.228mil,255.217mil) on Top Layer And Track (967.008mil,83.76mil)(967.008mil,276.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.209mil < 10mil) Between Pad DA2-2(923.228mil,205.217mil) on Top Layer And Track (880mil,217.717mil)(880mil,237.717mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.209mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA2-2(923.228mil,205.217mil) on Top Layer And Track (967.008mil,83.76mil)(967.008mil,276.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA2-3(923.228mil,155.217mil) on Top Layer And Track (967.008mil,83.76mil)(967.008mil,276.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA2-4(923.228mil,105.217mil) on Top Layer And Track (967.008mil,83.76mil)(967.008mil,276.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA2-5(1136.772mil,105.217mil) on Top Layer And Track (1092.992mil,83.76mil)(1092.992mil,276.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA2-6(1136.772mil,155.217mil) on Top Layer And Track (1092.992mil,83.76mil)(1092.992mil,276.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA2-7(1136.772mil,205.217mil) on Top Layer And Track (1092.992mil,83.76mil)(1092.992mil,276.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA2-8(1136.772mil,255.217mil) on Top Layer And Track (1092.992mil,83.76mil)(1092.992mil,276.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad R1-1(1215mil,355.217mil) on Top Layer And Track (1235mil,325.217mil)(1255mil,325.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad R1-1(1215mil,355.217mil) on Top Layer And Track (1235mil,385.217mil)(1255mil,385.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad R1-2(1277.5mil,355.217mil) on Top Layer And Track (1235mil,325.217mil)(1255mil,325.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad R1-2(1277.5mil,355.217mil) on Top Layer And Track (1235mil,385.217mil)(1255mil,385.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad R2-1(287.5mil,330.217mil) on Top Layer And Track (307.5mil,300.217mil)(327.5mil,300.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad R2-1(287.5mil,330.217mil) on Top Layer And Track (307.5mil,360.217mil)(327.5mil,360.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad R2-2(350mil,330.217mil) on Top Layer And Track (307.5mil,300.217mil)(327.5mil,300.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad R2-2(350mil,330.217mil) on Top Layer And Track (307.5mil,360.217mil)(327.5mil,360.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad R3-1(1070mil,355.217mil) on Top Layer And Track (1090mil,325.217mil)(1110mil,325.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad R3-1(1070mil,355.217mil) on Top Layer And Track (1090mil,385.217mil)(1110mil,385.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad R3-2(1132.5mil,355.217mil) on Top Layer And Track (1090mil,325.217mil)(1110mil,325.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad R3-2(1132.5mil,355.217mil) on Top Layer And Track (1090mil,385.217mil)(1110mil,385.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad R4-1(730mil,307.717mil) on Top Layer And Track (700mil,327.717mil)(700mil,347.717mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad R4-1(730mil,307.717mil) on Top Layer And Track (760mil,327.717mil)(760mil,347.717mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad R4-2(730mil,370.217mil) on Top Layer And Track (700mil,327.717mil)(700mil,347.717mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad R4-2(730mil,370.217mil) on Top Layer And Track (760mil,327.717mil)(760mil,347.717mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad R5-1(1220mil,210.217mil) on Top Layer And Track (1190mil,230.217mil)(1190mil,250.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad R5-1(1220mil,210.217mil) on Top Layer And Track (1250mil,230.217mil)(1250mil,250.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad R5-2(1220mil,272.717mil) on Top Layer And Track (1190mil,230.217mil)(1190mil,250.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad R5-2(1220mil,272.717mil) on Top Layer And Track (1250mil,230.217mil)(1250mil,250.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad R6-1(850mil,197.717mil) on Top Layer And Track (820mil,217.717mil)(820mil,237.717mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad R6-1(850mil,197.717mil) on Top Layer And Track (880mil,217.717mil)(880mil,237.717mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad R6-2(850mil,260.217mil) on Top Layer And Track (820mil,217.717mil)(820mil,237.717mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
+   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad R6-2(850mil,260.217mil) on Top Layer And Track (880mil,217.717mil)(880mil,237.717mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
+Rule Violations :76
+
+Processing Rule : Silk to Silk (Clearance=10mil) (All),(All)
+   Violation between Silk To Silk Clearance Constraint: (8.502mil < 10mil) Between Text "C10" (1475.3mil,281.219mil) on Top Overlay And Track (1320mil,267.717mil)(1520mil,267.717mil) on Top Overlay Silk Text to Silk Clearance [8.502mil]
+   Violation between Silk To Silk Clearance Constraint: (6.205mil < 10mil) Between Text "C7" (811.205mil,140.567mil) on Top Overlay And Track (800mil,120.217mil)(800mil,140.217mil) on Top Overlay Silk Text to Silk Clearance [6.205mil]
+   Violation between Silk To Silk Clearance Constraint: (8.502mil < 10mil) Between Text "C8" (1359.46mil,281.219mil) on Top Overlay And Track (1320mil,267.717mil)(1520mil,267.717mil) on Top Overlay Silk Text to Silk Clearance [8.502mil]
+   Violation between Silk To Silk Clearance Constraint: (8.502mil < 10mil) Between Text "C9" (1419.677mil,281.219mil) on Top Overlay And Track (1320mil,267.717mil)(1520mil,267.717mil) on Top Overlay Silk Text to Silk Clearance [8.502mil]
+   Violation between Silk To Silk Clearance Constraint: (6.219mil < 10mil) Between Text "R5" (1261.219mil,251.643mil) on Top Overlay And Track (1250mil,230.217mil)(1250mil,250.217mil) on Top Overlay Silk Text to Silk Clearance [6.219mil]
+   Violation between Silk To Silk Clearance Constraint: (6.219mil < 10mil) Between Text "R6" (808.781mil,218.79mil) on Top Overlay And Track (820mil,217.717mil)(820mil,237.717mil) on Top Overlay Silk Text to Silk Clearance [6.219mil]
+   Violation between Silk To Silk Clearance Constraint: (9.251mil < 10mil) Between Text "XP1" (1011.219mil,377.778mil) on Top Overlay And Track (1000mil,300.217mil)(1000mil,400.217mil) on Top Overlay Silk Text to Silk Clearance [9.251mil]
+   Violation between Silk To Silk Clearance Constraint: (9.251mil < 10mil) Between Text "XP2" (21.219mil,369.537mil) on Top Overlay And Track (50mil,300.217mil)(50mil,400.217mil) on Top Overlay Silk Text to Silk Clearance [9.251mil]
+Rule Violations :8
+
+Processing Rule : Net Antennae (Tolerance=0mil) (All)
+Rule Violations :0
+
+Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
+Rule Violations :0
+
+
+Violations Detected : 84
+Waived Violations : 0
+Time Elapsed        : 00:00:02