ARM GAS /tmp/ccji4ked.s page 1 1 .cpu cortex-m3 2 .arch armv7-m 3 .fpu softvfp 4 .eabi_attribute 20, 1 5 .eabi_attribute 21, 1 6 .eabi_attribute 23, 3 7 .eabi_attribute 24, 1 8 .eabi_attribute 25, 1 9 .eabi_attribute 26, 1 10 .eabi_attribute 30, 1 11 .eabi_attribute 34, 1 12 .eabi_attribute 18, 4 13 .file "system_stm32f1xx.c" 14 .text 15 .Ltext0: 16 .cfi_sections .debug_frame 17 .section .text.SystemInit,"ax",%progbits 18 .align 1 19 .global SystemInit 20 .syntax unified 21 .thumb 22 .thumb_func 24 SystemInit: 25 .LFB65: 26 .file 1 "Core/Src/system_stm32f1xx.c" 1:Core/Src/system_stm32f1xx.c **** /** 2:Core/Src/system_stm32f1xx.c **** ****************************************************************************** 3:Core/Src/system_stm32f1xx.c **** * @file system_stm32f1xx.c 4:Core/Src/system_stm32f1xx.c **** * @author MCD Application Team 5:Core/Src/system_stm32f1xx.c **** * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. 6:Core/Src/system_stm32f1xx.c **** * 7:Core/Src/system_stm32f1xx.c **** * 1. This file provides two functions and one global variable to be called from 8:Core/Src/system_stm32f1xx.c **** * user application: 9:Core/Src/system_stm32f1xx.c **** * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier 10:Core/Src/system_stm32f1xx.c **** * factors, AHB/APBx prescalers and Flash settings). 11:Core/Src/system_stm32f1xx.c **** * This function is called at startup just after reset and 12:Core/Src/system_stm32f1xx.c **** * before branch to main program. This call is made inside 13:Core/Src/system_stm32f1xx.c **** * the "startup_stm32f1xx_xx.s" file. 14:Core/Src/system_stm32f1xx.c **** * 15:Core/Src/system_stm32f1xx.c **** * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used 16:Core/Src/system_stm32f1xx.c **** * by the user application to setup the SysTick 17:Core/Src/system_stm32f1xx.c **** * timer or configure other parameters. 18:Core/Src/system_stm32f1xx.c **** * 19:Core/Src/system_stm32f1xx.c **** * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must 20:Core/Src/system_stm32f1xx.c **** * be called whenever the core clock is changed 21:Core/Src/system_stm32f1xx.c **** * during program execution. 22:Core/Src/system_stm32f1xx.c **** * 23:Core/Src/system_stm32f1xx.c **** * 2. After each device reset the HSI (8 MHz) is used as system clock source. 24:Core/Src/system_stm32f1xx.c **** * Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to 25:Core/Src/system_stm32f1xx.c **** * configure the system clock before to branch to main program. 26:Core/Src/system_stm32f1xx.c **** * 27:Core/Src/system_stm32f1xx.c **** * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on 28:Core/Src/system_stm32f1xx.c **** * the product used), refer to "HSE_VALUE". 29:Core/Src/system_stm32f1xx.c **** * When HSE is used as system clock source, directly or through PLL, and you 30:Core/Src/system_stm32f1xx.c **** * are using different crystal you have to adapt the HSE value to your own 31:Core/Src/system_stm32f1xx.c **** * configuration. 32:Core/Src/system_stm32f1xx.c **** * ARM GAS /tmp/ccji4ked.s page 2 33:Core/Src/system_stm32f1xx.c **** ****************************************************************************** 34:Core/Src/system_stm32f1xx.c **** * @attention 35:Core/Src/system_stm32f1xx.c **** * 36:Core/Src/system_stm32f1xx.c **** * Copyright (c) 2017-2021 STMicroelectronics. 37:Core/Src/system_stm32f1xx.c **** * All rights reserved. 38:Core/Src/system_stm32f1xx.c **** * 39:Core/Src/system_stm32f1xx.c **** * This software is licensed under terms that can be found in the LICENSE file 40:Core/Src/system_stm32f1xx.c **** * in the root directory of this software component. 41:Core/Src/system_stm32f1xx.c **** * If no LICENSE file comes with this software, it is provided AS-IS. 42:Core/Src/system_stm32f1xx.c **** * 43:Core/Src/system_stm32f1xx.c **** ****************************************************************************** 44:Core/Src/system_stm32f1xx.c **** */ 45:Core/Src/system_stm32f1xx.c **** 46:Core/Src/system_stm32f1xx.c **** /** @addtogroup CMSIS 47:Core/Src/system_stm32f1xx.c **** * @{ 48:Core/Src/system_stm32f1xx.c **** */ 49:Core/Src/system_stm32f1xx.c **** 50:Core/Src/system_stm32f1xx.c **** /** @addtogroup stm32f1xx_system 51:Core/Src/system_stm32f1xx.c **** * @{ 52:Core/Src/system_stm32f1xx.c **** */ 53:Core/Src/system_stm32f1xx.c **** 54:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Includes 55:Core/Src/system_stm32f1xx.c **** * @{ 56:Core/Src/system_stm32f1xx.c **** */ 57:Core/Src/system_stm32f1xx.c **** 58:Core/Src/system_stm32f1xx.c **** #include "stm32f1xx.h" 59:Core/Src/system_stm32f1xx.c **** 60:Core/Src/system_stm32f1xx.c **** /** 61:Core/Src/system_stm32f1xx.c **** * @} 62:Core/Src/system_stm32f1xx.c **** */ 63:Core/Src/system_stm32f1xx.c **** 64:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_TypesDefinitions 65:Core/Src/system_stm32f1xx.c **** * @{ 66:Core/Src/system_stm32f1xx.c **** */ 67:Core/Src/system_stm32f1xx.c **** 68:Core/Src/system_stm32f1xx.c **** /** 69:Core/Src/system_stm32f1xx.c **** * @} 70:Core/Src/system_stm32f1xx.c **** */ 71:Core/Src/system_stm32f1xx.c **** 72:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Defines 73:Core/Src/system_stm32f1xx.c **** * @{ 74:Core/Src/system_stm32f1xx.c **** */ 75:Core/Src/system_stm32f1xx.c **** 76:Core/Src/system_stm32f1xx.c **** #if !defined (HSE_VALUE) 77:Core/Src/system_stm32f1xx.c **** #define HSE_VALUE 8000000U /*!< Default value of the External oscillator in Hz. 78:Core/Src/system_stm32f1xx.c **** This value can be provided and adapted by the user 79:Core/Src/system_stm32f1xx.c **** #endif /* HSE_VALUE */ 80:Core/Src/system_stm32f1xx.c **** 81:Core/Src/system_stm32f1xx.c **** #if !defined (HSI_VALUE) 82:Core/Src/system_stm32f1xx.c **** #define HSI_VALUE 8000000U /*!< Default value of the Internal oscillator in Hz. 83:Core/Src/system_stm32f1xx.c **** This value can be provided and adapted by the user 84:Core/Src/system_stm32f1xx.c **** #endif /* HSI_VALUE */ 85:Core/Src/system_stm32f1xx.c **** 86:Core/Src/system_stm32f1xx.c **** /*!< Uncomment the following line if you need to use external SRAM */ 87:Core/Src/system_stm32f1xx.c **** #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || 88:Core/Src/system_stm32f1xx.c **** /* #define DATA_IN_ExtSRAM */ 89:Core/Src/system_stm32f1xx.c **** #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ ARM GAS /tmp/ccji4ked.s page 3 90:Core/Src/system_stm32f1xx.c **** 91:Core/Src/system_stm32f1xx.c **** /* Note: Following vector table addresses must be defined in line with linker 92:Core/Src/system_stm32f1xx.c **** configuration. */ 93:Core/Src/system_stm32f1xx.c **** /*!< Uncomment the following line if you need to relocate the vector table 94:Core/Src/system_stm32f1xx.c **** anywhere in Flash or Sram, else the vector table is kept at the automatic 95:Core/Src/system_stm32f1xx.c **** remap of boot address selected */ 96:Core/Src/system_stm32f1xx.c **** /* #define USER_VECT_TAB_ADDRESS */ 97:Core/Src/system_stm32f1xx.c **** 98:Core/Src/system_stm32f1xx.c **** #if defined(USER_VECT_TAB_ADDRESS) 99:Core/Src/system_stm32f1xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table 100:Core/Src/system_stm32f1xx.c **** in Sram else user remap will be done in Flash. */ 101:Core/Src/system_stm32f1xx.c **** /* #define VECT_TAB_SRAM */ 102:Core/Src/system_stm32f1xx.c **** #if defined(VECT_TAB_SRAM) 103:Core/Src/system_stm32f1xx.c **** #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. 104:Core/Src/system_stm32f1xx.c **** This value must be a multiple of 0x200. */ 105:Core/Src/system_stm32f1xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. 106:Core/Src/system_stm32f1xx.c **** This value must be a multiple of 0x200. */ 107:Core/Src/system_stm32f1xx.c **** #else 108:Core/Src/system_stm32f1xx.c **** #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. 109:Core/Src/system_stm32f1xx.c **** This value must be a multiple of 0x200. */ 110:Core/Src/system_stm32f1xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. 111:Core/Src/system_stm32f1xx.c **** This value must be a multiple of 0x200. */ 112:Core/Src/system_stm32f1xx.c **** #endif /* VECT_TAB_SRAM */ 113:Core/Src/system_stm32f1xx.c **** #endif /* USER_VECT_TAB_ADDRESS */ 114:Core/Src/system_stm32f1xx.c **** 115:Core/Src/system_stm32f1xx.c **** /******************************************************************************/ 116:Core/Src/system_stm32f1xx.c **** 117:Core/Src/system_stm32f1xx.c **** /** 118:Core/Src/system_stm32f1xx.c **** * @} 119:Core/Src/system_stm32f1xx.c **** */ 120:Core/Src/system_stm32f1xx.c **** 121:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Macros 122:Core/Src/system_stm32f1xx.c **** * @{ 123:Core/Src/system_stm32f1xx.c **** */ 124:Core/Src/system_stm32f1xx.c **** 125:Core/Src/system_stm32f1xx.c **** /** 126:Core/Src/system_stm32f1xx.c **** * @} 127:Core/Src/system_stm32f1xx.c **** */ 128:Core/Src/system_stm32f1xx.c **** 129:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Variables 130:Core/Src/system_stm32f1xx.c **** * @{ 131:Core/Src/system_stm32f1xx.c **** */ 132:Core/Src/system_stm32f1xx.c **** 133:Core/Src/system_stm32f1xx.c **** /* This variable is updated in three ways: 134:Core/Src/system_stm32f1xx.c **** 1) by calling CMSIS function SystemCoreClockUpdate() 135:Core/Src/system_stm32f1xx.c **** 2) by calling HAL API function HAL_RCC_GetHCLKFreq() 136:Core/Src/system_stm32f1xx.c **** 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 137:Core/Src/system_stm32f1xx.c **** Note: If you use this function to configure the system clock; then there 138:Core/Src/system_stm32f1xx.c **** is no need to call the 2 first functions listed above, since SystemCoreClock 139:Core/Src/system_stm32f1xx.c **** variable is updated automatically. 140:Core/Src/system_stm32f1xx.c **** */ 141:Core/Src/system_stm32f1xx.c **** uint32_t SystemCoreClock = 16000000; 142:Core/Src/system_stm32f1xx.c **** const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; 143:Core/Src/system_stm32f1xx.c **** const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4}; 144:Core/Src/system_stm32f1xx.c **** 145:Core/Src/system_stm32f1xx.c **** /** 146:Core/Src/system_stm32f1xx.c **** * @} ARM GAS /tmp/ccji4ked.s page 4 147:Core/Src/system_stm32f1xx.c **** */ 148:Core/Src/system_stm32f1xx.c **** 149:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_FunctionPrototypes 150:Core/Src/system_stm32f1xx.c **** * @{ 151:Core/Src/system_stm32f1xx.c **** */ 152:Core/Src/system_stm32f1xx.c **** 153:Core/Src/system_stm32f1xx.c **** #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || 154:Core/Src/system_stm32f1xx.c **** #ifdef DATA_IN_ExtSRAM 155:Core/Src/system_stm32f1xx.c **** static void SystemInit_ExtMemCtl(void); 156:Core/Src/system_stm32f1xx.c **** #endif /* DATA_IN_ExtSRAM */ 157:Core/Src/system_stm32f1xx.c **** #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ 158:Core/Src/system_stm32f1xx.c **** 159:Core/Src/system_stm32f1xx.c **** /** 160:Core/Src/system_stm32f1xx.c **** * @} 161:Core/Src/system_stm32f1xx.c **** */ 162:Core/Src/system_stm32f1xx.c **** 163:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Functions 164:Core/Src/system_stm32f1xx.c **** * @{ 165:Core/Src/system_stm32f1xx.c **** */ 166:Core/Src/system_stm32f1xx.c **** 167:Core/Src/system_stm32f1xx.c **** /** 168:Core/Src/system_stm32f1xx.c **** * @brief Setup the microcontroller system 169:Core/Src/system_stm32f1xx.c **** * Initialize the Embedded Flash Interface, the PLL and update the 170:Core/Src/system_stm32f1xx.c **** * SystemCoreClock variable. 171:Core/Src/system_stm32f1xx.c **** * @note This function should be used only after reset. 172:Core/Src/system_stm32f1xx.c **** * @param None 173:Core/Src/system_stm32f1xx.c **** * @retval None 174:Core/Src/system_stm32f1xx.c **** */ 175:Core/Src/system_stm32f1xx.c **** void SystemInit (void) 176:Core/Src/system_stm32f1xx.c **** { 27 .loc 1 176 1 view -0 28 .cfi_startproc 29 @ args = 0, pretend = 0, frame = 0 30 @ frame_needed = 0, uses_anonymous_args = 0 31 @ link register save eliminated. 177:Core/Src/system_stm32f1xx.c **** #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || 178:Core/Src/system_stm32f1xx.c **** #ifdef DATA_IN_ExtSRAM 179:Core/Src/system_stm32f1xx.c **** SystemInit_ExtMemCtl(); 180:Core/Src/system_stm32f1xx.c **** #endif /* DATA_IN_ExtSRAM */ 181:Core/Src/system_stm32f1xx.c **** #endif 182:Core/Src/system_stm32f1xx.c **** 183:Core/Src/system_stm32f1xx.c **** /* Configure the Vector Table location -------------------------------------*/ 184:Core/Src/system_stm32f1xx.c **** #if defined(USER_VECT_TAB_ADDRESS) 185:Core/Src/system_stm32f1xx.c **** SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. 186:Core/Src/system_stm32f1xx.c **** #endif /* USER_VECT_TAB_ADDRESS */ 187:Core/Src/system_stm32f1xx.c **** } 32 .loc 1 187 1 view .LVU1 33 0000 7047 bx lr 34 .cfi_endproc 35 .LFE65: 37 .section .text.SystemCoreClockUpdate,"ax",%progbits 38 .align 1 39 .global SystemCoreClockUpdate 40 .syntax unified 41 .thumb 42 .thumb_func 44 SystemCoreClockUpdate: ARM GAS /tmp/ccji4ked.s page 5 45 .LFB66: 188:Core/Src/system_stm32f1xx.c **** 189:Core/Src/system_stm32f1xx.c **** /** 190:Core/Src/system_stm32f1xx.c **** * @brief Update SystemCoreClock variable according to Clock Register Values. 191:Core/Src/system_stm32f1xx.c **** * The SystemCoreClock variable contains the core clock (HCLK), it can 192:Core/Src/system_stm32f1xx.c **** * be used by the user application to setup the SysTick timer or configure 193:Core/Src/system_stm32f1xx.c **** * other parameters. 194:Core/Src/system_stm32f1xx.c **** * 195:Core/Src/system_stm32f1xx.c **** * @note Each time the core clock (HCLK) changes, this function must be called 196:Core/Src/system_stm32f1xx.c **** * to update SystemCoreClock variable value. Otherwise, any configuration 197:Core/Src/system_stm32f1xx.c **** * based on this variable will be incorrect. 198:Core/Src/system_stm32f1xx.c **** * 199:Core/Src/system_stm32f1xx.c **** * @note - The system frequency computed by this function is not the real 200:Core/Src/system_stm32f1xx.c **** * frequency in the chip. It is calculated based on the predefined 201:Core/Src/system_stm32f1xx.c **** * constant and the selected clock source: 202:Core/Src/system_stm32f1xx.c **** * 203:Core/Src/system_stm32f1xx.c **** * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) 204:Core/Src/system_stm32f1xx.c **** * 205:Core/Src/system_stm32f1xx.c **** * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) 206:Core/Src/system_stm32f1xx.c **** * 207:Core/Src/system_stm32f1xx.c **** * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 208:Core/Src/system_stm32f1xx.c **** * or HSI_VALUE(*) multiplied by the PLL factors. 209:Core/Src/system_stm32f1xx.c **** * 210:Core/Src/system_stm32f1xx.c **** * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value 211:Core/Src/system_stm32f1xx.c **** * 8 MHz) but the real value may vary depending on the variations 212:Core/Src/system_stm32f1xx.c **** * in voltage and temperature. 213:Core/Src/system_stm32f1xx.c **** * 214:Core/Src/system_stm32f1xx.c **** * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value 215:Core/Src/system_stm32f1xx.c **** * 8 MHz or 25 MHz, depending on the product used), user has to ensure 216:Core/Src/system_stm32f1xx.c **** * that HSE_VALUE is same as the real frequency of the crystal used. 217:Core/Src/system_stm32f1xx.c **** * Otherwise, this function may have wrong result. 218:Core/Src/system_stm32f1xx.c **** * 219:Core/Src/system_stm32f1xx.c **** * - The result of this function could be not correct when using fractional 220:Core/Src/system_stm32f1xx.c **** * value for HSE crystal. 221:Core/Src/system_stm32f1xx.c **** * @param None 222:Core/Src/system_stm32f1xx.c **** * @retval None 223:Core/Src/system_stm32f1xx.c **** */ 224:Core/Src/system_stm32f1xx.c **** void SystemCoreClockUpdate (void) 225:Core/Src/system_stm32f1xx.c **** { 46 .loc 1 225 1 view -0 47 .cfi_startproc 48 @ args = 0, pretend = 0, frame = 0 49 @ frame_needed = 0, uses_anonymous_args = 0 50 @ link register save eliminated. 226:Core/Src/system_stm32f1xx.c **** uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U; 51 .loc 1 226 3 view .LVU3 52 .LVL0: 227:Core/Src/system_stm32f1xx.c **** 228:Core/Src/system_stm32f1xx.c **** #if defined(STM32F105xC) || defined(STM32F107xC) 229:Core/Src/system_stm32f1xx.c **** uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U; 230:Core/Src/system_stm32f1xx.c **** #endif /* STM32F105xC */ 231:Core/Src/system_stm32f1xx.c **** 232:Core/Src/system_stm32f1xx.c **** #if defined(STM32F100xB) || defined(STM32F100xE) 233:Core/Src/system_stm32f1xx.c **** uint32_t prediv1factor = 0U; 234:Core/Src/system_stm32f1xx.c **** #endif /* STM32F100xB or STM32F100xE */ 235:Core/Src/system_stm32f1xx.c **** 236:Core/Src/system_stm32f1xx.c **** /* Get SYSCLK source -------------------------------------------------------*/ ARM GAS /tmp/ccji4ked.s page 6 237:Core/Src/system_stm32f1xx.c **** tmp = RCC->CFGR & RCC_CFGR_SWS; 53 .loc 1 237 3 view .LVU4 54 .loc 1 237 12 is_stmt 0 view .LVU5 55 0000 1F4B ldr r3, .L10 56 0002 5B68 ldr r3, [r3, #4] 57 .loc 1 237 7 view .LVU6 58 0004 03F00C03 and r3, r3, #12 59 .LVL1: 238:Core/Src/system_stm32f1xx.c **** 239:Core/Src/system_stm32f1xx.c **** switch (tmp) 60 .loc 1 239 3 is_stmt 1 view .LVU7 61 0008 042B cmp r3, #4 62 000a 14D0 beq .L3 63 000c 082B cmp r3, #8 64 000e 16D0 beq .L4 65 0010 1BB1 cbz r3, .L9 240:Core/Src/system_stm32f1xx.c **** { 241:Core/Src/system_stm32f1xx.c **** case 0x00U: /* HSI used as system clock */ 242:Core/Src/system_stm32f1xx.c **** SystemCoreClock = HSI_VALUE; 243:Core/Src/system_stm32f1xx.c **** break; 244:Core/Src/system_stm32f1xx.c **** case 0x04U: /* HSE used as system clock */ 245:Core/Src/system_stm32f1xx.c **** SystemCoreClock = HSE_VALUE; 246:Core/Src/system_stm32f1xx.c **** break; 247:Core/Src/system_stm32f1xx.c **** case 0x08U: /* PLL used as system clock */ 248:Core/Src/system_stm32f1xx.c **** 249:Core/Src/system_stm32f1xx.c **** /* Get PLL clock source and multiplication factor ----------------------*/ 250:Core/Src/system_stm32f1xx.c **** pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; 251:Core/Src/system_stm32f1xx.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; 252:Core/Src/system_stm32f1xx.c **** 253:Core/Src/system_stm32f1xx.c **** #if !defined(STM32F105xC) && !defined(STM32F107xC) 254:Core/Src/system_stm32f1xx.c **** pllmull = ( pllmull >> 18U) + 2U; 255:Core/Src/system_stm32f1xx.c **** 256:Core/Src/system_stm32f1xx.c **** if (pllsource == 0x00U) 257:Core/Src/system_stm32f1xx.c **** { 258:Core/Src/system_stm32f1xx.c **** /* HSI oscillator clock divided by 2 selected as PLL clock entry */ 259:Core/Src/system_stm32f1xx.c **** SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; 260:Core/Src/system_stm32f1xx.c **** } 261:Core/Src/system_stm32f1xx.c **** else 262:Core/Src/system_stm32f1xx.c **** { 263:Core/Src/system_stm32f1xx.c **** #if defined(STM32F100xB) || defined(STM32F100xE) 264:Core/Src/system_stm32f1xx.c **** prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; 265:Core/Src/system_stm32f1xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */ 266:Core/Src/system_stm32f1xx.c **** SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 267:Core/Src/system_stm32f1xx.c **** #else 268:Core/Src/system_stm32f1xx.c **** /* HSE selected as PLL clock entry */ 269:Core/Src/system_stm32f1xx.c **** if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) 270:Core/Src/system_stm32f1xx.c **** {/* HSE oscillator clock divided by 2 */ 271:Core/Src/system_stm32f1xx.c **** SystemCoreClock = (HSE_VALUE >> 1U) * pllmull; 272:Core/Src/system_stm32f1xx.c **** } 273:Core/Src/system_stm32f1xx.c **** else 274:Core/Src/system_stm32f1xx.c **** { 275:Core/Src/system_stm32f1xx.c **** SystemCoreClock = HSE_VALUE * pllmull; 276:Core/Src/system_stm32f1xx.c **** } 277:Core/Src/system_stm32f1xx.c **** #endif 278:Core/Src/system_stm32f1xx.c **** } 279:Core/Src/system_stm32f1xx.c **** #else 280:Core/Src/system_stm32f1xx.c **** pllmull = pllmull >> 18U; ARM GAS /tmp/ccji4ked.s page 7 281:Core/Src/system_stm32f1xx.c **** 282:Core/Src/system_stm32f1xx.c **** if (pllmull != 0x0DU) 283:Core/Src/system_stm32f1xx.c **** { 284:Core/Src/system_stm32f1xx.c **** pllmull += 2U; 285:Core/Src/system_stm32f1xx.c **** } 286:Core/Src/system_stm32f1xx.c **** else 287:Core/Src/system_stm32f1xx.c **** { /* PLL multiplication factor = PLL input clock * 6.5 */ 288:Core/Src/system_stm32f1xx.c **** pllmull = 13U / 2U; 289:Core/Src/system_stm32f1xx.c **** } 290:Core/Src/system_stm32f1xx.c **** 291:Core/Src/system_stm32f1xx.c **** if (pllsource == 0x00U) 292:Core/Src/system_stm32f1xx.c **** { 293:Core/Src/system_stm32f1xx.c **** /* HSI oscillator clock divided by 2 selected as PLL clock entry */ 294:Core/Src/system_stm32f1xx.c **** SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; 295:Core/Src/system_stm32f1xx.c **** } 296:Core/Src/system_stm32f1xx.c **** else 297:Core/Src/system_stm32f1xx.c **** {/* PREDIV1 selected as PLL clock entry */ 298:Core/Src/system_stm32f1xx.c **** 299:Core/Src/system_stm32f1xx.c **** /* Get PREDIV1 clock source and division factor */ 300:Core/Src/system_stm32f1xx.c **** prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; 301:Core/Src/system_stm32f1xx.c **** prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; 302:Core/Src/system_stm32f1xx.c **** 303:Core/Src/system_stm32f1xx.c **** if (prediv1source == 0U) 304:Core/Src/system_stm32f1xx.c **** { 305:Core/Src/system_stm32f1xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */ 306:Core/Src/system_stm32f1xx.c **** SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 307:Core/Src/system_stm32f1xx.c **** } 308:Core/Src/system_stm32f1xx.c **** else 309:Core/Src/system_stm32f1xx.c **** {/* PLL2 clock selected as PREDIV1 clock entry */ 310:Core/Src/system_stm32f1xx.c **** 311:Core/Src/system_stm32f1xx.c **** /* Get PREDIV2 division factor and PLL2 multiplication factor */ 312:Core/Src/system_stm32f1xx.c **** prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U; 313:Core/Src/system_stm32f1xx.c **** pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U; 314:Core/Src/system_stm32f1xx.c **** SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; 315:Core/Src/system_stm32f1xx.c **** } 316:Core/Src/system_stm32f1xx.c **** } 317:Core/Src/system_stm32f1xx.c **** #endif /* STM32F105xC */ 318:Core/Src/system_stm32f1xx.c **** break; 319:Core/Src/system_stm32f1xx.c **** 320:Core/Src/system_stm32f1xx.c **** default: 321:Core/Src/system_stm32f1xx.c **** SystemCoreClock = HSI_VALUE; 66 .loc 1 321 7 view .LVU8 67 .loc 1 321 23 is_stmt 0 view .LVU9 68 0012 1C4B ldr r3, .L10+4 69 .LVL2: 70 .loc 1 321 23 view .LVU10 71 0014 1C4A ldr r2, .L10+8 72 0016 1A60 str r2, [r3] 322:Core/Src/system_stm32f1xx.c **** break; 73 .loc 1 322 7 is_stmt 1 view .LVU11 74 0018 02E0 b .L6 75 .LVL3: 76 .L9: 242:Core/Src/system_stm32f1xx.c **** break; 77 .loc 1 242 7 view .LVU12 242:Core/Src/system_stm32f1xx.c **** break; 78 .loc 1 242 23 is_stmt 0 view .LVU13 ARM GAS /tmp/ccji4ked.s page 8 79 001a 1A4B ldr r3, .L10+4 80 .LVL4: 242:Core/Src/system_stm32f1xx.c **** break; 81 .loc 1 242 23 view .LVU14 82 001c 1A4A ldr r2, .L10+8 83 001e 1A60 str r2, [r3] 243:Core/Src/system_stm32f1xx.c **** case 0x04U: /* HSE used as system clock */ 84 .loc 1 243 7 is_stmt 1 view .LVU15 85 .LVL5: 86 .L6: 323:Core/Src/system_stm32f1xx.c **** } 324:Core/Src/system_stm32f1xx.c **** 325:Core/Src/system_stm32f1xx.c **** /* Compute HCLK clock frequency ----------------*/ 326:Core/Src/system_stm32f1xx.c **** /* Get HCLK prescaler */ 327:Core/Src/system_stm32f1xx.c **** tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; 87 .loc 1 327 3 view .LVU16 88 .loc 1 327 28 is_stmt 0 view .LVU17 89 0020 174B ldr r3, .L10 90 0022 5B68 ldr r3, [r3, #4] 91 .loc 1 327 52 view .LVU18 92 0024 C3F30313 ubfx r3, r3, #4, #4 93 .loc 1 327 22 view .LVU19 94 0028 184A ldr r2, .L10+12 95 002a D15C ldrb r1, [r2, r3] @ zero_extendqisi2 96 .LVL6: 328:Core/Src/system_stm32f1xx.c **** /* HCLK clock frequency */ 329:Core/Src/system_stm32f1xx.c **** SystemCoreClock >>= tmp; 97 .loc 1 329 3 is_stmt 1 view .LVU20 98 .loc 1 329 19 is_stmt 0 view .LVU21 99 002c 154A ldr r2, .L10+4 100 002e 1368 ldr r3, [r2] 101 0030 CB40 lsrs r3, r3, r1 102 0032 1360 str r3, [r2] 330:Core/Src/system_stm32f1xx.c **** } 103 .loc 1 330 1 view .LVU22 104 0034 7047 bx lr 105 .LVL7: 106 .L3: 245:Core/Src/system_stm32f1xx.c **** break; 107 .loc 1 245 7 is_stmt 1 view .LVU23 245:Core/Src/system_stm32f1xx.c **** break; 108 .loc 1 245 23 is_stmt 0 view .LVU24 109 0036 134B ldr r3, .L10+4 110 .LVL8: 245:Core/Src/system_stm32f1xx.c **** break; 111 .loc 1 245 23 view .LVU25 112 0038 134A ldr r2, .L10+8 113 003a 1A60 str r2, [r3] 246:Core/Src/system_stm32f1xx.c **** case 0x08U: /* PLL used as system clock */ 114 .loc 1 246 7 is_stmt 1 view .LVU26 115 003c F0E7 b .L6 116 .LVL9: 117 .L4: 250:Core/Src/system_stm32f1xx.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; 118 .loc 1 250 7 view .LVU27 250:Core/Src/system_stm32f1xx.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; 119 .loc 1 250 20 is_stmt 0 view .LVU28 ARM GAS /tmp/ccji4ked.s page 9 120 003e 104A ldr r2, .L10 121 0040 5368 ldr r3, [r2, #4] 122 .LVL10: 251:Core/Src/system_stm32f1xx.c **** 123 .loc 1 251 7 is_stmt 1 view .LVU29 251:Core/Src/system_stm32f1xx.c **** 124 .loc 1 251 22 is_stmt 0 view .LVU30 125 0042 5268 ldr r2, [r2, #4] 126 .LVL11: 254:Core/Src/system_stm32f1xx.c **** 127 .loc 1 254 7 is_stmt 1 view .LVU31 254:Core/Src/system_stm32f1xx.c **** 128 .loc 1 254 27 is_stmt 0 view .LVU32 129 0044 C3F38343 ubfx r3, r3, #18, #4 130 .LVL12: 254:Core/Src/system_stm32f1xx.c **** 131 .loc 1 254 15 view .LVU33 132 0048 0233 adds r3, r3, #2 133 .LVL13: 256:Core/Src/system_stm32f1xx.c **** { 134 .loc 1 256 7 is_stmt 1 view .LVU34 256:Core/Src/system_stm32f1xx.c **** { 135 .loc 1 256 10 is_stmt 0 view .LVU35 136 004a 12F4803F tst r2, #65536 137 004e 05D1 bne .L7 259:Core/Src/system_stm32f1xx.c **** } 138 .loc 1 259 9 is_stmt 1 view .LVU36 259:Core/Src/system_stm32f1xx.c **** } 139 .loc 1 259 45 is_stmt 0 view .LVU37 140 0050 0F4A ldr r2, .L10+16 141 .LVL14: 259:Core/Src/system_stm32f1xx.c **** } 142 .loc 1 259 45 view .LVU38 143 0052 02FB03F3 mul r3, r2, r3 144 .LVL15: 259:Core/Src/system_stm32f1xx.c **** } 145 .loc 1 259 25 view .LVU39 146 0056 0B4A ldr r2, .L10+4 147 0058 1360 str r3, [r2] 148 005a E1E7 b .L6 149 .LVL16: 150 .L7: 269:Core/Src/system_stm32f1xx.c **** {/* HSE oscillator clock divided by 2 */ 151 .loc 1 269 9 is_stmt 1 view .LVU40 269:Core/Src/system_stm32f1xx.c **** {/* HSE oscillator clock divided by 2 */ 152 .loc 1 269 17 is_stmt 0 view .LVU41 153 005c 084A ldr r2, .L10 154 .LVL17: 269:Core/Src/system_stm32f1xx.c **** {/* HSE oscillator clock divided by 2 */ 155 .loc 1 269 17 view .LVU42 156 005e 5268 ldr r2, [r2, #4] 269:Core/Src/system_stm32f1xx.c **** {/* HSE oscillator clock divided by 2 */ 157 .loc 1 269 12 view .LVU43 158 0060 12F4003F tst r2, #131072 159 0064 05D0 beq .L8 271:Core/Src/system_stm32f1xx.c **** } 160 .loc 1 271 11 is_stmt 1 view .LVU44 ARM GAS /tmp/ccji4ked.s page 10 271:Core/Src/system_stm32f1xx.c **** } 161 .loc 1 271 47 is_stmt 0 view .LVU45 162 0066 0A4A ldr r2, .L10+16 163 0068 02FB03F3 mul r3, r2, r3 164 .LVL18: 271:Core/Src/system_stm32f1xx.c **** } 165 .loc 1 271 27 view .LVU46 166 006c 054A ldr r2, .L10+4 167 006e 1360 str r3, [r2] 168 0070 D6E7 b .L6 169 .LVL19: 170 .L8: 275:Core/Src/system_stm32f1xx.c **** } 171 .loc 1 275 11 is_stmt 1 view .LVU47 275:Core/Src/system_stm32f1xx.c **** } 172 .loc 1 275 39 is_stmt 0 view .LVU48 173 0072 054A ldr r2, .L10+8 174 0074 02FB03F3 mul r3, r2, r3 175 .LVL20: 275:Core/Src/system_stm32f1xx.c **** } 176 .loc 1 275 27 view .LVU49 177 0078 024A ldr r2, .L10+4 178 007a 1360 str r3, [r2] 179 007c D0E7 b .L6 180 .L11: 181 007e 00BF .align 2 182 .L10: 183 0080 00100240 .word 1073876992 184 0084 00000000 .word .LANCHOR0 185 0088 00127A00 .word 8000000 186 008c 00000000 .word .LANCHOR1 187 0090 00093D00 .word 4000000 188 .cfi_endproc 189 .LFE66: 191 .global APBPrescTable 192 .global AHBPrescTable 193 .global SystemCoreClock 194 .section .data.SystemCoreClock,"aw" 195 .align 2 196 .set .LANCHOR0,. + 0 199 SystemCoreClock: 200 0000 0024F400 .word 16000000 201 .section .rodata.AHBPrescTable,"a" 202 .align 2 203 .set .LANCHOR1,. + 0 206 AHBPrescTable: 207 0000 00000000 .ascii "\000\000\000\000\000\000\000\000\001\002\003\004\006" 207 00000000 207 01020304 207 06 208 000d 070809 .ascii "\007\010\011" 209 .section .rodata.APBPrescTable,"a" 210 .align 2 213 APBPrescTable: 214 0000 00000000 .ascii "\000\000\000\000\001\002\003\004" 214 01020304 215 .text ARM GAS /tmp/ccji4ked.s page 11 216 .Letext0: 217 .file 2 "/opt/gcc-arm/arm-none-eabi/include/machine/_default_types.h" 218 .file 3 "/opt/gcc-arm/arm-none-eabi/include/sys/_stdint.h" 219 .file 4 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h" 220 .file 5 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h" 221 .file 6 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h" ARM GAS /tmp/ccji4ked.s page 12 DEFINED SYMBOLS *ABS*:0000000000000000 system_stm32f1xx.c /tmp/ccji4ked.s:18 .text.SystemInit:0000000000000000 $t /tmp/ccji4ked.s:24 .text.SystemInit:0000000000000000 SystemInit /tmp/ccji4ked.s:38 .text.SystemCoreClockUpdate:0000000000000000 $t /tmp/ccji4ked.s:44 .text.SystemCoreClockUpdate:0000000000000000 SystemCoreClockUpdate /tmp/ccji4ked.s:183 .text.SystemCoreClockUpdate:0000000000000080 $d /tmp/ccji4ked.s:213 .rodata.APBPrescTable:0000000000000000 APBPrescTable /tmp/ccji4ked.s:206 .rodata.AHBPrescTable:0000000000000000 AHBPrescTable /tmp/ccji4ked.s:199 .data.SystemCoreClock:0000000000000000 SystemCoreClock /tmp/ccji4ked.s:195 .data.SystemCoreClock:0000000000000000 $d /tmp/ccji4ked.s:202 .rodata.AHBPrescTable:0000000000000000 $d /tmp/ccji4ked.s:210 .rodata.APBPrescTable:0000000000000000 $d NO UNDEFINED SYMBOLS