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- ARM GAS /tmp/ccBGIhL8.s page 1
- 1 .cpu cortex-m3
- 2 .arch armv7-m
- 3 .fpu softvfp
- 4 .eabi_attribute 20, 1
- 5 .eabi_attribute 21, 1
- 6 .eabi_attribute 23, 3
- 7 .eabi_attribute 24, 1
- 8 .eabi_attribute 25, 1
- 9 .eabi_attribute 26, 1
- 10 .eabi_attribute 30, 1
- 11 .eabi_attribute 34, 1
- 12 .eabi_attribute 18, 4
- 13 .file "main.c"
- 14 .text
- 15 .Ltext0:
- 16 .cfi_sections .debug_frame
- 17 .file 1 "Core/Src/main.c"
- 18 .section .text.NVIC_EncodePriority,"ax",%progbits
- 19 .align 1
- 20 .syntax unified
- 21 .thumb
- 22 .thumb_func
- 24 NVIC_EncodePriority:
- 25 .LVL0:
- 26 .LFB55:
- 27 .file 2 "Drivers/CMSIS/Include/core_cm3.h"
- 1:Drivers/CMSIS/Include/core_cm3.h **** /**************************************************************************//**
- 2:Drivers/CMSIS/Include/core_cm3.h **** * @file core_cm3.h
- 3:Drivers/CMSIS/Include/core_cm3.h **** * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- 4:Drivers/CMSIS/Include/core_cm3.h **** * @version V5.0.8
- 5:Drivers/CMSIS/Include/core_cm3.h **** * @date 04. June 2018
- 6:Drivers/CMSIS/Include/core_cm3.h **** ******************************************************************************/
- 7:Drivers/CMSIS/Include/core_cm3.h **** /*
- 8:Drivers/CMSIS/Include/core_cm3.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- 9:Drivers/CMSIS/Include/core_cm3.h **** *
- 10:Drivers/CMSIS/Include/core_cm3.h **** * SPDX-License-Identifier: Apache-2.0
- 11:Drivers/CMSIS/Include/core_cm3.h **** *
- 12:Drivers/CMSIS/Include/core_cm3.h **** * Licensed under the Apache License, Version 2.0 (the License); you may
- 13:Drivers/CMSIS/Include/core_cm3.h **** * not use this file except in compliance with the License.
- 14:Drivers/CMSIS/Include/core_cm3.h **** * You may obtain a copy of the License at
- 15:Drivers/CMSIS/Include/core_cm3.h **** *
- 16:Drivers/CMSIS/Include/core_cm3.h **** * www.apache.org/licenses/LICENSE-2.0
- 17:Drivers/CMSIS/Include/core_cm3.h **** *
- 18:Drivers/CMSIS/Include/core_cm3.h **** * Unless required by applicable law or agreed to in writing, software
- 19:Drivers/CMSIS/Include/core_cm3.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- 20:Drivers/CMSIS/Include/core_cm3.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- 21:Drivers/CMSIS/Include/core_cm3.h **** * See the License for the specific language governing permissions and
- 22:Drivers/CMSIS/Include/core_cm3.h **** * limitations under the License.
- 23:Drivers/CMSIS/Include/core_cm3.h **** */
- 24:Drivers/CMSIS/Include/core_cm3.h ****
- 25:Drivers/CMSIS/Include/core_cm3.h **** #if defined ( __ICCARM__ )
- 26:Drivers/CMSIS/Include/core_cm3.h **** #pragma system_include /* treat file as system include file for MISRA check */
- 27:Drivers/CMSIS/Include/core_cm3.h **** #elif defined (__clang__)
- 28:Drivers/CMSIS/Include/core_cm3.h **** #pragma clang system_header /* treat file as system include file */
- 29:Drivers/CMSIS/Include/core_cm3.h **** #endif
- 30:Drivers/CMSIS/Include/core_cm3.h ****
- 31:Drivers/CMSIS/Include/core_cm3.h **** #ifndef __CORE_CM3_H_GENERIC
- ARM GAS /tmp/ccBGIhL8.s page 2
- 32:Drivers/CMSIS/Include/core_cm3.h **** #define __CORE_CM3_H_GENERIC
- 33:Drivers/CMSIS/Include/core_cm3.h ****
- 34:Drivers/CMSIS/Include/core_cm3.h **** #include <stdint.h>
- 35:Drivers/CMSIS/Include/core_cm3.h ****
- 36:Drivers/CMSIS/Include/core_cm3.h **** #ifdef __cplusplus
- 37:Drivers/CMSIS/Include/core_cm3.h **** extern "C" {
- 38:Drivers/CMSIS/Include/core_cm3.h **** #endif
- 39:Drivers/CMSIS/Include/core_cm3.h ****
- 40:Drivers/CMSIS/Include/core_cm3.h **** /**
- 41:Drivers/CMSIS/Include/core_cm3.h **** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- 42:Drivers/CMSIS/Include/core_cm3.h **** CMSIS violates the following MISRA-C:2004 rules:
- 43:Drivers/CMSIS/Include/core_cm3.h ****
- 44:Drivers/CMSIS/Include/core_cm3.h **** \li Required Rule 8.5, object/function definition in header file.<br>
- 45:Drivers/CMSIS/Include/core_cm3.h **** Function definitions in header files are used to allow 'inlining'.
- 46:Drivers/CMSIS/Include/core_cm3.h ****
- 47:Drivers/CMSIS/Include/core_cm3.h **** \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- 48:Drivers/CMSIS/Include/core_cm3.h **** Unions are used for effective representation of core registers.
- 49:Drivers/CMSIS/Include/core_cm3.h ****
- 50:Drivers/CMSIS/Include/core_cm3.h **** \li Advisory Rule 19.7, Function-like macro defined.<br>
- 51:Drivers/CMSIS/Include/core_cm3.h **** Function-like macros are used to allow more efficient code.
- 52:Drivers/CMSIS/Include/core_cm3.h **** */
- 53:Drivers/CMSIS/Include/core_cm3.h ****
- 54:Drivers/CMSIS/Include/core_cm3.h ****
- 55:Drivers/CMSIS/Include/core_cm3.h **** /*******************************************************************************
- 56:Drivers/CMSIS/Include/core_cm3.h **** * CMSIS definitions
- 57:Drivers/CMSIS/Include/core_cm3.h **** ******************************************************************************/
- 58:Drivers/CMSIS/Include/core_cm3.h **** /**
- 59:Drivers/CMSIS/Include/core_cm3.h **** \ingroup Cortex_M3
- 60:Drivers/CMSIS/Include/core_cm3.h **** @{
- 61:Drivers/CMSIS/Include/core_cm3.h **** */
- 62:Drivers/CMSIS/Include/core_cm3.h ****
- 63:Drivers/CMSIS/Include/core_cm3.h **** #include "cmsis_version.h"
- 64:Drivers/CMSIS/Include/core_cm3.h ****
- 65:Drivers/CMSIS/Include/core_cm3.h **** /* CMSIS CM3 definitions */
- 66:Drivers/CMSIS/Include/core_cm3.h **** #define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] C
- 67:Drivers/CMSIS/Include/core_cm3.h **** #define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] C
- 68:Drivers/CMSIS/Include/core_cm3.h **** #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
- 69:Drivers/CMSIS/Include/core_cm3.h **** __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL
- 70:Drivers/CMSIS/Include/core_cm3.h ****
- 71:Drivers/CMSIS/Include/core_cm3.h **** #define __CORTEX_M (3U) /*!< Cortex-M Core */
- 72:Drivers/CMSIS/Include/core_cm3.h ****
- 73:Drivers/CMSIS/Include/core_cm3.h **** /** __FPU_USED indicates whether an FPU is used or not.
- 74:Drivers/CMSIS/Include/core_cm3.h **** This core does not support an FPU at all
- 75:Drivers/CMSIS/Include/core_cm3.h **** */
- 76:Drivers/CMSIS/Include/core_cm3.h **** #define __FPU_USED 0U
- 77:Drivers/CMSIS/Include/core_cm3.h ****
- 78:Drivers/CMSIS/Include/core_cm3.h **** #if defined ( __CC_ARM )
- 79:Drivers/CMSIS/Include/core_cm3.h **** #if defined __TARGET_FPU_VFP
- 80:Drivers/CMSIS/Include/core_cm3.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- 81:Drivers/CMSIS/Include/core_cm3.h **** #endif
- 82:Drivers/CMSIS/Include/core_cm3.h ****
- 83:Drivers/CMSIS/Include/core_cm3.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- 84:Drivers/CMSIS/Include/core_cm3.h **** #if defined __ARM_PCS_VFP
- 85:Drivers/CMSIS/Include/core_cm3.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- 86:Drivers/CMSIS/Include/core_cm3.h **** #endif
- 87:Drivers/CMSIS/Include/core_cm3.h ****
- 88:Drivers/CMSIS/Include/core_cm3.h **** #elif defined ( __GNUC__ )
- ARM GAS /tmp/ccBGIhL8.s page 3
- 89:Drivers/CMSIS/Include/core_cm3.h **** #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- 90:Drivers/CMSIS/Include/core_cm3.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- 91:Drivers/CMSIS/Include/core_cm3.h **** #endif
- 92:Drivers/CMSIS/Include/core_cm3.h ****
- 93:Drivers/CMSIS/Include/core_cm3.h **** #elif defined ( __ICCARM__ )
- 94:Drivers/CMSIS/Include/core_cm3.h **** #if defined __ARMVFP__
- 95:Drivers/CMSIS/Include/core_cm3.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- 96:Drivers/CMSIS/Include/core_cm3.h **** #endif
- 97:Drivers/CMSIS/Include/core_cm3.h ****
- 98:Drivers/CMSIS/Include/core_cm3.h **** #elif defined ( __TI_ARM__ )
- 99:Drivers/CMSIS/Include/core_cm3.h **** #if defined __TI_VFP_SUPPORT__
- 100:Drivers/CMSIS/Include/core_cm3.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- 101:Drivers/CMSIS/Include/core_cm3.h **** #endif
- 102:Drivers/CMSIS/Include/core_cm3.h ****
- 103:Drivers/CMSIS/Include/core_cm3.h **** #elif defined ( __TASKING__ )
- 104:Drivers/CMSIS/Include/core_cm3.h **** #if defined __FPU_VFP__
- 105:Drivers/CMSIS/Include/core_cm3.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- 106:Drivers/CMSIS/Include/core_cm3.h **** #endif
- 107:Drivers/CMSIS/Include/core_cm3.h ****
- 108:Drivers/CMSIS/Include/core_cm3.h **** #elif defined ( __CSMC__ )
- 109:Drivers/CMSIS/Include/core_cm3.h **** #if ( __CSMC__ & 0x400U)
- 110:Drivers/CMSIS/Include/core_cm3.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- 111:Drivers/CMSIS/Include/core_cm3.h **** #endif
- 112:Drivers/CMSIS/Include/core_cm3.h ****
- 113:Drivers/CMSIS/Include/core_cm3.h **** #endif
- 114:Drivers/CMSIS/Include/core_cm3.h ****
- 115:Drivers/CMSIS/Include/core_cm3.h **** #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
- 116:Drivers/CMSIS/Include/core_cm3.h ****
- 117:Drivers/CMSIS/Include/core_cm3.h ****
- 118:Drivers/CMSIS/Include/core_cm3.h **** #ifdef __cplusplus
- 119:Drivers/CMSIS/Include/core_cm3.h **** }
- 120:Drivers/CMSIS/Include/core_cm3.h **** #endif
- 121:Drivers/CMSIS/Include/core_cm3.h ****
- 122:Drivers/CMSIS/Include/core_cm3.h **** #endif /* __CORE_CM3_H_GENERIC */
- 123:Drivers/CMSIS/Include/core_cm3.h ****
- 124:Drivers/CMSIS/Include/core_cm3.h **** #ifndef __CMSIS_GENERIC
- 125:Drivers/CMSIS/Include/core_cm3.h ****
- 126:Drivers/CMSIS/Include/core_cm3.h **** #ifndef __CORE_CM3_H_DEPENDANT
- 127:Drivers/CMSIS/Include/core_cm3.h **** #define __CORE_CM3_H_DEPENDANT
- 128:Drivers/CMSIS/Include/core_cm3.h ****
- 129:Drivers/CMSIS/Include/core_cm3.h **** #ifdef __cplusplus
- 130:Drivers/CMSIS/Include/core_cm3.h **** extern "C" {
- 131:Drivers/CMSIS/Include/core_cm3.h **** #endif
- 132:Drivers/CMSIS/Include/core_cm3.h ****
- 133:Drivers/CMSIS/Include/core_cm3.h **** /* check device defines and use defaults */
- 134:Drivers/CMSIS/Include/core_cm3.h **** #if defined __CHECK_DEVICE_DEFINES
- 135:Drivers/CMSIS/Include/core_cm3.h **** #ifndef __CM3_REV
- 136:Drivers/CMSIS/Include/core_cm3.h **** #define __CM3_REV 0x0200U
- 137:Drivers/CMSIS/Include/core_cm3.h **** #warning "__CM3_REV not defined in device header file; using default!"
- 138:Drivers/CMSIS/Include/core_cm3.h **** #endif
- 139:Drivers/CMSIS/Include/core_cm3.h ****
- 140:Drivers/CMSIS/Include/core_cm3.h **** #ifndef __MPU_PRESENT
- 141:Drivers/CMSIS/Include/core_cm3.h **** #define __MPU_PRESENT 0U
- 142:Drivers/CMSIS/Include/core_cm3.h **** #warning "__MPU_PRESENT not defined in device header file; using default!"
- 143:Drivers/CMSIS/Include/core_cm3.h **** #endif
- 144:Drivers/CMSIS/Include/core_cm3.h ****
- 145:Drivers/CMSIS/Include/core_cm3.h **** #ifndef __NVIC_PRIO_BITS
- ARM GAS /tmp/ccBGIhL8.s page 4
- 146:Drivers/CMSIS/Include/core_cm3.h **** #define __NVIC_PRIO_BITS 3U
- 147:Drivers/CMSIS/Include/core_cm3.h **** #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- 148:Drivers/CMSIS/Include/core_cm3.h **** #endif
- 149:Drivers/CMSIS/Include/core_cm3.h ****
- 150:Drivers/CMSIS/Include/core_cm3.h **** #ifndef __Vendor_SysTickConfig
- 151:Drivers/CMSIS/Include/core_cm3.h **** #define __Vendor_SysTickConfig 0U
- 152:Drivers/CMSIS/Include/core_cm3.h **** #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- 153:Drivers/CMSIS/Include/core_cm3.h **** #endif
- 154:Drivers/CMSIS/Include/core_cm3.h **** #endif
- 155:Drivers/CMSIS/Include/core_cm3.h ****
- 156:Drivers/CMSIS/Include/core_cm3.h **** /* IO definitions (access restrictions to peripheral registers) */
- 157:Drivers/CMSIS/Include/core_cm3.h **** /**
- 158:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_glob_defs CMSIS Global Defines
- 159:Drivers/CMSIS/Include/core_cm3.h ****
- 160:Drivers/CMSIS/Include/core_cm3.h **** <strong>IO Type Qualifiers</strong> are used
- 161:Drivers/CMSIS/Include/core_cm3.h **** \li to specify the access to peripheral variables.
- 162:Drivers/CMSIS/Include/core_cm3.h **** \li for automatic generation of peripheral register debug information.
- 163:Drivers/CMSIS/Include/core_cm3.h **** */
- 164:Drivers/CMSIS/Include/core_cm3.h **** #ifdef __cplusplus
- 165:Drivers/CMSIS/Include/core_cm3.h **** #define __I volatile /*!< Defines 'read only' permissions */
- 166:Drivers/CMSIS/Include/core_cm3.h **** #else
- 167:Drivers/CMSIS/Include/core_cm3.h **** #define __I volatile const /*!< Defines 'read only' permissions */
- 168:Drivers/CMSIS/Include/core_cm3.h **** #endif
- 169:Drivers/CMSIS/Include/core_cm3.h **** #define __O volatile /*!< Defines 'write only' permissions */
- 170:Drivers/CMSIS/Include/core_cm3.h **** #define __IO volatile /*!< Defines 'read / write' permissions */
- 171:Drivers/CMSIS/Include/core_cm3.h ****
- 172:Drivers/CMSIS/Include/core_cm3.h **** /* following defines should be used for structure members */
- 173:Drivers/CMSIS/Include/core_cm3.h **** #define __IM volatile const /*! Defines 'read only' structure member permissions */
- 174:Drivers/CMSIS/Include/core_cm3.h **** #define __OM volatile /*! Defines 'write only' structure member permissions */
- 175:Drivers/CMSIS/Include/core_cm3.h **** #define __IOM volatile /*! Defines 'read / write' structure member permissions */
- 176:Drivers/CMSIS/Include/core_cm3.h ****
- 177:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of group Cortex_M3 */
- 178:Drivers/CMSIS/Include/core_cm3.h ****
- 179:Drivers/CMSIS/Include/core_cm3.h ****
- 180:Drivers/CMSIS/Include/core_cm3.h ****
- 181:Drivers/CMSIS/Include/core_cm3.h **** /*******************************************************************************
- 182:Drivers/CMSIS/Include/core_cm3.h **** * Register Abstraction
- 183:Drivers/CMSIS/Include/core_cm3.h **** Core Register contain:
- 184:Drivers/CMSIS/Include/core_cm3.h **** - Core Register
- 185:Drivers/CMSIS/Include/core_cm3.h **** - Core NVIC Register
- 186:Drivers/CMSIS/Include/core_cm3.h **** - Core SCB Register
- 187:Drivers/CMSIS/Include/core_cm3.h **** - Core SysTick Register
- 188:Drivers/CMSIS/Include/core_cm3.h **** - Core Debug Register
- 189:Drivers/CMSIS/Include/core_cm3.h **** - Core MPU Register
- 190:Drivers/CMSIS/Include/core_cm3.h **** ******************************************************************************/
- 191:Drivers/CMSIS/Include/core_cm3.h **** /**
- 192:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_core_register Defines and Type Definitions
- 193:Drivers/CMSIS/Include/core_cm3.h **** \brief Type definitions and defines for Cortex-M processor based devices.
- 194:Drivers/CMSIS/Include/core_cm3.h **** */
- 195:Drivers/CMSIS/Include/core_cm3.h ****
- 196:Drivers/CMSIS/Include/core_cm3.h **** /**
- 197:Drivers/CMSIS/Include/core_cm3.h **** \ingroup CMSIS_core_register
- 198:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_CORE Status and Control Registers
- 199:Drivers/CMSIS/Include/core_cm3.h **** \brief Core Register type definitions.
- 200:Drivers/CMSIS/Include/core_cm3.h **** @{
- 201:Drivers/CMSIS/Include/core_cm3.h **** */
- 202:Drivers/CMSIS/Include/core_cm3.h ****
- ARM GAS /tmp/ccBGIhL8.s page 5
- 203:Drivers/CMSIS/Include/core_cm3.h **** /**
- 204:Drivers/CMSIS/Include/core_cm3.h **** \brief Union type to access the Application Program Status Register (APSR).
- 205:Drivers/CMSIS/Include/core_cm3.h **** */
- 206:Drivers/CMSIS/Include/core_cm3.h **** typedef union
- 207:Drivers/CMSIS/Include/core_cm3.h **** {
- 208:Drivers/CMSIS/Include/core_cm3.h **** struct
- 209:Drivers/CMSIS/Include/core_cm3.h **** {
- 210:Drivers/CMSIS/Include/core_cm3.h **** uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
- 211:Drivers/CMSIS/Include/core_cm3.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- 212:Drivers/CMSIS/Include/core_cm3.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- 213:Drivers/CMSIS/Include/core_cm3.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- 214:Drivers/CMSIS/Include/core_cm3.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- 215:Drivers/CMSIS/Include/core_cm3.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- 216:Drivers/CMSIS/Include/core_cm3.h **** } b; /*!< Structure used for bit access */
- 217:Drivers/CMSIS/Include/core_cm3.h **** uint32_t w; /*!< Type used for word access */
- 218:Drivers/CMSIS/Include/core_cm3.h **** } APSR_Type;
- 219:Drivers/CMSIS/Include/core_cm3.h ****
- 220:Drivers/CMSIS/Include/core_cm3.h **** /* APSR Register Definitions */
- 221:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_N_Pos 31U /*!< APSR
- 222:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR
- 223:Drivers/CMSIS/Include/core_cm3.h ****
- 224:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_Z_Pos 30U /*!< APSR
- 225:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR
- 226:Drivers/CMSIS/Include/core_cm3.h ****
- 227:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_C_Pos 29U /*!< APSR
- 228:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR
- 229:Drivers/CMSIS/Include/core_cm3.h ****
- 230:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_V_Pos 28U /*!< APSR
- 231:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR
- 232:Drivers/CMSIS/Include/core_cm3.h ****
- 233:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_Q_Pos 27U /*!< APSR
- 234:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR
- 235:Drivers/CMSIS/Include/core_cm3.h ****
- 236:Drivers/CMSIS/Include/core_cm3.h ****
- 237:Drivers/CMSIS/Include/core_cm3.h **** /**
- 238:Drivers/CMSIS/Include/core_cm3.h **** \brief Union type to access the Interrupt Program Status Register (IPSR).
- 239:Drivers/CMSIS/Include/core_cm3.h **** */
- 240:Drivers/CMSIS/Include/core_cm3.h **** typedef union
- 241:Drivers/CMSIS/Include/core_cm3.h **** {
- 242:Drivers/CMSIS/Include/core_cm3.h **** struct
- 243:Drivers/CMSIS/Include/core_cm3.h **** {
- 244:Drivers/CMSIS/Include/core_cm3.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- 245:Drivers/CMSIS/Include/core_cm3.h **** uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- 246:Drivers/CMSIS/Include/core_cm3.h **** } b; /*!< Structure used for bit access */
- 247:Drivers/CMSIS/Include/core_cm3.h **** uint32_t w; /*!< Type used for word access */
- 248:Drivers/CMSIS/Include/core_cm3.h **** } IPSR_Type;
- 249:Drivers/CMSIS/Include/core_cm3.h ****
- 250:Drivers/CMSIS/Include/core_cm3.h **** /* IPSR Register Definitions */
- 251:Drivers/CMSIS/Include/core_cm3.h **** #define IPSR_ISR_Pos 0U /*!< IPSR
- 252:Drivers/CMSIS/Include/core_cm3.h **** #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR
- 253:Drivers/CMSIS/Include/core_cm3.h ****
- 254:Drivers/CMSIS/Include/core_cm3.h ****
- 255:Drivers/CMSIS/Include/core_cm3.h **** /**
- 256:Drivers/CMSIS/Include/core_cm3.h **** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- 257:Drivers/CMSIS/Include/core_cm3.h **** */
- 258:Drivers/CMSIS/Include/core_cm3.h **** typedef union
- 259:Drivers/CMSIS/Include/core_cm3.h **** {
- ARM GAS /tmp/ccBGIhL8.s page 6
- 260:Drivers/CMSIS/Include/core_cm3.h **** struct
- 261:Drivers/CMSIS/Include/core_cm3.h **** {
- 262:Drivers/CMSIS/Include/core_cm3.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- 263:Drivers/CMSIS/Include/core_cm3.h **** uint32_t _reserved0:1; /*!< bit: 9 Reserved */
- 264:Drivers/CMSIS/Include/core_cm3.h **** uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
- 265:Drivers/CMSIS/Include/core_cm3.h **** uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
- 266:Drivers/CMSIS/Include/core_cm3.h **** uint32_t T:1; /*!< bit: 24 Thumb bit */
- 267:Drivers/CMSIS/Include/core_cm3.h **** uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
- 268:Drivers/CMSIS/Include/core_cm3.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- 269:Drivers/CMSIS/Include/core_cm3.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- 270:Drivers/CMSIS/Include/core_cm3.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- 271:Drivers/CMSIS/Include/core_cm3.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- 272:Drivers/CMSIS/Include/core_cm3.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- 273:Drivers/CMSIS/Include/core_cm3.h **** } b; /*!< Structure used for bit access */
- 274:Drivers/CMSIS/Include/core_cm3.h **** uint32_t w; /*!< Type used for word access */
- 275:Drivers/CMSIS/Include/core_cm3.h **** } xPSR_Type;
- 276:Drivers/CMSIS/Include/core_cm3.h ****
- 277:Drivers/CMSIS/Include/core_cm3.h **** /* xPSR Register Definitions */
- 278:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_N_Pos 31U /*!< xPSR
- 279:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR
- 280:Drivers/CMSIS/Include/core_cm3.h ****
- 281:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_Z_Pos 30U /*!< xPSR
- 282:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR
- 283:Drivers/CMSIS/Include/core_cm3.h ****
- 284:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_C_Pos 29U /*!< xPSR
- 285:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR
- 286:Drivers/CMSIS/Include/core_cm3.h ****
- 287:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_V_Pos 28U /*!< xPSR
- 288:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR
- 289:Drivers/CMSIS/Include/core_cm3.h ****
- 290:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_Q_Pos 27U /*!< xPSR
- 291:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR
- 292:Drivers/CMSIS/Include/core_cm3.h ****
- 293:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR
- 294:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR
- 295:Drivers/CMSIS/Include/core_cm3.h ****
- 296:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_T_Pos 24U /*!< xPSR
- 297:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR
- 298:Drivers/CMSIS/Include/core_cm3.h ****
- 299:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR
- 300:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR
- 301:Drivers/CMSIS/Include/core_cm3.h ****
- 302:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_ISR_Pos 0U /*!< xPSR
- 303:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR
- 304:Drivers/CMSIS/Include/core_cm3.h ****
- 305:Drivers/CMSIS/Include/core_cm3.h ****
- 306:Drivers/CMSIS/Include/core_cm3.h **** /**
- 307:Drivers/CMSIS/Include/core_cm3.h **** \brief Union type to access the Control Registers (CONTROL).
- 308:Drivers/CMSIS/Include/core_cm3.h **** */
- 309:Drivers/CMSIS/Include/core_cm3.h **** typedef union
- 310:Drivers/CMSIS/Include/core_cm3.h **** {
- 311:Drivers/CMSIS/Include/core_cm3.h **** struct
- 312:Drivers/CMSIS/Include/core_cm3.h **** {
- 313:Drivers/CMSIS/Include/core_cm3.h **** uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- 314:Drivers/CMSIS/Include/core_cm3.h **** uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- 315:Drivers/CMSIS/Include/core_cm3.h **** uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
- 316:Drivers/CMSIS/Include/core_cm3.h **** } b; /*!< Structure used for bit access */
- ARM GAS /tmp/ccBGIhL8.s page 7
- 317:Drivers/CMSIS/Include/core_cm3.h **** uint32_t w; /*!< Type used for word access */
- 318:Drivers/CMSIS/Include/core_cm3.h **** } CONTROL_Type;
- 319:Drivers/CMSIS/Include/core_cm3.h ****
- 320:Drivers/CMSIS/Include/core_cm3.h **** /* CONTROL Register Definitions */
- 321:Drivers/CMSIS/Include/core_cm3.h **** #define CONTROL_SPSEL_Pos 1U /*!< CONT
- 322:Drivers/CMSIS/Include/core_cm3.h **** #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONT
- 323:Drivers/CMSIS/Include/core_cm3.h ****
- 324:Drivers/CMSIS/Include/core_cm3.h **** #define CONTROL_nPRIV_Pos 0U /*!< CONT
- 325:Drivers/CMSIS/Include/core_cm3.h **** #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONT
- 326:Drivers/CMSIS/Include/core_cm3.h ****
- 327:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of group CMSIS_CORE */
- 328:Drivers/CMSIS/Include/core_cm3.h ****
- 329:Drivers/CMSIS/Include/core_cm3.h ****
- 330:Drivers/CMSIS/Include/core_cm3.h **** /**
- 331:Drivers/CMSIS/Include/core_cm3.h **** \ingroup CMSIS_core_register
- 332:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- 333:Drivers/CMSIS/Include/core_cm3.h **** \brief Type definitions for the NVIC Registers
- 334:Drivers/CMSIS/Include/core_cm3.h **** @{
- 335:Drivers/CMSIS/Include/core_cm3.h **** */
- 336:Drivers/CMSIS/Include/core_cm3.h ****
- 337:Drivers/CMSIS/Include/core_cm3.h **** /**
- 338:Drivers/CMSIS/Include/core_cm3.h **** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- 339:Drivers/CMSIS/Include/core_cm3.h **** */
- 340:Drivers/CMSIS/Include/core_cm3.h **** typedef struct
- 341:Drivers/CMSIS/Include/core_cm3.h **** {
- 342:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- 343:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED0[24U];
- 344:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register
- 345:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RSERVED1[24U];
- 346:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register *
- 347:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED2[24U];
- 348:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register
- 349:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED3[24U];
- 350:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- 351:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED4[56U];
- 352:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bi
- 353:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED5[644U];
- 354:Drivers/CMSIS/Include/core_cm3.h **** __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regis
- 355:Drivers/CMSIS/Include/core_cm3.h **** } NVIC_Type;
- 356:Drivers/CMSIS/Include/core_cm3.h ****
- 357:Drivers/CMSIS/Include/core_cm3.h **** /* Software Triggered Interrupt Register Definitions */
- 358:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_STIR_INTID_Pos 0U /*!< STIR: I
- 359:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: I
- 360:Drivers/CMSIS/Include/core_cm3.h ****
- 361:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of group CMSIS_NVIC */
- 362:Drivers/CMSIS/Include/core_cm3.h ****
- 363:Drivers/CMSIS/Include/core_cm3.h ****
- 364:Drivers/CMSIS/Include/core_cm3.h **** /**
- 365:Drivers/CMSIS/Include/core_cm3.h **** \ingroup CMSIS_core_register
- 366:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_SCB System Control Block (SCB)
- 367:Drivers/CMSIS/Include/core_cm3.h **** \brief Type definitions for the System Control Block Registers
- 368:Drivers/CMSIS/Include/core_cm3.h **** @{
- 369:Drivers/CMSIS/Include/core_cm3.h **** */
- 370:Drivers/CMSIS/Include/core_cm3.h ****
- 371:Drivers/CMSIS/Include/core_cm3.h **** /**
- 372:Drivers/CMSIS/Include/core_cm3.h **** \brief Structure type to access the System Control Block (SCB).
- 373:Drivers/CMSIS/Include/core_cm3.h **** */
- ARM GAS /tmp/ccBGIhL8.s page 8
- 374:Drivers/CMSIS/Include/core_cm3.h **** typedef struct
- 375:Drivers/CMSIS/Include/core_cm3.h **** {
- 376:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- 377:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regi
- 378:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- 379:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset
- 380:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- 381:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register *
- 382:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registe
- 383:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State
- 384:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Regist
- 385:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- 386:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- 387:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register
- 388:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- 389:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register
- 390:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- 391:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- 392:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- 393:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- 394:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regis
- 395:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED0[5U];
- 396:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Regis
- 397:Drivers/CMSIS/Include/core_cm3.h **** } SCB_Type;
- 398:Drivers/CMSIS/Include/core_cm3.h ****
- 399:Drivers/CMSIS/Include/core_cm3.h **** /* SCB CPUID Register Definitions */
- 400:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB
- 401:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB
- 402:Drivers/CMSIS/Include/core_cm3.h ****
- 403:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB
- 404:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB
- 405:Drivers/CMSIS/Include/core_cm3.h ****
- 406:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB
- 407:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB
- 408:Drivers/CMSIS/Include/core_cm3.h ****
- 409:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB
- 410:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB
- 411:Drivers/CMSIS/Include/core_cm3.h ****
- 412:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_REVISION_Pos 0U /*!< SCB
- 413:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB
- 414:Drivers/CMSIS/Include/core_cm3.h ****
- 415:Drivers/CMSIS/Include/core_cm3.h **** /* SCB Interrupt Control State Register Definitions */
- 416:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB
- 417:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB
- 418:Drivers/CMSIS/Include/core_cm3.h ****
- 419:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB
- 420:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB
- 421:Drivers/CMSIS/Include/core_cm3.h ****
- 422:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB
- 423:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB
- 424:Drivers/CMSIS/Include/core_cm3.h ****
- 425:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB
- 426:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB
- 427:Drivers/CMSIS/Include/core_cm3.h ****
- 428:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB
- 429:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB
- 430:Drivers/CMSIS/Include/core_cm3.h ****
- ARM GAS /tmp/ccBGIhL8.s page 9
- 431:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB
- 432:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB
- 433:Drivers/CMSIS/Include/core_cm3.h ****
- 434:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB
- 435:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB
- 436:Drivers/CMSIS/Include/core_cm3.h ****
- 437:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB
- 438:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB
- 439:Drivers/CMSIS/Include/core_cm3.h ****
- 440:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB
- 441:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB
- 442:Drivers/CMSIS/Include/core_cm3.h ****
- 443:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB
- 444:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB
- 445:Drivers/CMSIS/Include/core_cm3.h ****
- 446:Drivers/CMSIS/Include/core_cm3.h **** /* SCB Vector Table Offset Register Definitions */
- 447:Drivers/CMSIS/Include/core_cm3.h **** #if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
- 448:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB
- 449:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB
- 450:Drivers/CMSIS/Include/core_cm3.h ****
- 451:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB
- 452:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB
- 453:Drivers/CMSIS/Include/core_cm3.h **** #else
- 454:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB
- 455:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB
- 456:Drivers/CMSIS/Include/core_cm3.h **** #endif
- 457:Drivers/CMSIS/Include/core_cm3.h ****
- 458:Drivers/CMSIS/Include/core_cm3.h **** /* SCB Application Interrupt and Reset Control Register Definitions */
- 459:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB
- 460:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB
- 461:Drivers/CMSIS/Include/core_cm3.h ****
- 462:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB
- 463:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB
- 464:Drivers/CMSIS/Include/core_cm3.h ****
- 465:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB
- 466:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB
- 467:Drivers/CMSIS/Include/core_cm3.h ****
- 468:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB
- 469:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB
- 470:Drivers/CMSIS/Include/core_cm3.h ****
- 471:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB
- 472:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB
- 473:Drivers/CMSIS/Include/core_cm3.h ****
- 474:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB
- 475:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB
- 476:Drivers/CMSIS/Include/core_cm3.h ****
- 477:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB
- 478:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB
- 479:Drivers/CMSIS/Include/core_cm3.h ****
- 480:Drivers/CMSIS/Include/core_cm3.h **** /* SCB System Control Register Definitions */
- 481:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB
- 482:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB
- 483:Drivers/CMSIS/Include/core_cm3.h ****
- 484:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB
- 485:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB
- 486:Drivers/CMSIS/Include/core_cm3.h ****
- 487:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB
- ARM GAS /tmp/ccBGIhL8.s page 10
- 488:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB
- 489:Drivers/CMSIS/Include/core_cm3.h ****
- 490:Drivers/CMSIS/Include/core_cm3.h **** /* SCB Configuration Control Register Definitions */
- 491:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB
- 492:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB
- 493:Drivers/CMSIS/Include/core_cm3.h ****
- 494:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB
- 495:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB
- 496:Drivers/CMSIS/Include/core_cm3.h ****
- 497:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB
- 498:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB
- 499:Drivers/CMSIS/Include/core_cm3.h ****
- 500:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB
- 501:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB
- 502:Drivers/CMSIS/Include/core_cm3.h ****
- 503:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB
- 504:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB
- 505:Drivers/CMSIS/Include/core_cm3.h ****
- 506:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB
- 507:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB
- 508:Drivers/CMSIS/Include/core_cm3.h ****
- 509:Drivers/CMSIS/Include/core_cm3.h **** /* SCB System Handler Control and State Register Definitions */
- 510:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB
- 511:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB
- 512:Drivers/CMSIS/Include/core_cm3.h ****
- 513:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB
- 514:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB
- 515:Drivers/CMSIS/Include/core_cm3.h ****
- 516:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB
- 517:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB
- 518:Drivers/CMSIS/Include/core_cm3.h ****
- 519:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB
- 520:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB
- 521:Drivers/CMSIS/Include/core_cm3.h ****
- 522:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB
- 523:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB
- 524:Drivers/CMSIS/Include/core_cm3.h ****
- 525:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB
- 526:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB
- 527:Drivers/CMSIS/Include/core_cm3.h ****
- 528:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB
- 529:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB
- 530:Drivers/CMSIS/Include/core_cm3.h ****
- 531:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB
- 532:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB
- 533:Drivers/CMSIS/Include/core_cm3.h ****
- 534:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB
- 535:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB
- 536:Drivers/CMSIS/Include/core_cm3.h ****
- 537:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB
- 538:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB
- 539:Drivers/CMSIS/Include/core_cm3.h ****
- 540:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB
- 541:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB
- 542:Drivers/CMSIS/Include/core_cm3.h ****
- 543:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB
- 544:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB
- ARM GAS /tmp/ccBGIhL8.s page 11
- 545:Drivers/CMSIS/Include/core_cm3.h ****
- 546:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB
- 547:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB
- 548:Drivers/CMSIS/Include/core_cm3.h ****
- 549:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB
- 550:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB
- 551:Drivers/CMSIS/Include/core_cm3.h ****
- 552:Drivers/CMSIS/Include/core_cm3.h **** /* SCB Configurable Fault Status Register Definitions */
- 553:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB
- 554:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB
- 555:Drivers/CMSIS/Include/core_cm3.h ****
- 556:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB
- 557:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB
- 558:Drivers/CMSIS/Include/core_cm3.h ****
- 559:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB
- 560:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB
- 561:Drivers/CMSIS/Include/core_cm3.h ****
- 562:Drivers/CMSIS/Include/core_cm3.h **** /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
- 563:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB
- 564:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB
- 565:Drivers/CMSIS/Include/core_cm3.h ****
- 566:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB
- 567:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB
- 568:Drivers/CMSIS/Include/core_cm3.h ****
- 569:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB
- 570:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB
- 571:Drivers/CMSIS/Include/core_cm3.h ****
- 572:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB
- 573:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB
- 574:Drivers/CMSIS/Include/core_cm3.h ****
- 575:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB
- 576:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB
- 577:Drivers/CMSIS/Include/core_cm3.h ****
- 578:Drivers/CMSIS/Include/core_cm3.h **** /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
- 579:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB
- 580:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB
- 581:Drivers/CMSIS/Include/core_cm3.h ****
- 582:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB
- 583:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB
- 584:Drivers/CMSIS/Include/core_cm3.h ****
- 585:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB
- 586:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB
- 587:Drivers/CMSIS/Include/core_cm3.h ****
- 588:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB
- 589:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB
- 590:Drivers/CMSIS/Include/core_cm3.h ****
- 591:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB
- 592:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB
- 593:Drivers/CMSIS/Include/core_cm3.h ****
- 594:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB
- 595:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB
- 596:Drivers/CMSIS/Include/core_cm3.h ****
- 597:Drivers/CMSIS/Include/core_cm3.h **** /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
- 598:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB
- 599:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB
- 600:Drivers/CMSIS/Include/core_cm3.h ****
- 601:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB
- ARM GAS /tmp/ccBGIhL8.s page 12
- 602:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB
- 603:Drivers/CMSIS/Include/core_cm3.h ****
- 604:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB
- 605:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB
- 606:Drivers/CMSIS/Include/core_cm3.h ****
- 607:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB
- 608:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB
- 609:Drivers/CMSIS/Include/core_cm3.h ****
- 610:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB
- 611:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB
- 612:Drivers/CMSIS/Include/core_cm3.h ****
- 613:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB
- 614:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB
- 615:Drivers/CMSIS/Include/core_cm3.h ****
- 616:Drivers/CMSIS/Include/core_cm3.h **** /* SCB Hard Fault Status Register Definitions */
- 617:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB
- 618:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB
- 619:Drivers/CMSIS/Include/core_cm3.h ****
- 620:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_HFSR_FORCED_Pos 30U /*!< SCB
- 621:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB
- 622:Drivers/CMSIS/Include/core_cm3.h ****
- 623:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB
- 624:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB
- 625:Drivers/CMSIS/Include/core_cm3.h ****
- 626:Drivers/CMSIS/Include/core_cm3.h **** /* SCB Debug Fault Status Register Definitions */
- 627:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB
- 628:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB
- 629:Drivers/CMSIS/Include/core_cm3.h ****
- 630:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB
- 631:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB
- 632:Drivers/CMSIS/Include/core_cm3.h ****
- 633:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB
- 634:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB
- 635:Drivers/CMSIS/Include/core_cm3.h ****
- 636:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_BKPT_Pos 1U /*!< SCB
- 637:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB
- 638:Drivers/CMSIS/Include/core_cm3.h ****
- 639:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_HALTED_Pos 0U /*!< SCB
- 640:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB
- 641:Drivers/CMSIS/Include/core_cm3.h ****
- 642:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of group CMSIS_SCB */
- 643:Drivers/CMSIS/Include/core_cm3.h ****
- 644:Drivers/CMSIS/Include/core_cm3.h ****
- 645:Drivers/CMSIS/Include/core_cm3.h **** /**
- 646:Drivers/CMSIS/Include/core_cm3.h **** \ingroup CMSIS_core_register
- 647:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- 648:Drivers/CMSIS/Include/core_cm3.h **** \brief Type definitions for the System Control and ID Register not in the SCB
- 649:Drivers/CMSIS/Include/core_cm3.h **** @{
- 650:Drivers/CMSIS/Include/core_cm3.h **** */
- 651:Drivers/CMSIS/Include/core_cm3.h ****
- 652:Drivers/CMSIS/Include/core_cm3.h **** /**
- 653:Drivers/CMSIS/Include/core_cm3.h **** \brief Structure type to access the System Control and ID Register not in the SCB.
- 654:Drivers/CMSIS/Include/core_cm3.h **** */
- 655:Drivers/CMSIS/Include/core_cm3.h **** typedef struct
- 656:Drivers/CMSIS/Include/core_cm3.h **** {
- 657:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED0[1U];
- 658:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Regist
- ARM GAS /tmp/ccBGIhL8.s page 13
- 659:Drivers/CMSIS/Include/core_cm3.h **** #if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
- 660:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
- 661:Drivers/CMSIS/Include/core_cm3.h **** #else
- 662:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED1[1U];
- 663:Drivers/CMSIS/Include/core_cm3.h **** #endif
- 664:Drivers/CMSIS/Include/core_cm3.h **** } SCnSCB_Type;
- 665:Drivers/CMSIS/Include/core_cm3.h ****
- 666:Drivers/CMSIS/Include/core_cm3.h **** /* Interrupt Controller Type Register Definitions */
- 667:Drivers/CMSIS/Include/core_cm3.h **** #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: I
- 668:Drivers/CMSIS/Include/core_cm3.h **** #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: I
- 669:Drivers/CMSIS/Include/core_cm3.h ****
- 670:Drivers/CMSIS/Include/core_cm3.h **** /* Auxiliary Control Register Definitions */
- 671:Drivers/CMSIS/Include/core_cm3.h ****
- 672:Drivers/CMSIS/Include/core_cm3.h **** #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR:
- 673:Drivers/CMSIS/Include/core_cm3.h **** #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR:
- 674:Drivers/CMSIS/Include/core_cm3.h ****
- 675:Drivers/CMSIS/Include/core_cm3.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR:
- 676:Drivers/CMSIS/Include/core_cm3.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR:
- 677:Drivers/CMSIS/Include/core_cm3.h ****
- 678:Drivers/CMSIS/Include/core_cm3.h **** #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR:
- 679:Drivers/CMSIS/Include/core_cm3.h **** #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR:
- 680:Drivers/CMSIS/Include/core_cm3.h ****
- 681:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of group CMSIS_SCnotSCB */
- 682:Drivers/CMSIS/Include/core_cm3.h ****
- 683:Drivers/CMSIS/Include/core_cm3.h ****
- 684:Drivers/CMSIS/Include/core_cm3.h **** /**
- 685:Drivers/CMSIS/Include/core_cm3.h **** \ingroup CMSIS_core_register
- 686:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- 687:Drivers/CMSIS/Include/core_cm3.h **** \brief Type definitions for the System Timer Registers.
- 688:Drivers/CMSIS/Include/core_cm3.h **** @{
- 689:Drivers/CMSIS/Include/core_cm3.h **** */
- 690:Drivers/CMSIS/Include/core_cm3.h ****
- 691:Drivers/CMSIS/Include/core_cm3.h **** /**
- 692:Drivers/CMSIS/Include/core_cm3.h **** \brief Structure type to access the System Timer (SysTick).
- 693:Drivers/CMSIS/Include/core_cm3.h **** */
- 694:Drivers/CMSIS/Include/core_cm3.h **** typedef struct
- 695:Drivers/CMSIS/Include/core_cm3.h **** {
- 696:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regis
- 697:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- 698:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register *
- 699:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
- 700:Drivers/CMSIS/Include/core_cm3.h **** } SysTick_Type;
- 701:Drivers/CMSIS/Include/core_cm3.h ****
- 702:Drivers/CMSIS/Include/core_cm3.h **** /* SysTick Control / Status Register Definitions */
- 703:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysT
- 704:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysT
- 705:Drivers/CMSIS/Include/core_cm3.h ****
- 706:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysT
- 707:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysT
- 708:Drivers/CMSIS/Include/core_cm3.h ****
- 709:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysT
- 710:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysT
- 711:Drivers/CMSIS/Include/core_cm3.h ****
- 712:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysT
- 713:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysT
- 714:Drivers/CMSIS/Include/core_cm3.h ****
- 715:Drivers/CMSIS/Include/core_cm3.h **** /* SysTick Reload Register Definitions */
- ARM GAS /tmp/ccBGIhL8.s page 14
- 716:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysT
- 717:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysT
- 718:Drivers/CMSIS/Include/core_cm3.h ****
- 719:Drivers/CMSIS/Include/core_cm3.h **** /* SysTick Current Register Definitions */
- 720:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_VAL_CURRENT_Pos 0U /*!< SysT
- 721:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysT
- 722:Drivers/CMSIS/Include/core_cm3.h ****
- 723:Drivers/CMSIS/Include/core_cm3.h **** /* SysTick Calibration Register Definitions */
- 724:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CALIB_NOREF_Pos 31U /*!< SysT
- 725:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysT
- 726:Drivers/CMSIS/Include/core_cm3.h ****
- 727:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CALIB_SKEW_Pos 30U /*!< SysT
- 728:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysT
- 729:Drivers/CMSIS/Include/core_cm3.h ****
- 730:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CALIB_TENMS_Pos 0U /*!< SysT
- 731:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysT
- 732:Drivers/CMSIS/Include/core_cm3.h ****
- 733:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of group CMSIS_SysTick */
- 734:Drivers/CMSIS/Include/core_cm3.h ****
- 735:Drivers/CMSIS/Include/core_cm3.h ****
- 736:Drivers/CMSIS/Include/core_cm3.h **** /**
- 737:Drivers/CMSIS/Include/core_cm3.h **** \ingroup CMSIS_core_register
- 738:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- 739:Drivers/CMSIS/Include/core_cm3.h **** \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- 740:Drivers/CMSIS/Include/core_cm3.h **** @{
- 741:Drivers/CMSIS/Include/core_cm3.h **** */
- 742:Drivers/CMSIS/Include/core_cm3.h ****
- 743:Drivers/CMSIS/Include/core_cm3.h **** /**
- 744:Drivers/CMSIS/Include/core_cm3.h **** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- 745:Drivers/CMSIS/Include/core_cm3.h **** */
- 746:Drivers/CMSIS/Include/core_cm3.h **** typedef struct
- 747:Drivers/CMSIS/Include/core_cm3.h **** {
- 748:Drivers/CMSIS/Include/core_cm3.h **** __OM union
- 749:Drivers/CMSIS/Include/core_cm3.h **** {
- 750:Drivers/CMSIS/Include/core_cm3.h **** __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- 751:Drivers/CMSIS/Include/core_cm3.h **** __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- 752:Drivers/CMSIS/Include/core_cm3.h **** __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- 753:Drivers/CMSIS/Include/core_cm3.h **** } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- 754:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED0[864U];
- 755:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- 756:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED1[15U];
- 757:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- 758:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED2[15U];
- 759:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- 760:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED3[29U];
- 761:Drivers/CMSIS/Include/core_cm3.h **** __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register *
- 762:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- 763:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Reg
- 764:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED4[43U];
- 765:Drivers/CMSIS/Include/core_cm3.h **** __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- 766:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- 767:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED5[6U];
- 768:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Re
- 769:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Re
- 770:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Re
- 771:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Re
- 772:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Re
- ARM GAS /tmp/ccBGIhL8.s page 15
- 773:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Re
- 774:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Re
- 775:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Re
- 776:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Re
- 777:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Re
- 778:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Re
- 779:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Re
- 780:Drivers/CMSIS/Include/core_cm3.h **** } ITM_Type;
- 781:Drivers/CMSIS/Include/core_cm3.h ****
- 782:Drivers/CMSIS/Include/core_cm3.h **** /* ITM Trace Privilege Register Definitions */
- 783:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM
- 784:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM
- 785:Drivers/CMSIS/Include/core_cm3.h ****
- 786:Drivers/CMSIS/Include/core_cm3.h **** /* ITM Trace Control Register Definitions */
- 787:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_BUSY_Pos 23U /*!< ITM
- 788:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM
- 789:Drivers/CMSIS/Include/core_cm3.h ****
- 790:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM
- 791:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM
- 792:Drivers/CMSIS/Include/core_cm3.h ****
- 793:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM
- 794:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM
- 795:Drivers/CMSIS/Include/core_cm3.h ****
- 796:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM
- 797:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM
- 798:Drivers/CMSIS/Include/core_cm3.h ****
- 799:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_SWOENA_Pos 4U /*!< ITM
- 800:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM
- 801:Drivers/CMSIS/Include/core_cm3.h ****
- 802:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_DWTENA_Pos 3U /*!< ITM
- 803:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM
- 804:Drivers/CMSIS/Include/core_cm3.h ****
- 805:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM
- 806:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM
- 807:Drivers/CMSIS/Include/core_cm3.h ****
- 808:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_TSENA_Pos 1U /*!< ITM
- 809:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM
- 810:Drivers/CMSIS/Include/core_cm3.h ****
- 811:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_ITMENA_Pos 0U /*!< ITM
- 812:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM
- 813:Drivers/CMSIS/Include/core_cm3.h ****
- 814:Drivers/CMSIS/Include/core_cm3.h **** /* ITM Integration Write Register Definitions */
- 815:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM
- 816:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM
- 817:Drivers/CMSIS/Include/core_cm3.h ****
- 818:Drivers/CMSIS/Include/core_cm3.h **** /* ITM Integration Read Register Definitions */
- 819:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM
- 820:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM
- 821:Drivers/CMSIS/Include/core_cm3.h ****
- 822:Drivers/CMSIS/Include/core_cm3.h **** /* ITM Integration Mode Control Register Definitions */
- 823:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM
- 824:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM
- 825:Drivers/CMSIS/Include/core_cm3.h ****
- 826:Drivers/CMSIS/Include/core_cm3.h **** /* ITM Lock Status Register Definitions */
- 827:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM
- 828:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM
- 829:Drivers/CMSIS/Include/core_cm3.h ****
- ARM GAS /tmp/ccBGIhL8.s page 16
- 830:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_LSR_Access_Pos 1U /*!< ITM
- 831:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM
- 832:Drivers/CMSIS/Include/core_cm3.h ****
- 833:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_LSR_Present_Pos 0U /*!< ITM
- 834:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM
- 835:Drivers/CMSIS/Include/core_cm3.h ****
- 836:Drivers/CMSIS/Include/core_cm3.h **** /*@}*/ /* end of group CMSIS_ITM */
- 837:Drivers/CMSIS/Include/core_cm3.h ****
- 838:Drivers/CMSIS/Include/core_cm3.h ****
- 839:Drivers/CMSIS/Include/core_cm3.h **** /**
- 840:Drivers/CMSIS/Include/core_cm3.h **** \ingroup CMSIS_core_register
- 841:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- 842:Drivers/CMSIS/Include/core_cm3.h **** \brief Type definitions for the Data Watchpoint and Trace (DWT)
- 843:Drivers/CMSIS/Include/core_cm3.h **** @{
- 844:Drivers/CMSIS/Include/core_cm3.h **** */
- 845:Drivers/CMSIS/Include/core_cm3.h ****
- 846:Drivers/CMSIS/Include/core_cm3.h **** /**
- 847:Drivers/CMSIS/Include/core_cm3.h **** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- 848:Drivers/CMSIS/Include/core_cm3.h **** */
- 849:Drivers/CMSIS/Include/core_cm3.h **** typedef struct
- 850:Drivers/CMSIS/Include/core_cm3.h **** {
- 851:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- 852:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- 853:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- 854:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Registe
- 855:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- 856:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- 857:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Registe
- 858:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register
- 859:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- 860:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
- 861:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- 862:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED0[1U];
- 863:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- 864:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
- 865:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- 866:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED1[1U];
- 867:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- 868:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
- 869:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- 870:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED2[1U];
- 871:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- 872:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
- 873:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
- 874:Drivers/CMSIS/Include/core_cm3.h **** } DWT_Type;
- 875:Drivers/CMSIS/Include/core_cm3.h ****
- 876:Drivers/CMSIS/Include/core_cm3.h **** /* DWT Control Register Definitions */
- 877:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTR
- 878:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTR
- 879:Drivers/CMSIS/Include/core_cm3.h ****
- 880:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTR
- 881:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTR
- 882:Drivers/CMSIS/Include/core_cm3.h ****
- 883:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTR
- 884:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTR
- 885:Drivers/CMSIS/Include/core_cm3.h ****
- 886:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTR
- ARM GAS /tmp/ccBGIhL8.s page 17
- 887:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTR
- 888:Drivers/CMSIS/Include/core_cm3.h ****
- 889:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTR
- 890:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTR
- 891:Drivers/CMSIS/Include/core_cm3.h ****
- 892:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTR
- 893:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTR
- 894:Drivers/CMSIS/Include/core_cm3.h ****
- 895:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTR
- 896:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTR
- 897:Drivers/CMSIS/Include/core_cm3.h ****
- 898:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTR
- 899:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTR
- 900:Drivers/CMSIS/Include/core_cm3.h ****
- 901:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTR
- 902:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTR
- 903:Drivers/CMSIS/Include/core_cm3.h ****
- 904:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTR
- 905:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTR
- 906:Drivers/CMSIS/Include/core_cm3.h ****
- 907:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTR
- 908:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTR
- 909:Drivers/CMSIS/Include/core_cm3.h ****
- 910:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTR
- 911:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTR
- 912:Drivers/CMSIS/Include/core_cm3.h ****
- 913:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTR
- 914:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTR
- 915:Drivers/CMSIS/Include/core_cm3.h ****
- 916:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTR
- 917:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTR
- 918:Drivers/CMSIS/Include/core_cm3.h ****
- 919:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTR
- 920:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTR
- 921:Drivers/CMSIS/Include/core_cm3.h ****
- 922:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTR
- 923:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTR
- 924:Drivers/CMSIS/Include/core_cm3.h ****
- 925:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTR
- 926:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTR
- 927:Drivers/CMSIS/Include/core_cm3.h ****
- 928:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTR
- 929:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTR
- 930:Drivers/CMSIS/Include/core_cm3.h ****
- 931:Drivers/CMSIS/Include/core_cm3.h **** /* DWT CPI Count Register Definitions */
- 932:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPI
- 933:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPI
- 934:Drivers/CMSIS/Include/core_cm3.h ****
- 935:Drivers/CMSIS/Include/core_cm3.h **** /* DWT Exception Overhead Count Register Definitions */
- 936:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXC
- 937:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXC
- 938:Drivers/CMSIS/Include/core_cm3.h ****
- 939:Drivers/CMSIS/Include/core_cm3.h **** /* DWT Sleep Count Register Definitions */
- 940:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLE
- 941:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLE
- 942:Drivers/CMSIS/Include/core_cm3.h ****
- 943:Drivers/CMSIS/Include/core_cm3.h **** /* DWT LSU Count Register Definitions */
- ARM GAS /tmp/ccBGIhL8.s page 18
- 944:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSU
- 945:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSU
- 946:Drivers/CMSIS/Include/core_cm3.h ****
- 947:Drivers/CMSIS/Include/core_cm3.h **** /* DWT Folded-instruction Count Register Definitions */
- 948:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOL
- 949:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOL
- 950:Drivers/CMSIS/Include/core_cm3.h ****
- 951:Drivers/CMSIS/Include/core_cm3.h **** /* DWT Comparator Mask Register Definitions */
- 952:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_MASK_MASK_Pos 0U /*!< DWT MAS
- 953:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MAS
- 954:Drivers/CMSIS/Include/core_cm3.h ****
- 955:Drivers/CMSIS/Include/core_cm3.h **** /* DWT Comparator Function Register Definitions */
- 956:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUN
- 957:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUN
- 958:Drivers/CMSIS/Include/core_cm3.h ****
- 959:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUN
- 960:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUN
- 961:Drivers/CMSIS/Include/core_cm3.h ****
- 962:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUN
- 963:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUN
- 964:Drivers/CMSIS/Include/core_cm3.h ****
- 965:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUN
- 966:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUN
- 967:Drivers/CMSIS/Include/core_cm3.h ****
- 968:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUN
- 969:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUN
- 970:Drivers/CMSIS/Include/core_cm3.h ****
- 971:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUN
- 972:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUN
- 973:Drivers/CMSIS/Include/core_cm3.h ****
- 974:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUN
- 975:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUN
- 976:Drivers/CMSIS/Include/core_cm3.h ****
- 977:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUN
- 978:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUN
- 979:Drivers/CMSIS/Include/core_cm3.h ****
- 980:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUN
- 981:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUN
- 982:Drivers/CMSIS/Include/core_cm3.h ****
- 983:Drivers/CMSIS/Include/core_cm3.h **** /*@}*/ /* end of group CMSIS_DWT */
- 984:Drivers/CMSIS/Include/core_cm3.h ****
- 985:Drivers/CMSIS/Include/core_cm3.h ****
- 986:Drivers/CMSIS/Include/core_cm3.h **** /**
- 987:Drivers/CMSIS/Include/core_cm3.h **** \ingroup CMSIS_core_register
- 988:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_TPI Trace Port Interface (TPI)
- 989:Drivers/CMSIS/Include/core_cm3.h **** \brief Type definitions for the Trace Port Interface (TPI)
- 990:Drivers/CMSIS/Include/core_cm3.h **** @{
- 991:Drivers/CMSIS/Include/core_cm3.h **** */
- 992:Drivers/CMSIS/Include/core_cm3.h ****
- 993:Drivers/CMSIS/Include/core_cm3.h **** /**
- 994:Drivers/CMSIS/Include/core_cm3.h **** \brief Structure type to access the Trace Port Interface Register (TPI).
- 995:Drivers/CMSIS/Include/core_cm3.h **** */
- 996:Drivers/CMSIS/Include/core_cm3.h **** typedef struct
- 997:Drivers/CMSIS/Include/core_cm3.h **** {
- 998:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Reg
- 999:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Regis
- 1000:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED0[2U];
- ARM GAS /tmp/ccBGIhL8.s page 19
- 1001:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Reg
- 1002:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED1[55U];
- 1003:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register *
- 1004:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED2[131U];
- 1005:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Regis
- 1006:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Regi
- 1007:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counte
- 1008:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED3[759U];
- 1009:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
- 1010:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- 1011:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- 1012:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED4[1U];
- 1013:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- 1014:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- 1015:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- 1016:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED5[39U];
- 1017:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- 1018:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- 1019:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED7[8U];
- 1020:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- 1021:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
- 1022:Drivers/CMSIS/Include/core_cm3.h **** } TPI_Type;
- 1023:Drivers/CMSIS/Include/core_cm3.h ****
- 1024:Drivers/CMSIS/Include/core_cm3.h **** /* TPI Asynchronous Clock Prescaler Register Definitions */
- 1025:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACP
- 1026:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACP
- 1027:Drivers/CMSIS/Include/core_cm3.h ****
- 1028:Drivers/CMSIS/Include/core_cm3.h **** /* TPI Selected Pin Protocol Register Definitions */
- 1029:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPP
- 1030:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPP
- 1031:Drivers/CMSIS/Include/core_cm3.h ****
- 1032:Drivers/CMSIS/Include/core_cm3.h **** /* TPI Formatter and Flush Status Register Definitions */
- 1033:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFS
- 1034:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFS
- 1035:Drivers/CMSIS/Include/core_cm3.h ****
- 1036:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFS
- 1037:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFS
- 1038:Drivers/CMSIS/Include/core_cm3.h ****
- 1039:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFS
- 1040:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFS
- 1041:Drivers/CMSIS/Include/core_cm3.h ****
- 1042:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFS
- 1043:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFS
- 1044:Drivers/CMSIS/Include/core_cm3.h ****
- 1045:Drivers/CMSIS/Include/core_cm3.h **** /* TPI Formatter and Flush Control Register Definitions */
- 1046:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFC
- 1047:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFC
- 1048:Drivers/CMSIS/Include/core_cm3.h ****
- 1049:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFC
- 1050:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFC
- 1051:Drivers/CMSIS/Include/core_cm3.h ****
- 1052:Drivers/CMSIS/Include/core_cm3.h **** /* TPI TRIGGER Register Definitions */
- 1053:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRI
- 1054:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRI
- 1055:Drivers/CMSIS/Include/core_cm3.h ****
- 1056:Drivers/CMSIS/Include/core_cm3.h **** /* TPI Integration ETM Data Register Definitions (FIFO0) */
- 1057:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIF
- ARM GAS /tmp/ccBGIhL8.s page 20
- 1058:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIF
- 1059:Drivers/CMSIS/Include/core_cm3.h ****
- 1060:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIF
- 1061:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIF
- 1062:Drivers/CMSIS/Include/core_cm3.h ****
- 1063:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIF
- 1064:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIF
- 1065:Drivers/CMSIS/Include/core_cm3.h ****
- 1066:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIF
- 1067:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIF
- 1068:Drivers/CMSIS/Include/core_cm3.h ****
- 1069:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIF
- 1070:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIF
- 1071:Drivers/CMSIS/Include/core_cm3.h ****
- 1072:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIF
- 1073:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIF
- 1074:Drivers/CMSIS/Include/core_cm3.h ****
- 1075:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIF
- 1076:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIF
- 1077:Drivers/CMSIS/Include/core_cm3.h ****
- 1078:Drivers/CMSIS/Include/core_cm3.h **** /* TPI ITATBCTR2 Register Definitions */
- 1079:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITA
- 1080:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITA
- 1081:Drivers/CMSIS/Include/core_cm3.h ****
- 1082:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITA
- 1083:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITA
- 1084:Drivers/CMSIS/Include/core_cm3.h ****
- 1085:Drivers/CMSIS/Include/core_cm3.h **** /* TPI Integration ITM Data Register Definitions (FIFO1) */
- 1086:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIF
- 1087:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIF
- 1088:Drivers/CMSIS/Include/core_cm3.h ****
- 1089:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIF
- 1090:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIF
- 1091:Drivers/CMSIS/Include/core_cm3.h ****
- 1092:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIF
- 1093:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIF
- 1094:Drivers/CMSIS/Include/core_cm3.h ****
- 1095:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIF
- 1096:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIF
- 1097:Drivers/CMSIS/Include/core_cm3.h ****
- 1098:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIF
- 1099:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIF
- 1100:Drivers/CMSIS/Include/core_cm3.h ****
- 1101:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIF
- 1102:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIF
- 1103:Drivers/CMSIS/Include/core_cm3.h ****
- 1104:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIF
- 1105:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIF
- 1106:Drivers/CMSIS/Include/core_cm3.h ****
- 1107:Drivers/CMSIS/Include/core_cm3.h **** /* TPI ITATBCTR0 Register Definitions */
- 1108:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITA
- 1109:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITA
- 1110:Drivers/CMSIS/Include/core_cm3.h ****
- 1111:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITA
- 1112:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITA
- 1113:Drivers/CMSIS/Include/core_cm3.h ****
- 1114:Drivers/CMSIS/Include/core_cm3.h **** /* TPI Integration Mode Control Register Definitions */
- ARM GAS /tmp/ccBGIhL8.s page 21
- 1115:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITC
- 1116:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITC
- 1117:Drivers/CMSIS/Include/core_cm3.h ****
- 1118:Drivers/CMSIS/Include/core_cm3.h **** /* TPI DEVID Register Definitions */
- 1119:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEV
- 1120:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEV
- 1121:Drivers/CMSIS/Include/core_cm3.h ****
- 1122:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEV
- 1123:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEV
- 1124:Drivers/CMSIS/Include/core_cm3.h ****
- 1125:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEV
- 1126:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEV
- 1127:Drivers/CMSIS/Include/core_cm3.h ****
- 1128:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEV
- 1129:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEV
- 1130:Drivers/CMSIS/Include/core_cm3.h ****
- 1131:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEV
- 1132:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEV
- 1133:Drivers/CMSIS/Include/core_cm3.h ****
- 1134:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEV
- 1135:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEV
- 1136:Drivers/CMSIS/Include/core_cm3.h ****
- 1137:Drivers/CMSIS/Include/core_cm3.h **** /* TPI DEVTYPE Register Definitions */
- 1138:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEV
- 1139:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEV
- 1140:Drivers/CMSIS/Include/core_cm3.h ****
- 1141:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEV
- 1142:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEV
- 1143:Drivers/CMSIS/Include/core_cm3.h ****
- 1144:Drivers/CMSIS/Include/core_cm3.h **** /*@}*/ /* end of group CMSIS_TPI */
- 1145:Drivers/CMSIS/Include/core_cm3.h ****
- 1146:Drivers/CMSIS/Include/core_cm3.h ****
- 1147:Drivers/CMSIS/Include/core_cm3.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- 1148:Drivers/CMSIS/Include/core_cm3.h **** /**
- 1149:Drivers/CMSIS/Include/core_cm3.h **** \ingroup CMSIS_core_register
- 1150:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- 1151:Drivers/CMSIS/Include/core_cm3.h **** \brief Type definitions for the Memory Protection Unit (MPU)
- 1152:Drivers/CMSIS/Include/core_cm3.h **** @{
- 1153:Drivers/CMSIS/Include/core_cm3.h **** */
- 1154:Drivers/CMSIS/Include/core_cm3.h ****
- 1155:Drivers/CMSIS/Include/core_cm3.h **** /**
- 1156:Drivers/CMSIS/Include/core_cm3.h **** \brief Structure type to access the Memory Protection Unit (MPU).
- 1157:Drivers/CMSIS/Include/core_cm3.h **** */
- 1158:Drivers/CMSIS/Include/core_cm3.h **** typedef struct
- 1159:Drivers/CMSIS/Include/core_cm3.h **** {
- 1160:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- 1161:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- 1162:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- 1163:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register
- 1164:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Re
- 1165:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address
- 1166:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and
- 1167:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address
- 1168:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and
- 1169:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address
- 1170:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and
- 1171:Drivers/CMSIS/Include/core_cm3.h **** } MPU_Type;
- ARM GAS /tmp/ccBGIhL8.s page 22
- 1172:Drivers/CMSIS/Include/core_cm3.h ****
- 1173:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_TYPE_RALIASES 4U
- 1174:Drivers/CMSIS/Include/core_cm3.h ****
- 1175:Drivers/CMSIS/Include/core_cm3.h **** /* MPU Type Register Definitions */
- 1176:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_TYPE_IREGION_Pos 16U /*!< MPU
- 1177:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU
- 1178:Drivers/CMSIS/Include/core_cm3.h ****
- 1179:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_TYPE_DREGION_Pos 8U /*!< MPU
- 1180:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU
- 1181:Drivers/CMSIS/Include/core_cm3.h ****
- 1182:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU
- 1183:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU
- 1184:Drivers/CMSIS/Include/core_cm3.h ****
- 1185:Drivers/CMSIS/Include/core_cm3.h **** /* MPU Control Register Definitions */
- 1186:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU
- 1187:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU
- 1188:Drivers/CMSIS/Include/core_cm3.h ****
- 1189:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU
- 1190:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU
- 1191:Drivers/CMSIS/Include/core_cm3.h ****
- 1192:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU
- 1193:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU
- 1194:Drivers/CMSIS/Include/core_cm3.h ****
- 1195:Drivers/CMSIS/Include/core_cm3.h **** /* MPU Region Number Register Definitions */
- 1196:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RNR_REGION_Pos 0U /*!< MPU
- 1197:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU
- 1198:Drivers/CMSIS/Include/core_cm3.h ****
- 1199:Drivers/CMSIS/Include/core_cm3.h **** /* MPU Region Base Address Register Definitions */
- 1200:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RBAR_ADDR_Pos 5U /*!< MPU
- 1201:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU
- 1202:Drivers/CMSIS/Include/core_cm3.h ****
- 1203:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RBAR_VALID_Pos 4U /*!< MPU
- 1204:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU
- 1205:Drivers/CMSIS/Include/core_cm3.h ****
- 1206:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RBAR_REGION_Pos 0U /*!< MPU
- 1207:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU
- 1208:Drivers/CMSIS/Include/core_cm3.h ****
- 1209:Drivers/CMSIS/Include/core_cm3.h **** /* MPU Region Attribute and Size Register Definitions */
- 1210:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_ATTRS_Pos 16U /*!< MPU
- 1211:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU
- 1212:Drivers/CMSIS/Include/core_cm3.h ****
- 1213:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_XN_Pos 28U /*!< MPU
- 1214:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU
- 1215:Drivers/CMSIS/Include/core_cm3.h ****
- 1216:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_AP_Pos 24U /*!< MPU
- 1217:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU
- 1218:Drivers/CMSIS/Include/core_cm3.h ****
- 1219:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_TEX_Pos 19U /*!< MPU
- 1220:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU
- 1221:Drivers/CMSIS/Include/core_cm3.h ****
- 1222:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_S_Pos 18U /*!< MPU
- 1223:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU
- 1224:Drivers/CMSIS/Include/core_cm3.h ****
- 1225:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_C_Pos 17U /*!< MPU
- 1226:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU
- 1227:Drivers/CMSIS/Include/core_cm3.h ****
- 1228:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_B_Pos 16U /*!< MPU
- ARM GAS /tmp/ccBGIhL8.s page 23
- 1229:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU
- 1230:Drivers/CMSIS/Include/core_cm3.h ****
- 1231:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_SRD_Pos 8U /*!< MPU
- 1232:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU
- 1233:Drivers/CMSIS/Include/core_cm3.h ****
- 1234:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_SIZE_Pos 1U /*!< MPU
- 1235:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU
- 1236:Drivers/CMSIS/Include/core_cm3.h ****
- 1237:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_ENABLE_Pos 0U /*!< MPU
- 1238:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU
- 1239:Drivers/CMSIS/Include/core_cm3.h ****
- 1240:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of group CMSIS_MPU */
- 1241:Drivers/CMSIS/Include/core_cm3.h **** #endif
- 1242:Drivers/CMSIS/Include/core_cm3.h ****
- 1243:Drivers/CMSIS/Include/core_cm3.h ****
- 1244:Drivers/CMSIS/Include/core_cm3.h **** /**
- 1245:Drivers/CMSIS/Include/core_cm3.h **** \ingroup CMSIS_core_register
- 1246:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- 1247:Drivers/CMSIS/Include/core_cm3.h **** \brief Type definitions for the Core Debug Registers
- 1248:Drivers/CMSIS/Include/core_cm3.h **** @{
- 1249:Drivers/CMSIS/Include/core_cm3.h **** */
- 1250:Drivers/CMSIS/Include/core_cm3.h ****
- 1251:Drivers/CMSIS/Include/core_cm3.h **** /**
- 1252:Drivers/CMSIS/Include/core_cm3.h **** \brief Structure type to access the Core Debug Register (CoreDebug).
- 1253:Drivers/CMSIS/Include/core_cm3.h **** */
- 1254:Drivers/CMSIS/Include/core_cm3.h **** typedef struct
- 1255:Drivers/CMSIS/Include/core_cm3.h **** {
- 1256:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status
- 1257:Drivers/CMSIS/Include/core_cm3.h **** __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Reg
- 1258:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Registe
- 1259:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Cont
- 1260:Drivers/CMSIS/Include/core_cm3.h **** } CoreDebug_Type;
- 1261:Drivers/CMSIS/Include/core_cm3.h ****
- 1262:Drivers/CMSIS/Include/core_cm3.h **** /* Debug Halting Control and Status Register Definitions */
- 1263:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< Core
- 1264:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< Core
- 1265:Drivers/CMSIS/Include/core_cm3.h ****
- 1266:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< Core
- 1267:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< Core
- 1268:Drivers/CMSIS/Include/core_cm3.h ****
- 1269:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< Core
- 1270:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< Core
- 1271:Drivers/CMSIS/Include/core_cm3.h ****
- 1272:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< Core
- 1273:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< Core
- 1274:Drivers/CMSIS/Include/core_cm3.h ****
- 1275:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< Core
- 1276:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< Core
- 1277:Drivers/CMSIS/Include/core_cm3.h ****
- 1278:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< Core
- 1279:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< Core
- 1280:Drivers/CMSIS/Include/core_cm3.h ****
- 1281:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< Core
- 1282:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< Core
- 1283:Drivers/CMSIS/Include/core_cm3.h ****
- 1284:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< Core
- 1285:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< Core
- ARM GAS /tmp/ccBGIhL8.s page 24
- 1286:Drivers/CMSIS/Include/core_cm3.h ****
- 1287:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< Core
- 1288:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< Core
- 1289:Drivers/CMSIS/Include/core_cm3.h ****
- 1290:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< Core
- 1291:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< Core
- 1292:Drivers/CMSIS/Include/core_cm3.h ****
- 1293:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< Core
- 1294:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< Core
- 1295:Drivers/CMSIS/Include/core_cm3.h ****
- 1296:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< Core
- 1297:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< Core
- 1298:Drivers/CMSIS/Include/core_cm3.h ****
- 1299:Drivers/CMSIS/Include/core_cm3.h **** /* Debug Core Register Selector Register Definitions */
- 1300:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< Core
- 1301:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core
- 1302:Drivers/CMSIS/Include/core_cm3.h ****
- 1303:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< Core
- 1304:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< Core
- 1305:Drivers/CMSIS/Include/core_cm3.h ****
- 1306:Drivers/CMSIS/Include/core_cm3.h **** /* Debug Exception and Monitor Control Register Definitions */
- 1307:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< Core
- 1308:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< Core
- 1309:Drivers/CMSIS/Include/core_cm3.h ****
- 1310:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< Core
- 1311:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< Core
- 1312:Drivers/CMSIS/Include/core_cm3.h ****
- 1313:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< Core
- 1314:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< Core
- 1315:Drivers/CMSIS/Include/core_cm3.h ****
- 1316:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< Core
- 1317:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< Core
- 1318:Drivers/CMSIS/Include/core_cm3.h ****
- 1319:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< Core
- 1320:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< Core
- 1321:Drivers/CMSIS/Include/core_cm3.h ****
- 1322:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< Core
- 1323:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< Core
- 1324:Drivers/CMSIS/Include/core_cm3.h ****
- 1325:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< Core
- 1326:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< Core
- 1327:Drivers/CMSIS/Include/core_cm3.h ****
- 1328:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< Core
- 1329:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< Core
- 1330:Drivers/CMSIS/Include/core_cm3.h ****
- 1331:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< Core
- 1332:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< Core
- 1333:Drivers/CMSIS/Include/core_cm3.h ****
- 1334:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< Core
- 1335:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< Core
- 1336:Drivers/CMSIS/Include/core_cm3.h ****
- 1337:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< Core
- 1338:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< Core
- 1339:Drivers/CMSIS/Include/core_cm3.h ****
- 1340:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< Core
- 1341:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< Core
- 1342:Drivers/CMSIS/Include/core_cm3.h ****
- ARM GAS /tmp/ccBGIhL8.s page 25
- 1343:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< Core
- 1344:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< Core
- 1345:Drivers/CMSIS/Include/core_cm3.h ****
- 1346:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of group CMSIS_CoreDebug */
- 1347:Drivers/CMSIS/Include/core_cm3.h ****
- 1348:Drivers/CMSIS/Include/core_cm3.h ****
- 1349:Drivers/CMSIS/Include/core_cm3.h **** /**
- 1350:Drivers/CMSIS/Include/core_cm3.h **** \ingroup CMSIS_core_register
- 1351:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_core_bitfield Core register bit field macros
- 1352:Drivers/CMSIS/Include/core_cm3.h **** \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- 1353:Drivers/CMSIS/Include/core_cm3.h **** @{
- 1354:Drivers/CMSIS/Include/core_cm3.h **** */
- 1355:Drivers/CMSIS/Include/core_cm3.h ****
- 1356:Drivers/CMSIS/Include/core_cm3.h **** /**
- 1357:Drivers/CMSIS/Include/core_cm3.h **** \brief Mask and shift a bit field value for use in a register bit range.
- 1358:Drivers/CMSIS/Include/core_cm3.h **** \param[in] field Name of the register bit field.
- 1359:Drivers/CMSIS/Include/core_cm3.h **** \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
- 1360:Drivers/CMSIS/Include/core_cm3.h **** \return Masked and shifted value.
- 1361:Drivers/CMSIS/Include/core_cm3.h **** */
- 1362:Drivers/CMSIS/Include/core_cm3.h **** #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
- 1363:Drivers/CMSIS/Include/core_cm3.h ****
- 1364:Drivers/CMSIS/Include/core_cm3.h **** /**
- 1365:Drivers/CMSIS/Include/core_cm3.h **** \brief Mask and shift a register value to extract a bit filed value.
- 1366:Drivers/CMSIS/Include/core_cm3.h **** \param[in] field Name of the register bit field.
- 1367:Drivers/CMSIS/Include/core_cm3.h **** \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
- 1368:Drivers/CMSIS/Include/core_cm3.h **** \return Masked and shifted bit field value.
- 1369:Drivers/CMSIS/Include/core_cm3.h **** */
- 1370:Drivers/CMSIS/Include/core_cm3.h **** #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
- 1371:Drivers/CMSIS/Include/core_cm3.h ****
- 1372:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of group CMSIS_core_bitfield */
- 1373:Drivers/CMSIS/Include/core_cm3.h ****
- 1374:Drivers/CMSIS/Include/core_cm3.h ****
- 1375:Drivers/CMSIS/Include/core_cm3.h **** /**
- 1376:Drivers/CMSIS/Include/core_cm3.h **** \ingroup CMSIS_core_register
- 1377:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_core_base Core Definitions
- 1378:Drivers/CMSIS/Include/core_cm3.h **** \brief Definitions for base addresses, unions, and structures.
- 1379:Drivers/CMSIS/Include/core_cm3.h **** @{
- 1380:Drivers/CMSIS/Include/core_cm3.h **** */
- 1381:Drivers/CMSIS/Include/core_cm3.h ****
- 1382:Drivers/CMSIS/Include/core_cm3.h **** /* Memory mapping of Core Hardware */
- 1383:Drivers/CMSIS/Include/core_cm3.h **** #define SCS_BASE (0xE000E000UL) /*!< System Control Space Bas
- 1384:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
- 1385:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
- 1386:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
- 1387:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address
- 1388:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
- 1389:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
- 1390:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Bas
- 1391:Drivers/CMSIS/Include/core_cm3.h ****
- 1392:Drivers/CMSIS/Include/core_cm3.h **** #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register
- 1393:Drivers/CMSIS/Include/core_cm3.h **** #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct
- 1394:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration st
- 1395:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc
- 1396:Drivers/CMSIS/Include/core_cm3.h **** #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct
- 1397:Drivers/CMSIS/Include/core_cm3.h **** #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct
- 1398:Drivers/CMSIS/Include/core_cm3.h **** #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct
- 1399:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration
- ARM GAS /tmp/ccBGIhL8.s page 26
- 1400:Drivers/CMSIS/Include/core_cm3.h ****
- 1401:Drivers/CMSIS/Include/core_cm3.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- 1402:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit *
- 1403:Drivers/CMSIS/Include/core_cm3.h **** #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit *
- 1404:Drivers/CMSIS/Include/core_cm3.h **** #endif
- 1405:Drivers/CMSIS/Include/core_cm3.h ****
- 1406:Drivers/CMSIS/Include/core_cm3.h **** /*@} */
- 1407:Drivers/CMSIS/Include/core_cm3.h ****
- 1408:Drivers/CMSIS/Include/core_cm3.h ****
- 1409:Drivers/CMSIS/Include/core_cm3.h ****
- 1410:Drivers/CMSIS/Include/core_cm3.h **** /*******************************************************************************
- 1411:Drivers/CMSIS/Include/core_cm3.h **** * Hardware Abstraction Layer
- 1412:Drivers/CMSIS/Include/core_cm3.h **** Core Function Interface contains:
- 1413:Drivers/CMSIS/Include/core_cm3.h **** - Core NVIC Functions
- 1414:Drivers/CMSIS/Include/core_cm3.h **** - Core SysTick Functions
- 1415:Drivers/CMSIS/Include/core_cm3.h **** - Core Debug Functions
- 1416:Drivers/CMSIS/Include/core_cm3.h **** - Core Register Access Functions
- 1417:Drivers/CMSIS/Include/core_cm3.h **** ******************************************************************************/
- 1418:Drivers/CMSIS/Include/core_cm3.h **** /**
- 1419:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
- 1420:Drivers/CMSIS/Include/core_cm3.h **** */
- 1421:Drivers/CMSIS/Include/core_cm3.h ****
- 1422:Drivers/CMSIS/Include/core_cm3.h ****
- 1423:Drivers/CMSIS/Include/core_cm3.h ****
- 1424:Drivers/CMSIS/Include/core_cm3.h **** /* ########################## NVIC functions #################################### */
- 1425:Drivers/CMSIS/Include/core_cm3.h **** /**
- 1426:Drivers/CMSIS/Include/core_cm3.h **** \ingroup CMSIS_Core_FunctionInterface
- 1427:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- 1428:Drivers/CMSIS/Include/core_cm3.h **** \brief Functions that manage interrupts and exceptions via the NVIC.
- 1429:Drivers/CMSIS/Include/core_cm3.h **** @{
- 1430:Drivers/CMSIS/Include/core_cm3.h **** */
- 1431:Drivers/CMSIS/Include/core_cm3.h ****
- 1432:Drivers/CMSIS/Include/core_cm3.h **** #ifdef CMSIS_NVIC_VIRTUAL
- 1433:Drivers/CMSIS/Include/core_cm3.h **** #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
- 1434:Drivers/CMSIS/Include/core_cm3.h **** #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
- 1435:Drivers/CMSIS/Include/core_cm3.h **** #endif
- 1436:Drivers/CMSIS/Include/core_cm3.h **** #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
- 1437:Drivers/CMSIS/Include/core_cm3.h **** #else
- 1438:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
- 1439:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
- 1440:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_EnableIRQ __NVIC_EnableIRQ
- 1441:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
- 1442:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_DisableIRQ __NVIC_DisableIRQ
- 1443:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
- 1444:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
- 1445:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
- 1446:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_GetActive __NVIC_GetActive
- 1447:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_SetPriority __NVIC_SetPriority
- 1448:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_GetPriority __NVIC_GetPriority
- 1449:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_SystemReset __NVIC_SystemReset
- 1450:Drivers/CMSIS/Include/core_cm3.h **** #endif /* CMSIS_NVIC_VIRTUAL */
- 1451:Drivers/CMSIS/Include/core_cm3.h ****
- 1452:Drivers/CMSIS/Include/core_cm3.h **** #ifdef CMSIS_VECTAB_VIRTUAL
- 1453:Drivers/CMSIS/Include/core_cm3.h **** #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
- 1454:Drivers/CMSIS/Include/core_cm3.h **** #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
- 1455:Drivers/CMSIS/Include/core_cm3.h **** #endif
- 1456:Drivers/CMSIS/Include/core_cm3.h **** #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
- ARM GAS /tmp/ccBGIhL8.s page 27
- 1457:Drivers/CMSIS/Include/core_cm3.h **** #else
- 1458:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_SetVector __NVIC_SetVector
- 1459:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_GetVector __NVIC_GetVector
- 1460:Drivers/CMSIS/Include/core_cm3.h **** #endif /* (CMSIS_VECTAB_VIRTUAL) */
- 1461:Drivers/CMSIS/Include/core_cm3.h ****
- 1462:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_USER_IRQ_OFFSET 16
- 1463:Drivers/CMSIS/Include/core_cm3.h ****
- 1464:Drivers/CMSIS/Include/core_cm3.h ****
- 1465:Drivers/CMSIS/Include/core_cm3.h **** /* The following EXC_RETURN values are saved the LR on exception entry */
- 1466:Drivers/CMSIS/Include/core_cm3.h **** #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after ret
- 1467:Drivers/CMSIS/Include/core_cm3.h **** #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after retu
- 1468:Drivers/CMSIS/Include/core_cm3.h **** #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after retu
- 1469:Drivers/CMSIS/Include/core_cm3.h ****
- 1470:Drivers/CMSIS/Include/core_cm3.h ****
- 1471:Drivers/CMSIS/Include/core_cm3.h **** /**
- 1472:Drivers/CMSIS/Include/core_cm3.h **** \brief Set Priority Grouping
- 1473:Drivers/CMSIS/Include/core_cm3.h **** \details Sets the priority grouping field using the required unlock sequence.
- 1474:Drivers/CMSIS/Include/core_cm3.h **** The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- 1475:Drivers/CMSIS/Include/core_cm3.h **** Only values from 0..7 are used.
- 1476:Drivers/CMSIS/Include/core_cm3.h **** In case of a conflict between priority grouping and available
- 1477:Drivers/CMSIS/Include/core_cm3.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- 1478:Drivers/CMSIS/Include/core_cm3.h **** \param [in] PriorityGroup Priority grouping field.
- 1479:Drivers/CMSIS/Include/core_cm3.h **** */
- 1480:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
- 1481:Drivers/CMSIS/Include/core_cm3.h **** {
- 1482:Drivers/CMSIS/Include/core_cm3.h **** uint32_t reg_value;
- 1483:Drivers/CMSIS/Include/core_cm3.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 a
- 1484:Drivers/CMSIS/Include/core_cm3.h ****
- 1485:Drivers/CMSIS/Include/core_cm3.h **** reg_value = SCB->AIRCR; /* read old register
- 1486:Drivers/CMSIS/Include/core_cm3.h **** reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan
- 1487:Drivers/CMSIS/Include/core_cm3.h **** reg_value = (reg_value |
- 1488:Drivers/CMSIS/Include/core_cm3.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- 1489:Drivers/CMSIS/Include/core_cm3.h **** (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key a
- 1490:Drivers/CMSIS/Include/core_cm3.h **** SCB->AIRCR = reg_value;
- 1491:Drivers/CMSIS/Include/core_cm3.h **** }
- 1492:Drivers/CMSIS/Include/core_cm3.h ****
- 1493:Drivers/CMSIS/Include/core_cm3.h ****
- 1494:Drivers/CMSIS/Include/core_cm3.h **** /**
- 1495:Drivers/CMSIS/Include/core_cm3.h **** \brief Get Priority Grouping
- 1496:Drivers/CMSIS/Include/core_cm3.h **** \details Reads the priority grouping field from the NVIC Interrupt Controller.
- 1497:Drivers/CMSIS/Include/core_cm3.h **** \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- 1498:Drivers/CMSIS/Include/core_cm3.h **** */
- 1499:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
- 1500:Drivers/CMSIS/Include/core_cm3.h **** {
- 1501:Drivers/CMSIS/Include/core_cm3.h **** return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
- 1502:Drivers/CMSIS/Include/core_cm3.h **** }
- 1503:Drivers/CMSIS/Include/core_cm3.h ****
- 1504:Drivers/CMSIS/Include/core_cm3.h ****
- 1505:Drivers/CMSIS/Include/core_cm3.h **** /**
- 1506:Drivers/CMSIS/Include/core_cm3.h **** \brief Enable Interrupt
- 1507:Drivers/CMSIS/Include/core_cm3.h **** \details Enables a device specific interrupt in the NVIC interrupt controller.
- 1508:Drivers/CMSIS/Include/core_cm3.h **** \param [in] IRQn Device specific interrupt number.
- 1509:Drivers/CMSIS/Include/core_cm3.h **** \note IRQn must not be negative.
- 1510:Drivers/CMSIS/Include/core_cm3.h **** */
- 1511:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
- 1512:Drivers/CMSIS/Include/core_cm3.h **** {
- 1513:Drivers/CMSIS/Include/core_cm3.h **** if ((int32_t)(IRQn) >= 0)
- ARM GAS /tmp/ccBGIhL8.s page 28
- 1514:Drivers/CMSIS/Include/core_cm3.h **** {
- 1515:Drivers/CMSIS/Include/core_cm3.h **** NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- 1516:Drivers/CMSIS/Include/core_cm3.h **** }
- 1517:Drivers/CMSIS/Include/core_cm3.h **** }
- 1518:Drivers/CMSIS/Include/core_cm3.h ****
- 1519:Drivers/CMSIS/Include/core_cm3.h ****
- 1520:Drivers/CMSIS/Include/core_cm3.h **** /**
- 1521:Drivers/CMSIS/Include/core_cm3.h **** \brief Get Interrupt Enable status
- 1522:Drivers/CMSIS/Include/core_cm3.h **** \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
- 1523:Drivers/CMSIS/Include/core_cm3.h **** \param [in] IRQn Device specific interrupt number.
- 1524:Drivers/CMSIS/Include/core_cm3.h **** \return 0 Interrupt is not enabled.
- 1525:Drivers/CMSIS/Include/core_cm3.h **** \return 1 Interrupt is enabled.
- 1526:Drivers/CMSIS/Include/core_cm3.h **** \note IRQn must not be negative.
- 1527:Drivers/CMSIS/Include/core_cm3.h **** */
- 1528:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
- 1529:Drivers/CMSIS/Include/core_cm3.h **** {
- 1530:Drivers/CMSIS/Include/core_cm3.h **** if ((int32_t)(IRQn) >= 0)
- 1531:Drivers/CMSIS/Include/core_cm3.h **** {
- 1532:Drivers/CMSIS/Include/core_cm3.h **** return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL)
- 1533:Drivers/CMSIS/Include/core_cm3.h **** }
- 1534:Drivers/CMSIS/Include/core_cm3.h **** else
- 1535:Drivers/CMSIS/Include/core_cm3.h **** {
- 1536:Drivers/CMSIS/Include/core_cm3.h **** return(0U);
- 1537:Drivers/CMSIS/Include/core_cm3.h **** }
- 1538:Drivers/CMSIS/Include/core_cm3.h **** }
- 1539:Drivers/CMSIS/Include/core_cm3.h ****
- 1540:Drivers/CMSIS/Include/core_cm3.h ****
- 1541:Drivers/CMSIS/Include/core_cm3.h **** /**
- 1542:Drivers/CMSIS/Include/core_cm3.h **** \brief Disable Interrupt
- 1543:Drivers/CMSIS/Include/core_cm3.h **** \details Disables a device specific interrupt in the NVIC interrupt controller.
- 1544:Drivers/CMSIS/Include/core_cm3.h **** \param [in] IRQn Device specific interrupt number.
- 1545:Drivers/CMSIS/Include/core_cm3.h **** \note IRQn must not be negative.
- 1546:Drivers/CMSIS/Include/core_cm3.h **** */
- 1547:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
- 1548:Drivers/CMSIS/Include/core_cm3.h **** {
- 1549:Drivers/CMSIS/Include/core_cm3.h **** if ((int32_t)(IRQn) >= 0)
- 1550:Drivers/CMSIS/Include/core_cm3.h **** {
- 1551:Drivers/CMSIS/Include/core_cm3.h **** NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- 1552:Drivers/CMSIS/Include/core_cm3.h **** __DSB();
- 1553:Drivers/CMSIS/Include/core_cm3.h **** __ISB();
- 1554:Drivers/CMSIS/Include/core_cm3.h **** }
- 1555:Drivers/CMSIS/Include/core_cm3.h **** }
- 1556:Drivers/CMSIS/Include/core_cm3.h ****
- 1557:Drivers/CMSIS/Include/core_cm3.h ****
- 1558:Drivers/CMSIS/Include/core_cm3.h **** /**
- 1559:Drivers/CMSIS/Include/core_cm3.h **** \brief Get Pending Interrupt
- 1560:Drivers/CMSIS/Include/core_cm3.h **** \details Reads the NVIC pending register and returns the pending bit for the specified device spe
- 1561:Drivers/CMSIS/Include/core_cm3.h **** \param [in] IRQn Device specific interrupt number.
- 1562:Drivers/CMSIS/Include/core_cm3.h **** \return 0 Interrupt status is not pending.
- 1563:Drivers/CMSIS/Include/core_cm3.h **** \return 1 Interrupt status is pending.
- 1564:Drivers/CMSIS/Include/core_cm3.h **** \note IRQn must not be negative.
- 1565:Drivers/CMSIS/Include/core_cm3.h **** */
- 1566:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
- 1567:Drivers/CMSIS/Include/core_cm3.h **** {
- 1568:Drivers/CMSIS/Include/core_cm3.h **** if ((int32_t)(IRQn) >= 0)
- 1569:Drivers/CMSIS/Include/core_cm3.h **** {
- 1570:Drivers/CMSIS/Include/core_cm3.h **** return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL)
- ARM GAS /tmp/ccBGIhL8.s page 29
- 1571:Drivers/CMSIS/Include/core_cm3.h **** }
- 1572:Drivers/CMSIS/Include/core_cm3.h **** else
- 1573:Drivers/CMSIS/Include/core_cm3.h **** {
- 1574:Drivers/CMSIS/Include/core_cm3.h **** return(0U);
- 1575:Drivers/CMSIS/Include/core_cm3.h **** }
- 1576:Drivers/CMSIS/Include/core_cm3.h **** }
- 1577:Drivers/CMSIS/Include/core_cm3.h ****
- 1578:Drivers/CMSIS/Include/core_cm3.h ****
- 1579:Drivers/CMSIS/Include/core_cm3.h **** /**
- 1580:Drivers/CMSIS/Include/core_cm3.h **** \brief Set Pending Interrupt
- 1581:Drivers/CMSIS/Include/core_cm3.h **** \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
- 1582:Drivers/CMSIS/Include/core_cm3.h **** \param [in] IRQn Device specific interrupt number.
- 1583:Drivers/CMSIS/Include/core_cm3.h **** \note IRQn must not be negative.
- 1584:Drivers/CMSIS/Include/core_cm3.h **** */
- 1585:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
- 1586:Drivers/CMSIS/Include/core_cm3.h **** {
- 1587:Drivers/CMSIS/Include/core_cm3.h **** if ((int32_t)(IRQn) >= 0)
- 1588:Drivers/CMSIS/Include/core_cm3.h **** {
- 1589:Drivers/CMSIS/Include/core_cm3.h **** NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- 1590:Drivers/CMSIS/Include/core_cm3.h **** }
- 1591:Drivers/CMSIS/Include/core_cm3.h **** }
- 1592:Drivers/CMSIS/Include/core_cm3.h ****
- 1593:Drivers/CMSIS/Include/core_cm3.h ****
- 1594:Drivers/CMSIS/Include/core_cm3.h **** /**
- 1595:Drivers/CMSIS/Include/core_cm3.h **** \brief Clear Pending Interrupt
- 1596:Drivers/CMSIS/Include/core_cm3.h **** \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
- 1597:Drivers/CMSIS/Include/core_cm3.h **** \param [in] IRQn Device specific interrupt number.
- 1598:Drivers/CMSIS/Include/core_cm3.h **** \note IRQn must not be negative.
- 1599:Drivers/CMSIS/Include/core_cm3.h **** */
- 1600:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
- 1601:Drivers/CMSIS/Include/core_cm3.h **** {
- 1602:Drivers/CMSIS/Include/core_cm3.h **** if ((int32_t)(IRQn) >= 0)
- 1603:Drivers/CMSIS/Include/core_cm3.h **** {
- 1604:Drivers/CMSIS/Include/core_cm3.h **** NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- 1605:Drivers/CMSIS/Include/core_cm3.h **** }
- 1606:Drivers/CMSIS/Include/core_cm3.h **** }
- 1607:Drivers/CMSIS/Include/core_cm3.h ****
- 1608:Drivers/CMSIS/Include/core_cm3.h ****
- 1609:Drivers/CMSIS/Include/core_cm3.h **** /**
- 1610:Drivers/CMSIS/Include/core_cm3.h **** \brief Get Active Interrupt
- 1611:Drivers/CMSIS/Include/core_cm3.h **** \details Reads the active register in the NVIC and returns the active bit for the device specific
- 1612:Drivers/CMSIS/Include/core_cm3.h **** \param [in] IRQn Device specific interrupt number.
- 1613:Drivers/CMSIS/Include/core_cm3.h **** \return 0 Interrupt status is not active.
- 1614:Drivers/CMSIS/Include/core_cm3.h **** \return 1 Interrupt status is active.
- 1615:Drivers/CMSIS/Include/core_cm3.h **** \note IRQn must not be negative.
- 1616:Drivers/CMSIS/Include/core_cm3.h **** */
- 1617:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
- 1618:Drivers/CMSIS/Include/core_cm3.h **** {
- 1619:Drivers/CMSIS/Include/core_cm3.h **** if ((int32_t)(IRQn) >= 0)
- 1620:Drivers/CMSIS/Include/core_cm3.h **** {
- 1621:Drivers/CMSIS/Include/core_cm3.h **** return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL)
- 1622:Drivers/CMSIS/Include/core_cm3.h **** }
- 1623:Drivers/CMSIS/Include/core_cm3.h **** else
- 1624:Drivers/CMSIS/Include/core_cm3.h **** {
- 1625:Drivers/CMSIS/Include/core_cm3.h **** return(0U);
- 1626:Drivers/CMSIS/Include/core_cm3.h **** }
- 1627:Drivers/CMSIS/Include/core_cm3.h **** }
- ARM GAS /tmp/ccBGIhL8.s page 30
- 1628:Drivers/CMSIS/Include/core_cm3.h ****
- 1629:Drivers/CMSIS/Include/core_cm3.h ****
- 1630:Drivers/CMSIS/Include/core_cm3.h **** /**
- 1631:Drivers/CMSIS/Include/core_cm3.h **** \brief Set Interrupt Priority
- 1632:Drivers/CMSIS/Include/core_cm3.h **** \details Sets the priority of a device specific interrupt or a processor exception.
- 1633:Drivers/CMSIS/Include/core_cm3.h **** The interrupt number can be positive to specify a device specific interrupt,
- 1634:Drivers/CMSIS/Include/core_cm3.h **** or negative to specify a processor exception.
- 1635:Drivers/CMSIS/Include/core_cm3.h **** \param [in] IRQn Interrupt number.
- 1636:Drivers/CMSIS/Include/core_cm3.h **** \param [in] priority Priority to set.
- 1637:Drivers/CMSIS/Include/core_cm3.h **** \note The priority cannot be set for every processor exception.
- 1638:Drivers/CMSIS/Include/core_cm3.h **** */
- 1639:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
- 1640:Drivers/CMSIS/Include/core_cm3.h **** {
- 1641:Drivers/CMSIS/Include/core_cm3.h **** if ((int32_t)(IRQn) >= 0)
- 1642:Drivers/CMSIS/Include/core_cm3.h **** {
- 1643:Drivers/CMSIS/Include/core_cm3.h **** NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (u
- 1644:Drivers/CMSIS/Include/core_cm3.h **** }
- 1645:Drivers/CMSIS/Include/core_cm3.h **** else
- 1646:Drivers/CMSIS/Include/core_cm3.h **** {
- 1647:Drivers/CMSIS/Include/core_cm3.h **** SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (u
- 1648:Drivers/CMSIS/Include/core_cm3.h **** }
- 1649:Drivers/CMSIS/Include/core_cm3.h **** }
- 1650:Drivers/CMSIS/Include/core_cm3.h ****
- 1651:Drivers/CMSIS/Include/core_cm3.h ****
- 1652:Drivers/CMSIS/Include/core_cm3.h **** /**
- 1653:Drivers/CMSIS/Include/core_cm3.h **** \brief Get Interrupt Priority
- 1654:Drivers/CMSIS/Include/core_cm3.h **** \details Reads the priority of a device specific interrupt or a processor exception.
- 1655:Drivers/CMSIS/Include/core_cm3.h **** The interrupt number can be positive to specify a device specific interrupt,
- 1656:Drivers/CMSIS/Include/core_cm3.h **** or negative to specify a processor exception.
- 1657:Drivers/CMSIS/Include/core_cm3.h **** \param [in] IRQn Interrupt number.
- 1658:Drivers/CMSIS/Include/core_cm3.h **** \return Interrupt Priority.
- 1659:Drivers/CMSIS/Include/core_cm3.h **** Value is aligned automatically to the implemented priority bits of the microc
- 1660:Drivers/CMSIS/Include/core_cm3.h **** */
- 1661:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
- 1662:Drivers/CMSIS/Include/core_cm3.h **** {
- 1663:Drivers/CMSIS/Include/core_cm3.h ****
- 1664:Drivers/CMSIS/Include/core_cm3.h **** if ((int32_t)(IRQn) >= 0)
- 1665:Drivers/CMSIS/Include/core_cm3.h **** {
- 1666:Drivers/CMSIS/Include/core_cm3.h **** return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
- 1667:Drivers/CMSIS/Include/core_cm3.h **** }
- 1668:Drivers/CMSIS/Include/core_cm3.h **** else
- 1669:Drivers/CMSIS/Include/core_cm3.h **** {
- 1670:Drivers/CMSIS/Include/core_cm3.h **** return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
- 1671:Drivers/CMSIS/Include/core_cm3.h **** }
- 1672:Drivers/CMSIS/Include/core_cm3.h **** }
- 1673:Drivers/CMSIS/Include/core_cm3.h ****
- 1674:Drivers/CMSIS/Include/core_cm3.h ****
- 1675:Drivers/CMSIS/Include/core_cm3.h **** /**
- 1676:Drivers/CMSIS/Include/core_cm3.h **** \brief Encode Priority
- 1677:Drivers/CMSIS/Include/core_cm3.h **** \details Encodes the priority for an interrupt with the given priority group,
- 1678:Drivers/CMSIS/Include/core_cm3.h **** preemptive priority value, and subpriority value.
- 1679:Drivers/CMSIS/Include/core_cm3.h **** In case of a conflict between priority grouping and available
- 1680:Drivers/CMSIS/Include/core_cm3.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- 1681:Drivers/CMSIS/Include/core_cm3.h **** \param [in] PriorityGroup Used priority group.
- 1682:Drivers/CMSIS/Include/core_cm3.h **** \param [in] PreemptPriority Preemptive priority value (starting from 0).
- 1683:Drivers/CMSIS/Include/core_cm3.h **** \param [in] SubPriority Subpriority value (starting from 0).
- 1684:Drivers/CMSIS/Include/core_cm3.h **** \return Encoded priority. Value can be used in the function \ref NVIC_SetP
- ARM GAS /tmp/ccBGIhL8.s page 31
- 1685:Drivers/CMSIS/Include/core_cm3.h **** */
- 1686:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin
- 1687:Drivers/CMSIS/Include/core_cm3.h **** {
- 28 .loc 2 1687 1 view -0
- 29 .cfi_startproc
- 30 @ args = 0, pretend = 0, frame = 0
- 31 @ frame_needed = 0, uses_anonymous_args = 0
- 32 .loc 2 1687 1 is_stmt 0 view .LVU1
- 33 0000 00B5 push {lr}
- 34 .LCFI0:
- 35 .cfi_def_cfa_offset 4
- 36 .cfi_offset 14, -4
- 1688:Drivers/CMSIS/Include/core_cm3.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used
- 37 .loc 2 1688 3 is_stmt 1 view .LVU2
- 38 .loc 2 1688 12 is_stmt 0 view .LVU3
- 39 0002 00F00700 and r0, r0, #7
- 40 .LVL1:
- 1689:Drivers/CMSIS/Include/core_cm3.h **** uint32_t PreemptPriorityBits;
- 41 .loc 2 1689 3 is_stmt 1 view .LVU4
- 1690:Drivers/CMSIS/Include/core_cm3.h **** uint32_t SubPriorityBits;
- 42 .loc 2 1690 3 view .LVU5
- 1691:Drivers/CMSIS/Include/core_cm3.h ****
- 1692:Drivers/CMSIS/Include/core_cm3.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV
- 43 .loc 2 1692 3 view .LVU6
- 44 .loc 2 1692 31 is_stmt 0 view .LVU7
- 45 0006 C0F1070C rsb ip, r0, #7
- 46 .loc 2 1692 23 view .LVU8
- 47 000a BCF1040F cmp ip, #4
- 48 000e 28BF it cs
- 49 0010 4FF0040C movcs ip, #4
- 50 .LVL2:
- 1693:Drivers/CMSIS/Include/core_cm3.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
- 51 .loc 2 1693 3 is_stmt 1 view .LVU9
- 52 .loc 2 1693 44 is_stmt 0 view .LVU10
- 53 0014 031D adds r3, r0, #4
- 54 .loc 2 1693 109 view .LVU11
- 55 0016 062B cmp r3, #6
- 56 0018 0FD9 bls .L3
- 57 .loc 2 1693 109 discriminator 1 view .LVU12
- 58 001a C31E subs r3, r0, #3
- 59 .L2:
- 60 .LVL3:
- 1694:Drivers/CMSIS/Include/core_cm3.h ****
- 1695:Drivers/CMSIS/Include/core_cm3.h **** return (
- 61 .loc 2 1695 3 is_stmt 1 view .LVU13
- 1696:Drivers/CMSIS/Include/core_cm3.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits
- 62 .loc 2 1696 30 is_stmt 0 view .LVU14
- 63 001c 4FF0FF3E mov lr, #-1
- 64 0020 0EFA0CF0 lsl r0, lr, ip
- 65 .LVL4:
- 66 .loc 2 1696 30 view .LVU15
- 67 0024 21EA0001 bic r1, r1, r0
- 68 .LVL5:
- 69 .loc 2 1696 82 view .LVU16
- 70 0028 9940 lsls r1, r1, r3
- 1697:Drivers/CMSIS/Include/core_cm3.h **** ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- 71 .loc 2 1697 30 view .LVU17
- ARM GAS /tmp/ccBGIhL8.s page 32
- 72 002a 0EFA03FE lsl lr, lr, r3
- 73 002e 22EA0E02 bic r2, r2, lr
- 74 .LVL6:
- 1698:Drivers/CMSIS/Include/core_cm3.h **** );
- 1699:Drivers/CMSIS/Include/core_cm3.h **** }
- 75 .loc 2 1699 1 view .LVU18
- 76 0032 41EA0200 orr r0, r1, r2
- 77 0036 5DF804FB ldr pc, [sp], #4
- 78 .LVL7:
- 79 .L3:
- 1693:Drivers/CMSIS/Include/core_cm3.h ****
- 80 .loc 2 1693 109 discriminator 2 view .LVU19
- 81 003a 0023 movs r3, #0
- 82 003c EEE7 b .L2
- 83 .cfi_endproc
- 84 .LFE55:
- 86 .section .text.LL_ADC_INJ_SetSequencerRanks,"ax",%progbits
- 87 .align 1
- 88 .syntax unified
- 89 .thumb
- 90 .thumb_func
- 92 LL_ADC_INJ_SetSequencerRanks:
- 93 .LVL8:
- 94 .LFB92:
- 95 .file 3 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h"
- 1:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 2:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ******************************************************************************
- 3:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @file stm32f1xx_ll_adc.h
- 4:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @author MCD Application Team
- 5:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Header file of ADC LL module.
- 6:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ******************************************************************************
- 7:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @attention
- 8:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** *
- 9:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Copyright (c) 2017 STMicroelectronics.
- 10:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * All rights reserved.
- 11:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** *
- 12:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * This software is licensed under terms that can be found in the LICENSE file
- 13:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * in the root directory of this software component.
- 14:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * If no LICENSE file comes with this software, it is provided AS-IS.
- 15:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** *
- 16:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ******************************************************************************
- 17:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 18:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 19:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Define to prevent recursive inclusion -------------------------------------*/
- 20:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #ifndef __STM32F1xx_LL_ADC_H
- 21:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define __STM32F1xx_LL_ADC_H
- 22:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 23:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #ifdef __cplusplus
- 24:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** extern "C" {
- 25:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #endif
- 26:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 27:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Includes ------------------------------------------------------------------*/
- 28:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #include "stm32f1xx.h"
- 29:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 30:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @addtogroup STM32F1xx_LL_Driver
- 31:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 32:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- ARM GAS /tmp/ccBGIhL8.s page 33
- 33:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 34:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #if defined (ADC1) || defined (ADC2) || defined (ADC3)
- 35:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 36:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL ADC
- 37:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 38:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 39:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 40:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Private types -------------------------------------------------------------*/
- 41:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Private variables ---------------------------------------------------------*/
- 42:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 43:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Private constants ---------------------------------------------------------*/
- 44:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_Private_Constants ADC Private Constants
- 45:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 46:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 47:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 48:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Internal mask for ADC group regular sequencer: */
- 49:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
- 50:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* - sequencer register offset */
- 51:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* - sequencer rank bits position into the selected register */
- 52:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 53:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Internal register offset for ADC group regular sequencer configuration */
- 54:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* (offset placed into a spare area of literal definition) */
- 55:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_SQR1_REGOFFSET 0x00000000U
- 56:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_SQR2_REGOFFSET 0x00000100U
- 57:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_SQR3_REGOFFSET 0x00000200U
- 58:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_SQR4_REGOFFSET 0x00000300U
- 59:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 60:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGO
- 61:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
- 62:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 63:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Definition of ADC group regular sequencer bits information to be inserted */
- 64:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* into ADC group regular sequencer ranks literals definition. */
- 65:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1)
- 66:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2)
- 67:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3)
- 68:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4)
- 69:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5)
- 70:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6)
- 71:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7)
- 72:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8)
- 73:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9)
- 74:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10)
- 75:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11)
- 76:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12)
- 77:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13)
- 78:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14)
- 79:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15)
- 80:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16)
- 81:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 82:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Internal mask for ADC group injected sequencer: */
- 83:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
- 84:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* - data register offset */
- 85:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* - offset register offset */
- 86:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* - sequencer rank bits position into the selected register */
- 87:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 88:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Internal register offset for ADC group injected data register */
- 89:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* (offset placed into a spare area of literal definition) */
- ARM GAS /tmp/ccBGIhL8.s page 34
- 90:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_JDR1_REGOFFSET 0x00000000U
- 91:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_JDR2_REGOFFSET 0x00000100U
- 92:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_JDR3_REGOFFSET 0x00000200U
- 93:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_JDR4_REGOFFSET 0x00000300U
- 94:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 95:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Internal register offset for ADC group injected offset configuration */
- 96:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* (offset placed into a spare area of literal definition) */
- 97:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_JOFR1_REGOFFSET 0x00000000U
- 98:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_JOFR2_REGOFFSET 0x00001000U
- 99:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_JOFR3_REGOFFSET 0x00002000U
- 100:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_JOFR4_REGOFFSET 0x00003000U
- 101:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 102:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGO
- 103:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_R
- 104:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
- 105:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 106:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Internal mask for ADC channel: */
- 107:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
- 108:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* - channel identifier defined by number */
- 109:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* - channel differentiation between external channels (connected to */
- 110:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* GPIO pins) and internal channels (connected to internal paths) */
- 111:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* - channel sampling time defined by SMPRx register offset */
- 112:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* and SMPx bits positions into SMPRx register */
- 113:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
- 114:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID
- 115:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH
- 116:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
- 117:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_
- 118:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 119:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Channel differentiation between external and internal channels */
- 120:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */
- 121:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000U /* Marker of internal channel for other AD
- 122:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH
- 123:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 124:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Internal register offset for ADC channel sampling time configuration */
- 125:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* (offset placed into a spare area of literal definition) */
- 126:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_SMPR1_REGOFFSET 0x00000000U
- 127:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_SMPR2_REGOFFSET 0x02000000U
- 128:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
- 129:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 130:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U
- 131:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_
- 132:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 133:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Definition of channels ID number information to be inserted into */
- 134:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* channels literals definition. */
- 135:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_0_NUMBER 0x00000000U
- 136:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_1_NUMBER (
- 137:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_2_NUMBER ( A
- 138:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_3_NUMBER ( A
- 139:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2
- 140:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2
- 141:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | A
- 142:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | A
- 143:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3
- 144:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3
- 145:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | A
- 146:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | A
- ARM GAS /tmp/ccBGIhL8.s page 35
- 147:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2
- 148:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2
- 149:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | A
- 150:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | A
- 151:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4
- 152:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4
- 153:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 154:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Definition of channels sampling time information to be inserted into */
- 155:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* channels literals definition. */
- 156:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFF
- 157:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFF
- 158:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFF
- 159:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFF
- 160:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFF
- 161:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFF
- 162:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFF
- 163:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFF
- 164:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFF
- 165:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFF
- 166:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFF
- 167:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFF
- 168:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFF
- 169:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFF
- 170:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFF
- 171:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFF
- 172:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFF
- 173:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFF
- 174:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 175:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Internal mask for ADC analog watchdog: */
- 176:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
- 177:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* (concatenation of multiple bits used in different analog watchdogs, */
- 178:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* (feature of several watchdogs not available on all STM32 families)). */
- 179:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* - analog watchdog 1: monitored channel defined by number, */
- 180:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* selection of ADC group (ADC groups regular and-or injected). */
- 181:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 182:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Internal register offset for ADC analog watchdog channel configuration */
- 183:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_AWD_CR1_REGOFFSET 0x00000000U
- 184:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 185:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
- 186:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 187:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR
- 188:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
- 189:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 190:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Internal register offset for ADC analog watchdog threshold configuration */
- 191:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U
- 192:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U
- 193:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
- 194:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 195:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* ADC registers bits positions */
- 196:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define ADC_CR1_DUALMOD_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR1_DUALMO
- 197:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 198:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 199:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 200:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 201:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 202:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 203:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Private macros ------------------------------------------------------------*/
- ARM GAS /tmp/ccBGIhL8.s page 36
- 204:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_Private_Macros ADC Private Macros
- 205:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 206:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 207:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 208:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 209:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Driver macro reserved for internal use: isolate bits with the
- 210:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * selected mask and shift them to the register LSB
- 211:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (shift mask on register position bit 0).
- 212:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __BITS__ Bits in register 32 bits
- 213:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __MASK__ Mask in register 32 bits
- 214:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Bits in register 32 bits
- 215:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 216:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
- 217:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
- 218:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 219:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 220:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Driver macro reserved for internal use: set a pointer to
- 221:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * a register from a register basis from which an offset
- 222:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * is applied.
- 223:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __REG__ Register basis from which the offset is applied.
- 224:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
- 225:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Pointer to register address
- 226:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 227:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
- 228:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
- 229:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 230:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 231:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 232:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 233:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 234:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 235:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Exported types ------------------------------------------------------------*/
- 236:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #if defined(USE_FULL_LL_DRIVER)
- 237:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
- 238:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 239:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 240:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 241:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 242:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Structure definition of some features of ADC common parameters
- 243:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * and multimode
- 244:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (all ADC instances belonging to the same ADC common instance).
- 245:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
- 246:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * is conditioned to ADC instances state (all ADC instances
- 247:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * sharing the same ADC common instance):
- 248:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * All ADC instances sharing the same ADC common instance must be
- 249:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * disabled.
- 250:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 251:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** typedef struct
- 252:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 253:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independ
- 254:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** This parameter can be a value of @ref ADC_LL_EC_MULTI_
- 255:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 256:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** This feature can be modified afterwards using unitary
- 257:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** } LL_ADC_CommonInitTypeDef;
- 258:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 259:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Structure definition of some features of ADC instance.
- 260:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note These parameters have an impact on ADC scope: ADC instance.
- ARM GAS /tmp/ccBGIhL8.s page 37
- 261:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Affects both group regular and group injected (availability
- 262:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * of ADC group injected depends on STM32 families).
- 263:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Refer to corresponding unitary functions into
- 264:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @ref ADC_LL_EF_Configuration_ADC_Instance .
- 265:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note The setting of these parameters by function @ref LL_ADC_Init()
- 266:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * is conditioned to ADC state:
- 267:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * ADC instance must be disabled.
- 268:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * This condition is applied to all ADC features, for efficiency
- 269:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * and compatibility over all STM32 families. However, the different
- 270:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * features can be set under different ADC state conditions
- 271:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (setting possible with ADC enabled without conversion on going,
- 272:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * ADC enabled with conversion on going, ...)
- 273:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Each feature can be updated afterwards with a unitary function
- 274:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * and potentially with ADC in a different state than disabled,
- 275:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * refer to description of each function for setting
- 276:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * conditioned to ADC state.
- 277:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 278:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** typedef struct
- 279:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 280:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
- 281:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** This parameter can be a value of @ref ADC_LL_EC_DATA_A
- 282:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 283:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** This feature can be modified afterwards using unitary
- 284:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 285:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** uint32_t SequencersScanMode; /*!< Set ADC scan selection.
- 286:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** This parameter can be a value of @ref ADC_LL_EC_SCAN_S
- 287:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 288:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** This feature can be modified afterwards using unitary
- 289:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 290:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** } LL_ADC_InitTypeDef;
- 291:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 292:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 293:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Structure definition of some features of ADC group regular.
- 294:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note These parameters have an impact on ADC scope: ADC group regular.
- 295:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Refer to corresponding unitary functions into
- 296:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
- 297:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (functions with prefix "REG").
- 298:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
- 299:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * is conditioned to ADC state:
- 300:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * ADC instance must be disabled.
- 301:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * This condition is applied to all ADC features, for efficiency
- 302:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * and compatibility over all STM32 families. However, the different
- 303:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * features can be set under different ADC state conditions
- 304:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (setting possible with ADC enabled without conversion on going,
- 305:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * ADC enabled with conversion on going, ...)
- 306:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Each feature can be updated afterwards with a unitary function
- 307:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * and potentially with ADC in a different state than disabled,
- 308:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * refer to description of each function for setting
- 309:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * conditioned to ADC state.
- 310:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 311:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** typedef struct
- 312:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 313:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: inter
- 314:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** This parameter can be a value of @ref ADC_LL_EC_REG_TR
- 315:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** @note On this STM32 series, external trigger is set wi
- 316:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (only trigger polarity available on this STM32 s
- 317:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- ARM GAS /tmp/ccBGIhL8.s page 38
- 318:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** This feature can be modified afterwards using unitary
- 319:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 320:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
- 321:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** This parameter can be a value of @ref ADC_LL_EC_REG_SE
- 322:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** @note This parameter is discarded if scan mode is disa
- 323:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 324:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** This feature can be modified afterwards using unitary
- 325:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 326:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: se
- 327:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** This parameter can be a value of @ref ADC_LL_EC_REG_SE
- 328:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** @note This parameter has an effect only if group regul
- 329:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (scan length of 2 ranks or more).
- 330:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 331:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** This feature can be modified afterwards using unitary
- 332:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 333:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regula
- 334:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** This parameter can be a value of @ref ADC_LL_EC_REG_CO
- 335:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** Note: It is not possible to enable both ADC group regu
- 336:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 337:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** This feature can be modified afterwards using unitary
- 338:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 339:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no tra
- 340:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** This parameter can be a value of @ref ADC_LL_EC_REG_DM
- 341:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 342:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** This feature can be modified afterwards using unitary
- 343:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 344:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** } LL_ADC_REG_InitTypeDef;
- 345:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 346:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 347:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Structure definition of some features of ADC group injected.
- 348:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note These parameters have an impact on ADC scope: ADC group injected.
- 349:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Refer to corresponding unitary functions into
- 350:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
- 351:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (functions with prefix "INJ").
- 352:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
- 353:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * is conditioned to ADC state:
- 354:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * ADC instance must be disabled.
- 355:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * This condition is applied to all ADC features, for efficiency
- 356:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * and compatibility over all STM32 families. However, the different
- 357:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * features can be set under different ADC state conditions
- 358:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (setting possible with ADC enabled without conversion on going,
- 359:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * ADC enabled with conversion on going, ...)
- 360:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Each feature can be updated afterwards with a unitary function
- 361:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * and potentially with ADC in a different state than disabled,
- 362:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * refer to description of each function for setting
- 363:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * conditioned to ADC state.
- 364:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 365:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** typedef struct
- 366:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 367:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: inte
- 368:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** This parameter can be a value of @ref ADC_LL_EC_INJ_TR
- 369:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** @note On this STM32 series, external trigger is set wi
- 370:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (only trigger polarity available on this STM32 s
- 371:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 372:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** This feature can be modified afterwards using unitary
- 373:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 374:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
- ARM GAS /tmp/ccBGIhL8.s page 39
- 375:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** This parameter can be a value of @ref ADC_LL_EC_INJ_SE
- 376:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** @note This parameter is discarded if scan mode is disa
- 377:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 378:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** This feature can be modified afterwards using unitary
- 379:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 380:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: s
- 381:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** This parameter can be a value of @ref ADC_LL_EC_INJ_SE
- 382:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** @note This parameter has an effect only if group injec
- 383:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (scan length of 2 ranks or more).
- 384:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 385:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** This feature can be modified afterwards using unitary
- 386:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 387:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent
- 388:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** This parameter can be a value of @ref ADC_LL_EC_INJ_TR
- 389:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** Note: This parameter must be set to set to independent
- 390:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 391:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** This feature can be modified afterwards using unitary
- 392:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 393:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** } LL_ADC_INJ_InitTypeDef;
- 394:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 395:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 396:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 397:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 398:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #endif /* USE_FULL_LL_DRIVER */
- 399:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 400:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Exported constants --------------------------------------------------------*/
- 401:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
- 402:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 403:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 404:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 405:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_FLAG ADC flags
- 406:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Flags defines which can be used with LL_ADC_ReadReg function
- 407:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 408:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 409:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conve
- 410:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_FLAG_EOS ADC_SR_EOC /*!< ADC flag ADC group regular end o
- 411:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conv
- 412:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end
- 413:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 *
- 414:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #if defined(ADC_MULTIMODE_SUPPORT)
- 415:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_FLAG_EOS_MST ADC_SR_EOC /*!< ADC flag ADC multimode master gr
- 416:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_FLAG_EOS_SLV ADC_SR_EOC /*!< ADC flag ADC multimode slave gro
- 417:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_FLAG_JEOS_MST ADC_SR_JEOC /*!< ADC flag ADC multimode master gr
- 418:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_FLAG_JEOS_SLV ADC_SR_JEOC /*!< ADC flag ADC multimode slave gro
- 419:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_FLAG_AWD1_MST ADC_SR_AWD /*!< ADC flag ADC multimode master an
- 420:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_FLAG_AWD1_SLV ADC_SR_AWD /*!< ADC flag ADC multimode slave ana
- 421:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #endif
- 422:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 423:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 424:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 425:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 426:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
- 427:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
- 428:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 429:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 430:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_IT_EOS ADC_CR1_EOCIE /*!< ADC interruption ADC group regul
- 431:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injec
- ARM GAS /tmp/ccBGIhL8.s page 40
- 432:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watc
- 433:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 434:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 435:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 436:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 437:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
- 438:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 439:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 440:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* List of ADC registers intended to be used (most commonly) with */
- 441:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* DMA transfer. */
- 442:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
- 443:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000U /* ADC group regular conversion data reg
- 444:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #if defined(ADC_MULTIMODE_SUPPORT)
- 445:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001U /* ADC group regular conversion data reg
- 446:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #endif
- 447:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 448:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 449:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 450:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 451:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
- 452:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 453:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 454:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Note: Other measurement paths to internal channels may be available */
- 455:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* (connections to other peripherals). */
- 456:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* If they are not listed below, they do not require any specific */
- 457:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* path enable. In this case, Access to measurement path is done */
- 458:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* only by selecting the corresponding ADC internal channel. */
- 459:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_PATH_INTERNAL_NONE 0x00000000U /*!< ADC measurement paths all di
- 460:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CR2_TSVREFE) /*!< ADC measurement path to inte
- 461:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CR2_TSVREFE) /*!< ADC measurement path to inte
- 462:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 463:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 464:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 465:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 466:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
- 467:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 468:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 469:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_RESOLUTION_12B 0x00000000U /*!< ADC resolution
- 470:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 471:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 472:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 473:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 474:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
- 475:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 476:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 477:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_DATA_ALIGN_RIGHT 0x00000000U /*!< ADC conversion data alignmen
- 478:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignmen
- 479:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 480:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 481:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 482:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 483:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
- 484:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 485:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 486:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC conversion is performed in unita
- 487:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in seq
- 488:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- ARM GAS /tmp/ccBGIhL8.s page 41
- 489:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 490:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 491:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 492:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
- 493:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 494:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 495:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_GROUP_REGULAR 0x00000001U /*!< ADC group regular (available on all S
- 496:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_GROUP_INJECTED 0x00000002U /*!< ADC group injected (not available on
- 497:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003U /*!< ADC both groups regular and injected
- 498:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 499:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 500:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 501:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 502:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
- 503:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 504:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 505:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC ex
- 506:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC ex
- 507:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC ex
- 508:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC ex
- 509:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC ex
- 510:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC ex
- 511:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC ex
- 512:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC ex
- 513:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC ex
- 514:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC ex
- 515:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC ex
- 516:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC ex
- 517:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC ex
- 518:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC ex
- 519:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC ex
- 520:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC ex
- 521:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC ex
- 522:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC ex
- 523:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< AD
- 524:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< AD
- 525:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 526:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 527:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 528:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 529:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
- 530:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 531:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 532:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* ADC group regular external triggers for ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx
- 533:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_TRIG_SOFTWARE (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)
- 534:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1)
- 535:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* ADC group regular external triggers for ADC instances: ADC1, ADC2 (for ADC instances ADCx availa
- 536:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 0x00000000U
- 537:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0)
- 538:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)
- 539:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_2)
- 540:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)
- 541:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)
- 542:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC
- 543:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */
- 544:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* XL-density devices. */
- 545:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Note: To use TIM8_TRGO on ADC1 or ADC2, a remap of trigger must be done */
- ARM GAS /tmp/ccBGIhL8.s page 42
- 546:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* A remap of trigger must be done at top level (refer to */
- 547:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* AFIO peripheral). */
- 548:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)
- 549:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
- 550:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #if defined (STM32F103xE) || defined (STM32F103xG)
- 551:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* ADC group regular external triggers for ADC instances: ADC3 (for ADC instances ADCx available on
- 552:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1)
- 553:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (LL_ADC_REG_TRIG_EXT_TIM1_CH2)
- 554:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (LL_ADC_REG_TRIG_EXT_TIM2_CH2)
- 555:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (LL_ADC_REG_TRIG_EXT_TIM3_TRGO)
- 556:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM5_CH1 (LL_ADC_REG_TRIG_EXT_TIM4_CH4)
- 557:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_TIM5_CH3 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)
- 558:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #endif
- 559:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 560:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 561:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 562:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 563:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
- 564:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 565:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 566:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_TRIG_EXT_RISING ADC_CR2_EXTTRIG /*!< ADC group r
- 567:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 568:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 569:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 570:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 571:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
- 572:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 573:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 574:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_CONV_SINGLE 0x00000000U /*!< ADC conversions are perform
- 575:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are perform
- 576:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 577:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 578:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 579:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 580:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
- 581:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 582:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 583:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000U /*!< ADC conversions are not tr
- 584:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DMA) /*!< ADC conversion
- 585:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 586:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 587:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 588:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 589:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
- 590:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 591:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 592:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000U
- 593:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L
- 594:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1
- 595:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L
- 596:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2
- 597:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L
- 598:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1
- 599:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L
- 600:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3
- 601:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L
- 602:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1
- ARM GAS /tmp/ccBGIhL8.s page 43
- 603:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L
- 604:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2
- 605:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L
- 606:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1
- 607:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L
- 608:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 609:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 610:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 611:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 612:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
- 613:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 614:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 615:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000U
- 616:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_1RANK (
- 617:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM
- 618:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1
- 619:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM
- 620:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2
- 621:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM
- 622:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1
- 623:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM
- 624:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 625:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 626:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 627:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 628:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
- 629:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 630:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 631:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)
- 632:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)
- 633:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)
- 634:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)
- 635:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)
- 636:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)
- 637:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)
- 638:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)
- 639:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)
- 640:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS
- 641:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS
- 642:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS
- 643:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS
- 644:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS
- 645:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS
- 646:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS
- 647:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 648:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 649:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 650:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 651:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
- 652:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 653:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 654:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* ADC group injected external triggers for ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx
- 655:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_SOFTWARE (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL
- 656:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO 0x00000000U
- 657:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_CR2_JEXTSEL_0)
- 658:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* ADC group injected external triggers for ADC instances: ADC1, ADC2 (for ADC instances ADCx avail
- 659:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1)
- ARM GAS /tmp/ccBGIhL8.s page 44
- 660:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)
- 661:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2)
- 662:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)
- 663:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1)
- 664:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC
- 665:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Note: TIM8_CH4 is available on ADC1 and ADC2 only in high-density and */
- 666:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* XL-density devices. */
- 667:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Note: To use TIM8_TRGO on ADC1 or ADC2, a remap of trigger must be done */
- 668:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* A remap of trigger must be done at top level (refer to */
- 669:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* AFIO peripheral). */
- 670:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)
- 671:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
- 672:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #if defined (STM32F103xE) || defined (STM32F103xG)
- 673:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* ADC group injected external triggers for ADC instances: ADC3 (for ADC instances ADCx available o
- 674:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)
- 675:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)
- 676:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)
- 677:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)
- 678:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)
- 679:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #endif
- 680:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 681:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 682:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 683:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 684:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
- 685:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 686:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 687:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_EXT_RISING ADC_CR2_JEXTTRIG /*!< ADC group i
- 688:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 689:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 690:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 691:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 692:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
- 693:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 694:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 695:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000U /*!< ADC group injected conversio
- 696:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversio
- 697:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 698:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 699:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 700:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 701:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 702:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
- 703:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 704:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 705:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group injected
- 706:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected
- 707:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected
- 708:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected
- 709:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 710:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 711:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 712:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 713:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
- 714:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 715:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 716:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group injected sequencer
- ARM GAS /tmp/ccBGIhL8.s page 45
- 717:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer
- 718:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 719:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 720:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 721:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 722:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
- 723:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 724:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 725:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U)
- 726:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U)
- 727:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U)
- 728:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U)
- 729:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 730:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 731:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 732:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 733:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
- 734:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 735:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 736:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_1CYCLE_5 0x00000000U
- 737:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR2_SMP0_0)
- 738:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_13CYCLES_5 (ADC_SMPR2_SMP0_1)
- 739:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)
- 740:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_41CYCLES_5 (ADC_SMPR2_SMP0_2)
- 741:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_55CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)
- 742:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_71CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1)
- 743:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_SAMPLINGTIME_239CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)
- 744:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 745:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 746:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 747:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 748:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
- 749:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 750:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 751:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!<
- 752:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 753:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 754:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 755:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 756:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
- 757:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 758:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 759:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_DISABLE 0x00000000U
- 760:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_ALL_CHANNELS_REG (
- 761:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAW
- 762:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAW
- 763:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK)
- 764:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 765:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 766:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK)
- 767:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 768:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 769:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK)
- 770:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 771:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 772:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK)
- 773:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- ARM GAS /tmp/ccBGIhL8.s page 46
- 774:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 775:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK)
- 776:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 777:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 778:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK)
- 779:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 780:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 781:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK)
- 782:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 783:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 784:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK)
- 785:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 786:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 787:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK)
- 788:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 789:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 790:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK)
- 791:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 792:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 793:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)
- 794:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 795:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 796:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK)
- 797:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 798:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 799:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK)
- 800:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 801:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 802:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK)
- 803:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 804:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 805:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK)
- 806:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 807:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 808:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK)
- 809:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 810:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 811:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK)
- 812:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 813:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 814:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK)
- 815:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 816:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAW
- 817:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK)
- 818:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC
- 819:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC
- 820:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK)
- 821:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC
- 822:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC
- 823:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 824:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 825:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 826:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 827:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
- 828:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 829:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 830:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog th
- ARM GAS /tmp/ccBGIhL8.s page 47
- 831:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog th
- 832:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 833:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 834:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 835:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 836:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #if !defined(ADC_MULTIMODE_SUPPORT)
- 837:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
- 838:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 839:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 840:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_MULTI_INDEPENDENT 0x00000000U
- 841:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 842:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 843:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 844:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #endif
- 845:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #if defined(ADC_MULTIMODE_SUPPORT)
- 846:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
- 847:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 848:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 849:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_MULTI_INDEPENDENT 0x00000000U
- 850:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUAL
- 851:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_MULTI_DUAL_REG_INTERL_FAST ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUAL
- 852:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_MULTI_DUAL_REG_INTERL_SLOW (ADC_CR1_DUALMOD_3
- 853:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CR1_DUALMOD_2
- 854:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CR1_DUALMOD_3
- 855:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM (
- 856:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CR1_DUAL
- 857:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM ( ADC_CR1_DUAL
- 858:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM ( ADC_CR1_DUALMOD_2
- 859:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 860:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 861:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 862:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 863:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 864:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
- 865:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 866:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 867:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_MULTI_MASTER ( ADC_DR_DATA) /*!< In multimode, selec
- 868:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_MULTI_SLAVE (ADC_DR_ADC2DATA ) /*!< In multimode, selec
- 869:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_MULTI_MASTER_SLAVE (ADC_DR_ADC2DATA | ADC_DR_DATA) /*!< In multimode, selec
- 870:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 871:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 872:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 873:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 874:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #endif /* ADC_MULTIMODE_SUPPORT */
- 875:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 876:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 877:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
- 878:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Only ADC IP HW delays are defined in ADC LL driver driver,
- 879:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * not timeout values.
- 880:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * For details on delays values, refer to descriptions in source code
- 881:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * above each literal definition.
- 882:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 883:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 884:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 885:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
- 886:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* not timeout values. */
- 887:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Timeout values for ADC operations are dependent to device clock */
- ARM GAS /tmp/ccBGIhL8.s page 48
- 888:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* configuration (system clock versus ADC clock), */
- 889:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* and therefore must be defined in user application. */
- 890:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Indications for estimation of ADC timeout delays, for this */
- 891:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* STM32 series: */
- 892:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* - ADC enable time: maximum delay is 1us */
- 893:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* (refer to device datasheet, parameter "tSTAB") */
- 894:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* - ADC conversion time: duration depending on ADC clock and ADC */
- 895:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* configuration. */
- 896:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* (refer to device reference manual, section "Timing") */
- 897:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 898:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Delay for temperature sensor stabilization time. */
- 899:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Literal set to maximum value (refer to device datasheet, */
- 900:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* parameter "tSTART"). */
- 901:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Unit: us */
- 902:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_DELAY_TEMPSENSOR_STAB_US (10U) /*!< Delay for internal voltage reference stab
- 903:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 904:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Delay required between ADC disable and ADC calibration start. */
- 905:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Note: On this STM32 series, before starting a calibration, */
- 906:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* ADC must be disabled. */
- 907:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* A minimum number of ADC clock cycles are required */
- 908:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* between ADC disable state and calibration start. */
- 909:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Refer to literal @ref LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES. */
- 910:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Wait time can be computed in user application by waiting for the */
- 911:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* equivalent number of CPU cycles, by taking into account */
- 912:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* ratio of CPU clock versus ADC clock prescalers. */
- 913:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Unit: ADC clock cycles. */
- 914:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES (2U) /*!< Delay required between ADC disable and AD
- 915:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 916:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Delay required between end of ADC Enable and the start of ADC calibration. */
- 917:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Note: On this STM32 series, a minimum number of ADC clock cycles */
- 918:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* are required between the end of ADC enable and the start of ADC */
- 919:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* calibration. */
- 920:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Wait time can be computed in user application by waiting for the */
- 921:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* equivalent number of CPU cycles, by taking into account */
- 922:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* ratio of CPU clock versus ADC clock prescalers. */
- 923:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Unit: ADC clock cycles. */
- 924:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES (2U) /*!< Delay required between end of ADC enable a
- 925:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 926:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 927:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 928:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 929:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 930:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 931:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 932:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 933:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 934:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 935:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Exported macro ------------------------------------------------------------*/
- 936:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
- 937:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 938:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 939:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 940:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
- 941:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 942:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 943:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 944:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- ARM GAS /tmp/ccBGIhL8.s page 49
- 945:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Write a value in ADC register
- 946:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __INSTANCE__ ADC Instance
- 947:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __REG__ Register to be written
- 948:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __VALUE__ Value to be written in the register
- 949:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval None
- 950:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 951:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE
- 952:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 953:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 954:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Read a value in ADC register
- 955:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __INSTANCE__ ADC Instance
- 956:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __REG__ Register to be read
- 957:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Register value
- 958:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 959:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
- 960:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 961:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 962:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 963:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 964:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
- 965:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 966:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 967:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 968:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 969:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Helper macro to get ADC channel number in decimal format
- 970:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * from literals LL_ADC_CHANNEL_x.
- 971:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Example:
- 972:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
- 973:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * will return decimal number "4".
- 974:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note The input can be a value from functions where a channel
- 975:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * number is returned, either defined with number
- 976:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * or with bitfield (only one bit must be set).
- 977:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __CHANNEL__ This parameter can be one of the following values:
- 978:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_0
- 979:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_1
- 980:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_2
- 981:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_3
- 982:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_4
- 983:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_5
- 984:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_6
- 985:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_7
- 986:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_8
- 987:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_9
- 988:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_10
- 989:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_11
- 990:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_12
- 991:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_13
- 992:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_14
- 993:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_15
- 994:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_16
- 995:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_17
- 996:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- 997:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- 998:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** *
- 999:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (1) On STM32F1, parameter available only on ADC instance: ADC1.
- 1000:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Value between Min_Data=0 and Max_Data=18
- 1001:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- ARM GAS /tmp/ccBGIhL8.s page 50
- 1002:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
- 1003:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
- 1004:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1005:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1006:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
- 1007:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * from number in decimal format.
- 1008:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Example:
- 1009:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
- 1010:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * will return a data equivalent to "LL_ADC_CHANNEL_4".
- 1011:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18
- 1012:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Returned value can be one of the following values:
- 1013:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_0
- 1014:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_1
- 1015:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_2
- 1016:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_3
- 1017:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_4
- 1018:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_5
- 1019:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_6
- 1020:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_7
- 1021:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_8
- 1022:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_9
- 1023:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_10
- 1024:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_11
- 1025:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_12
- 1026:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_13
- 1027:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_14
- 1028:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_15
- 1029:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_16
- 1030:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_17
- 1031:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- 1032:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- 1033:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** *
- 1034:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n
- 1035:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (1) For ADC channel read back from ADC register,
- 1036:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * comparison with internal channel parameter to be done
- 1037:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
- 1038:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1039:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)
- 1040:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (((__DECIMAL_NB__) <= 9U)
- 1041:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ? (
- 1042:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
- 1043:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_P
- 1044:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** )
- 1045:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** :
- 1046:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (
- 1047:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
- 1048:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BIT
- 1049:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** )
- 1050:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** )
- 1051:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1052:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1053:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Helper macro to determine whether the selected channel
- 1054:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * corresponds to literal definitions of driver.
- 1055:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note The different literal definitions of ADC channels are:
- 1056:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - ADC internal channel:
- 1057:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
- 1058:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - ADC external channel (channel connected to a GPIO pin):
- ARM GAS /tmp/ccBGIhL8.s page 51
- 1059:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
- 1060:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note The channel parameter must be a value defined from literal
- 1061:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
- 1062:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * LL_ADC_CHANNEL_TEMPSENSOR, ...),
- 1063:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
- 1064:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * must not be a value from functions where a channel number is
- 1065:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * returned from ADC registers,
- 1066:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * because internal and external channels share the same channel
- 1067:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * number in ADC registers. The differentiation is made only with
- 1068:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * parameters definitions of driver.
- 1069:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __CHANNEL__ This parameter can be one of the following values:
- 1070:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_0
- 1071:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_1
- 1072:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_2
- 1073:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_3
- 1074:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_4
- 1075:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_5
- 1076:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_6
- 1077:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_7
- 1078:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_8
- 1079:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_9
- 1080:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_10
- 1081:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_11
- 1082:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_12
- 1083:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_13
- 1084:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_14
- 1085:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_15
- 1086:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_16
- 1087:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_17
- 1088:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- 1089:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- 1090:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** *
- 1091:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (1) On STM32F1, parameter available only on ADC instance: ADC1.
- 1092:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channe
- 1093:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Value "1" if the channel corresponds to a parameter definition of a ADC internal channe
- 1094:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1095:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
- 1096:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
- 1097:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1098:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1099:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Helper macro to convert a channel defined from parameter
- 1100:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
- 1101:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * LL_ADC_CHANNEL_TEMPSENSOR, ...),
- 1102:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * to its equivalent parameter definition of a ADC external channel
- 1103:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
- 1104:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note The channel parameter can be, additionally to a value
- 1105:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * defined from parameter definition of a ADC internal channel
- 1106:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
- 1107:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * a value defined from parameter definition of
- 1108:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
- 1109:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * or a value from functions where a channel number is returned
- 1110:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * from ADC registers.
- 1111:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __CHANNEL__ This parameter can be one of the following values:
- 1112:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_0
- 1113:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_1
- 1114:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_2
- 1115:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_3
- ARM GAS /tmp/ccBGIhL8.s page 52
- 1116:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_4
- 1117:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_5
- 1118:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_6
- 1119:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_7
- 1120:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_8
- 1121:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_9
- 1122:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_10
- 1123:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_11
- 1124:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_12
- 1125:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_13
- 1126:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_14
- 1127:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_15
- 1128:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_16
- 1129:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_17
- 1130:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- 1131:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- 1132:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** *
- 1133:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (1) On STM32F1, parameter available only on ADC instance: ADC1.
- 1134:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Returned value can be one of the following values:
- 1135:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_0
- 1136:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_1
- 1137:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_2
- 1138:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_3
- 1139:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_4
- 1140:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_5
- 1141:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_6
- 1142:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_7
- 1143:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_8
- 1144:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_9
- 1145:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_10
- 1146:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_11
- 1147:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_12
- 1148:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_13
- 1149:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_14
- 1150:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_15
- 1151:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_16
- 1152:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_17
- 1153:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1154:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
- 1155:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
- 1156:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1157:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1158:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Helper macro to determine whether the internal channel
- 1159:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * selected is available on the ADC instance selected.
- 1160:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note The channel parameter must be a value defined from parameter
- 1161:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
- 1162:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * LL_ADC_CHANNEL_TEMPSENSOR, ...),
- 1163:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * must not be a value defined from parameter definition of
- 1164:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
- 1165:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * or a value from functions where a channel number is
- 1166:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * returned from ADC registers,
- 1167:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * because internal and external channels share the same channel
- 1168:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * number in ADC registers. The differentiation is made only with
- 1169:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * parameters definitions of driver.
- 1170:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __ADC_INSTANCE__ ADC instance
- 1171:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __CHANNEL__ This parameter can be one of the following values:
- 1172:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- ARM GAS /tmp/ccBGIhL8.s page 53
- 1173:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- 1174:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** *
- 1175:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (1) On STM32F1, parameter available only on ADC instance: ADC1.
- 1176:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Value "0" if the internal channel selected is not available on the ADC instance selecte
- 1177:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Value "1" if the internal channel selected is available on the ADC instance selected.
- 1178:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1179:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
- 1180:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (((__ADC_INSTANCE__) == ADC1) \
- 1181:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ? ( \
- 1182:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
- 1183:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \
- 1184:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ) \
- 1185:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** : \
- 1186:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (0U) \
- 1187:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** )
- 1188:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1189:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1190:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Helper macro to define ADC analog watchdog parameter:
- 1191:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * define a single channel to monitor with analog watchdog
- 1192:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * from sequencer channel and groups definition.
- 1193:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
- 1194:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Example:
- 1195:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * LL_ADC_SetAnalogWDMonitChannels(
- 1196:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * ADC1, LL_ADC_AWD1,
- 1197:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
- 1198:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __CHANNEL__ This parameter can be one of the following values:
- 1199:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_0
- 1200:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_1
- 1201:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_2
- 1202:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_3
- 1203:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_4
- 1204:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_5
- 1205:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_6
- 1206:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_7
- 1207:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_8
- 1208:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_9
- 1209:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_10
- 1210:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_11
- 1211:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_12
- 1212:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_13
- 1213:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_14
- 1214:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_15
- 1215:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_16
- 1216:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_17
- 1217:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- 1218:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- 1219:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** *
- 1220:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n
- 1221:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (1) For ADC channel read back from ADC register,
- 1222:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * comparison with internal channel parameter to be done
- 1223:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
- 1224:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __GROUP__ This parameter can be one of the following values:
- 1225:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_GROUP_REGULAR
- 1226:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_GROUP_INJECTED
- 1227:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
- 1228:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Returned value can be one of the following values:
- 1229:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_DISABLE
- ARM GAS /tmp/ccBGIhL8.s page 54
- 1230:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
- 1231:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
- 1232:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
- 1233:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
- 1234:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
- 1235:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
- 1236:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
- 1237:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
- 1238:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
- 1239:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
- 1240:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
- 1241:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
- 1242:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
- 1243:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
- 1244:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
- 1245:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
- 1246:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
- 1247:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
- 1248:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
- 1249:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
- 1250:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
- 1251:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
- 1252:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
- 1253:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
- 1254:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
- 1255:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
- 1256:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
- 1257:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
- 1258:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
- 1259:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
- 1260:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
- 1261:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
- 1262:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
- 1263:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
- 1264:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
- 1265:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
- 1266:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
- 1267:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
- 1268:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
- 1269:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
- 1270:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
- 1271:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
- 1272:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
- 1273:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
- 1274:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
- 1275:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
- 1276:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
- 1277:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
- 1278:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
- 1279:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
- 1280:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
- 1281:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
- 1282:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
- 1283:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
- 1284:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
- 1285:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
- 1286:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
- ARM GAS /tmp/ccBGIhL8.s page 55
- 1287:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
- 1288:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
- 1289:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
- 1290:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)
- 1291:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)
- 1292:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
- 1293:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** *
- 1294:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (1) On STM32F1, parameter available only on ADC instance: ADC1.
- 1295:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1296:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)
- 1297:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (((__GROUP__) == LL_ADC_GROUP_REGULAR)
- 1298:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
- 1299:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** :
- 1300:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ((__GROUP__) == LL_ADC_GROUP_INJECTED)
- 1301:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
- 1302:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** :
- 1303:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
- 1304:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** )
- 1305:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1306:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1307:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Helper macro to set the value of ADC analog watchdog threshold high
- 1308:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * or low in function of ADC resolution, when ADC resolution is
- 1309:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * different of 12 bits.
- 1310:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
- 1311:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Example, with a ADC resolution of 8 bits, to set the value of
- 1312:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * analog watchdog threshold high (on 8 bits):
- 1313:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * LL_ADC_SetAnalogWDThresholds
- 1314:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (< ADCx param >,
- 1315:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8
- 1316:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * );
- 1317:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
- 1318:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_12B
- 1319:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
- 1320:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
- 1321:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1322:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Note: On this STM32 series, ADC is fixed to resolution 12 bits. */
- 1323:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* This macro has been kept anyway for compatibility with other */
- 1324:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* STM32 families featuring different ADC resolutions. */
- 1325:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
- 1326:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ((__AWD_THRESHOLD__) << (0U))
- 1327:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1328:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1329:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Helper macro to get the value of ADC analog watchdog threshold high
- 1330:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * or low in function of ADC resolution, when ADC resolution is
- 1331:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * different of 12 bits.
- 1332:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
- 1333:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Example, with a ADC resolution of 8 bits, to get the value of
- 1334:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * analog watchdog threshold high (on 8 bits):
- 1335:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
- 1336:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (LL_ADC_RESOLUTION_8B,
- 1337:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
- 1338:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * );
- 1339:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
- 1340:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_12B
- 1341:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
- 1342:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
- 1343:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- ARM GAS /tmp/ccBGIhL8.s page 56
- 1344:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Note: On this STM32 series, ADC is fixed to resolution 12 bits. */
- 1345:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* This macro has been kept anyway for compatibility with other */
- 1346:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* STM32 families featuring different ADC resolutions. */
- 1347:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
- 1348:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (__AWD_THRESHOLD_12_BITS__)
- 1349:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1350:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #if defined(ADC_MULTIMODE_SUPPORT)
- 1351:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1352:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Helper macro to get the ADC multimode conversion data of ADC master
- 1353:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * or ADC slave from raw value with both ADC conversion data concatenated.
- 1354:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note This macro is intended to be used when multimode transfer by DMA
- 1355:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * is enabled.
- 1356:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * In this case the transferred data need to processed with this macro
- 1357:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * to separate the conversion data of ADC master and ADC slave.
- 1358:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
- 1359:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_MULTI_MASTER
- 1360:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_MULTI_SLAVE
- 1361:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
- 1362:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
- 1363:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1364:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__)
- 1365:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_DR_DATA)
- 1366:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #endif
- 1367:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1368:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1369:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Helper macro to select the ADC common instance
- 1370:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * to which is belonging the selected ADC instance.
- 1371:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note ADC common register instance can be used for:
- 1372:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - Set parameters common to several ADC instances
- 1373:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - Multimode (for devices with several ADC instances)
- 1374:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Refer to functions having argument "ADCxy_COMMON" as parameter.
- 1375:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note On STM32F1, there is no common ADC instance.
- 1376:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * However, ADC instance ADC1 has a role of common ADC instance
- 1377:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * for ADC1 and ADC2:
- 1378:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * this instance is used to manage internal channels
- 1379:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * and multimode (these features are managed in ADC common
- 1380:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * instances on some other STM32 devices).
- 1381:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * ADC instance ADC3 (if available on the selected device)
- 1382:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * has no ADC common instance.
- 1383:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __ADCx__ ADC instance
- 1384:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval ADC common register instance
- 1385:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1386:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #if defined(ADC1) && defined(ADC2) && defined(ADC3)
- 1387:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
- 1388:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) \
- 1389:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ? ( \
- 1390:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (ADC12_COMMON) \
- 1391:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ) \
- 1392:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** : \
- 1393:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ( \
- 1394:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (0U) \
- 1395:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ) \
- 1396:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** )
- 1397:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #elif defined(ADC1) && defined(ADC2)
- 1398:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
- 1399:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (ADC12_COMMON)
- 1400:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #else
- ARM GAS /tmp/ccBGIhL8.s page 57
- 1401:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
- 1402:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (ADC1_COMMON)
- 1403:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #endif
- 1404:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1405:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1406:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Helper macro to check if all ADC instances sharing the same
- 1407:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * ADC common instance are disabled.
- 1408:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note This check is required by functions with setting conditioned to
- 1409:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * ADC state:
- 1410:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * All ADC instances of the ADC common group must be disabled.
- 1411:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Refer to functions having argument "ADCxy_COMMON" as parameter.
- 1412:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note On devices with only 1 ADC common instance, parameter of this macro
- 1413:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * is useless and can be ignored (parameter kept for compatibility
- 1414:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * with devices featuring several ADC common instances).
- 1415:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note On STM32F1, there is no common ADC instance.
- 1416:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * However, ADC instance ADC1 has a role of common ADC instance
- 1417:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * for ADC1 and ADC2:
- 1418:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * this instance is used to manage internal channels
- 1419:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * and multimode (these features are managed in ADC common
- 1420:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * instances on some other STM32 devices).
- 1421:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * ADC instance ADC3 (if available on the selected device)
- 1422:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * has no ADC common instance.
- 1423:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __ADCXY_COMMON__ ADC common instance
- 1424:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
- 1425:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Value "0" if all ADC instances sharing the same ADC common instance
- 1426:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * are disabled.
- 1427:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Value "1" if at least one ADC instance sharing the same ADC common instance
- 1428:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * is enabled.
- 1429:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1430:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #if defined(ADC1) && defined(ADC2) && defined(ADC3)
- 1431:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
- 1432:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (((__ADCXY_COMMON__) == ADC12_COMMON) \
- 1433:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ? ( \
- 1434:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (LL_ADC_IsEnabled(ADC1) | \
- 1435:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** LL_ADC_IsEnabled(ADC2) ) \
- 1436:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ) \
- 1437:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** : \
- 1438:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ( \
- 1439:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** LL_ADC_IsEnabled(ADC3) \
- 1440:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ) \
- 1441:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** )
- 1442:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #elif defined(ADC1) && defined(ADC2)
- 1443:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
- 1444:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (LL_ADC_IsEnabled(ADC1) | \
- 1445:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** LL_ADC_IsEnabled(ADC2) )
- 1446:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #else
- 1447:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
- 1448:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** LL_ADC_IsEnabled(ADC1)
- 1449:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #endif
- 1450:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1451:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1452:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Helper macro to define the ADC conversion data full-scale digital
- 1453:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * value corresponding to the selected ADC resolution.
- 1454:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note ADC conversion data full-scale corresponds to voltage range
- 1455:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * determined by analog voltage references Vref+ and Vref-
- 1456:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (refer to reference manual).
- 1457:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
- ARM GAS /tmp/ccBGIhL8.s page 58
- 1458:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_12B
- 1459:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval ADC conversion data equivalent voltage value (unit: mVolt)
- 1460:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1461:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
- 1462:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (0xFFFU)
- 1463:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1464:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1465:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1466:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Helper macro to calculate the voltage (unit: mVolt)
- 1467:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * corresponding to a ADC conversion data (unit: digital value).
- 1468:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Analog reference voltage (Vref+) must be known from
- 1469:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * user board environment or can be calculated using ADC measurement.
- 1470:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
- 1471:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
- 1472:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (unit: digital value).
- 1473:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
- 1474:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_12B
- 1475:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval ADC conversion data equivalent voltage value (unit: mVolt)
- 1476:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1477:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
- 1478:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __ADC_DATA__,\
- 1479:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __ADC_RESOLUTION__) \
- 1480:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
- 1481:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
- 1482:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** )
- 1483:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1484:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1485:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1486:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Helper macro to calculate the temperature (unit: degree Celsius)
- 1487:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * from ADC conversion data of internal temperature sensor.
- 1488:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Computation is using temperature sensor typical values
- 1489:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (refer to device datasheet).
- 1490:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Calculation formula:
- 1491:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
- 1492:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * / Avg_Slope + CALx_TEMP
- 1493:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * with TS_ADC_DATA = temperature sensor raw data measured by ADC
- 1494:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (unit: digital value)
- 1495:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Avg_Slope = temperature sensor slope
- 1496:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (unit: uV/Degree Celsius)
- 1497:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * TS_TYP_CALx_VOLT = temperature sensor digital value at
- 1498:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * temperature CALx_TEMP (unit: mV)
- 1499:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Caution: Calculation relevancy under reserve the temperature sensor
- 1500:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * of the current device has characteristics in line with
- 1501:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * datasheet typical values.
- 1502:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * If temperature sensor calibration values are available on
- 1503:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
- 1504:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * temperature calculation will be more accurate using
- 1505:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
- 1506:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note As calculation input, the analog reference voltage (Vref+) must be
- 1507:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * defined as it impacts the ADC LSB equivalent voltage.
- 1508:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Analog reference voltage (Vref+) must be known from
- 1509:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * user board environment or can be calculated using ADC measurement.
- 1510:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note ADC measurement data must correspond to a resolution of 12bits
- 1511:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (full scale digital value 4095). If not the case, the data must be
- 1512:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * preliminarily rescaled to an equivalent resolution of 12 bits.
- 1513:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical v
- 1514:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * On STM32F1, refer to device datasheet parameter "Avg_Slop
- ARM GAS /tmp/ccBGIhL8.s page 59
- 1515:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical
- 1516:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * On STM32F1, refer to device datasheet parameter "V25".
- 1517:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature s
- 1518:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
- 1519:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit:
- 1520:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor volta
- 1521:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * This parameter can be one of the following values:
- 1522:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_RESOLUTION_12B
- 1523:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Temperature (unit: degree Celsius)
- 1524:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1525:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
- 1526:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __TEMPSENSOR_TYP_CALX_V__,\
- 1527:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __TEMPSENSOR_CALX_TEMP__,\
- 1528:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __VREFANALOG_VOLTAGE__,\
- 1529:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __TEMPSENSOR_ADC_DATA__,\
- 1530:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __ADC_RESOLUTION__) \
- 1531:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ((( ( \
- 1532:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
- 1533:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * 1000) \
- 1534:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** - \
- 1535:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
- 1536:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
- 1537:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * 1000) \
- 1538:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ) \
- 1539:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
- 1540:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ) + (__TEMPSENSOR_CALX_TEMP__) \
- 1541:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** )
- 1542:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1543:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1544:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 1545:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1546:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1547:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1548:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 1549:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1550:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1551:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1552:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Exported functions --------------------------------------------------------*/
- 1553:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
- 1554:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 1555:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1556:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1557:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
- 1558:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 1559:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1560:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Note: LL ADC functions to set DMA transfer are located into sections of */
- 1561:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* configuration of ADC instance, groups and multimode (if available): */
- 1562:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* @ref LL_ADC_REG_SetDMATransfer(), ... */
- 1563:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1564:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1565:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Function to help to configure DMA transfer from ADC: retrieve the
- 1566:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * ADC register address from ADC instance and a list of ADC registers
- 1567:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * intended to be used (most commonly) with DMA transfer.
- 1568:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note These ADC registers are data registers:
- 1569:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * when ADC conversion data is available in ADC data registers,
- 1570:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * ADC generates a DMA transfer request.
- 1571:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note This macro is intended to be used with LL DMA driver, refer to
- ARM GAS /tmp/ccBGIhL8.s page 60
- 1572:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * function "LL_DMA_ConfigAddresses()".
- 1573:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Example:
- 1574:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * LL_DMA_ConfigAddresses(DMA1,
- 1575:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * LL_DMA_CHANNEL_1,
- 1576:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
- 1577:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (uint32_t)&< array or variable >,
- 1578:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
- 1579:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note For devices with several ADC: in multimode, some devices
- 1580:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * use a different data register outside of ADC instance scope
- 1581:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (common data register). This macro manages this register difference,
- 1582:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * only ADC instance has to be set as parameter.
- 1583:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note On STM32F1, only ADC instances ADC1 and ADC3 have DMA transfer
- 1584:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * capability, not ADC2 (ADC2 and ADC3 instances not available on
- 1585:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * all devices).
- 1586:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note On STM32F1, multimode can be used only with ADC1 and ADC2, not ADC3.
- 1587:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Therefore, the corresponding parameter of data transfer
- 1588:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * for multimode can be used only with ADC1 and ADC2.
- 1589:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (ADC2 and ADC3 instances not available on all devices).
- 1590:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr
- 1591:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 1592:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param Register This parameter can be one of the following values:
- 1593:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
- 1594:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
- 1595:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** *
- 1596:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (1) Available on devices with several ADC instances.
- 1597:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval ADC register address
- 1598:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1599:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #if defined(ADC_MULTIMODE_SUPPORT)
- 1600:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
- 1601:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 1602:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** uint32_t data_reg_addr = 0U;
- 1603:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1604:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
- 1605:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 1606:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Retrieve address of register DR */
- 1607:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** data_reg_addr = (uint32_t)&(ADCx->DR);
- 1608:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 1609:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
- 1610:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 1611:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Retrieve address of register of multimode data */
- 1612:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** data_reg_addr = (uint32_t)&(ADC12_COMMON->DR);
- 1613:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 1614:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1615:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** return data_reg_addr;
- 1616:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 1617:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #else
- 1618:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
- 1619:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 1620:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Retrieve address of register DR */
- 1621:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** return (uint32_t)&(ADCx->DR);
- 1622:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 1623:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** #endif
- 1624:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1625:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1626:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 1627:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1628:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- ARM GAS /tmp/ccBGIhL8.s page 61
- 1629:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to
- 1630:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 1631:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1632:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1633:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1634:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Set parameter common to several ADC: measurement path to internal
- 1635:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * channels (VrefInt, temperature sensor, ...).
- 1636:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note One or several values can be selected.
- 1637:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
- 1638:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
- 1639:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Stabilization time of measurement path to internal channel:
- 1640:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * After enabling internal paths, before starting ADC conversion,
- 1641:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * a delay is required for internal voltage reference and
- 1642:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * temperature sensor stabilization time.
- 1643:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Refer to device datasheet.
- 1644:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
- 1645:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note ADC internal channel sampling time constraint:
- 1646:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * For ADC conversion of internal channels,
- 1647:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * a sampling time minimum value is required.
- 1648:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Refer to device datasheet.
- 1649:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll CR2 TSVREFE LL_ADC_SetCommonPathInternalCh
- 1650:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCxy_COMMON ADC common instance
- 1651:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
- 1652:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param PathInternal This parameter can be a combination of the following values:
- 1653:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_PATH_INTERNAL_NONE
- 1654:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
- 1655:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
- 1656:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval None
- 1657:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1658:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Path
- 1659:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 1660:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** MODIFY_REG(ADCxy_COMMON->CR2, (ADC_CR2_TSVREFE), PathInternal);
- 1661:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 1662:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1663:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1664:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Get parameter common to several ADC: measurement path to internal
- 1665:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * channels (VrefInt, temperature sensor, ...).
- 1666:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note One or several values can be selected.
- 1667:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
- 1668:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
- 1669:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll CR2 TSVREFE LL_ADC_GetCommonPathInternalCh
- 1670:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCxy_COMMON ADC common instance
- 1671:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMO
- 1672:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Returned value can be a combination of the following values:
- 1673:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_PATH_INTERNAL_NONE
- 1674:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
- 1675:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
- 1676:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1677:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
- 1678:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 1679:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCxy_COMMON->CR2, ADC_CR2_TSVREFE));
- 1680:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 1681:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1682:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1683:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 1684:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1685:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- ARM GAS /tmp/ccBGIhL8.s page 62
- 1686:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC ins
- 1687:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 1688:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1689:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1690:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1691:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Set ADC conversion data alignment.
- 1692:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Refer to reference manual for alignments formats
- 1693:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * dependencies to ADC resolutions.
- 1694:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
- 1695:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 1696:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param DataAlignment This parameter can be one of the following values:
- 1697:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
- 1698:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_DATA_ALIGN_LEFT
- 1699:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval None
- 1700:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1701:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
- 1702:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 1703:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);
- 1704:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 1705:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1706:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1707:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Get ADC conversion data alignment.
- 1708:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Refer to reference manual for alignments formats
- 1709:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * dependencies to ADC resolutions.
- 1710:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
- 1711:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 1712:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Returned value can be one of the following values:
- 1713:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
- 1714:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_DATA_ALIGN_LEFT
- 1715:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1716:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
- 1717:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 1718:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));
- 1719:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 1720:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1721:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1722:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Set ADC sequencers scan mode, for all ADC groups
- 1723:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (group regular, group injected).
- 1724:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note According to sequencers scan mode :
- 1725:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - If disabled: ADC conversion is performed in unitary conversion
- 1726:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * mode (one channel converted, that defined in rank 1).
- 1727:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Configuration of sequencers of all ADC groups
- 1728:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (sequencer scan length, ...) is discarded: equivalent to
- 1729:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * scan length of 1 rank.
- 1730:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - If enabled: ADC conversions are performed in sequence conversions
- 1731:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * mode, according to configuration of sequencers of
- 1732:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * each ADC group (sequencer scan length, ...).
- 1733:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Refer to function @ref LL_ADC_REG_SetSequencerLength()
- 1734:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * and to function @ref LL_ADC_INJ_SetSequencerLength().
- 1735:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode
- 1736:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 1737:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ScanMode This parameter can be one of the following values:
- 1738:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
- 1739:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
- 1740:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval None
- 1741:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1742:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)
- ARM GAS /tmp/ccBGIhL8.s page 63
- 1743:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 1744:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);
- 1745:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 1746:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1747:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1748:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Get ADC sequencers scan mode, for all ADC groups
- 1749:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (group regular, group injected).
- 1750:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note According to sequencers scan mode :
- 1751:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - If disabled: ADC conversion is performed in unitary conversion
- 1752:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * mode (one channel converted, that defined in rank 1).
- 1753:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Configuration of sequencers of all ADC groups
- 1754:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (sequencer scan length, ...) is discarded: equivalent to
- 1755:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * scan length of 1 rank.
- 1756:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - If enabled: ADC conversions are performed in sequence conversions
- 1757:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * mode, according to configuration of sequencers of
- 1758:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * each ADC group (sequencer scan length, ...).
- 1759:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Refer to function @ref LL_ADC_REG_SetSequencerLength()
- 1760:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * and to function @ref LL_ADC_INJ_SetSequencerLength().
- 1761:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode
- 1762:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 1763:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Returned value can be one of the following values:
- 1764:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
- 1765:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
- 1766:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1767:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
- 1768:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 1769:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));
- 1770:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 1771:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1772:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1773:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 1774:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1775:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1776:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: gr
- 1777:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 1778:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1779:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1780:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1781:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Set ADC group regular conversion trigger source:
- 1782:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * internal (SW start) or from external IP (timer event,
- 1783:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * external interrupt line).
- 1784:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note On this STM32 series, external trigger is set with trigger polarity:
- 1785:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * rising edge (only trigger polarity available on this STM32 series).
- 1786:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Availability of parameters of trigger sources from timer
- 1787:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * depends on timers availability on the selected device.
- 1788:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource
- 1789:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 1790:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param TriggerSource This parameter can be one of the following values:
- 1791:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
- 1792:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1)
- 1793:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (2)
- 1794:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (2)
- 1795:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (2)
- 1796:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (2)
- 1797:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (2)
- 1798:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (2)
- 1799:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (2)(4)
- ARM GAS /tmp/ccBGIhL8.s page 64
- 1800:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (3)
- 1801:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (3)
- 1802:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (3)
- 1803:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (3)
- 1804:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3)
- 1805:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 (3)
- 1806:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 (3)
- 1807:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** *
- 1808:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC ins
- 1809:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instance
- 1810:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx
- 1811:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (4) On STM32F1, parameter available only on high-density and XL-density devices. A rema
- 1812:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval None
- 1813:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1814:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
- 1815:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 1816:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Note: On this STM32 series, ADC group regular external trigger edge */
- 1817:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* is used to perform a ADC conversion start. */
- 1818:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* This function does not set external trigger edge. */
- 1819:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* This feature is set using function */
- 1820:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* @ref LL_ADC_REG_StartConversionExtTrig(). */
- 1821:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));
- 1822:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 1823:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1824:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1825:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Get ADC group regular conversion trigger source:
- 1826:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * internal (SW start) or from external IP (timer event,
- 1827:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * external interrupt line).
- 1828:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note To determine whether group regular trigger source is
- 1829:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * internal (SW start) or external, without detail
- 1830:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * of which peripheral is selected as external trigger,
- 1831:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (equivalent to
- 1832:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
- 1833:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
- 1834:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Availability of parameters of trigger sources from timer
- 1835:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * depends on timers availability on the selected device.
- 1836:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource
- 1837:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 1838:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Returned value can be one of the following values:
- 1839:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
- 1840:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1)
- 1841:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (2)
- 1842:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (2)
- 1843:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (2)
- 1844:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (2)
- 1845:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (2)
- 1846:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (2)
- 1847:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (2)(4)
- 1848:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (3)
- 1849:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (3)
- 1850:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (3)
- 1851:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (3)
- 1852:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3)
- 1853:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 (3)
- 1854:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 (3)
- 1855:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** *
- 1856:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC ins
- ARM GAS /tmp/ccBGIhL8.s page 65
- 1857:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instance
- 1858:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx
- 1859:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (4) On STM32F1, parameter available only on high-density and XL-density devices. A rema
- 1860:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1861:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
- 1862:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 1863:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL));
- 1864:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 1865:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1866:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1867:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Get ADC group regular conversion trigger source internal (SW start)
- 1868:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** or external.
- 1869:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note In case of group regular trigger source set to external trigger,
- 1870:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * to determine which peripheral is selected as external trigger,
- 1871:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * use function @ref LL_ADC_REG_GetTriggerSource().
- 1872:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll CR2 EXTSEL LL_ADC_REG_IsTriggerSourceSWStart
- 1873:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 1874:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Value "0" if trigger source external trigger
- 1875:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Value "1" if trigger source SW start.
- 1876:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1877:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
- 1878:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 1879:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** return (READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL) == (LL_ADC_REG_TRIG_SOFTWARE));
- 1880:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 1881:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1882:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1883:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1884:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Set ADC group regular sequencer length and scan direction.
- 1885:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Description of ADC group regular sequencer features:
- 1886:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - For devices with sequencer fully configurable
- 1887:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (function "LL_ADC_REG_SetSequencerRanks()" available):
- 1888:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * sequencer length and each rank affectation to a channel
- 1889:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * are configurable.
- 1890:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * This function performs configuration of:
- 1891:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - Sequence length: Number of ranks in the scan sequence.
- 1892:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - Sequence direction: Unless specified in parameters, sequencer
- 1893:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * scan direction is forward (from rank 1 to rank n).
- 1894:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Sequencer ranks are selected using
- 1895:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * function "LL_ADC_REG_SetSequencerRanks()".
- 1896:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - For devices with sequencer not fully configurable
- 1897:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (function "LL_ADC_REG_SetSequencerChannels()" available):
- 1898:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * sequencer length and each rank affectation to a channel
- 1899:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * are defined by channel number.
- 1900:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * This function performs configuration of:
- 1901:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - Sequence length: Number of ranks in the scan sequence is
- 1902:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * defined by number of channels set in the sequence,
- 1903:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * rank of each channel is fixed by channel HW number.
- 1904:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
- 1905:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - Sequence direction: Unless specified in parameters, sequencer
- 1906:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * scan direction is forward (from lowest channel number to
- 1907:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * highest channel number).
- 1908:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Sequencer ranks are selected using
- 1909:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * function "LL_ADC_REG_SetSequencerChannels()".
- 1910:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note On this STM32 series, group regular sequencer configuration
- 1911:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * is conditioned to ADC instance sequencer mode.
- 1912:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * If ADC instance sequencer mode is disabled, sequencers of
- 1913:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * all groups (group regular, group injected) can be configured
- ARM GAS /tmp/ccBGIhL8.s page 66
- 1914:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * but their execution is disabled (limited to rank 1).
- 1915:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Refer to function @ref LL_ADC_SetSequencersScanMode().
- 1916:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Sequencer disabled is equivalent to sequencer of 1 rank:
- 1917:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * ADC conversion on only 1 channel.
- 1918:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
- 1919:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 1920:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param SequencerNbRanks This parameter can be one of the following values:
- 1921:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
- 1922:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
- 1923:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
- 1924:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
- 1925:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
- 1926:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
- 1927:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
- 1928:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
- 1929:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
- 1930:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
- 1931:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
- 1932:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
- 1933:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
- 1934:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
- 1935:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
- 1936:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
- 1937:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval None
- 1938:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1939:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
- 1940:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 1941:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
- 1942:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 1943:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 1944:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 1945:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Get ADC group regular sequencer length and scan direction.
- 1946:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Description of ADC group regular sequencer features:
- 1947:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - For devices with sequencer fully configurable
- 1948:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (function "LL_ADC_REG_SetSequencerRanks()" available):
- 1949:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * sequencer length and each rank affectation to a channel
- 1950:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * are configurable.
- 1951:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * This function retrieves:
- 1952:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - Sequence length: Number of ranks in the scan sequence.
- 1953:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - Sequence direction: Unless specified in parameters, sequencer
- 1954:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * scan direction is forward (from rank 1 to rank n).
- 1955:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Sequencer ranks are selected using
- 1956:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * function "LL_ADC_REG_SetSequencerRanks()".
- 1957:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - For devices with sequencer not fully configurable
- 1958:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (function "LL_ADC_REG_SetSequencerChannels()" available):
- 1959:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * sequencer length and each rank affectation to a channel
- 1960:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * are defined by channel number.
- 1961:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * This function retrieves:
- 1962:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - Sequence length: Number of ranks in the scan sequence is
- 1963:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * defined by number of channels set in the sequence,
- 1964:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * rank of each channel is fixed by channel HW number.
- 1965:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
- 1966:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - Sequence direction: Unless specified in parameters, sequencer
- 1967:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * scan direction is forward (from lowest channel number to
- 1968:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * highest channel number).
- 1969:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Sequencer ranks are selected using
- 1970:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * function "LL_ADC_REG_SetSequencerChannels()".
- ARM GAS /tmp/ccBGIhL8.s page 67
- 1971:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note On this STM32 series, group regular sequencer configuration
- 1972:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * is conditioned to ADC instance sequencer mode.
- 1973:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * If ADC instance sequencer mode is disabled, sequencers of
- 1974:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * all groups (group regular, group injected) can be configured
- 1975:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * but their execution is disabled (limited to rank 1).
- 1976:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Refer to function @ref LL_ADC_SetSequencersScanMode().
- 1977:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Sequencer disabled is equivalent to sequencer of 1 rank:
- 1978:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * ADC conversion on only 1 channel.
- 1979:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
- 1980:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 1981:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Returned value can be one of the following values:
- 1982:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
- 1983:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
- 1984:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
- 1985:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
- 1986:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
- 1987:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
- 1988:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
- 1989:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
- 1990:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
- 1991:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
- 1992:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
- 1993:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
- 1994:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
- 1995:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
- 1996:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
- 1997:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
- 1998:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 1999:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
- 2000:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 2001:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
- 2002:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 2003:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2004:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 2005:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Set ADC group regular sequencer discontinuous mode:
- 2006:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * sequence subdivided and scan conversions interrupted every selected
- 2007:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * number of ranks.
- 2008:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note It is not possible to enable both ADC group regular
- 2009:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * continuous mode and sequencer discontinuous mode.
- 2010:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note It is not possible to enable both ADC auto-injected mode
- 2011:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * and ADC group regular sequencer discontinuous mode.
- 2012:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
- 2013:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont
- 2014:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 2015:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param SeqDiscont This parameter can be one of the following values:
- 2016:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
- 2017:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
- 2018:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
- 2019:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
- 2020:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
- 2021:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
- 2022:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
- 2023:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
- 2024:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
- 2025:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval None
- 2026:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 2027:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
- ARM GAS /tmp/ccBGIhL8.s page 68
- 2028:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 2029:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont);
- 2030:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 2031:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2032:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 2033:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Get ADC group regular sequencer discontinuous mode:
- 2034:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * sequence subdivided and scan conversions interrupted every selected
- 2035:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * number of ranks.
- 2036:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
- 2037:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont
- 2038:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 2039:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Returned value can be one of the following values:
- 2040:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
- 2041:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
- 2042:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
- 2043:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
- 2044:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
- 2045:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
- 2046:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
- 2047:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
- 2048:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
- 2049:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 2050:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
- 2051:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 2052:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM));
- 2053:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 2054:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2055:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 2056:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Set ADC group regular sequence: channel on the selected
- 2057:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * scan sequence rank.
- 2058:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note This function performs configuration of:
- 2059:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - Channels ordering into each rank of scan sequence:
- 2060:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * whatever channel can be placed into whatever rank.
- 2061:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note On this STM32 series, ADC group regular sequencer is
- 2062:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * fully configurable: sequencer length and each rank
- 2063:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * affectation to a channel are configurable.
- 2064:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
- 2065:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Depending on devices and packages, some channels may not be available.
- 2066:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Refer to device datasheet for channels availability.
- 2067:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note On this STM32 series, to measure internal channels (VrefInt,
- 2068:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * TempSensor, ...), measurement paths to internal channels must be
- 2069:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * enabled separately.
- 2070:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
- 2071:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n
- 2072:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n
- 2073:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n
- 2074:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n
- 2075:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n
- 2076:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n
- 2077:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
- 2078:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
- 2079:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
- 2080:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n
- 2081:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n
- 2082:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n
- 2083:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n
- 2084:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n
- ARM GAS /tmp/ccBGIhL8.s page 69
- 2085:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n
- 2086:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks
- 2087:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 2088:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param Rank This parameter can be one of the following values:
- 2089:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_1
- 2090:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_2
- 2091:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_3
- 2092:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_4
- 2093:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_5
- 2094:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_6
- 2095:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_7
- 2096:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_8
- 2097:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_9
- 2098:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_10
- 2099:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_11
- 2100:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_12
- 2101:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_13
- 2102:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_14
- 2103:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_15
- 2104:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_16
- 2105:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param Channel This parameter can be one of the following values:
- 2106:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_0
- 2107:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_1
- 2108:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_2
- 2109:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_3
- 2110:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_4
- 2111:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_5
- 2112:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_6
- 2113:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_7
- 2114:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_8
- 2115:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_9
- 2116:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_10
- 2117:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_11
- 2118:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_12
- 2119:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_13
- 2120:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_14
- 2121:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_15
- 2122:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_16
- 2123:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_17
- 2124:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- 2125:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- 2126:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** *
- 2127:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (1) On STM32F1, parameter available only on ADC instance: ADC1.
- 2128:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval None
- 2129:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 2130:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channe
- 2131:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 2132:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Set bits with content of parameter "Channel" with bits position */
- 2133:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* in register and register position depending on parameter "Rank". */
- 2134:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Parameters "Rank" and "Channel" are used with masks because containing */
- 2135:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* other bits reserved for other purpose. */
- 2136:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFF
- 2137:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2138:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** MODIFY_REG(*preg,
- 2139:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
- 2140:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
- 2141:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- ARM GAS /tmp/ccBGIhL8.s page 70
- 2142:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2143:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 2144:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Get ADC group regular sequence: channel on the selected
- 2145:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * scan sequence rank.
- 2146:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note On this STM32 series, ADC group regular sequencer is
- 2147:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * fully configurable: sequencer length and each rank
- 2148:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * affectation to a channel are configurable.
- 2149:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
- 2150:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Depending on devices and packages, some channels may not be available.
- 2151:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Refer to device datasheet for channels availability.
- 2152:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Usage of the returned channel number:
- 2153:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - To reinject this channel into another function LL_ADC_xxx:
- 2154:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * the returned channel number is only partly formatted on definition
- 2155:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
- 2156:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * with parts of literals LL_ADC_CHANNEL_x or using
- 2157:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
- 2158:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Then the selected literal LL_ADC_CHANNEL_x can be used
- 2159:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * as parameter for another function.
- 2160:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - To get the channel number in decimal format:
- 2161:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * process the returned value with the helper macro
- 2162:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
- 2163:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n
- 2164:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n
- 2165:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n
- 2166:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n
- 2167:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n
- 2168:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n
- 2169:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
- 2170:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
- 2171:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
- 2172:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n
- 2173:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n
- 2174:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n
- 2175:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n
- 2176:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n
- 2177:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n
- 2178:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks
- 2179:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 2180:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param Rank This parameter can be one of the following values:
- 2181:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_1
- 2182:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_2
- 2183:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_3
- 2184:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_4
- 2185:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_5
- 2186:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_6
- 2187:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_7
- 2188:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_8
- 2189:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_9
- 2190:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_10
- 2191:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_11
- 2192:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_12
- 2193:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_13
- 2194:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_14
- 2195:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_15
- 2196:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_RANK_16
- 2197:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Returned value can be one of the following values:
- 2198:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_0
- ARM GAS /tmp/ccBGIhL8.s page 71
- 2199:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_1
- 2200:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_2
- 2201:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_3
- 2202:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_4
- 2203:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_5
- 2204:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_6
- 2205:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_7
- 2206:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_8
- 2207:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_9
- 2208:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_10
- 2209:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_11
- 2210:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_12
- 2211:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_13
- 2212:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_14
- 2213:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_15
- 2214:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_16
- 2215:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_17
- 2216:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- 2217:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- 2218:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** *
- 2219:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n
- 2220:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (1) For ADC channel read back from ADC register,
- 2221:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * comparison with internal channel parameter to be done
- 2222:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
- 2223:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 2224:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
- 2225:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 2226:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFF
- 2227:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2228:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** return (uint32_t) (READ_BIT(*preg,
- 2229:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
- 2230:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
- 2231:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** );
- 2232:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 2233:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2234:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 2235:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Set ADC continuous conversion mode on ADC group regular.
- 2236:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Description of ADC continuous conversion mode:
- 2237:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - single mode: one conversion per trigger
- 2238:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - continuous mode: after the first trigger, following
- 2239:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * conversions launched successively automatically.
- 2240:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note It is not possible to enable both ADC group regular
- 2241:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * continuous mode and sequencer discontinuous mode.
- 2242:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode
- 2243:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 2244:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param Continuous This parameter can be one of the following values:
- 2245:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_CONV_SINGLE
- 2246:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
- 2247:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval None
- 2248:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 2249:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
- 2250:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 2251:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);
- 2252:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 2253:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2254:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 2255:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Get ADC continuous conversion mode on ADC group regular.
- ARM GAS /tmp/ccBGIhL8.s page 72
- 2256:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Description of ADC continuous conversion mode:
- 2257:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - single mode: one conversion per trigger
- 2258:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - continuous mode: after the first trigger, following
- 2259:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * conversions launched successively automatically.
- 2260:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode
- 2261:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 2262:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Returned value can be one of the following values:
- 2263:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_CONV_SINGLE
- 2264:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
- 2265:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 2266:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
- 2267:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 2268:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));
- 2269:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 2270:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2271:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 2272:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Set ADC group regular conversion data transfer: no transfer or
- 2273:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * transfer by DMA, and DMA requests mode.
- 2274:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note If transfer by DMA selected, specifies the DMA requests
- 2275:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * mode:
- 2276:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - Limited mode (One shot mode): DMA transfer requests are stopped
- 2277:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * when number of DMA data transfers (number of
- 2278:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * ADC conversions) is reached.
- 2279:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * This ADC mode is intended to be used with DMA mode non-circular.
- 2280:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - Unlimited mode: DMA transfer requests are unlimited,
- 2281:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * whatever number of DMA data transfers (number of
- 2282:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * ADC conversions).
- 2283:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * This ADC mode is intended to be used with DMA mode circular.
- 2284:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note If ADC DMA requests mode is set to unlimited and DMA is set to
- 2285:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * mode non-circular:
- 2286:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * when DMA transfers size will be reached, DMA will stop transfers of
- 2287:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * ADC conversions data ADC will raise an overrun error
- 2288:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (overrun flag and interruption if enabled).
- 2289:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note To configure DMA source address (peripheral address),
- 2290:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * use function @ref LL_ADC_DMA_GetRegAddr().
- 2291:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer
- 2292:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 2293:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param DMATransfer This parameter can be one of the following values:
- 2294:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
- 2295:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
- 2296:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval None
- 2297:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 2298:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
- 2299:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 2300:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** MODIFY_REG(ADCx->CR2, ADC_CR2_DMA, DMATransfer);
- 2301:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 2302:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2303:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 2304:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Get ADC group regular conversion data transfer: no transfer or
- 2305:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * transfer by DMA, and DMA requests mode.
- 2306:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note If transfer by DMA selected, specifies the DMA requests
- 2307:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * mode:
- 2308:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - Limited mode (One shot mode): DMA transfer requests are stopped
- 2309:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * when number of DMA data transfers (number of
- 2310:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * ADC conversions) is reached.
- 2311:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * This ADC mode is intended to be used with DMA mode non-circular.
- 2312:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - Unlimited mode: DMA transfer requests are unlimited,
- ARM GAS /tmp/ccBGIhL8.s page 73
- 2313:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * whatever number of DMA data transfers (number of
- 2314:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * ADC conversions).
- 2315:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * This ADC mode is intended to be used with DMA mode circular.
- 2316:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note If ADC DMA requests mode is set to unlimited and DMA is set to
- 2317:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * mode non-circular:
- 2318:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * when DMA transfers size will be reached, DMA will stop transfers of
- 2319:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * ADC conversions data ADC will raise an overrun error
- 2320:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (overrun flag and interruption if enabled).
- 2321:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note To configure DMA source address (peripheral address),
- 2322:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * use function @ref LL_ADC_DMA_GetRegAddr().
- 2323:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer
- 2324:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 2325:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Returned value can be one of the following values:
- 2326:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
- 2327:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
- 2328:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 2329:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
- 2330:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 2331:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA));
- 2332:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 2333:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2334:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 2335:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 2336:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 2337:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2338:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: g
- 2339:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 2340:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 2341:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2342:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 2343:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Set ADC group injected conversion trigger source:
- 2344:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * internal (SW start) or from external IP (timer event,
- 2345:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * external interrupt line).
- 2346:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note On this STM32 series, external trigger is set with trigger polarity:
- 2347:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * rising edge (only trigger polarity available on this STM32 series).
- 2348:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Availability of parameters of trigger sources from timer
- 2349:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * depends on timers availability on the selected device.
- 2350:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource
- 2351:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 2352:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param TriggerSource This parameter can be one of the following values:
- 2353:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
- 2354:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (1)
- 2355:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (1)
- 2356:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (2)
- 2357:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (2)
- 2358:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (2)
- 2359:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (2)
- 2360:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (2)
- 2361:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (2)(4)
- 2362:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (3)
- 2363:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (3)
- 2364:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (3)
- 2365:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (3)
- 2366:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (3)
- 2367:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (3)
- 2368:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** *
- 2369:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC ins
- ARM GAS /tmp/ccBGIhL8.s page 74
- 2370:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instance
- 2371:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx
- 2372:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (4) On STM32F1, parameter available only on high-density and XL-density devices. A rema
- 2373:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval None
- 2374:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 2375:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
- 2376:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 2377:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Note: On this STM32 series, ADC group injected external trigger edge */
- 2378:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* is used to perform a ADC conversion start. */
- 2379:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* This function does not set external trigger edge. */
- 2380:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* This feature is set using function */
- 2381:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* @ref LL_ADC_INJ_StartConversionExtTrig(). */
- 2382:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));
- 2383:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 2384:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2385:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 2386:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Get ADC group injected conversion trigger source:
- 2387:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * internal (SW start) or from external IP (timer event,
- 2388:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * external interrupt line).
- 2389:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note To determine whether group injected trigger source is
- 2390:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * internal (SW start) or external, without detail
- 2391:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * of which peripheral is selected as external trigger,
- 2392:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (equivalent to
- 2393:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
- 2394:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
- 2395:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Availability of parameters of trigger sources from timer
- 2396:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * depends on timers availability on the selected device.
- 2397:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource
- 2398:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 2399:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Returned value can be one of the following values:
- 2400:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
- 2401:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (1)
- 2402:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (1)
- 2403:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (2)
- 2404:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (2)
- 2405:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (2)
- 2406:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (2)
- 2407:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (2)
- 2408:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (2)(4)
- 2409:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (3)
- 2410:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (3)
- 2411:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (3)
- 2412:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (3)
- 2413:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (3)
- 2414:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (3)
- 2415:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** *
- 2416:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC ins
- 2417:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instance
- 2418:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx
- 2419:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (4) On STM32F1, parameter available only on high-density and XL-density devices. A rema
- 2420:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 2421:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
- 2422:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 2423:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL));
- 2424:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 2425:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2426:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- ARM GAS /tmp/ccBGIhL8.s page 75
- 2427:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Get ADC group injected conversion trigger source internal (SW start)
- 2428:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** or external
- 2429:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note In case of group injected trigger source set to external trigger,
- 2430:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * to determine which peripheral is selected as external trigger,
- 2431:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * use function @ref LL_ADC_INJ_GetTriggerSource.
- 2432:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll CR2 JEXTSEL LL_ADC_INJ_IsTriggerSourceSWStart
- 2433:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 2434:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Value "0" if trigger source external trigger
- 2435:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Value "1" if trigger source SW start.
- 2436:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 2437:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
- 2438:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 2439:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL) == LL_ADC_INJ_TRIG_SOFTWARE);
- 2440:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 2441:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2442:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 2443:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Set ADC group injected sequencer length and scan direction.
- 2444:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note This function performs configuration of:
- 2445:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - Sequence length: Number of ranks in the scan sequence.
- 2446:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - Sequence direction: Unless specified in parameters, sequencer
- 2447:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * scan direction is forward (from rank 1 to rank n).
- 2448:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note On this STM32 series, group injected sequencer configuration
- 2449:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * is conditioned to ADC instance sequencer mode.
- 2450:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * If ADC instance sequencer mode is disabled, sequencers of
- 2451:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * all groups (group regular, group injected) can be configured
- 2452:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * but their execution is disabled (limited to rank 1).
- 2453:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Refer to function @ref LL_ADC_SetSequencersScanMode().
- 2454:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Sequencer disabled is equivalent to sequencer of 1 rank:
- 2455:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * ADC conversion on only 1 channel.
- 2456:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
- 2457:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 2458:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param SequencerNbRanks This parameter can be one of the following values:
- 2459:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
- 2460:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
- 2461:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
- 2462:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
- 2463:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval None
- 2464:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 2465:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
- 2466:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 2467:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
- 2468:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 2469:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2470:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 2471:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Get ADC group injected sequencer length and scan direction.
- 2472:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note This function retrieves:
- 2473:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - Sequence length: Number of ranks in the scan sequence.
- 2474:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - Sequence direction: Unless specified in parameters, sequencer
- 2475:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * scan direction is forward (from rank 1 to rank n).
- 2476:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note On this STM32 series, group injected sequencer configuration
- 2477:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * is conditioned to ADC instance sequencer mode.
- 2478:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * If ADC instance sequencer mode is disabled, sequencers of
- 2479:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * all groups (group regular, group injected) can be configured
- 2480:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * but their execution is disabled (limited to rank 1).
- 2481:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Refer to function @ref LL_ADC_SetSequencersScanMode().
- 2482:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Sequencer disabled is equivalent to sequencer of 1 rank:
- 2483:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * ADC conversion on only 1 channel.
- ARM GAS /tmp/ccBGIhL8.s page 76
- 2484:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
- 2485:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 2486:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Returned value can be one of the following values:
- 2487:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
- 2488:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
- 2489:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
- 2490:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
- 2491:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 2492:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
- 2493:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 2494:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
- 2495:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 2496:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2497:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 2498:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Set ADC group injected sequencer discontinuous mode:
- 2499:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * sequence subdivided and scan conversions interrupted every selected
- 2500:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * number of ranks.
- 2501:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note It is not possible to enable both ADC group injected
- 2502:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * auto-injected mode and sequencer discontinuous mode.
- 2503:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont
- 2504:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 2505:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param SeqDiscont This parameter can be one of the following values:
- 2506:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
- 2507:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
- 2508:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval None
- 2509:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 2510:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
- 2511:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 2512:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);
- 2513:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 2514:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2515:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 2516:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Get ADC group injected sequencer discontinuous mode:
- 2517:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * sequence subdivided and scan conversions interrupted every selected
- 2518:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * number of ranks.
- 2519:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont
- 2520:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 2521:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Returned value can be one of the following values:
- 2522:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
- 2523:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
- 2524:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 2525:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
- 2526:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 2527:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));
- 2528:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 2529:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2530:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 2531:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Set ADC group injected sequence: channel on the selected
- 2532:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * sequence rank.
- 2533:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Depending on devices and packages, some channels may not be available.
- 2534:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Refer to device datasheet for channels availability.
- 2535:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note On this STM32 series, to measure internal channels (VrefInt,
- 2536:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * TempSensor, ...), measurement paths to internal channels must be
- 2537:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * enabled separately.
- 2538:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
- 2539:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
- 2540:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
- ARM GAS /tmp/ccBGIhL8.s page 77
- 2541:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
- 2542:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
- 2543:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 2544:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param Rank This parameter can be one of the following values:
- 2545:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_RANK_1
- 2546:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_RANK_2
- 2547:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_RANK_3
- 2548:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_RANK_4
- 2549:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param Channel This parameter can be one of the following values:
- 2550:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_0
- 2551:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_1
- 2552:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_2
- 2553:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_3
- 2554:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_4
- 2555:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_5
- 2556:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_6
- 2557:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_7
- 2558:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_8
- 2559:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_9
- 2560:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_10
- 2561:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_11
- 2562:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_12
- 2563:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_13
- 2564:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_14
- 2565:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_15
- 2566:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_16
- 2567:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_17
- 2568:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- 2569:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- 2570:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** *
- 2571:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (1) On STM32F1, parameter available only on ADC instance: ADC1.
- 2572:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval None
- 2573:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 2574:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channe
- 2575:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 96 .loc 3 2575 1 is_stmt 1 view -0
- 97 .cfi_startproc
- 98 @ args = 0, pretend = 0, frame = 0
- 99 @ frame_needed = 0, uses_anonymous_args = 0
- 100 @ link register save eliminated.
- 101 .loc 3 2575 1 is_stmt 0 view .LVU21
- 102 0000 10B4 push {r4}
- 103 .LCFI1:
- 104 .cfi_def_cfa_offset 4
- 105 .cfi_offset 4, -4
- 2576:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Set bits with content of parameter "Channel" with bits position */
- 2577:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* in register depending on parameter "Rank". */
- 2578:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Parameters "Rank" and "Channel" are used with masks because containing */
- 2579:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* other bits reserved for other purpose. */
- 2580:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
- 106 .loc 3 2580 3 is_stmt 1 view .LVU22
- 107 .loc 3 2580 23 is_stmt 0 view .LVU23
- 108 0002 836B ldr r3, [r0, #56]
- 109 .loc 3 2580 57 view .LVU24
- 110 0004 C3F30153 ubfx r3, r3, #20, #2
- 111 .loc 3 2580 12 view .LVU25
- 112 0008 0133 adds r3, r3, #1
- ARM GAS /tmp/ccBGIhL8.s page 78
- 113 .LVL9:
- 2581:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2582:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** MODIFY_REG(ADCx->JSQR,
- 114 .loc 3 2582 3 is_stmt 1 view .LVU26
- 115 000a 846B ldr r4, [r0, #56]
- 116 000c CB1A subs r3, r1, r3
- 117 .LVL10:
- 118 .loc 3 2582 3 is_stmt 0 view .LVU27
- 119 000e DBB2 uxtb r3, r3
- 120 0010 0333 adds r3, r3, #3
- 121 0012 DBB2 uxtb r3, r3
- 122 0014 03EB8303 add r3, r3, r3, lsl #2
- 123 0018 1F21 movs r1, #31
- 124 .LVL11:
- 125 .loc 3 2582 3 view .LVU28
- 126 001a 9940 lsls r1, r1, r3
- 127 001c 24EA0104 bic r4, r4, r1
- 128 0020 02F01F02 and r2, r2, #31
- 129 .LVL12:
- 130 .loc 3 2582 3 view .LVU29
- 131 0024 9A40 lsls r2, r2, r3
- 132 0026 1443 orrs r4, r4, r2
- 133 0028 8463 str r4, [r0, #56]
- 2583:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))),
- 2584:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))))
- 2585:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 134 .loc 3 2585 1 view .LVU30
- 135 002a 10BC pop {r4}
- 136 .LCFI2:
- 137 .cfi_restore 4
- 138 .cfi_def_cfa_offset 0
- 139 002c 7047 bx lr
- 140 .cfi_endproc
- 141 .LFE92:
- 143 .section .text.LL_TIM_OC_DisableFast,"ax",%progbits
- 144 .align 1
- 145 .syntax unified
- 146 .thumb
- 147 .thumb_func
- 149 LL_TIM_OC_DisableFast:
- 150 .LVL13:
- 151 .LFB457:
- 152 .file 4 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h"
- 1:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** ******************************************************************************
- 3:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @file stm32f1xx_ll_tim.h
- 4:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @author MCD Application Team
- 5:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Header file of TIM LL module.
- 6:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** ******************************************************************************
- 7:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @attention
- 8:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** *
- 9:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * Copyright (c) 2016 STMicroelectronics.
- 10:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * All rights reserved.
- 11:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** *
- 12:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * This software is licensed under terms that can be found in the LICENSE file
- 13:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * in the root directory of this software component.
- 14:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * If no LICENSE file comes with this software, it is provided AS-IS.
- ARM GAS /tmp/ccBGIhL8.s page 79
- 15:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** *
- 16:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** ******************************************************************************
- 17:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 18:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 19:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /* Define to prevent recursive inclusion -------------------------------------*/
- 20:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #ifndef __STM32F1xx_LL_TIM_H
- 21:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define __STM32F1xx_LL_TIM_H
- 22:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 23:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #ifdef __cplusplus
- 24:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** extern "C" {
- 25:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #endif
- 26:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 27:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /* Includes ------------------------------------------------------------------*/
- 28:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #include "stm32f1xx.h"
- 29:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 30:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @addtogroup STM32F1xx_LL_Driver
- 31:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 32:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 33:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 34:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defin
- 35:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 36:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL TIM
- 37:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 38:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 39:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 40:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /* Private types -------------------------------------------------------------*/
- 41:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /* Private variables ---------------------------------------------------------*/
- 42:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Variables TIM Private Variables
- 43:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 44:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 45:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** static const uint8_t OFFSET_TAB_CCMRx[] =
- 46:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 47:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 0x00U, /* 0: TIMx_CH1 */
- 48:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 0x00U, /* 1: TIMx_CH1N */
- 49:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 0x00U, /* 2: TIMx_CH2 */
- 50:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 0x00U, /* 3: TIMx_CH2N */
- 51:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 0x04U, /* 4: TIMx_CH3 */
- 52:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 0x04U, /* 5: TIMx_CH3N */
- 53:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 0x04U /* 6: TIMx_CH4 */
- 54:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** };
- 55:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 56:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** static const uint8_t SHIFT_TAB_OCxx[] =
- 57:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 58:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 0U, /* 0: OC1M, OC1FE, OC1PE */
- 59:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 0U, /* 1: - NA */
- 60:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 8U, /* 2: OC2M, OC2FE, OC2PE */
- 61:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 0U, /* 3: - NA */
- 62:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 0U, /* 4: OC3M, OC3FE, OC3PE */
- 63:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 0U, /* 5: - NA */
- 64:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 8U /* 6: OC4M, OC4FE, OC4PE */
- 65:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** };
- 66:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 67:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** static const uint8_t SHIFT_TAB_ICxx[] =
- 68:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 69:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 0U, /* 0: CC1S, IC1PSC, IC1F */
- 70:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 0U, /* 1: - NA */
- 71:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 8U, /* 2: CC2S, IC2PSC, IC2F */
- ARM GAS /tmp/ccBGIhL8.s page 80
- 72:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 0U, /* 3: - NA */
- 73:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 0U, /* 4: CC3S, IC3PSC, IC3F */
- 74:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 0U, /* 5: - NA */
- 75:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 8U /* 6: CC4S, IC4PSC, IC4F */
- 76:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** };
- 77:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 78:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** static const uint8_t SHIFT_TAB_CCxP[] =
- 79:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 80:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 0U, /* 0: CC1P */
- 81:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 2U, /* 1: CC1NP */
- 82:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 4U, /* 2: CC2P */
- 83:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 6U, /* 3: CC2NP */
- 84:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 8U, /* 4: CC3P */
- 85:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 10U, /* 5: CC3NP */
- 86:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 12U /* 6: CC4P */
- 87:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** };
- 88:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 89:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** static const uint8_t SHIFT_TAB_OISx[] =
- 90:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 91:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 0U, /* 0: OIS1 */
- 92:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 1U, /* 1: OIS1N */
- 93:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 2U, /* 2: OIS2 */
- 94:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 3U, /* 3: OIS2N */
- 95:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 4U, /* 4: OIS3 */
- 96:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 5U, /* 5: OIS3N */
- 97:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 6U /* 6: OIS4 */
- 98:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** };
- 99:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 100:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 101:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 102:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 103:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /* Private constants ---------------------------------------------------------*/
- 104:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Constants TIM Private Constants
- 105:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 106:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 107:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 108:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 109:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 110:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
- 111:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define DT_DELAY_1 ((uint8_t)0x7F)
- 112:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define DT_DELAY_2 ((uint8_t)0x3F)
- 113:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define DT_DELAY_3 ((uint8_t)0x1F)
- 114:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define DT_DELAY_4 ((uint8_t)0x1F)
- 115:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 116:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
- 117:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define DT_RANGE_1 ((uint8_t)0x00)
- 118:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define DT_RANGE_2 ((uint8_t)0x80)
- 119:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define DT_RANGE_3 ((uint8_t)0xC0)
- 120:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define DT_RANGE_4 ((uint8_t)0xE0)
- 121:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 122:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 123:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 124:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 125:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 126:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 127:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /* Private macros ------------------------------------------------------------*/
- 128:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Macros TIM Private Macros
- ARM GAS /tmp/ccBGIhL8.s page 81
- 129:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 130:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 131:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @brief Convert channel id into channel index.
- 132:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param __CHANNEL__ This parameter can be one of the following values:
- 133:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- 134:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N
- 135:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- 136:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N
- 137:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 138:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N
- 139:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- 140:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval none
- 141:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 142:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
- 143:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
- 144:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
- 145:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
- 146:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
- 147:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
- 148:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
- 149:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 150:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @brief Calculate the deadtime sampling period(in ps).
- 151:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz).
- 152:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param __CKD__ This parameter can be one of the following values:
- 153:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
- 154:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
- 155:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
- 156:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval none
- 157:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 158:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
- 159:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
- 160:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
- 161:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
- 162:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 163:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 164:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 165:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 166:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 167:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /* Exported types ------------------------------------------------------------*/
- 168:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER)
- 169:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
- 170:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 171:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 172:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 173:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 174:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief TIM Time Base configuration structure definition.
- 175:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 176:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** typedef struct
- 177:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 178:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
- 179:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a number between Min_Data=0x0000 and Max_D
- 180:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 181:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary function
- 182:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_SetPrescaler().*/
- 183:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 184:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t CounterMode; /*!< Specifies the counter mode.
- 185:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
- ARM GAS /tmp/ccBGIhL8.s page 82
- 186:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 187:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary function
- 188:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_SetCounterMode().*/
- 189:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 190:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
- 191:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** Auto-Reload Register at the next update event.
- 192:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter must be a number between Min_Data=0x0000 and Max_
- 193:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** Some timer instances may support 32 bits counters. In that case
- 194:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** be a number between 0x0000 and 0xFFFFFFFF.
- 195:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 196:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary function
- 197:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_SetAutoReload().*/
- 198:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 199:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t ClockDivision; /*!< Specifies the clock division.
- 200:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
- 201:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 202:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary function
- 203:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_SetClockDivision().*/
- 204:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 205:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downc
- 206:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** reaches zero, an update event is generated and counting restarts
- 207:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** from the RCR value (N).
- 208:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This means in PWM mode that (N+1) corresponds to:
- 209:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** - the number of PWM periods in edge-aligned mode
- 210:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** - the number of half PWM period in center-aligned mode
- 211:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** GP timers: this parameter must be a number between Min_Data = 0x
- 212:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** Max_Data = 0xFF.
- 213:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** Advanced timers: this parameter must be a number between Min_Dat
- 214:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** Max_Data = 0xFFFF.
- 215:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 216:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary function
- 217:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_SetRepetitionCounter().*/
- 218:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** } LL_TIM_InitTypeDef;
- 219:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 220:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 221:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief TIM Output Compare configuration structure definition.
- 222:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 223:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** typedef struct
- 224:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 225:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t OCMode; /*!< Specifies the output mode.
- 226:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCMODE.
- 227:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 228:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary function
- 229:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_OC_SetMode().*/
- 230:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 231:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t OCState; /*!< Specifies the TIM Output Compare state.
- 232:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
- 233:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 234:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary functions
- 235:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
- 236:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 237:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
- 238:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
- 239:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 240:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary functions
- 241:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
- 242:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- ARM GAS /tmp/ccBGIhL8.s page 83
- 243:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Re
- 244:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a number between Min_Data=0x0000 and Max_Data=
- 245:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 246:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary function
- 247:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** LL_TIM_OC_SetCompareCHx (x=1..6).*/
- 248:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 249:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t OCPolarity; /*!< Specifies the output polarity.
- 250:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
- 251:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 252:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary function
- 253:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_OC_SetPolarity().*/
- 254:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 255:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
- 256:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
- 257:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 258:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary function
- 259:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_OC_SetPolarity().*/
- 260:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 261:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 262:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- 263:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
- 264:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 265:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary function
- 266:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_OC_SetIdleState().*/
- 267:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 268:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- 269:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
- 270:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 271:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary function
- 272:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_OC_SetIdleState().*/
- 273:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** } LL_TIM_OC_InitTypeDef;
- 274:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 275:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 276:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief TIM Input Capture configuration structure definition.
- 277:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 278:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 279:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** typedef struct
- 280:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 281:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 282:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
- 283:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
- 284:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 285:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary function
- 286:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/
- 287:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 288:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t ICActiveInput; /*!< Specifies the input.
- 289:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
- 290:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 291:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary function
- 292:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_IC_SetActiveInput().*/
- 293:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 294:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
- 295:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC.
- 296:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 297:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary function
- 298:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/
- 299:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- ARM GAS /tmp/ccBGIhL8.s page 84
- 300:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t ICFilter; /*!< Specifies the input capture filter.
- 301:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
- 302:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 303:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary function
- 304:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/
- 305:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** } LL_TIM_IC_InitTypeDef;
- 306:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 307:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 308:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 309:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief TIM Encoder interface configuration structure definition.
- 310:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 311:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** typedef struct
- 312:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 313:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
- 314:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
- 315:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 316:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary function
- 317:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_SetEncoderMode().*/
- 318:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 319:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
- 320:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
- 321:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 322:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary function
- 323:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/
- 324:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 325:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
- 326:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
- 327:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 328:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary function
- 329:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_IC_SetActiveInput().*/
- 330:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 331:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
- 332:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC.
- 333:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 334:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary function
- 335:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/
- 336:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 337:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
- 338:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
- 339:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 340:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary function
- 341:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/
- 342:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 343:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
- 344:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
- 345:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 346:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary function
- 347:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/
- 348:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 349:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
- 350:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
- 351:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 352:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary function
- 353:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_IC_SetActiveInput().*/
- 354:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 355:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
- 356:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC.
- ARM GAS /tmp/ccBGIhL8.s page 85
- 357:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 358:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary function
- 359:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/
- 360:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 361:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
- 362:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
- 363:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 364:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary function
- 365:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/
- 366:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 367:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** } LL_TIM_ENCODER_InitTypeDef;
- 368:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 369:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 370:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief TIM Hall sensor interface configuration structure definition.
- 371:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 372:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** typedef struct
- 373:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 374:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 375:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
- 376:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
- 377:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 378:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary function
- 379:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/
- 380:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 381:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
- 382:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** Prescaler must be set to get a maximum counter period longer th
- 383:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** time interval between 2 consecutive changes on the Hall inputs.
- 384:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC.
- 385:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 386:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary function
- 387:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/
- 388:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 389:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
- 390:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of
- 391:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref TIM_LL_EC_IC_FILTER.
- 392:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 393:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary function
- 394:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/
- 395:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 396:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compa
- 397:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** A positive pulse (TRGO event) is generated with a programmable
- 398:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** a change occurs on the Hall inputs.
- 399:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a number between Min_Data = 0x0000 and Ma
- 400:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 401:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary function
- 402:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_OC_SetCompareCH2().*/
- 403:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** } LL_TIM_HALLSENSOR_InitTypeDef;
- 404:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 405:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 406:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief BDTR (Break and Dead Time) structure definition
- 407:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 408:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** typedef struct
- 409:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 410:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
- 411:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OSSR
- 412:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 413:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary functio
- ARM GAS /tmp/ccBGIhL8.s page 86
- 414:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_SetOffStates()
- 415:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 416:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @note This bit-field cannot be modified as long as LOCK level
- 417:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** programmed. */
- 418:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 419:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
- 420:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OSSI
- 421:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 422:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary functio
- 423:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_SetOffStates()
- 424:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 425:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @note This bit-field cannot be modified as long as LOCK level
- 426:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** programmed. */
- 427:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 428:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
- 429:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
- 430:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 431:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @note The LOCK bits can be written only once after the reset.
- 432:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** register has been written, their content is frozen until the
- 433:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 434:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
- 435:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** switching-on of the outputs.
- 436:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a number between Min_Data = 0x00 and Ma
- 437:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 438:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary functio
- 439:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_OC_SetDeadTime()
- 440:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 441:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve
- 442:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** programmed. */
- 443:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 444:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
- 445:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
- 446:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 447:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary functio
- 448:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
- 449:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 450:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve
- 451:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** programmed. */
- 452:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 453:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
- 454:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARIT
- 455:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 456:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary functio
- 457:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_ConfigBRK()
- 458:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 459:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve
- 460:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** programmed. */
- 461:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 462:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled
- 463:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTP
- 464:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 465:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** This feature can be modified afterwards using unitary functio
- 466:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAut
- 467:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 468:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve
- 469:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** programmed. */
- 470:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** } LL_TIM_BDTR_InitTypeDef;
- ARM GAS /tmp/ccBGIhL8.s page 87
- 471:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 472:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 473:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 474:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 475:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */
- 476:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 477:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /* Exported constants --------------------------------------------------------*/
- 478:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
- 479:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 480:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 481:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 482:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
- 483:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Flags defines which can be used with LL_TIM_ReadReg function.
- 484:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 485:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 486:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
- 487:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrup
- 488:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrup
- 489:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrup
- 490:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrup
- 491:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
- 492:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
- 493:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
- 494:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapt
- 495:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapt
- 496:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapt
- 497:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapt
- 498:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 499:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 500:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 501:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 502:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER)
- 503:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
- 504:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 505:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 506:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
- 507:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
- 508:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 509:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 510:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 511:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 512:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
- 513:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 514:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 515:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by
- 516:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by softw
- 517:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 518:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 519:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 520:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */
- 521:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 522:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_IT IT Defines
- 523:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
- 524:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 525:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 526:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
- 527:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrup
- ARM GAS /tmp/ccBGIhL8.s page 88
- 528:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrup
- 529:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrup
- 530:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrup
- 531:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
- 532:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable *
- 533:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
- 534:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 535:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 536:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 537:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 538:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
- 539:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 540:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 541:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow
- 542:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/unde
- 543:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 544:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 545:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 546:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 547:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
- 548:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 549:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 550:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at
- 551:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at
- 552:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 553:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 554:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 555:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 556:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
- 557:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 558:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 559:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter *
- 560:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounte
- 561:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and
- 562:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and d
- 563:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and
- 564:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 565:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 566:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 567:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 568:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
- 569:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 570:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 571:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
- 572:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
- 573:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
- 574:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 575:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 576:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 577:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 578:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
- 579:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 580:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 581:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
- 582:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down
- 583:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 584:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- ARM GAS /tmp/ccBGIhL8.s page 89
- 585:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 586:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 587:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
- 588:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 589:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 590:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bi
- 591:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bi
- 592:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 593:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 594:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 595:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 596:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
- 597:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 598:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 599:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when
- 600:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when
- 601:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 602:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 603:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 604:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 605:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
- 606:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 607:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 608:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write
- 609:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
- 610:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
- 611:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
- 612:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 613:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 614:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 615:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 616:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CHANNEL Channel
- 617:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 618:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 619:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1
- 620:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output ch
- 621:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2
- 622:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output ch
- 623:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3
- 624:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output ch
- 625:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4
- 626:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 627:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 628:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 629:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 630:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER)
- 631:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
- 632:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 633:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 634:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
- 635:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on
- 636:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 637:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 638:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 639:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */
- 640:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 641:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
- ARM GAS /tmp/ccBGIhL8.s page 90
- 642:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 643:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 644:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_OCMODE_FROZEN 0x00000000U
- 645:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
- 646:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
- 647:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
- 648:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
- 649:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
- 650:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
- 651:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1
- 652:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 653:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 654:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 655:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 656:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
- 657:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 658:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 659:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
- 660:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
- 661:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 662:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 663:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 664:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 665:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
- 666:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 667:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 668:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time
- 669:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time
- 670:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 671:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 672:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 673:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 674:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 675:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
- 676:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 677:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 678:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx
- 679:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy
- 680:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC
- 681:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 682:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 683:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 684:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 685:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
- 686:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 687:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 688:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, ca
- 689:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done
- 690:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done
- 691:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done
- 692:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 693:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 694:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 695:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 696:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
- 697:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 698:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- ARM GAS /tmp/ccBGIhL8.s page 91
- 699:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_IC_FILTER_FDIV1 0x00000000U
- 700:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U)
- 701:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U)
- 702:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
- 703:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U)
- 704:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
- 705:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
- 706:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC
- 707:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U)
- 708:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)
- 709:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)
- 710:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC
- 711:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)
- 712:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC
- 713:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC
- 714:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U)
- 715:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 716:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 717:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 718:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 719:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
- 720:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 721:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 722:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is
- 723:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is
- 724:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 725:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 726:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 727:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 728:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
- 729:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 730:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 731:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U
- 732:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
- 733:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE
- 734:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 735:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 736:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 737:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 738:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
- 739:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 740:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 741:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0
- 742:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1
- 743:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
- 744:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 745:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 746:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 747:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 748:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_TRGO Trigger Output
- 749:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 750:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 751:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_TRGO_RESET 0x00000000U /*!<
- 752:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!<
- 753:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!<
- 754:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!<
- 755:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!<
- ARM GAS /tmp/ccBGIhL8.s page 92
- 756:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!<
- 757:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!<
- 758:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!<
- 759:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 760:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 761:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 762:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 763:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 764:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
- 765:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 766:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 767:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode
- 768:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode
- 769:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode
- 770:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mod
- 771:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 772:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 773:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 774:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 775:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_TS Trigger Selection
- 776:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 777:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 778:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_TS_ITR0 0x00000000U
- 779:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0
- 780:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1
- 781:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
- 782:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2
- 783:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)
- 784:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)
- 785:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)
- 786:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 787:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 788:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 789:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 790:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
- 791:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 792:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 793:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, ac
- 794:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active
- 795:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 796:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 797:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 798:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 799:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
- 800:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 801:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 802:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
- 803:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divide
- 804:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divide
- 805:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divide
- 806:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 807:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 808:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 809:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 810:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
- 811:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 812:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- ARM GAS /tmp/ccBGIhL8.s page 93
- 813:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U
- 814:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0
- 815:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1
- 816:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
- 817:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2
- 818:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
- 819:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)
- 820:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
- 821:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3
- 822:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)
- 823:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)
- 824:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
- 825:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)
- 826:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
- 827:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)
- 828:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF
- 829:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 830:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 831:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 832:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 833:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 834:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
- 835:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 836:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 837:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is ac
- 838:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is ac
- 839:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 840:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 841:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 842:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 843:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 844:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 845:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 846:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OSSI OSSI
- 847:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 848:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 849:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN
- 850:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN
- 851:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 852:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 853:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 854:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 855:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OSSR OSSR
- 856:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 857:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 858:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN
- 859:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN o
- 860:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 861:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 862:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 863:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 864:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 865:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
- 866:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 867:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 868:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U
- 869:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0
- ARM GAS /tmp/ccBGIhL8.s page 94
- 870:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1
- 871:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
- 872:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2
- 873:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
- 874:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
- 875:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
- 876:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3
- 877:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)
- 878:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)
- 879:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
- 880:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)
- 881:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
- 882:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
- 883:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM
- 884:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4
- 885:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)
- 886:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 887:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 888:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 889:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 890:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
- 891:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 892:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 893:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U
- 894:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0
- 895:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1
- 896:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
- 897:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2
- 898:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
- 899:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
- 900:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
- 901:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3
- 902:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)
- 903:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)
- 904:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
- 905:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)
- 906:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
- 907:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
- 908:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM
- 909:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4
- 910:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0)
- 911:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 912:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 913:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 914:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 915:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 916:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 917:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 918:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 919:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 920:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 921:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /* Exported macro ------------------------------------------------------------*/
- 922:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
- 923:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 924:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 925:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 926:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
- ARM GAS /tmp/ccBGIhL8.s page 95
- 927:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 928:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 929:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 930:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Write a value in TIM register.
- 931:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param __INSTANCE__ TIM Instance
- 932:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param __REG__ Register to be written
- 933:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param __VALUE__ Value to be written in the register
- 934:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 935:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 936:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VAL
- 937:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 938:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 939:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Read a value in TIM register.
- 940:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param __INSTANCE__ TIM Instance
- 941:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param __REG__ Register to be read
- 942:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval Register value
- 943:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 944:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
- 945:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 946:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 947:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 948:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 949:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 950:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested de
- 951:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
- 952:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz)
- 953:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param __CKD__ This parameter can be one of the following values:
- 954:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
- 955:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
- 956:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
- 957:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param __DT__ deadtime duration (in ns)
- 958:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval DTG[0:7]
- 959:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 960:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
- 961:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ?
- 962:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) :
- 963:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__C
- 964:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMC
- 965:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2))
- 966:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__C
- 967:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMC
- 968:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3))
- 969:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__
- 970:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMC
- 971:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4))
- 972:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** 0U)
- 973:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 974:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 975:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief HELPER macro calculating the prescaler value to achieve the required counter clock freq
- 976:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
- 977:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz)
- 978:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param __CNTCLK__ counter clock frequency (in Hz)
- 979:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
- 980:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 981:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
- 982:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U
- 983:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- ARM GAS /tmp/ccBGIhL8.s page 96
- 984:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 985:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief HELPER macro calculating the auto-reload value to achieve the required output signal fr
- 986:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
- 987:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz)
- 988:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param __PSC__ prescaler
- 989:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param __FREQ__ output signal frequency (in Hz)
- 990:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
- 991:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 992:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
- 993:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))
- 994:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 995:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 996:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief HELPER macro calculating the compare value required to achieve the required timer outpu
- 997:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * active/inactive delay.
- 998:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
- 999:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz)
- 1000:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param __PSC__ prescaler
- 1001:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param __DELAY__ timer output compare active/inactive delay (in us)
- 1002:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval Compare value (between Min_Data=0 and Max_Data=65535)
- 1003:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1004:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
- 1005:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
- 1006:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
- 1007:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1008:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1009:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
- 1010:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * (when the timer operates in one pulse mode).
- 1011:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
- 1012:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz)
- 1013:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param __PSC__ prescaler
- 1014:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param __DELAY__ timer output compare active/inactive delay (in us)
- 1015:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param __PULSE__ pulse duration (in us)
- 1016:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
- 1017:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1018:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
- 1019:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
- 1020:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
- 1021:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1022:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1023:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief HELPER macro retrieving the ratio of the input capture prescaler
- 1024:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
- 1025:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param __ICPSC__ This parameter can be one of the following values:
- 1026:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1
- 1027:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV2
- 1028:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV4
- 1029:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV8
- 1030:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval Input capture prescaler ratio (1, 2, 4 or 8)
- 1031:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1032:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
- 1033:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
- 1034:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1035:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1036:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1037:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 1038:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1039:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1040:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /* Exported functions --------------------------------------------------------*/
- ARM GAS /tmp/ccBGIhL8.s page 97
- 1041:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
- 1042:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 1043:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1044:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1045:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
- 1046:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 1047:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1048:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1049:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Enable timer counter.
- 1050:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR1 CEN LL_TIM_EnableCounter
- 1051:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1052:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1053:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1054:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
- 1055:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1056:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_CEN);
- 1057:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1058:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1059:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1060:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Disable timer counter.
- 1061:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR1 CEN LL_TIM_DisableCounter
- 1062:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1063:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1064:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1065:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
- 1066:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1067:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
- 1068:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1069:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1070:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1071:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Indicates whether the timer counter is enabled.
- 1072:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
- 1073:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1074:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval State of bit (1 or 0).
- 1075:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1076:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
- 1077:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1078:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
- 1079:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1080:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1081:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1082:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Enable update event generation.
- 1083:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
- 1084:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1085:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1086:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1087:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
- 1088:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1089:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
- 1090:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1091:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1092:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1093:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Disable update event generation.
- 1094:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
- 1095:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1096:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1097:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- ARM GAS /tmp/ccBGIhL8.s page 98
- 1098:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
- 1099:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1100:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
- 1101:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1102:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1103:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1104:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Indicates whether update event generation is enabled.
- 1105:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
- 1106:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1107:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval Inverted state of bit (0 or 1).
- 1108:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1109:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
- 1110:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1111:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
- 1112:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1113:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1114:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1115:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Set update event source
- 1116:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
- 1117:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * generate an update interrupt or DMA request if enabled:
- 1118:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * - Counter overflow/underflow
- 1119:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * - Setting the UG bit
- 1120:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * - Update generation through the slave mode controller
- 1121:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
- 1122:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * overflow/underflow generates an update interrupt or DMA request if enabled.
- 1123:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR1 URS LL_TIM_SetUpdateSource
- 1124:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1125:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param UpdateSource This parameter can be one of the following values:
- 1126:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
- 1127:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
- 1128:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1129:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1130:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
- 1131:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1132:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
- 1133:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1134:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1135:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1136:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Get actual event update source
- 1137:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR1 URS LL_TIM_GetUpdateSource
- 1138:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1139:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval Returned value can be one of the following values:
- 1140:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
- 1141:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
- 1142:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1143:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
- 1144:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1145:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
- 1146:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1147:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1148:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1149:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Set one pulse mode (one shot v.s. repetitive).
- 1150:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
- 1151:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1152:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param OnePulseMode This parameter can be one of the following values:
- 1153:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
- 1154:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
- ARM GAS /tmp/ccBGIhL8.s page 99
- 1155:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1156:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1157:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
- 1158:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1159:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
- 1160:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1161:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1162:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1163:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Get actual one pulse mode.
- 1164:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
- 1165:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1166:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval Returned value can be one of the following values:
- 1167:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
- 1168:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
- 1169:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1170:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
- 1171:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1172:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
- 1173:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1174:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1175:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1176:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Set the timer counter counting mode.
- 1177:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
- 1178:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * check whether or not the counter mode selection feature is supported
- 1179:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * by a timer instance.
- 1180:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
- 1181:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * requires a timer reset to avoid unexpected direction
- 1182:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * due to DIR bit readonly in center aligned mode.
- 1183:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
- 1184:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CR1 CMS LL_TIM_SetCounterMode
- 1185:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1186:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param CounterMode This parameter can be one of the following values:
- 1187:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_UP
- 1188:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_DOWN
- 1189:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
- 1190:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
- 1191:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
- 1192:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1193:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1194:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
- 1195:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1196:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
- 1197:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1198:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1199:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1200:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Get actual counter mode.
- 1201:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
- 1202:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * check whether or not the counter mode selection feature is supported
- 1203:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * by a timer instance.
- 1204:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
- 1205:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CR1 CMS LL_TIM_GetCounterMode
- 1206:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1207:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval Returned value can be one of the following values:
- 1208:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_UP
- 1209:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_DOWN
- 1210:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
- 1211:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
- ARM GAS /tmp/ccBGIhL8.s page 100
- 1212:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
- 1213:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1214:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
- 1215:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1216:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t counter_mode;
- 1217:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1218:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
- 1219:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1220:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** if (counter_mode == 0U)
- 1221:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1222:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
- 1223:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1224:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1225:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return counter_mode;
- 1226:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1227:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1228:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1229:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Enable auto-reload (ARR) preload.
- 1230:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
- 1231:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1232:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1233:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1234:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
- 1235:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1236:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
- 1237:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1238:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1239:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1240:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Disable auto-reload (ARR) preload.
- 1241:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
- 1242:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1243:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1244:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1245:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
- 1246:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1247:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
- 1248:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1249:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1250:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1251:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Indicates whether auto-reload (ARR) preload is enabled.
- 1252:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
- 1253:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1254:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval State of bit (1 or 0).
- 1255:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1256:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
- 1257:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1258:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
- 1259:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1260:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1261:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1262:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Set the division ratio between the timer clock and the sampling clock used by the dead
- 1263:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * (when supported) and the digital filters.
- 1264:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
- 1265:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * whether or not the clock division feature is supported by the timer
- 1266:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * instance.
- 1267:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR1 CKD LL_TIM_SetClockDivision
- 1268:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- ARM GAS /tmp/ccBGIhL8.s page 101
- 1269:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param ClockDivision This parameter can be one of the following values:
- 1270:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
- 1271:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
- 1272:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
- 1273:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1274:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1275:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
- 1276:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1277:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
- 1278:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1279:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1280:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1281:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Get the actual division ratio between the timer clock and the sampling clock used by t
- 1282:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * generators (when supported) and the digital filters.
- 1283:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
- 1284:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * whether or not the clock division feature is supported by the timer
- 1285:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * instance.
- 1286:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR1 CKD LL_TIM_GetClockDivision
- 1287:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1288:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval Returned value can be one of the following values:
- 1289:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
- 1290:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
- 1291:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
- 1292:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1293:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
- 1294:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1295:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
- 1296:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1297:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1298:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1299:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Set the counter value.
- 1300:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CNT CNT LL_TIM_SetCounter
- 1301:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1302:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF)
- 1303:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1304:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1305:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
- 1306:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1307:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** WRITE_REG(TIMx->CNT, Counter);
- 1308:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1309:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1310:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1311:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Get the counter value.
- 1312:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CNT CNT LL_TIM_GetCounter
- 1313:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1314:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF)
- 1315:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1316:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
- 1317:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1318:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CNT));
- 1319:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1320:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1321:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1322:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Get the current direction of the counter
- 1323:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR1 DIR LL_TIM_GetDirection
- 1324:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1325:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval Returned value can be one of the following values:
- ARM GAS /tmp/ccBGIhL8.s page 102
- 1326:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERDIRECTION_UP
- 1327:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
- 1328:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1329:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
- 1330:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1331:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
- 1332:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1333:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1334:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1335:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Set the prescaler value.
- 1336:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
- 1337:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note The prescaler can be changed on the fly as this control register is buffered. The new
- 1338:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * prescaler ratio is taken into account at the next update event.
- 1339:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
- 1340:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll PSC PSC LL_TIM_SetPrescaler
- 1341:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1342:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Prescaler between Min_Data=0 and Max_Data=65535
- 1343:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1344:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1345:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
- 1346:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1347:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** WRITE_REG(TIMx->PSC, Prescaler);
- 1348:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1349:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1350:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1351:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Get the prescaler value.
- 1352:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll PSC PSC LL_TIM_GetPrescaler
- 1353:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1354:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval Prescaler value between Min_Data=0 and Max_Data=65535
- 1355:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1356:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
- 1357:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1358:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->PSC));
- 1359:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1360:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1361:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1362:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Set the auto-reload value.
- 1363:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note The counter is blocked while the auto-reload value is null.
- 1364:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
- 1365:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll ARR ARR LL_TIM_SetAutoReload
- 1366:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1367:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param AutoReload between Min_Data=0 and Max_Data=65535
- 1368:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1369:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1370:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
- 1371:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1372:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** WRITE_REG(TIMx->ARR, AutoReload);
- 1373:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1374:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1375:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1376:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Get the auto-reload value.
- 1377:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll ARR ARR LL_TIM_GetAutoReload
- 1378:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1379:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval Auto-reload value
- 1380:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1381:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
- 1382:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- ARM GAS /tmp/ccBGIhL8.s page 103
- 1383:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->ARR));
- 1384:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1385:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1386:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1387:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Set the repetition counter value.
- 1388:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
- 1389:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * whether or not a timer instance supports a repetition counter.
- 1390:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
- 1391:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1392:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
- 1393:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1394:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1395:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
- 1396:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1397:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** WRITE_REG(TIMx->RCR, RepetitionCounter);
- 1398:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1399:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1400:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1401:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Get the repetition counter value.
- 1402:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
- 1403:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * whether or not a timer instance supports a repetition counter.
- 1404:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
- 1405:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1406:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval Repetition counter value
- 1407:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1408:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
- 1409:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1410:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->RCR));
- 1411:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1412:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1413:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1414:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 1415:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1416:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1417:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
- 1418:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 1419:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1420:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1421:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
- 1422:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
- 1423:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * they are updated only when a commutation event (COM) occurs.
- 1424:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Only on channels that have a complementary output.
- 1425:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
- 1426:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * whether or not a timer instance is able to generate a commutation event.
- 1427:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
- 1428:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1429:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1430:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1431:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
- 1432:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1433:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
- 1434:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1435:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1436:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1437:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
- 1438:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
- 1439:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * whether or not a timer instance is able to generate a commutation event.
- ARM GAS /tmp/ccBGIhL8.s page 104
- 1440:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
- 1441:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1442:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1443:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1444:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
- 1445:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1446:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
- 1447:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1448:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1449:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1450:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
- 1451:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
- 1452:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * whether or not a timer instance is able to generate a commutation event.
- 1453:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
- 1454:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1455:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param CCUpdateSource This parameter can be one of the following values:
- 1456:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
- 1457:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
- 1458:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1459:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1460:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
- 1461:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1462:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
- 1463:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1464:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1465:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1466:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Set the trigger of the capture/compare DMA request.
- 1467:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
- 1468:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1469:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param DMAReqTrigger This parameter can be one of the following values:
- 1470:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_CC
- 1471:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
- 1472:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1473:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1474:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
- 1475:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1476:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
- 1477:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1478:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1479:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1480:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Get actual trigger of the capture/compare DMA request.
- 1481:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
- 1482:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1483:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval Returned value can be one of the following values:
- 1484:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_CC
- 1485:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
- 1486:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1487:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
- 1488:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1489:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
- 1490:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1491:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1492:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1493:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Set the lock level to freeze the
- 1494:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * configuration of several capture/compare parameters.
- 1495:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- 1496:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * the lock mechanism is supported by a timer instance.
- ARM GAS /tmp/ccBGIhL8.s page 105
- 1497:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
- 1498:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1499:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param LockLevel This parameter can be one of the following values:
- 1500:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_OFF
- 1501:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_1
- 1502:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_2
- 1503:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_3
- 1504:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1505:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1506:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
- 1507:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1508:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
- 1509:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1510:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1511:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1512:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Enable capture/compare channels.
- 1513:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
- 1514:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC1NE LL_TIM_CC_EnableChannel\n
- 1515:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC2E LL_TIM_CC_EnableChannel\n
- 1516:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC2NE LL_TIM_CC_EnableChannel\n
- 1517:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC3E LL_TIM_CC_EnableChannel\n
- 1518:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC3NE LL_TIM_CC_EnableChannel\n
- 1519:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC4E LL_TIM_CC_EnableChannel
- 1520:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1521:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Channels This parameter can be a combination of the following values:
- 1522:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- 1523:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N
- 1524:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- 1525:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N
- 1526:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 1527:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N
- 1528:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- 1529:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1530:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1531:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
- 1532:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1533:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** SET_BIT(TIMx->CCER, Channels);
- 1534:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1535:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1536:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1537:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Disable capture/compare channels.
- 1538:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
- 1539:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC1NE LL_TIM_CC_DisableChannel\n
- 1540:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC2E LL_TIM_CC_DisableChannel\n
- 1541:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC2NE LL_TIM_CC_DisableChannel\n
- 1542:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC3E LL_TIM_CC_DisableChannel\n
- 1543:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC3NE LL_TIM_CC_DisableChannel\n
- 1544:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC4E LL_TIM_CC_DisableChannel
- 1545:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1546:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Channels This parameter can be a combination of the following values:
- 1547:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- 1548:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N
- 1549:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- 1550:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N
- 1551:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 1552:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N
- 1553:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- ARM GAS /tmp/ccBGIhL8.s page 106
- 1554:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1555:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1556:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
- 1557:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1558:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** CLEAR_BIT(TIMx->CCER, Channels);
- 1559:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1560:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1561:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1562:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Indicate whether channel(s) is(are) enabled.
- 1563:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
- 1564:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
- 1565:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
- 1566:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
- 1567:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
- 1568:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
- 1569:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC4E LL_TIM_CC_IsEnabledChannel
- 1570:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1571:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Channels This parameter can be a combination of the following values:
- 1572:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- 1573:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N
- 1574:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- 1575:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N
- 1576:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 1577:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N
- 1578:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- 1579:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval State of bit (1 or 0).
- 1580:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1581:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
- 1582:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1583:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
- 1584:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1585:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1586:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1587:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 1588:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1589:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1590:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
- 1591:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 1592:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1593:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1594:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Configure an output channel.
- 1595:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
- 1596:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
- 1597:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
- 1598:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
- 1599:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC1P LL_TIM_OC_ConfigOutput\n
- 1600:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC2P LL_TIM_OC_ConfigOutput\n
- 1601:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC3P LL_TIM_OC_ConfigOutput\n
- 1602:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC4P LL_TIM_OC_ConfigOutput\n
- 1603:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
- 1604:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
- 1605:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
- 1606:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CR2 OIS4 LL_TIM_OC_ConfigOutput
- 1607:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1608:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Channel This parameter can be one of the following values:
- 1609:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- 1610:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- ARM GAS /tmp/ccBGIhL8.s page 107
- 1611:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 1612:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- 1613:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Configuration This parameter must be a combination of all the following values:
- 1614:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
- 1615:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
- 1616:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1617:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1618:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configura
- 1619:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1620:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 1621:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
- 1622:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
- 1623:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
- 1624:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
- 1625:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
- 1626:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
- 1627:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1628:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1629:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1630:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Define the behavior of the output reference signal OCxREF from which
- 1631:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * OCx and OCxN (when relevant) are derived.
- 1632:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
- 1633:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR1 OC2M LL_TIM_OC_SetMode\n
- 1634:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 OC3M LL_TIM_OC_SetMode\n
- 1635:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 OC4M LL_TIM_OC_SetMode
- 1636:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1637:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Channel This parameter can be one of the following values:
- 1638:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- 1639:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- 1640:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 1641:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- 1642:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Mode This parameter can be one of the following values:
- 1643:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FROZEN
- 1644:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ACTIVE
- 1645:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_INACTIVE
- 1646:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_TOGGLE
- 1647:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
- 1648:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
- 1649:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM1
- 1650:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM2
- 1651:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1652:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1653:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
- 1654:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1655:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 1656:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
- 1657:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT
- 1658:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1659:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1660:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1661:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Get the output compare mode of an output channel.
- 1662:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
- 1663:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR1 OC2M LL_TIM_OC_GetMode\n
- 1664:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 OC3M LL_TIM_OC_GetMode\n
- 1665:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 OC4M LL_TIM_OC_GetMode
- 1666:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1667:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Channel This parameter can be one of the following values:
- ARM GAS /tmp/ccBGIhL8.s page 108
- 1668:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- 1669:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- 1670:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 1671:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- 1672:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval Returned value can be one of the following values:
- 1673:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FROZEN
- 1674:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ACTIVE
- 1675:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_INACTIVE
- 1676:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_TOGGLE
- 1677:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
- 1678:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
- 1679:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM1
- 1680:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM2
- 1681:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1682:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
- 1683:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1684:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 1685:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC
- 1686:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT
- 1687:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1688:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1689:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1690:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Set the polarity of an output channel.
- 1691:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
- 1692:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC1NP LL_TIM_OC_SetPolarity\n
- 1693:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC2P LL_TIM_OC_SetPolarity\n
- 1694:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC2NP LL_TIM_OC_SetPolarity\n
- 1695:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC3P LL_TIM_OC_SetPolarity\n
- 1696:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC3NP LL_TIM_OC_SetPolarity\n
- 1697:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC4P LL_TIM_OC_SetPolarity
- 1698:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1699:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Channel This parameter can be one of the following values:
- 1700:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- 1701:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N
- 1702:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- 1703:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N
- 1704:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 1705:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N
- 1706:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- 1707:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Polarity This parameter can be one of the following values:
- 1708:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_HIGH
- 1709:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_LOW
- 1710:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1711:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1712:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
- 1713:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1714:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 1715:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[i
- 1716:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1717:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1718:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1719:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Get the polarity of an output channel.
- 1720:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
- 1721:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC1NP LL_TIM_OC_GetPolarity\n
- 1722:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC2P LL_TIM_OC_GetPolarity\n
- 1723:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC2NP LL_TIM_OC_GetPolarity\n
- 1724:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC3P LL_TIM_OC_GetPolarity\n
- ARM GAS /tmp/ccBGIhL8.s page 109
- 1725:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC3NP LL_TIM_OC_GetPolarity\n
- 1726:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC4P LL_TIM_OC_GetPolarity
- 1727:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1728:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Channel This parameter can be one of the following values:
- 1729:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- 1730:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N
- 1731:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- 1732:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N
- 1733:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 1734:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N
- 1735:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- 1736:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval Returned value can be one of the following values:
- 1737:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_HIGH
- 1738:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_LOW
- 1739:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1740:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
- 1741:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1742:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 1743:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChan
- 1744:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1745:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1746:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1747:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Set the IDLE state of an output channel
- 1748:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note This function is significant only for the timer instances
- 1749:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
- 1750:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * can be used to check whether or not a timer instance provides
- 1751:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * a break input.
- 1752:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
- 1753:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CR2 OIS1N LL_TIM_OC_SetIdleState\n
- 1754:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CR2 OIS2 LL_TIM_OC_SetIdleState\n
- 1755:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_SetIdleState\n
- 1756:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CR2 OIS3 LL_TIM_OC_SetIdleState\n
- 1757:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CR2 OIS3N LL_TIM_OC_SetIdleState\n
- 1758:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CR2 OIS4 LL_TIM_OC_SetIdleState
- 1759:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1760:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Channel This parameter can be one of the following values:
- 1761:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- 1762:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N
- 1763:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- 1764:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N
- 1765:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 1766:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N
- 1767:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- 1768:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param IdleState This parameter can be one of the following values:
- 1769:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_LOW
- 1770:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_HIGH
- 1771:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1772:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1773:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState
- 1774:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1775:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 1776:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iC
- 1777:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1778:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1779:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1780:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Get the IDLE state of an output channel
- 1781:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
- ARM GAS /tmp/ccBGIhL8.s page 110
- 1782:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CR2 OIS1N LL_TIM_OC_GetIdleState\n
- 1783:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CR2 OIS2 LL_TIM_OC_GetIdleState\n
- 1784:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_GetIdleState\n
- 1785:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CR2 OIS3 LL_TIM_OC_GetIdleState\n
- 1786:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CR2 OIS3N LL_TIM_OC_GetIdleState\n
- 1787:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CR2 OIS4 LL_TIM_OC_GetIdleState
- 1788:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1789:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Channel This parameter can be one of the following values:
- 1790:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- 1791:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N
- 1792:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- 1793:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N
- 1794:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 1795:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N
- 1796:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- 1797:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval Returned value can be one of the following values:
- 1798:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_LOW
- 1799:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_HIGH
- 1800:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1801:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
- 1802:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1803:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 1804:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChanne
- 1805:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1806:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1807:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1808:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Enable fast mode for the output channel.
- 1809:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
- 1810:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
- 1811:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
- 1812:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
- 1813:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 OC4FE LL_TIM_OC_EnableFast
- 1814:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1815:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Channel This parameter can be one of the following values:
- 1816:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- 1817:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- 1818:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 1819:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- 1820:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1821:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1822:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
- 1823:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1824:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 1825:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
- 1826:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
- 1827:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1828:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1829:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1830:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1831:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Disable fast mode for the output channel.
- 1832:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
- 1833:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
- 1834:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
- 1835:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 OC4FE LL_TIM_OC_DisableFast
- 1836:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1837:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Channel This parameter can be one of the following values:
- 1838:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- ARM GAS /tmp/ccBGIhL8.s page 111
- 1839:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- 1840:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 1841:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- 1842:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1843:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1844:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
- 1845:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 153 .loc 4 1845 1 is_stmt 1 view -0
- 154 .cfi_startproc
- 155 @ args = 0, pretend = 0, frame = 0
- 156 @ frame_needed = 0, uses_anonymous_args = 0
- 157 @ link register save eliminated.
- 158 .loc 4 1845 1 is_stmt 0 view .LVU32
- 159 0000 10B4 push {r4}
- 160 .LCFI3:
- 161 .cfi_def_cfa_offset 4
- 162 .cfi_offset 4, -4
- 1846:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 163 .loc 4 1846 3 is_stmt 1 view .LVU33
- 164 0002 4029 cmp r1, #64
- 165 0004 10D0 beq .L10
- 166 0006 07D8 bhi .L9
- 167 0008 0429 cmp r1, #4
- 168 000a 0FD0 beq .L11
- 169 000c 1029 cmp r1, #16
- 170 000e 0FD0 beq .L12
- 171 0010 0129 cmp r1, #1
- 172 0012 0FD1 bne .L13
- 1845:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 173 .loc 4 1845 1 is_stmt 0 view .LVU34
- 174 0014 0022 movs r2, #0
- 175 0016 10E0 b .L8
- 176 .L9:
- 177 0018 B1F5807F cmp r1, #256
- 178 001c 0CD0 beq .L14
- 179 001e B1F5806F cmp r1, #1024
- 180 0022 19D1 bne .L15
- 181 0024 0522 movs r2, #5
- 182 0026 08E0 b .L8
- 183 .L10:
- 1845:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 184 .loc 4 1845 1 view .LVU35
- 185 0028 0322 movs r2, #3
- 186 002a 06E0 b .L8
- 187 .L11:
- 188 002c 0122 movs r2, #1
- 189 002e 04E0 b .L8
- 190 .L12:
- 191 0030 0222 movs r2, #2
- 192 0032 02E0 b .L8
- 193 .L13:
- 194 0034 0622 movs r2, #6
- 195 0036 00E0 b .L8
- 196 .L14:
- 1845:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 197 .loc 4 1845 1 view .LVU36
- 198 0038 0422 movs r2, #4
- ARM GAS /tmp/ccBGIhL8.s page 112
- 199 .L8:
- 200 .LVL14:
- 1847:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
- 201 .loc 4 1847 3 is_stmt 1 view .LVU37
- 202 .loc 4 1847 65 is_stmt 0 view .LVU38
- 203 003a 1830 adds r0, r0, #24
- 204 .LVL15:
- 205 .loc 4 1847 97 view .LVU39
- 206 003c 074B ldr r3, .L17
- 207 003e 995C ldrb r1, [r3, r2] @ zero_extendqisi2
- 208 .LVL16:
- 1848:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
- 209 .loc 4 1848 3 is_stmt 1 view .LVU40
- 210 0040 4358 ldr r3, [r0, r1]
- 211 0042 074C ldr r4, .L17+4
- 212 0044 14F802C0 ldrb ip, [r4, r2] @ zero_extendqisi2
- 213 0048 0422 movs r2, #4
- 214 .LVL17:
- 215 .loc 4 1848 3 is_stmt 0 view .LVU41
- 216 004a 02FA0CF2 lsl r2, r2, ip
- 217 004e 23EA0203 bic r3, r3, r2
- 218 0052 4350 str r3, [r0, r1]
- 1849:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1850:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 219 .loc 4 1850 1 view .LVU42
- 220 0054 10BC pop {r4}
- 221 .LCFI4:
- 222 .cfi_remember_state
- 223 .cfi_restore 4
- 224 .cfi_def_cfa_offset 0
- 225 0056 7047 bx lr
- 226 .LVL18:
- 227 .L15:
- 228 .LCFI5:
- 229 .cfi_restore_state
- 1845:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 230 .loc 4 1845 1 view .LVU43
- 231 0058 0622 movs r2, #6
- 232 005a EEE7 b .L8
- 233 .L18:
- 234 .align 2
- 235 .L17:
- 236 005c 00000000 .word OFFSET_TAB_CCMRx
- 237 0060 00000000 .word SHIFT_TAB_OCxx
- 238 .cfi_endproc
- 239 .LFE457:
- 241 .section .text.MX_DMA_Init,"ax",%progbits
- 242 .align 1
- 243 .syntax unified
- 244 .thumb
- 245 .thumb_func
- 247 MX_DMA_Init:
- 248 .LFB659:
- 1:Core/Src/main.c **** /* USER CODE BEGIN Header */
- 2:Core/Src/main.c **** /**
- 3:Core/Src/main.c **** ******************************************************************************
- 4:Core/Src/main.c **** * @file : main.c
- ARM GAS /tmp/ccBGIhL8.s page 113
- 5:Core/Src/main.c **** * @brief : Main program body
- 6:Core/Src/main.c **** ******************************************************************************
- 7:Core/Src/main.c **** * @attention
- 8:Core/Src/main.c **** *
- 9:Core/Src/main.c **** * Copyright (c) 2024 STMicroelectronics.
- 10:Core/Src/main.c **** * All rights reserved.
- 11:Core/Src/main.c **** *
- 12:Core/Src/main.c **** * This software is licensed under terms that can be found in the LICENSE file
- 13:Core/Src/main.c **** * in the root directory of this software component.
- 14:Core/Src/main.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
- 15:Core/Src/main.c **** *
- 16:Core/Src/main.c **** ******************************************************************************
- 17:Core/Src/main.c **** */
- 18:Core/Src/main.c **** /* USER CODE END Header */
- 19:Core/Src/main.c **** /* Includes ------------------------------------------------------------------*/
- 20:Core/Src/main.c **** #include "main.h"
- 21:Core/Src/main.c **** #include "usb_device.h"
- 22:Core/Src/main.c ****
- 23:Core/Src/main.c **** /* Private includes ----------------------------------------------------------*/
- 24:Core/Src/main.c **** /* USER CODE BEGIN Includes */
- 25:Core/Src/main.c **** #include "RFDAproto.h"
- 26:Core/Src/main.c **** /* USER CODE END Includes */
- 27:Core/Src/main.c ****
- 28:Core/Src/main.c **** /* Private typedef -----------------------------------------------------------*/
- 29:Core/Src/main.c **** /* USER CODE BEGIN PTD */
- 30:Core/Src/main.c ****
- 31:Core/Src/main.c **** /* USER CODE END PTD */
- 32:Core/Src/main.c ****
- 33:Core/Src/main.c **** /* Private define ------------------------------------------------------------*/
- 34:Core/Src/main.c **** /* USER CODE BEGIN PD */
- 35:Core/Src/main.c ****
- 36:Core/Src/main.c **** /* USER CODE END PD */
- 37:Core/Src/main.c ****
- 38:Core/Src/main.c **** /* Private macro -------------------------------------------------------------*/
- 39:Core/Src/main.c **** /* USER CODE BEGIN PM */
- 40:Core/Src/main.c ****
- 41:Core/Src/main.c **** /* USER CODE END PM */
- 42:Core/Src/main.c ****
- 43:Core/Src/main.c **** /* Private variables ---------------------------------------------------------*/
- 44:Core/Src/main.c ****
- 45:Core/Src/main.c **** /* USER CODE BEGIN PV */
- 46:Core/Src/main.c ****
- 47:Core/Src/main.c **** /* USER CODE END PV */
- 48:Core/Src/main.c ****
- 49:Core/Src/main.c **** /* Private function prototypes -----------------------------------------------*/
- 50:Core/Src/main.c **** void SystemClock_Config(void);
- 51:Core/Src/main.c **** static void MX_GPIO_Init(void);
- 52:Core/Src/main.c **** static void MX_DMA_Init(void);
- 53:Core/Src/main.c **** static void MX_ADC1_Init(void);
- 54:Core/Src/main.c **** static void MX_TIM1_Init(void);
- 55:Core/Src/main.c **** /* USER CODE BEGIN PFP */
- 56:Core/Src/main.c ****
- 57:Core/Src/main.c **** /* USER CODE END PFP */
- 58:Core/Src/main.c ****
- 59:Core/Src/main.c **** /* Private user code ---------------------------------------------------------*/
- 60:Core/Src/main.c **** /* USER CODE BEGIN 0 */
- 61:Core/Src/main.c ****
- ARM GAS /tmp/ccBGIhL8.s page 114
- 62:Core/Src/main.c **** /* USER CODE END 0 */
- 63:Core/Src/main.c ****
- 64:Core/Src/main.c **** /**
- 65:Core/Src/main.c **** * @brief The application entry point.
- 66:Core/Src/main.c **** * @retval int
- 67:Core/Src/main.c **** */
- 68:Core/Src/main.c **** int main(void)
- 69:Core/Src/main.c **** {
- 70:Core/Src/main.c **** /* USER CODE BEGIN 1 */
- 71:Core/Src/main.c ****
- 72:Core/Src/main.c **** /* USER CODE END 1 */
- 73:Core/Src/main.c ****
- 74:Core/Src/main.c **** /* MCU Configuration--------------------------------------------------------*/
- 75:Core/Src/main.c ****
- 76:Core/Src/main.c **** /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
- 77:Core/Src/main.c **** HAL_Init();
- 78:Core/Src/main.c ****
- 79:Core/Src/main.c **** /* USER CODE BEGIN Init */
- 80:Core/Src/main.c ****
- 81:Core/Src/main.c **** /* USER CODE END Init */
- 82:Core/Src/main.c ****
- 83:Core/Src/main.c **** /* Configure the system clock */
- 84:Core/Src/main.c **** SystemClock_Config();
- 85:Core/Src/main.c ****
- 86:Core/Src/main.c **** /* USER CODE BEGIN SysInit */
- 87:Core/Src/main.c ****
- 88:Core/Src/main.c **** /* USER CODE END SysInit */
- 89:Core/Src/main.c ****
- 90:Core/Src/main.c **** /* Initialize all configured peripherals */
- 91:Core/Src/main.c **** MX_GPIO_Init();
- 92:Core/Src/main.c **** MX_DMA_Init();
- 93:Core/Src/main.c **** MX_ADC1_Init();
- 94:Core/Src/main.c **** MX_USB_DEVICE_Init();
- 95:Core/Src/main.c **** MX_TIM1_Init();
- 96:Core/Src/main.c **** /* USER CODE BEGIN 2 */
- 97:Core/Src/main.c **** PWM_init();
- 98:Core/Src/main.c **** LL_mDelay(500);
- 99:Core/Src/main.c **** /* USER CODE END 2 */
- 100:Core/Src/main.c ****
- 101:Core/Src/main.c **** /* Infinite loop */
- 102:Core/Src/main.c **** /* USER CODE BEGIN WHILE */
- 103:Core/Src/main.c **** while (1)
- 104:Core/Src/main.c **** {
- 105:Core/Src/main.c **** /* USER CODE END WHILE */
- 106:Core/Src/main.c ****
- 107:Core/Src/main.c **** /* USER CODE BEGIN 3 */
- 108:Core/Src/main.c **** LL_mDelay(500);
- 109:Core/Src/main.c **** }
- 110:Core/Src/main.c **** /* USER CODE END 3 */
- 111:Core/Src/main.c **** }
- 112:Core/Src/main.c ****
- 113:Core/Src/main.c **** /**
- 114:Core/Src/main.c **** * @brief System Clock Configuration
- 115:Core/Src/main.c **** * @retval None
- 116:Core/Src/main.c **** */
- 117:Core/Src/main.c **** void SystemClock_Config(void)
- 118:Core/Src/main.c **** {
- ARM GAS /tmp/ccBGIhL8.s page 115
- 119:Core/Src/main.c **** LL_FLASH_SetLatency(LL_FLASH_LATENCY_1);
- 120:Core/Src/main.c **** while(LL_FLASH_GetLatency()!= LL_FLASH_LATENCY_1)
- 121:Core/Src/main.c **** {
- 122:Core/Src/main.c **** }
- 123:Core/Src/main.c **** LL_RCC_HSE_Enable();
- 124:Core/Src/main.c ****
- 125:Core/Src/main.c **** /* Wait till HSE is ready */
- 126:Core/Src/main.c **** while(LL_RCC_HSE_IsReady() != 1)
- 127:Core/Src/main.c **** {
- 128:Core/Src/main.c ****
- 129:Core/Src/main.c **** }
- 130:Core/Src/main.c **** LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE_DIV_1, LL_RCC_PLL_MUL_6);
- 131:Core/Src/main.c **** LL_RCC_PLL_Enable();
- 132:Core/Src/main.c ****
- 133:Core/Src/main.c **** /* Wait till PLL is ready */
- 134:Core/Src/main.c **** while(LL_RCC_PLL_IsReady() != 1)
- 135:Core/Src/main.c **** {
- 136:Core/Src/main.c ****
- 137:Core/Src/main.c **** }
- 138:Core/Src/main.c **** LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
- 139:Core/Src/main.c **** LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2);
- 140:Core/Src/main.c **** LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
- 141:Core/Src/main.c **** LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
- 142:Core/Src/main.c ****
- 143:Core/Src/main.c **** /* Wait till System clock is ready */
- 144:Core/Src/main.c **** while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
- 145:Core/Src/main.c **** {
- 146:Core/Src/main.c ****
- 147:Core/Src/main.c **** }
- 148:Core/Src/main.c **** LL_SetSystemCoreClock(48000000);
- 149:Core/Src/main.c ****
- 150:Core/Src/main.c **** /* Update the time base */
- 151:Core/Src/main.c **** if (HAL_InitTick (TICK_INT_PRIORITY) != HAL_OK)
- 152:Core/Src/main.c **** {
- 153:Core/Src/main.c **** Error_Handler();
- 154:Core/Src/main.c **** }
- 155:Core/Src/main.c **** LL_RCC_SetADCClockSource(LL_RCC_ADC_CLKSRC_PCLK2_DIV_4);
- 156:Core/Src/main.c **** LL_RCC_SetUSBClockSource(LL_RCC_USB_CLKSOURCE_PLL);
- 157:Core/Src/main.c **** }
- 158:Core/Src/main.c ****
- 159:Core/Src/main.c **** /**
- 160:Core/Src/main.c **** * @brief ADC1 Initialization Function
- 161:Core/Src/main.c **** * @param None
- 162:Core/Src/main.c **** * @retval None
- 163:Core/Src/main.c **** */
- 164:Core/Src/main.c **** static void MX_ADC1_Init(void)
- 165:Core/Src/main.c **** {
- 166:Core/Src/main.c ****
- 167:Core/Src/main.c **** /* USER CODE BEGIN ADC1_Init 0 */
- 168:Core/Src/main.c ****
- 169:Core/Src/main.c **** /* USER CODE END ADC1_Init 0 */
- 170:Core/Src/main.c ****
- 171:Core/Src/main.c **** LL_ADC_InitTypeDef ADC_InitStruct = {0};
- 172:Core/Src/main.c **** LL_ADC_CommonInitTypeDef ADC_CommonInitStruct = {0};
- 173:Core/Src/main.c **** LL_ADC_REG_InitTypeDef ADC_REG_InitStruct = {0};
- 174:Core/Src/main.c **** LL_ADC_INJ_InitTypeDef ADC_INJ_InitStruct = {0};
- 175:Core/Src/main.c ****
- ARM GAS /tmp/ccBGIhL8.s page 116
- 176:Core/Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
- 177:Core/Src/main.c ****
- 178:Core/Src/main.c **** /* Peripheral clock enable */
- 179:Core/Src/main.c **** LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_ADC1);
- 180:Core/Src/main.c ****
- 181:Core/Src/main.c **** LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_GPIOA);
- 182:Core/Src/main.c **** /**ADC1 GPIO Configuration
- 183:Core/Src/main.c **** PA3 ------> ADC1_IN3
- 184:Core/Src/main.c **** PA4 ------> ADC1_IN4
- 185:Core/Src/main.c **** */
- 186:Core/Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_3|LL_GPIO_PIN_4;
- 187:Core/Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG;
- 188:Core/Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- 189:Core/Src/main.c ****
- 190:Core/Src/main.c **** /* USER CODE BEGIN ADC1_Init 1 */
- 191:Core/Src/main.c ****
- 192:Core/Src/main.c **** /* USER CODE END ADC1_Init 1 */
- 193:Core/Src/main.c ****
- 194:Core/Src/main.c **** /** Common config
- 195:Core/Src/main.c **** */
- 196:Core/Src/main.c **** ADC_InitStruct.DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
- 197:Core/Src/main.c **** ADC_InitStruct.SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE;
- 198:Core/Src/main.c **** LL_ADC_Init(ADC1, &ADC_InitStruct);
- 199:Core/Src/main.c **** ADC_CommonInitStruct.Multimode = LL_ADC_MULTI_INDEPENDENT;
- 200:Core/Src/main.c **** LL_ADC_CommonInit(__LL_ADC_COMMON_INSTANCE(ADC1), &ADC_CommonInitStruct);
- 201:Core/Src/main.c **** ADC_REG_InitStruct.TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
- 202:Core/Src/main.c **** ADC_REG_InitStruct.SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
- 203:Core/Src/main.c **** ADC_REG_InitStruct.SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
- 204:Core/Src/main.c **** ADC_REG_InitStruct.ContinuousMode = LL_ADC_REG_CONV_SINGLE;
- 205:Core/Src/main.c **** ADC_REG_InitStruct.DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
- 206:Core/Src/main.c **** LL_ADC_REG_Init(ADC1, &ADC_REG_InitStruct);
- 207:Core/Src/main.c **** ADC_INJ_InitStruct.TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
- 208:Core/Src/main.c **** ADC_INJ_InitStruct.SequencerLength = LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS;
- 209:Core/Src/main.c **** ADC_INJ_InitStruct.SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
- 210:Core/Src/main.c **** ADC_INJ_InitStruct.TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
- 211:Core/Src/main.c **** LL_ADC_INJ_Init(ADC1, &ADC_INJ_InitStruct);
- 212:Core/Src/main.c ****
- 213:Core/Src/main.c **** /** Configure Injected Channel
- 214:Core/Src/main.c **** */
- 215:Core/Src/main.c **** LL_ADC_INJ_SetSequencerRanks(ADC1, LL_ADC_INJ_RANK_1, LL_ADC_CHANNEL_3);
- 216:Core/Src/main.c **** LL_ADC_SetChannelSamplingTime(ADC1, LL_ADC_CHANNEL_3, LL_ADC_SAMPLINGTIME_1CYCLE_5);
- 217:Core/Src/main.c **** LL_ADC_INJ_SetOffset(ADC1, LL_ADC_INJ_RANK_1, 0);
- 218:Core/Src/main.c ****
- 219:Core/Src/main.c **** /** Configure Injected Channel
- 220:Core/Src/main.c **** */
- 221:Core/Src/main.c **** LL_ADC_INJ_SetSequencerRanks(ADC1, LL_ADC_INJ_RANK_2, LL_ADC_CHANNEL_4);
- 222:Core/Src/main.c **** LL_ADC_SetChannelSamplingTime(ADC1, LL_ADC_CHANNEL_4, LL_ADC_SAMPLINGTIME_1CYCLE_5);
- 223:Core/Src/main.c **** LL_ADC_INJ_SetOffset(ADC1, LL_ADC_INJ_RANK_2, 0);
- 224:Core/Src/main.c **** /* USER CODE BEGIN ADC1_Init 2 */
- 225:Core/Src/main.c ****
- 226:Core/Src/main.c **** /* USER CODE END ADC1_Init 2 */
- 227:Core/Src/main.c ****
- 228:Core/Src/main.c **** }
- 229:Core/Src/main.c ****
- 230:Core/Src/main.c **** /**
- 231:Core/Src/main.c **** * @brief TIM1 Initialization Function
- 232:Core/Src/main.c **** * @param None
- ARM GAS /tmp/ccBGIhL8.s page 117
- 233:Core/Src/main.c **** * @retval None
- 234:Core/Src/main.c **** */
- 235:Core/Src/main.c **** static void MX_TIM1_Init(void)
- 236:Core/Src/main.c **** {
- 237:Core/Src/main.c ****
- 238:Core/Src/main.c **** /* USER CODE BEGIN TIM1_Init 0 */
- 239:Core/Src/main.c ****
- 240:Core/Src/main.c **** /* USER CODE END TIM1_Init 0 */
- 241:Core/Src/main.c ****
- 242:Core/Src/main.c **** LL_TIM_InitTypeDef TIM_InitStruct = {0};
- 243:Core/Src/main.c **** LL_TIM_OC_InitTypeDef TIM_OC_InitStruct = {0};
- 244:Core/Src/main.c **** LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct = {0};
- 245:Core/Src/main.c ****
- 246:Core/Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
- 247:Core/Src/main.c ****
- 248:Core/Src/main.c **** /* Peripheral clock enable */
- 249:Core/Src/main.c **** LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1);
- 250:Core/Src/main.c ****
- 251:Core/Src/main.c **** /* TIM1 DMA Init */
- 252:Core/Src/main.c ****
- 253:Core/Src/main.c **** /* TIM1_UP Init */
- 254:Core/Src/main.c **** LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_CHANNEL_5, LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
- 255:Core/Src/main.c ****
- 256:Core/Src/main.c **** LL_DMA_SetChannelPriorityLevel(DMA1, LL_DMA_CHANNEL_5, LL_DMA_PRIORITY_LOW);
- 257:Core/Src/main.c ****
- 258:Core/Src/main.c **** LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_5, LL_DMA_MODE_NORMAL);
- 259:Core/Src/main.c ****
- 260:Core/Src/main.c **** LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_CHANNEL_5, LL_DMA_PERIPH_NOINCREMENT);
- 261:Core/Src/main.c ****
- 262:Core/Src/main.c **** LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_CHANNEL_5, LL_DMA_MEMORY_INCREMENT);
- 263:Core/Src/main.c ****
- 264:Core/Src/main.c **** LL_DMA_SetPeriphSize(DMA1, LL_DMA_CHANNEL_5, LL_DMA_PDATAALIGN_WORD);
- 265:Core/Src/main.c ****
- 266:Core/Src/main.c **** LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_5, LL_DMA_MDATAALIGN_WORD);
- 267:Core/Src/main.c ****
- 268:Core/Src/main.c **** /* USER CODE BEGIN TIM1_Init 1 */
- 269:Core/Src/main.c ****
- 270:Core/Src/main.c **** /* USER CODE END TIM1_Init 1 */
- 271:Core/Src/main.c **** TIM_InitStruct.Prescaler = 4800;
- 272:Core/Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_CENTER_DOWN;
- 273:Core/Src/main.c **** TIM_InitStruct.Autoreload = 100;
- 274:Core/Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
- 275:Core/Src/main.c **** TIM_InitStruct.RepetitionCounter = 1;
- 276:Core/Src/main.c **** LL_TIM_Init(TIM1, &TIM_InitStruct);
- 277:Core/Src/main.c **** LL_TIM_DisableARRPreload(TIM1);
- 278:Core/Src/main.c **** LL_TIM_SetClockSource(TIM1, LL_TIM_CLOCKSOURCE_INTERNAL);
- 279:Core/Src/main.c **** TIM_OC_InitStruct.OCMode = LL_TIM_OCMODE_TOGGLE;
- 280:Core/Src/main.c **** TIM_OC_InitStruct.OCState = LL_TIM_OCSTATE_DISABLE;
- 281:Core/Src/main.c **** TIM_OC_InitStruct.OCNState = LL_TIM_OCSTATE_DISABLE;
- 282:Core/Src/main.c **** TIM_OC_InitStruct.CompareValue = 70;
- 283:Core/Src/main.c **** TIM_OC_InitStruct.OCPolarity = LL_TIM_OCPOLARITY_HIGH;
- 284:Core/Src/main.c **** TIM_OC_InitStruct.OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
- 285:Core/Src/main.c **** TIM_OC_InitStruct.OCIdleState = LL_TIM_OCIDLESTATE_LOW;
- 286:Core/Src/main.c **** TIM_OC_InitStruct.OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
- 287:Core/Src/main.c **** LL_TIM_OC_Init(TIM1, LL_TIM_CHANNEL_CH1, &TIM_OC_InitStruct);
- 288:Core/Src/main.c **** LL_TIM_OC_DisableFast(TIM1, LL_TIM_CHANNEL_CH1);
- 289:Core/Src/main.c **** LL_TIM_SetTriggerOutput(TIM1, LL_TIM_TRGO_RESET);
- ARM GAS /tmp/ccBGIhL8.s page 118
- 290:Core/Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM1);
- 291:Core/Src/main.c **** TIM_BDTRInitStruct.OSSRState = LL_TIM_OSSR_DISABLE;
- 292:Core/Src/main.c **** TIM_BDTRInitStruct.OSSIState = LL_TIM_OSSI_DISABLE;
- 293:Core/Src/main.c **** TIM_BDTRInitStruct.LockLevel = LL_TIM_LOCKLEVEL_OFF;
- 294:Core/Src/main.c **** TIM_BDTRInitStruct.DeadTime = 0;
- 295:Core/Src/main.c **** TIM_BDTRInitStruct.BreakState = LL_TIM_BREAK_DISABLE;
- 296:Core/Src/main.c **** TIM_BDTRInitStruct.BreakPolarity = LL_TIM_BREAK_POLARITY_HIGH;
- 297:Core/Src/main.c **** TIM_BDTRInitStruct.AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
- 298:Core/Src/main.c **** LL_TIM_BDTR_Init(TIM1, &TIM_BDTRInitStruct);
- 299:Core/Src/main.c **** /* USER CODE BEGIN TIM1_Init 2 */
- 300:Core/Src/main.c ****
- 301:Core/Src/main.c **** /* USER CODE END TIM1_Init 2 */
- 302:Core/Src/main.c **** LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_GPIOA);
- 303:Core/Src/main.c **** /**TIM1 GPIO Configuration
- 304:Core/Src/main.c **** PA8 ------> TIM1_CH1
- 305:Core/Src/main.c **** */
- 306:Core/Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_8;
- 307:Core/Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
- 308:Core/Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
- 309:Core/Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
- 310:Core/Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- 311:Core/Src/main.c ****
- 312:Core/Src/main.c **** }
- 313:Core/Src/main.c ****
- 314:Core/Src/main.c **** /**
- 315:Core/Src/main.c **** * Enable DMA controller clock
- 316:Core/Src/main.c **** */
- 317:Core/Src/main.c **** static void MX_DMA_Init(void)
- 318:Core/Src/main.c **** {
- 249 .loc 1 318 1 is_stmt 1 view -0
- 250 .cfi_startproc
- 251 @ args = 0, pretend = 0, frame = 8
- 252 @ frame_needed = 0, uses_anonymous_args = 0
- 253 0000 00B5 push {lr}
- 254 .LCFI6:
- 255 .cfi_def_cfa_offset 4
- 256 .cfi_offset 14, -4
- 257 0002 83B0 sub sp, sp, #12
- 258 .LCFI7:
- 259 .cfi_def_cfa_offset 16
- 319:Core/Src/main.c ****
- 320:Core/Src/main.c **** /* Init with LL driver */
- 321:Core/Src/main.c **** /* DMA controller clock enable */
- 322:Core/Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1);
- 260 .loc 1 322 3 view .LVU45
- 261 .LVL19:
- 262 .LBB96:
- 263 .LBI96:
- 264 .file 5 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h"
- 1:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /**
- 2:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** ******************************************************************************
- 3:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @file stm32f1xx_ll_bus.h
- 4:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @author MCD Application Team
- 5:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @brief Header file of BUS LL module.
- 6:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 7:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** @verbatim
- 8:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** ##### RCC Limitations #####
- ARM GAS /tmp/ccBGIhL8.s page 119
- 9:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** ==============================================================================
- 10:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** [..]
- 11:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** A delay between an RCC peripheral clock enable and the effective peripheral
- 12:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** enabling should be taken into account in order to manage the peripheral read/write
- 13:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** from/to registers.
- 14:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** (+) This delay depends on the peripheral mapping.
- 15:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** (++) AHB & APB peripherals, 1 dummy read is necessary
- 16:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 17:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** [..]
- 18:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** Workarounds:
- 19:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
- 20:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
- 21:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 22:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** @endverbatim
- 23:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** ******************************************************************************
- 24:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @attention
- 25:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** *
- 26:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * Copyright (c) 2016 STMicroelectronics.
- 27:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * All rights reserved.
- 28:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** *
- 29:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * This software is licensed under terms that can be found in the LICENSE file in
- 30:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * the root directory of this software component.
- 31:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * If no LICENSE file comes with this software, it is provided AS-IS.
- 32:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** ******************************************************************************
- 33:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** */
- 34:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 35:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/
- 36:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #ifndef __STM32F1xx_LL_BUS_H
- 37:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define __STM32F1xx_LL_BUS_H
- 38:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 39:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #ifdef __cplusplus
- 40:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** extern "C" {
- 41:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif
- 42:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 43:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/
- 44:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #include "stm32f1xx.h"
- 45:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 46:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /** @addtogroup STM32F1xx_LL_Driver
- 47:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @{
- 48:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** */
- 49:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 50:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(RCC)
- 51:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 52:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /** @defgroup BUS_LL BUS
- 53:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @{
- 54:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** */
- 55:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 56:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/
- 57:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/
- 58:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 59:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/
- 60:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(RCC_AHBRSTR_OTGFSRST) || defined(RCC_AHBRSTR_ETHMACRST)
- 61:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define RCC_AHBRSTR_SUPPORT
- 62:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /* RCC_AHBRSTR_OTGFSRST || RCC_AHBRSTR_ETHMACRST */
- 63:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 64:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/
- 65:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- ARM GAS /tmp/ccBGIhL8.s page 120
- 66:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/
- 67:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/
- 68:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
- 69:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @{
- 70:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** */
- 71:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 72:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
- 73:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @{
- 74:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** */
- 75:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
- 76:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
- 77:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
- 78:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(DMA2)
- 79:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
- 80:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*DMA2*/
- 81:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(ETH)
- 82:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHBENR_ETHMACEN
- 83:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHBENR_ETHMACRXEN
- 84:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHBENR_ETHMACTXEN
- 85:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*ETH*/
- 86:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
- 87:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(FSMC_Bank1)
- 88:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_FSMC RCC_AHBENR_FSMCEN
- 89:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*FSMC_Bank1*/
- 90:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(USB_OTG_FS)
- 91:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGFS RCC_AHBENR_OTGFSEN
- 92:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*USB_OTG_FS*/
- 93:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(SDIO)
- 94:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SDIO RCC_AHBENR_SDIOEN
- 95:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*SDIO*/
- 96:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN
- 97:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /**
- 98:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @}
- 99:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** */
- 100:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 101:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
- 102:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @{
- 103:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** */
- 104:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
- 105:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_BKP RCC_APB1ENR_BKPEN
- 106:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(CAN1)
- 107:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN
- 108:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*CAN1*/
- 109:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(CAN2)
- 110:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN
- 111:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*CAN2*/
- 112:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(CEC)
- 113:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
- 114:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*CEC*/
- 115:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(DAC)
- 116:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
- 117:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*DAC*/
- 118:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
- 119:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(I2C2)
- 120:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
- 121:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*I2C2*/
- 122:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
- ARM GAS /tmp/ccBGIhL8.s page 121
- 123:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(SPI2)
- 124:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
- 125:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*SPI2*/
- 126:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(SPI3)
- 127:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
- 128:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*SPI3*/
- 129:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(TIM12)
- 130:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
- 131:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*TIM12*/
- 132:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(TIM13)
- 133:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
- 134:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*TIM13*/
- 135:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(TIM14)
- 136:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
- 137:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*TIM14*/
- 138:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
- 139:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
- 140:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(TIM4)
- 141:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
- 142:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*TIM4*/
- 143:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(TIM5)
- 144:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
- 145:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*TIM5*/
- 146:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(TIM6)
- 147:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
- 148:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*TIM6*/
- 149:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(TIM7)
- 150:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
- 151:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*TIM7*/
- 152:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(UART4)
- 153:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
- 154:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*UART4*/
- 155:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(UART5)
- 156:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
- 157:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*UART5*/
- 158:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
- 159:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(USART3)
- 160:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
- 161:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*USART3*/
- 162:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(USB)
- 163:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
- 164:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*USB*/
- 165:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
- 166:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /**
- 167:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @}
- 168:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** */
- 169:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 170:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
- 171:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @{
- 172:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** */
- 173:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
- 174:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
- 175:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(ADC2)
- 176:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN
- 177:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*ADC2*/
- 178:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(ADC3)
- 179:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN
- ARM GAS /tmp/ccBGIhL8.s page 122
- 180:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*ADC3*/
- 181:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_AFIO RCC_APB2ENR_AFIOEN
- 182:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_GPIOA RCC_APB2ENR_IOPAEN
- 183:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_GPIOB RCC_APB2ENR_IOPBEN
- 184:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_GPIOC RCC_APB2ENR_IOPCEN
- 185:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_GPIOD RCC_APB2ENR_IOPDEN
- 186:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(GPIOE)
- 187:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_GPIOE RCC_APB2ENR_IOPEEN
- 188:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*GPIOE*/
- 189:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(GPIOF)
- 190:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_GPIOF RCC_APB2ENR_IOPFEN
- 191:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*GPIOF*/
- 192:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(GPIOG)
- 193:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_GPIOG RCC_APB2ENR_IOPGEN
- 194:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*GPIOG*/
- 195:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
- 196:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(TIM10)
- 197:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
- 198:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*TIM10*/
- 199:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(TIM11)
- 200:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
- 201:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*TIM11*/
- 202:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(TIM15)
- 203:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
- 204:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*TIM15*/
- 205:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(TIM16)
- 206:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
- 207:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*TIM16*/
- 208:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(TIM17)
- 209:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
- 210:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*TIM17*/
- 211:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
- 212:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(TIM8)
- 213:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
- 214:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*TIM8*/
- 215:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(TIM9)
- 216:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
- 217:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /*TIM9*/
- 218:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
- 219:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /**
- 220:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @}
- 221:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** */
- 222:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 223:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /**
- 224:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @}
- 225:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** */
- 226:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 227:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/
- 228:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 229:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/
- 230:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
- 231:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @{
- 232:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** */
- 233:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 234:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1
- 235:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @{
- 236:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** */
- ARM GAS /tmp/ccBGIhL8.s page 123
- 237:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 238:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /**
- 239:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock.
- 240:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
- 241:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
- 242:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
- 243:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR ETHMACEN LL_AHB1_GRP1_EnableClock\n
- 244:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n
- 245:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n
- 246:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
- 247:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR FSMCEN LL_AHB1_GRP1_EnableClock\n
- 248:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR OTGFSEN LL_AHB1_GRP1_EnableClock\n
- 249:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR SDIOEN LL_AHB1_GRP1_EnableClock\n
- 250:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock
- 251:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values:
- 252:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
- 253:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- 254:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
- 255:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
- 256:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
- 257:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
- 258:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
- 259:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
- 260:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
- 261:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
- 262:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
- 263:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** *
- 264:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * (*) value not defined in all devices.
- 265:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @retval None
- 266:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** */
- 267:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
- 265 .loc 5 267 22 view .LVU46
- 266 .LBB97:
- 268:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** {
- 269:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** __IO uint32_t tmpreg;
- 267 .loc 5 269 3 view .LVU47
- 270:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** SET_BIT(RCC->AHBENR, Periphs);
- 268 .loc 5 270 3 view .LVU48
- 269 0004 0E4B ldr r3, .L21
- 270 0006 5A69 ldr r2, [r3, #20]
- 271 0008 42F00102 orr r2, r2, #1
- 272 000c 5A61 str r2, [r3, #20]
- 271:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */
- 272:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHBENR, Periphs);
- 273 .loc 5 272 3 view .LVU49
- 274 .loc 5 272 12 is_stmt 0 view .LVU50
- 275 000e 5B69 ldr r3, [r3, #20]
- 276 0010 03F00103 and r3, r3, #1
- 277 .loc 5 272 10 view .LVU51
- 278 0014 0193 str r3, [sp, #4]
- 273:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** (void)tmpreg;
- 279 .loc 5 273 3 is_stmt 1 view .LVU52
- 280 0016 019B ldr r3, [sp, #4]
- 281 .LVL20:
- 282 .loc 5 273 3 is_stmt 0 view .LVU53
- 283 .LBE97:
- 284 .LBE96:
- ARM GAS /tmp/ccBGIhL8.s page 124
- 323:Core/Src/main.c ****
- 324:Core/Src/main.c **** /* DMA interrupt init */
- 325:Core/Src/main.c **** /* DMA1_Channel5_IRQn interrupt configuration */
- 326:Core/Src/main.c **** NVIC_SetPriority(DMA1_Channel5_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
- 285 .loc 1 326 3 is_stmt 1 view .LVU54
- 286 .LBB98:
- 287 .LBI98:
- 1499:Drivers/CMSIS/Include/core_cm3.h **** {
- 288 .loc 2 1499 26 view .LVU55
- 289 .LBB99:
- 1501:Drivers/CMSIS/Include/core_cm3.h **** }
- 290 .loc 2 1501 3 view .LVU56
- 1501:Drivers/CMSIS/Include/core_cm3.h **** }
- 291 .loc 2 1501 26 is_stmt 0 view .LVU57
- 292 0018 0A4B ldr r3, .L21+4
- 293 001a D868 ldr r0, [r3, #12]
- 294 .LBE99:
- 295 .LBE98:
- 296 .loc 1 326 3 discriminator 1 view .LVU58
- 297 001c 0022 movs r2, #0
- 298 001e 1146 mov r1, r2
- 299 0020 C0F30220 ubfx r0, r0, #8, #3
- 300 0024 FFF7FEFF bl NVIC_EncodePriority
- 301 .LVL21:
- 302 .LBB100:
- 303 .LBI100:
- 1639:Drivers/CMSIS/Include/core_cm3.h **** {
- 304 .loc 2 1639 22 is_stmt 1 view .LVU59
- 305 .LBB101:
- 1641:Drivers/CMSIS/Include/core_cm3.h **** {
- 306 .loc 2 1641 3 view .LVU60
- 1643:Drivers/CMSIS/Include/core_cm3.h **** }
- 307 .loc 2 1643 5 view .LVU61
- 1643:Drivers/CMSIS/Include/core_cm3.h **** }
- 308 .loc 2 1643 48 is_stmt 0 view .LVU62
- 309 0028 0001 lsls r0, r0, #4
- 310 .LVL22:
- 1643:Drivers/CMSIS/Include/core_cm3.h **** }
- 311 .loc 2 1643 48 view .LVU63
- 312 002a C0B2 uxtb r0, r0
- 1643:Drivers/CMSIS/Include/core_cm3.h **** }
- 313 .loc 2 1643 46 view .LVU64
- 314 002c 064B ldr r3, .L21+8
- 315 002e 83F80F03 strb r0, [r3, #783]
- 316 .LVL23:
- 1643:Drivers/CMSIS/Include/core_cm3.h **** }
- 317 .loc 2 1643 46 view .LVU65
- 318 .LBE101:
- 319 .LBE100:
- 327:Core/Src/main.c **** NVIC_EnableIRQ(DMA1_Channel5_IRQn);
- 320 .loc 1 327 3 is_stmt 1 view .LVU66
- 321 .LBB102:
- 322 .LBI102:
- 1511:Drivers/CMSIS/Include/core_cm3.h **** {
- 323 .loc 2 1511 22 view .LVU67
- 324 .LBB103:
- 1513:Drivers/CMSIS/Include/core_cm3.h **** {
- ARM GAS /tmp/ccBGIhL8.s page 125
- 325 .loc 2 1513 3 view .LVU68
- 1515:Drivers/CMSIS/Include/core_cm3.h **** }
- 326 .loc 2 1515 5 view .LVU69
- 1515:Drivers/CMSIS/Include/core_cm3.h **** }
- 327 .loc 2 1515 43 is_stmt 0 view .LVU70
- 328 0032 4FF40042 mov r2, #32768
- 329 0036 1A60 str r2, [r3]
- 330 .LVL24:
- 1515:Drivers/CMSIS/Include/core_cm3.h **** }
- 331 .loc 2 1515 43 view .LVU71
- 332 .LBE103:
- 333 .LBE102:
- 328:Core/Src/main.c ****
- 329:Core/Src/main.c **** }
- 334 .loc 1 329 1 view .LVU72
- 335 0038 03B0 add sp, sp, #12
- 336 .LCFI8:
- 337 .cfi_def_cfa_offset 4
- 338 @ sp needed
- 339 003a 5DF804FB ldr pc, [sp], #4
- 340 .L22:
- 341 003e 00BF .align 2
- 342 .L21:
- 343 0040 00100240 .word 1073876992
- 344 0044 00ED00E0 .word -536810240
- 345 0048 00E100E0 .word -536813312
- 346 .cfi_endproc
- 347 .LFE659:
- 349 .section .text.MX_GPIO_Init,"ax",%progbits
- 350 .align 1
- 351 .syntax unified
- 352 .thumb
- 353 .thumb_func
- 355 MX_GPIO_Init:
- 356 .LFB660:
- 330:Core/Src/main.c ****
- 331:Core/Src/main.c **** /**
- 332:Core/Src/main.c **** * @brief GPIO Initialization Function
- 333:Core/Src/main.c **** * @param None
- 334:Core/Src/main.c **** * @retval None
- 335:Core/Src/main.c **** */
- 336:Core/Src/main.c **** static void MX_GPIO_Init(void)
- 337:Core/Src/main.c **** {
- 357 .loc 1 337 1 is_stmt 1 view -0
- 358 .cfi_startproc
- 359 @ args = 0, pretend = 0, frame = 32
- 360 @ frame_needed = 0, uses_anonymous_args = 0
- 361 0000 F0B5 push {r4, r5, r6, r7, lr}
- 362 .LCFI9:
- 363 .cfi_def_cfa_offset 20
- 364 .cfi_offset 4, -20
- 365 .cfi_offset 5, -16
- 366 .cfi_offset 6, -12
- 367 .cfi_offset 7, -8
- 368 .cfi_offset 14, -4
- 369 0002 89B0 sub sp, sp, #36
- 370 .LCFI10:
- ARM GAS /tmp/ccBGIhL8.s page 126
- 371 .cfi_def_cfa_offset 56
- 338:Core/Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
- 372 .loc 1 338 3 view .LVU74
- 373 .loc 1 338 23 is_stmt 0 view .LVU75
- 374 0004 0024 movs r4, #0
- 375 0006 0394 str r4, [sp, #12]
- 376 0008 0494 str r4, [sp, #16]
- 377 000a 0594 str r4, [sp, #20]
- 378 000c 0694 str r4, [sp, #24]
- 379 000e 0794 str r4, [sp, #28]
- 339:Core/Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_1 */
- 340:Core/Src/main.c **** /* USER CODE END MX_GPIO_Init_1 */
- 341:Core/Src/main.c ****
- 342:Core/Src/main.c **** /* GPIO Ports Clock Enable */
- 343:Core/Src/main.c **** LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_GPIOC);
- 380 .loc 1 343 3 is_stmt 1 view .LVU76
- 381 .LVL25:
- 382 .LBB104:
- 383 .LBI104:
- 274:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** }
- 275:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 276:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /**
- 277:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @brief Check if AHB1 peripheral clock is enabled or not
- 278:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
- 279:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
- 280:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
- 281:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n
- 282:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n
- 283:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n
- 284:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
- 285:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR FSMCEN LL_AHB1_GRP1_IsEnabledClock\n
- 286:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR OTGFSEN LL_AHB1_GRP1_IsEnabledClock\n
- 287:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR SDIOEN LL_AHB1_GRP1_IsEnabledClock\n
- 288:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock
- 289:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values:
- 290:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
- 291:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- 292:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
- 293:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
- 294:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
- 295:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
- 296:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
- 297:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
- 298:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
- 299:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
- 300:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
- 301:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** *
- 302:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * (*) value not defined in all devices.
- 303:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @retval State of Periphs (1 or 0).
- 304:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** */
- 305:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
- 306:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** {
- 307:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
- 308:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** }
- 309:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 310:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /**
- 311:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock.
- ARM GAS /tmp/ccBGIhL8.s page 127
- 312:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
- 313:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
- 314:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
- 315:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR ETHMACEN LL_AHB1_GRP1_DisableClock\n
- 316:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n
- 317:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n
- 318:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
- 319:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR FSMCEN LL_AHB1_GRP1_DisableClock\n
- 320:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR OTGFSEN LL_AHB1_GRP1_DisableClock\n
- 321:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR SDIOEN LL_AHB1_GRP1_DisableClock\n
- 322:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock
- 323:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values:
- 324:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
- 325:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- 326:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
- 327:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
- 328:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
- 329:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
- 330:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
- 331:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
- 332:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
- 333:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
- 334:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
- 335:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** *
- 336:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * (*) value not defined in all devices.
- 337:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @retval None
- 338:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** */
- 339:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
- 340:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** {
- 341:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** CLEAR_BIT(RCC->AHBENR, Periphs);
- 342:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** }
- 343:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 344:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #if defined(RCC_AHBRSTR_SUPPORT)
- 345:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /**
- 346:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @brief Force AHB1 peripherals reset.
- 347:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n
- 348:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBRSTR OTGFSRST LL_AHB1_GRP1_ForceReset
- 349:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values:
- 350:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
- 351:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
- 352:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
- 353:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** *
- 354:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * (*) value not defined in all devices.
- 355:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @retval None
- 356:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** */
- 357:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
- 358:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** {
- 359:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** SET_BIT(RCC->AHBRSTR, Periphs);
- 360:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** }
- 361:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 362:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /**
- 363:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @brief Release AHB1 peripherals reset.
- 364:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n
- 365:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * AHBRSTR OTGFSRST LL_AHB1_GRP1_ReleaseReset
- 366:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values:
- 367:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
- 368:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
- ARM GAS /tmp/ccBGIhL8.s page 128
- 369:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
- 370:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** *
- 371:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * (*) value not defined in all devices.
- 372:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @retval None
- 373:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** */
- 374:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
- 375:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** {
- 376:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** CLEAR_BIT(RCC->AHBRSTR, Periphs);
- 377:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** }
- 378:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** #endif /* RCC_AHBRSTR_SUPPORT */
- 379:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 380:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /**
- 381:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @}
- 382:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** */
- 383:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 384:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB1 APB1
- 385:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @{
- 386:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** */
- 387:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 388:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /**
- 389:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @brief Enable APB1 peripherals clock.
- 390:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_EnableClock\n
- 391:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n
- 392:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n
- 393:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n
- 394:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
- 395:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
- 396:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
- 397:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
- 398:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
- 399:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
- 400:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n
- 401:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n
- 402:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
- 403:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
- 404:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
- 405:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
- 406:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
- 407:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
- 408:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
- 409:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
- 410:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
- 411:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
- 412:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
- 413:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
- 414:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock
- 415:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values:
- 416:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_BKP
- 417:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
- 418:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
- 419:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
- 420:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
- 421:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- 422:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
- 423:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- 424:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
- 425:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
- ARM GAS /tmp/ccBGIhL8.s page 129
- 426:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
- 427:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
- 428:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
- 429:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- 430:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- 431:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
- 432:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
- 433:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
- 434:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
- 435:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
- 436:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
- 437:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- 438:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
- 439:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
- 440:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- 441:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** *
- 442:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * (*) value not defined in all devices.
- 443:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @retval None
- 444:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** */
- 445:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
- 446:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** {
- 447:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** __IO uint32_t tmpreg;
- 448:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs);
- 449:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */
- 450:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
- 451:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** (void)tmpreg;
- 452:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** }
- 453:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 454:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /**
- 455:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @brief Check if APB1 peripheral clock is enabled or not
- 456:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_IsEnabledClock\n
- 457:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n
- 458:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n
- 459:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n
- 460:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
- 461:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
- 462:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
- 463:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
- 464:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
- 465:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
- 466:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
- 467:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
- 468:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
- 469:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
- 470:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
- 471:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
- 472:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
- 473:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
- 474:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
- 475:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
- 476:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
- 477:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
- 478:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
- 479:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
- 480:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock
- 481:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values:
- 482:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_BKP
- ARM GAS /tmp/ccBGIhL8.s page 130
- 483:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
- 484:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
- 485:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
- 486:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
- 487:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- 488:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
- 489:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- 490:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
- 491:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
- 492:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
- 493:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
- 494:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
- 495:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- 496:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- 497:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
- 498:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
- 499:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
- 500:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
- 501:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
- 502:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
- 503:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- 504:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
- 505:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
- 506:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- 507:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** *
- 508:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * (*) value not defined in all devices.
- 509:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @retval State of Periphs (1 or 0).
- 510:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** */
- 511:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
- 512:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** {
- 513:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
- 514:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** }
- 515:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 516:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /**
- 517:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @brief Disable APB1 peripherals clock.
- 518:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_DisableClock\n
- 519:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n
- 520:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n
- 521:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n
- 522:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
- 523:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
- 524:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
- 525:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
- 526:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
- 527:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
- 528:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n
- 529:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n
- 530:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
- 531:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
- 532:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
- 533:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
- 534:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
- 535:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
- 536:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
- 537:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
- 538:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
- 539:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
- ARM GAS /tmp/ccBGIhL8.s page 131
- 540:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
- 541:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
- 542:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock
- 543:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values:
- 544:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_BKP
- 545:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
- 546:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
- 547:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
- 548:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
- 549:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- 550:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
- 551:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- 552:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
- 553:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
- 554:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
- 555:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
- 556:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
- 557:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- 558:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- 559:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
- 560:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
- 561:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
- 562:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
- 563:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
- 564:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
- 565:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- 566:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
- 567:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
- 568:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- 569:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** *
- 570:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * (*) value not defined in all devices.
- 571:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @retval None
- 572:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** */
- 573:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
- 574:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** {
- 575:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** CLEAR_BIT(RCC->APB1ENR, Periphs);
- 576:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** }
- 577:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 578:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /**
- 579:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @brief Force APB1 peripherals reset.
- 580:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ForceReset\n
- 581:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n
- 582:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n
- 583:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n
- 584:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
- 585:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
- 586:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
- 587:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
- 588:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
- 589:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
- 590:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n
- 591:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n
- 592:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
- 593:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
- 594:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
- 595:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
- 596:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
- ARM GAS /tmp/ccBGIhL8.s page 132
- 597:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
- 598:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
- 599:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
- 600:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
- 601:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
- 602:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
- 603:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
- 604:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset
- 605:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values:
- 606:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_ALL
- 607:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_BKP
- 608:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
- 609:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
- 610:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
- 611:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
- 612:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- 613:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
- 614:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- 615:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
- 616:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
- 617:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
- 618:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
- 619:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
- 620:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- 621:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- 622:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
- 623:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
- 624:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
- 625:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
- 626:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
- 627:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
- 628:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- 629:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
- 630:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
- 631:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- 632:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** *
- 633:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * (*) value not defined in all devices.
- 634:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @retval None
- 635:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** */
- 636:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
- 637:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** {
- 638:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** SET_BIT(RCC->APB1RSTR, Periphs);
- 639:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** }
- 640:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 641:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /**
- 642:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @brief Release APB1 peripherals reset.
- 643:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ReleaseReset\n
- 644:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n
- 645:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n
- 646:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n
- 647:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
- 648:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
- 649:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
- 650:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
- 651:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
- 652:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
- 653:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
- ARM GAS /tmp/ccBGIhL8.s page 133
- 654:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
- 655:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
- 656:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
- 657:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
- 658:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
- 659:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
- 660:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
- 661:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
- 662:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
- 663:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
- 664:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
- 665:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
- 666:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
- 667:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset
- 668:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values:
- 669:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_ALL
- 670:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_BKP
- 671:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
- 672:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
- 673:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
- 674:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
- 675:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- 676:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
- 677:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- 678:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
- 679:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
- 680:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
- 681:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
- 682:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
- 683:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- 684:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- 685:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
- 686:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
- 687:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
- 688:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
- 689:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
- 690:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
- 691:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- 692:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
- 693:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
- 694:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- 695:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** *
- 696:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * (*) value not defined in all devices.
- 697:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @retval None
- 698:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** */
- 699:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
- 700:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** {
- 701:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** CLEAR_BIT(RCC->APB1RSTR, Periphs);
- 702:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** }
- 703:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 704:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /**
- 705:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @}
- 706:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** */
- 707:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 708:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB2 APB2
- 709:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @{
- 710:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** */
- ARM GAS /tmp/ccBGIhL8.s page 134
- 711:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h ****
- 712:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /**
- 713:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @brief Enable APB2 peripherals clock.
- 714:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
- 715:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n
- 716:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n
- 717:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB2ENR AFIOEN LL_APB2_GRP1_EnableClock\n
- 718:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB2ENR IOPAEN LL_APB2_GRP1_EnableClock\n
- 719:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB2ENR IOPBEN LL_APB2_GRP1_EnableClock\n
- 720:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB2ENR IOPCEN LL_APB2_GRP1_EnableClock\n
- 721:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB2ENR IOPDEN LL_APB2_GRP1_EnableClock\n
- 722:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB2ENR IOPEEN LL_APB2_GRP1_EnableClock\n
- 723:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB2ENR IOPFEN LL_APB2_GRP1_EnableClock\n
- 724:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB2ENR IOPGEN LL_APB2_GRP1_EnableClock\n
- 725:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
- 726:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
- 727:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n
- 728:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
- 729:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
- 730:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
- 731:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
- 732:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
- 733:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
- 734:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_EnableClock
- 735:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values:
- 736:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
- 737:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
- 738:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
- 739:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
- 740:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
- 741:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
- 742:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
- 743:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
- 744:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
- 745:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
- 746:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
- 747:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
- 748:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
- 749:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
- 750:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
- 751:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
- 752:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
- 753:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
- 754:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
- 755:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
- 756:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- 757:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** *
- 758:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * (*) value not defined in all devices.
- 759:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** * @retval None
- 760:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** */
- 761:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
- 384 .loc 5 761 22 view .LVU77
- 385 .LBB105:
- 762:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** {
- 763:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** __IO uint32_t tmpreg;
- 386 .loc 5 763 3 view .LVU78
- 764:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs);
- ARM GAS /tmp/ccBGIhL8.s page 135
- 387 .loc 5 764 3 view .LVU79
- 388 0010 1B4B ldr r3, .L25
- 389 0012 9A69 ldr r2, [r3, #24]
- 390 0014 42F01002 orr r2, r2, #16
- 391 0018 9A61 str r2, [r3, #24]
- 765:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */
- 766:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
- 392 .loc 5 766 3 view .LVU80
- 393 .loc 5 766 12 is_stmt 0 view .LVU81
- 394 001a 9A69 ldr r2, [r3, #24]
- 395 001c 02F01002 and r2, r2, #16
- 396 .loc 5 766 10 view .LVU82
- 397 0020 0292 str r2, [sp, #8]
- 767:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** (void)tmpreg;
- 398 .loc 5 767 3 is_stmt 1 view .LVU83
- 399 0022 029A ldr r2, [sp, #8]
- 400 .LVL26:
- 401 .loc 5 767 3 is_stmt 0 view .LVU84
- 402 .LBE105:
- 403 .LBE104:
- 344:Core/Src/main.c **** LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_GPIOD);
- 404 .loc 1 344 3 is_stmt 1 view .LVU85
- 405 .LBB106:
- 406 .LBI106:
- 761:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** {
- 407 .loc 5 761 22 view .LVU86
- 408 .LBB107:
- 763:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs);
- 409 .loc 5 763 3 view .LVU87
- 764:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */
- 410 .loc 5 764 3 view .LVU88
- 411 0024 9A69 ldr r2, [r3, #24]
- 412 0026 42F02002 orr r2, r2, #32
- 413 002a 9A61 str r2, [r3, #24]
- 766:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** (void)tmpreg;
- 414 .loc 5 766 3 view .LVU89
- 766:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** (void)tmpreg;
- 415 .loc 5 766 12 is_stmt 0 view .LVU90
- 416 002c 9A69 ldr r2, [r3, #24]
- 417 002e 02F02002 and r2, r2, #32
- 766:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** (void)tmpreg;
- 418 .loc 5 766 10 view .LVU91
- 419 0032 0192 str r2, [sp, #4]
- 420 .loc 5 767 3 is_stmt 1 view .LVU92
- 421 0034 019A ldr r2, [sp, #4]
- 422 .LVL27:
- 423 .loc 5 767 3 is_stmt 0 view .LVU93
- 424 .LBE107:
- 425 .LBE106:
- 345:Core/Src/main.c **** LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_GPIOA);
- 426 .loc 1 345 3 is_stmt 1 view .LVU94
- 427 .LBB108:
- 428 .LBI108:
- 761:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** {
- 429 .loc 5 761 22 view .LVU95
- 430 .LBB109:
- 763:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs);
- ARM GAS /tmp/ccBGIhL8.s page 136
- 431 .loc 5 763 3 view .LVU96
- 764:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */
- 432 .loc 5 764 3 view .LVU97
- 433 0036 9A69 ldr r2, [r3, #24]
- 434 0038 42F00402 orr r2, r2, #4
- 435 003c 9A61 str r2, [r3, #24]
- 766:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** (void)tmpreg;
- 436 .loc 5 766 3 view .LVU98
- 766:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** (void)tmpreg;
- 437 .loc 5 766 12 is_stmt 0 view .LVU99
- 438 003e 9B69 ldr r3, [r3, #24]
- 439 0040 03F00403 and r3, r3, #4
- 766:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** (void)tmpreg;
- 440 .loc 5 766 10 view .LVU100
- 441 0044 0093 str r3, [sp]
- 442 .loc 5 767 3 is_stmt 1 view .LVU101
- 443 0046 009B ldr r3, [sp]
- 444 .LVL28:
- 445 .loc 5 767 3 is_stmt 0 view .LVU102
- 446 .LBE109:
- 447 .LBE108:
- 346:Core/Src/main.c ****
- 347:Core/Src/main.c **** /**/
- 348:Core/Src/main.c **** LL_GPIO_ResetOutputPin(GPIOC, LL_GPIO_PIN_13);
- 448 .loc 1 348 3 is_stmt 1 view .LVU103
- 449 .LBB110:
- 450 .LBI110:
- 451 .file 6 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h"
- 1:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 2:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** ******************************************************************************
- 3:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @file stm32f1xx_ll_gpio.h
- 4:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @author MCD Application Team
- 5:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @brief Header file of GPIO LL module.
- 6:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** ******************************************************************************
- 7:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @attention
- 8:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** *
- 9:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * Copyright (c) 2016 STMicroelectronics.
- 10:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * All rights reserved.
- 11:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** *
- 12:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * This software is licensed under terms that can be found in the LICENSE file
- 13:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * in the root directory of this software component.
- 14:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * If no LICENSE file comes with this software, it is provided AS-IS.
- 15:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** *
- 16:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** ******************************************************************************
- 17:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 18:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 19:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /* Define to prevent recursive inclusion -------------------------------------*/
- 20:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #ifndef STM32F1xx_LL_GPIO_H
- 21:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define STM32F1xx_LL_GPIO_H
- 22:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 23:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #ifdef __cplusplus
- 24:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** extern "C" {
- 25:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #endif
- 26:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 27:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /* Includes ------------------------------------------------------------------*/
- 28:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #include "stm32f1xx.h"
- 29:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- ARM GAS /tmp/ccBGIhL8.s page 137
- 30:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /** @addtogroup STM32F1xx_LL_Driver
- 31:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @{
- 32:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 33:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 34:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) ||
- 35:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 36:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /** @defgroup GPIO_LL GPIO
- 37:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @{
- 38:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 39:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 40:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /* Private types -------------------------------------------------------------*/
- 41:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /* Private variables ---------------------------------------------------------*/
- 42:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /* Private constants ---------------------------------------------------------*/
- 43:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 44:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /** @defgroup GPIO_LL_Private_Constants GPIO Private Constants
- 45:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @{
- 46:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 47:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /* Defines used for Pin Mask Initialization */
- 48:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define GPIO_PIN_MASK_POS 8U
- 49:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define GPIO_PIN_NB 16U
- 50:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 51:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @}
- 52:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 53:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 54:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /* Private macros ------------------------------------------------------------*/
- 55:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #if defined(USE_FULL_LL_DRIVER)
- 56:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
- 57:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @{
- 58:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 59:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 60:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 61:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @}
- 62:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 63:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #endif /*USE_FULL_LL_DRIVER*/
- 64:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 65:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /* Exported types ------------------------------------------------------------*/
- 66:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #if defined(USE_FULL_LL_DRIVER)
- 67:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
- 68:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @{
- 69:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 70:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 71:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 72:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @brief LL GPIO Init Structure definition
- 73:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 74:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** typedef struct
- 75:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** {
- 76:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
- 77:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** This parameter can be any value of @ref GPIO_LL_EC_PIN */
- 78:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 79:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
- 80:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** This parameter can be a value of @ref GPIO_LL_EC_MODE.
- 81:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 82:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** GPIO HW configuration can be modified afterwards using unitary functi
- 83:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 84:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** uint32_t Speed; /*!< Specifies the speed for the selected pins.
- 85:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** This parameter can be a value of @ref GPIO_LL_EC_SPEED.
- 86:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- ARM GAS /tmp/ccBGIhL8.s page 138
- 87:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** GPIO HW configuration can be modified afterwards using unitary functi
- 88:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 89:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** uint32_t OutputType; /*!< Specifies the operating output type for the selected pins.
- 90:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
- 91:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 92:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** GPIO HW configuration can be modified afterwards using unitary functi
- 93:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 94:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
- 95:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** This parameter can be a value of @ref GPIO_LL_EC_PULL.
- 96:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 97:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** GPIO HW configuration can be modified afterwards using unitary functi
- 98:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** } LL_GPIO_InitTypeDef;
- 99:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 100:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 101:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @}
- 102:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 103:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #endif /* USE_FULL_LL_DRIVER */
- 104:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 105:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /* Exported constants --------------------------------------------------------*/
- 106:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
- 107:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @{
- 108:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 109:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 110:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_PIN PIN
- 111:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @{
- 112:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 113:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_PIN_0 ((GPIO_BSRR_BS0 << GPIO_PIN_MASK_POS) | 0x00000001U) /*!
- 114:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_PIN_1 ((GPIO_BSRR_BS1 << GPIO_PIN_MASK_POS) | 0x00000002U) /*!
- 115:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_PIN_2 ((GPIO_BSRR_BS2 << GPIO_PIN_MASK_POS) | 0x00000004U) /*!
- 116:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_PIN_3 ((GPIO_BSRR_BS3 << GPIO_PIN_MASK_POS) | 0x00000008U) /*!
- 117:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_PIN_4 ((GPIO_BSRR_BS4 << GPIO_PIN_MASK_POS) | 0x00000010U) /*!
- 118:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_PIN_5 ((GPIO_BSRR_BS5 << GPIO_PIN_MASK_POS) | 0x00000020U) /*!
- 119:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_PIN_6 ((GPIO_BSRR_BS6 << GPIO_PIN_MASK_POS) | 0x00000040U) /*!
- 120:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_PIN_7 ((GPIO_BSRR_BS7 << GPIO_PIN_MASK_POS) | 0x00000080U) /*!
- 121:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_PIN_8 ((GPIO_BSRR_BS8 << GPIO_PIN_MASK_POS) | 0x04000001U) /*!
- 122:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_PIN_9 ((GPIO_BSRR_BS9 << GPIO_PIN_MASK_POS) | 0x04000002U) /*!
- 123:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_PIN_10 ((GPIO_BSRR_BS10 << GPIO_PIN_MASK_POS) | 0x04000004U) /*!
- 124:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_PIN_11 ((GPIO_BSRR_BS11 << GPIO_PIN_MASK_POS) | 0x04000008U) /*!
- 125:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_PIN_12 ((GPIO_BSRR_BS12 << GPIO_PIN_MASK_POS) | 0x04000010U) /*!
- 126:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_PIN_13 ((GPIO_BSRR_BS13 << GPIO_PIN_MASK_POS) | 0x04000020U) /*!
- 127:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_PIN_14 ((GPIO_BSRR_BS14 << GPIO_PIN_MASK_POS) | 0x04000040U) /*!
- 128:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_PIN_15 ((GPIO_BSRR_BS15 << GPIO_PIN_MASK_POS) | 0x04000080U) /*!
- 129:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_PIN_ALL (LL_GPIO_PIN_0 | LL_GPIO_PIN_1 | LL_GPIO_PIN_2 | \
- 130:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** LL_GPIO_PIN_3 | LL_GPIO_PIN_4 | LL_GPIO_PIN_5 | \
- 131:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** LL_GPIO_PIN_6 | LL_GPIO_PIN_7 | LL_GPIO_PIN_8 | \
- 132:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** LL_GPIO_PIN_9 | LL_GPIO_PIN_10 | LL_GPIO_PIN_11 | \
- 133:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** LL_GPIO_PIN_12 | LL_GPIO_PIN_13 | LL_GPIO_PIN_14 | \
- 134:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** LL_GPIO_PIN_15) /*!<
- 135:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 136:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @}
- 137:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 138:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 139:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_MODE Mode
- 140:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @{
- 141:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 142:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_MODE_ANALOG 0x00000000U /*!< Select analog mode */
- 143:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_MODE_FLOATING GPIO_CRL_CNF0_0 /*!< Select floating mode */
- ARM GAS /tmp/ccBGIhL8.s page 139
- 144:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_MODE_INPUT GPIO_CRL_CNF0_1 /*!< Select input mode */
- 145:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_MODE_OUTPUT GPIO_CRL_MODE0_0 /*!< Select general purpose output mode
- 146:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_MODE_ALTERNATE (GPIO_CRL_CNF0_1 | GPIO_CRL_MODE0_0) /*!< Select alternate
- 147:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 148:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @}
- 149:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 150:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 151:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_OUTPUT Output Type
- 152:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @{
- 153:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 154:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_OUTPUT_PUSHPULL 0x00000000U /*!< Select push-pull as output
- 155:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_OUTPUT_OPENDRAIN GPIO_CRL_CNF0_0 /*!< Select open-drain as outpu
- 156:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 157:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @}
- 158:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 159:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 160:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_SPEED Output Speed
- 161:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @{
- 162:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 163:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_MODE_OUTPUT_10MHz GPIO_CRL_MODE0_0 /*!< Select Output mode, max s
- 164:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_MODE_OUTPUT_2MHz GPIO_CRL_MODE0_1 /*!< Select Output mode, max s
- 165:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_MODE_OUTPUT_50MHz GPIO_CRL_MODE0 /*!< Select Output mode, max s
- 166:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 167:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @}
- 168:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 169:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 170:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_SPEED_FREQ_LOW LL_GPIO_MODE_OUTPUT_2MHz /*!< Select I/O low output spe
- 171:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_SPEED_FREQ_MEDIUM LL_GPIO_MODE_OUTPUT_10MHz /*!< Select I/O medium output
- 172:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_SPEED_FREQ_HIGH LL_GPIO_MODE_OUTPUT_50MHz /*!< Select I/O high output sp
- 173:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 174:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
- 175:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @{
- 176:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 177:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_PULL_DOWN 0x00000000U /*!< Select I/O pull down */
- 178:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_PULL_UP GPIO_ODR_ODR0 /*!< Select I/O pull up */
- 179:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 180:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 181:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @}
- 182:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 183:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 184:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /** @defgroup GPIO_LL_EVENTOUT_PIN EVENTOUT Pin
- 185:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @{
- 186:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 187:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 188:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */
- 189:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */
- 190:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */
- 191:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */
- 192:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */
- 193:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */
- 194:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */
- 195:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */
- 196:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */
- 197:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */
- 198:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */
- 199:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */
- 200:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */
- ARM GAS /tmp/ccBGIhL8.s page 140
- 201:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */
- 202:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */
- 203:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */
- 204:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 205:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 206:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @}
- 207:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 208:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 209:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /** @defgroup GPIO_LL_EVENTOUT_PORT EVENTOUT Port
- 210:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @{
- 211:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 212:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 213:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */
- 214:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */
- 215:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */
- 216:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */
- 217:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */
- 218:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 219:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 220:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @}
- 221:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 222:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 223:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_EXTI_PORT GPIO EXTI PORT
- 224:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @{
- 225:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 226:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EXTI_PORTA 0U /*!< EXTI PORT A */
- 227:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EXTI_PORTB 1U /*!< EXTI PORT B */
- 228:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EXTI_PORTC 2U /*!< EXTI PORT C */
- 229:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EXTI_PORTD 3U /*!< EXTI PORT D */
- 230:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EXTI_PORTE 4U /*!< EXTI PORT E */
- 231:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EXTI_PORTF 5U /*!< EXTI PORT F */
- 232:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EXTI_PORTG 6U /*!< EXTI PORT G */
- 233:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 234:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @}
- 235:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 236:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 237:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /** @defgroup GPIO_LL_EC_EXTI_LINE GPIO EXTI LINE
- 238:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @{
- 239:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 240:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EXTI_LINE0 (0x000FU << 16U | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] *
- 241:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EXTI_LINE1 (0x00F0U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] *
- 242:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EXTI_LINE2 (0x0F00U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] *
- 243:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EXTI_LINE3 (0xF000U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] *
- 244:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EXTI_LINE4 (0x000FU << 16U | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] *
- 245:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EXTI_LINE5 (0x00F0U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] *
- 246:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EXTI_LINE6 (0x0F00U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] *
- 247:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EXTI_LINE7 (0xF000U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] *
- 248:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EXTI_LINE8 (0x000FU << 16U | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] *
- 249:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EXTI_LINE9 (0x00F0U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] *
- 250:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EXTI_LINE10 (0x0F00U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] *
- 251:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EXTI_LINE11 (0xF000U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] *
- 252:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EXTI_LINE12 (0x000FU << 16U | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] *
- 253:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EXTI_LINE13 (0x00F0U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] *
- 254:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EXTI_LINE14 (0x0F00U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] *
- 255:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_AF_EXTI_LINE15 (0xF000U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] *
- 256:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 257:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @}
- ARM GAS /tmp/ccBGIhL8.s page 141
- 258:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 259:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 260:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 261:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @}
- 262:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 263:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 264:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /* Exported macro ------------------------------------------------------------*/
- 265:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
- 266:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @{
- 267:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 268:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 269:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
- 270:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @{
- 271:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 272:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 273:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 274:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @brief Write a value in GPIO register
- 275:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param __INSTANCE__ GPIO Instance
- 276:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param __REG__ Register to be written
- 277:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param __VALUE__ Value to be written in the register
- 278:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @retval None
- 279:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 280:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALU
- 281:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 282:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 283:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @brief Read a value in GPIO register
- 284:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param __INSTANCE__ GPIO Instance
- 285:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param __REG__ Register to be read
- 286:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @retval Register value
- 287:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 288:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** #define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
- 289:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 290:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @}
- 291:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 292:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 293:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 294:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @}
- 295:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 296:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 297:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /* Exported functions --------------------------------------------------------*/
- 298:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
- 299:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @{
- 300:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 301:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 302:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
- 303:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @{
- 304:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 305:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 306:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 307:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @brief Configure gpio mode for a dedicated pin on dedicated port.
- 308:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose O
- 309:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * Alternate function Output.
- 310:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter.
- 311:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @rmtoll CRL CNFy LL_GPIO_SetPinMode
- 312:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @rmtoll CRL MODEy LL_GPIO_SetPinMode
- 313:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @rmtoll CRH CNFy LL_GPIO_SetPinMode
- 314:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @rmtoll CRH MODEy LL_GPIO_SetPinMode
- ARM GAS /tmp/ccBGIhL8.s page 142
- 315:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param GPIOx GPIO Port
- 316:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values:
- 317:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0
- 318:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1
- 319:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2
- 320:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3
- 321:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4
- 322:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5
- 323:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6
- 324:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7
- 325:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8
- 326:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9
- 327:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10
- 328:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11
- 329:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12
- 330:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13
- 331:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14
- 332:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15
- 333:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param Mode This parameter can be one of the following values:
- 334:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_ANALOG
- 335:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_FLOATING
- 336:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_INPUT
- 337:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_OUTPUT
- 338:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_ALTERNATE
- 339:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @retval None
- 340:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 341:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
- 342:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** {
- 343:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
- 344:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** MODIFY_REG(*pReg, ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U)), (Mode << (POSIT
- 345:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** }
- 346:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 347:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 348:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @brief Return gpio mode for a dedicated pin on dedicated port.
- 349:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose O
- 350:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * Alternate function Output.
- 351:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter.
- 352:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @rmtoll CRL CNFy LL_GPIO_GetPinMode
- 353:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @rmtoll CRL MODEy LL_GPIO_GetPinMode
- 354:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @rmtoll CRH CNFy LL_GPIO_GetPinMode
- 355:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @rmtoll CRH MODEy LL_GPIO_GetPinMode
- 356:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param GPIOx GPIO Port
- 357:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values:
- 358:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0
- 359:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1
- 360:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2
- 361:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3
- 362:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4
- 363:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5
- 364:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6
- 365:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7
- 366:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8
- 367:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9
- 368:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10
- 369:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11
- 370:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12
- 371:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13
- ARM GAS /tmp/ccBGIhL8.s page 143
- 372:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14
- 373:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15
- 374:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @retval Returned value can be one of the following values:
- 375:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_ANALOG
- 376:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_FLOATING
- 377:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_INPUT
- 378:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_OUTPUT
- 379:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_ALTERNATE
- 380:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 381:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
- 382:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** {
- 383:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
- 384:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** return (READ_BIT(*pReg, ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U))) >> (POSIT
- 385:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** }
- 386:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 387:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 388:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @brief Configure gpio speed for a dedicated pin on dedicated port.
- 389:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @note I/O speed can be Low, Medium or Fast speed.
- 390:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter.
- 391:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @note Refer to datasheet for frequency specifications and the power
- 392:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * supply and load conditions for each speed.
- 393:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @rmtoll CRL MODEy LL_GPIO_SetPinSpeed
- 394:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @rmtoll CRH MODEy LL_GPIO_SetPinSpeed
- 395:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param GPIOx GPIO Port
- 396:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values:
- 397:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0
- 398:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1
- 399:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2
- 400:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3
- 401:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4
- 402:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5
- 403:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6
- 404:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7
- 405:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8
- 406:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9
- 407:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10
- 408:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11
- 409:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12
- 410:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13
- 411:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14
- 412:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15
- 413:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param Speed This parameter can be one of the following values:
- 414:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_LOW
- 415:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
- 416:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
- 417:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @retval None
- 418:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 419:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
- 420:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** {
- 421:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
- 422:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** MODIFY_REG(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U)),
- 423:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** (Speed << (POSITION_VAL(Pin) * 4U)));
- 424:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** }
- 425:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 426:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 427:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @brief Return gpio speed for a dedicated pin on dedicated port.
- 428:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @note I/O speed can be Low, Medium, Fast or High speed.
- ARM GAS /tmp/ccBGIhL8.s page 144
- 429:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter.
- 430:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @note Refer to datasheet for frequency specifications and the power
- 431:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * supply and load conditions for each speed.
- 432:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @rmtoll CRL MODEy LL_GPIO_GetPinSpeed
- 433:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @rmtoll CRH MODEy LL_GPIO_GetPinSpeed
- 434:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param GPIOx GPIO Port
- 435:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values:
- 436:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0
- 437:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1
- 438:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2
- 439:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3
- 440:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4
- 441:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5
- 442:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6
- 443:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7
- 444:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8
- 445:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9
- 446:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10
- 447:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11
- 448:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12
- 449:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13
- 450:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14
- 451:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15
- 452:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @retval Returned value can be one of the following values:
- 453:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_LOW
- 454:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
- 455:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
- 456:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 457:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
- 458:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** {
- 459:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
- 460:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** return (READ_BIT(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)
- 461:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** }
- 462:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 463:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 464:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @brief Configure gpio output type for several pins on dedicated port.
- 465:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @note Output type as to be set when gpio pin is in output or
- 466:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * alternate modes. Possible type are Push-pull or Open-drain.
- 467:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @rmtoll CRL MODEy LL_GPIO_SetPinOutputType
- 468:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @rmtoll CRH MODEy LL_GPIO_SetPinOutputType
- 469:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param GPIOx GPIO Port
- 470:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param Pin This parameter can be a combination of the following values:
- 471:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0
- 472:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1
- 473:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2
- 474:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3
- 475:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4
- 476:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5
- 477:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6
- 478:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7
- 479:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8
- 480:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9
- 481:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10
- 482:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11
- 483:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12
- 484:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13
- 485:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14
- ARM GAS /tmp/ccBGIhL8.s page 145
- 486:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15
- 487:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_ALL
- 488:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param OutputType This parameter can be one of the following values:
- 489:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
- 490:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
- 491:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @retval None
- 492:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 493:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputTyp
- 494:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** {
- 495:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
- 496:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** MODIFY_REG(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U)),
- 497:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** (OutputType << (POSITION_VAL(Pin) * 4U)));
- 498:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** }
- 499:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 500:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 501:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @brief Return gpio output type for several pins on dedicated port.
- 502:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @note Output type as to be set when gpio pin is in output or
- 503:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * alternate modes. Possible type are Push-pull or Open-drain.
- 504:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter.
- 505:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @rmtoll CRL MODEy LL_GPIO_GetPinOutputType
- 506:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @rmtoll CRH MODEy LL_GPIO_GetPinOutputType
- 507:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param GPIOx GPIO Port
- 508:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values:
- 509:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0
- 510:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1
- 511:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2
- 512:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3
- 513:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4
- 514:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5
- 515:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6
- 516:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7
- 517:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8
- 518:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9
- 519:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10
- 520:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11
- 521:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12
- 522:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13
- 523:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14
- 524:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15
- 525:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_ALL
- 526:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @retval Returned value can be one of the following values:
- 527:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
- 528:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
- 529:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 530:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
- 531:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** {
- 532:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
- 533:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** return (READ_BIT(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U
- 534:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 535:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** }
- 536:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 537:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 538:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
- 539:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter.
- 540:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @rmtoll ODR ODR LL_GPIO_SetPinPull
- 541:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param GPIOx GPIO Port
- 542:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values:
- ARM GAS /tmp/ccBGIhL8.s page 146
- 543:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0
- 544:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1
- 545:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2
- 546:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3
- 547:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4
- 548:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5
- 549:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6
- 550:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7
- 551:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8
- 552:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9
- 553:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10
- 554:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11
- 555:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12
- 556:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13
- 557:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14
- 558:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15
- 559:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param Pull This parameter can be one of the following values:
- 560:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PULL_DOWN
- 561:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PULL_UP
- 562:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @retval None
- 563:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 564:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
- 565:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** {
- 566:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** MODIFY_REG(GPIOx->ODR, (Pin >> GPIO_PIN_MASK_POS), Pull << (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS
- 567:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** }
- 568:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 569:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 570:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
- 571:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter.
- 572:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @rmtoll ODR ODR LL_GPIO_GetPinPull
- 573:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param GPIOx GPIO Port
- 574:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values:
- 575:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0
- 576:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1
- 577:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2
- 578:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3
- 579:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4
- 580:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5
- 581:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6
- 582:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7
- 583:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8
- 584:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9
- 585:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10
- 586:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11
- 587:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12
- 588:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13
- 589:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14
- 590:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15
- 591:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @retval Returned value can be one of the following values:
- 592:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PULL_DOWN
- 593:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PULL_UP
- 594:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 595:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
- 596:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** {
- 597:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** return (READ_BIT(GPIOx->ODR, (GPIO_ODR_ODR0 << (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)))) >> (POS
- 598:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** }
- 599:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- ARM GAS /tmp/ccBGIhL8.s page 147
- 600:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 601:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @brief Lock configuration of several pins for a dedicated port.
- 602:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @note When the lock sequence has been applied on a port bit, the
- 603:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * value of this port bit can no longer be modified until the
- 604:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * next reset.
- 605:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @note Each lock bit freezes a specific configuration register
- 606:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * (control and alternate function registers).
- 607:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @rmtoll LCKR LCKK LL_GPIO_LockPin
- 608:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param GPIOx GPIO Port
- 609:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param PinMask This parameter can be a combination of the following values:
- 610:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0
- 611:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1
- 612:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2
- 613:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3
- 614:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4
- 615:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5
- 616:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6
- 617:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7
- 618:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8
- 619:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9
- 620:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10
- 621:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11
- 622:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12
- 623:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13
- 624:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14
- 625:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15
- 626:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_ALL
- 627:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @retval None
- 628:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 629:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
- 630:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** {
- 631:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** __IO uint32_t temp;
- 632:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
- 633:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** WRITE_REG(GPIOx->LCKR, ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
- 634:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
- 635:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** temp = READ_REG(GPIOx->LCKR);
- 636:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** (void) temp;
- 637:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** }
- 638:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 639:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 640:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return
- 641:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
- 642:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param GPIOx GPIO Port
- 643:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param PinMask This parameter can be a combination of the following values:
- 644:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0
- 645:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1
- 646:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2
- 647:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3
- 648:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4
- 649:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5
- 650:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6
- 651:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7
- 652:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8
- 653:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9
- 654:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10
- 655:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11
- 656:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12
- ARM GAS /tmp/ccBGIhL8.s page 148
- 657:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13
- 658:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14
- 659:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15
- 660:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_ALL
- 661:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @retval State of bit (1 or 0).
- 662:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 663:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
- 664:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** {
- 665:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** return (READ_BIT(GPIOx->LCKR, ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)) == ((PinMask >> GPI
- 666:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** }
- 667:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 668:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 669:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0.
- 670:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
- 671:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param GPIOx GPIO Port
- 672:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @retval State of bit (1 or 0).
- 673:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 674:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
- 675:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** {
- 676:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
- 677:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** }
- 678:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 679:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 680:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @}
- 681:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 682:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 683:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /** @defgroup GPIO_LL_EF_Data_Access Data Access
- 684:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @{
- 685:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 686:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 687:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 688:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @brief Return full input data register value for a dedicated port.
- 689:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @rmtoll IDR IDy LL_GPIO_ReadInputPort
- 690:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param GPIOx GPIO Port
- 691:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @retval Input data register value of port
- 692:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 693:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
- 694:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** {
- 695:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** return (READ_REG(GPIOx->IDR));
- 696:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** }
- 697:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 698:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 699:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @brief Return if input data level for several pins of dedicated port is high or low.
- 700:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @rmtoll IDR IDy LL_GPIO_IsInputPinSet
- 701:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param GPIOx GPIO Port
- 702:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param PinMask This parameter can be a combination of the following values:
- 703:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0
- 704:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1
- 705:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2
- 706:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3
- 707:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4
- 708:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5
- 709:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6
- 710:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7
- 711:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8
- 712:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9
- 713:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10
- ARM GAS /tmp/ccBGIhL8.s page 149
- 714:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11
- 715:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12
- 716:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13
- 717:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14
- 718:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15
- 719:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_ALL
- 720:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @retval State of bit (1 or 0).
- 721:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 722:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
- 723:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** {
- 724:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** return (READ_BIT(GPIOx->IDR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU) == ((PinMask >> GPIO_P
- 725:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** }
- 726:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 727:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 728:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @brief Write output data register for the port.
- 729:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @rmtoll ODR ODy LL_GPIO_WriteOutputPort
- 730:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param GPIOx GPIO Port
- 731:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param PortValue Level value for each pin of the port
- 732:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @retval None
- 733:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 734:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
- 735:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** {
- 736:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** WRITE_REG(GPIOx->ODR, PortValue);
- 737:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** }
- 738:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 739:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 740:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @brief Return full output data register value for a dedicated port.
- 741:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @rmtoll ODR ODy LL_GPIO_ReadOutputPort
- 742:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param GPIOx GPIO Port
- 743:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @retval Output data register value of port
- 744:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 745:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
- 746:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** {
- 747:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** return (uint32_t)(READ_REG(GPIOx->ODR));
- 748:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** }
- 749:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 750:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 751:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @brief Return if input data level for several pins of dedicated port is high or low.
- 752:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
- 753:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param GPIOx GPIO Port
- 754:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param PinMask This parameter can be a combination of the following values:
- 755:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0
- 756:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1
- 757:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2
- 758:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3
- 759:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4
- 760:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5
- 761:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6
- 762:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7
- 763:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8
- 764:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9
- 765:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10
- 766:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11
- 767:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12
- 768:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13
- 769:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14
- 770:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15
- ARM GAS /tmp/ccBGIhL8.s page 150
- 771:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_ALL
- 772:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @retval State of bit (1 or 0).
- 773:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 774:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
- 775:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** {
- 776:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** return (READ_BIT(GPIOx->ODR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU) == ((PinMask >> GPIO_P
- 777:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** }
- 778:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 779:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 780:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @brief Set several pins to high level on dedicated gpio port.
- 781:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @rmtoll BSRR BSy LL_GPIO_SetOutputPin
- 782:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param GPIOx GPIO Port
- 783:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param PinMask This parameter can be a combination of the following values:
- 784:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0
- 785:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1
- 786:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2
- 787:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3
- 788:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4
- 789:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5
- 790:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6
- 791:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7
- 792:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8
- 793:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9
- 794:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10
- 795:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11
- 796:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12
- 797:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13
- 798:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14
- 799:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15
- 800:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_ALL
- 801:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @retval None
- 802:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 803:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
- 804:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** {
- 805:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** WRITE_REG(GPIOx->BSRR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU);
- 806:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** }
- 807:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h ****
- 808:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** /**
- 809:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @brief Set several pins to low level on dedicated gpio port.
- 810:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @rmtoll BRR BRy LL_GPIO_ResetOutputPin
- 811:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param GPIOx GPIO Port
- 812:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @param PinMask This parameter can be a combination of the following values:
- 813:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0
- 814:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1
- 815:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2
- 816:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3
- 817:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4
- 818:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5
- 819:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6
- 820:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7
- 821:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8
- 822:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9
- 823:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10
- 824:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11
- 825:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12
- 826:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13
- 827:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14
- ARM GAS /tmp/ccBGIhL8.s page 151
- 828:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15
- 829:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_ALL
- 830:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** * @retval None
- 831:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** */
- 832:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
- 452 .loc 6 832 22 view .LVU104
- 453 .LBB111:
- 833:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** {
- 834:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** WRITE_REG(GPIOx->BRR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU);
- 454 .loc 6 834 3 view .LVU105
- 455 0048 0E48 ldr r0, .L25+4
- 456 004a 4FF40053 mov r3, #8192
- 457 004e 4361 str r3, [r0, #20]
- 458 .LVL29:
- 459 .loc 6 834 3 is_stmt 0 view .LVU106
- 460 .LBE111:
- 461 .LBE110:
- 349:Core/Src/main.c ****
- 350:Core/Src/main.c **** /**/
- 351:Core/Src/main.c **** LL_GPIO_ResetOutputPin(GPIOA, LL_GPIO_PIN_1|LL_GPIO_PIN_2);
- 462 .loc 1 351 3 is_stmt 1 view .LVU107
- 463 .LBB112:
- 464 .LBI112:
- 832:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h **** {
- 465 .loc 6 832 22 view .LVU108
- 466 .LBB113:
- 467 .loc 6 834 3 view .LVU109
- 468 0050 0D4D ldr r5, .L25+8
- 469 0052 0623 movs r3, #6
- 470 0054 6B61 str r3, [r5, #20]
- 471 .LVL30:
- 472 .loc 6 834 3 is_stmt 0 view .LVU110
- 473 .LBE113:
- 474 .LBE112:
- 352:Core/Src/main.c ****
- 353:Core/Src/main.c **** /**/
- 354:Core/Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_13;
- 475 .loc 1 354 3 is_stmt 1 view .LVU111
- 476 .loc 1 354 23 is_stmt 0 view .LVU112
- 477 0056 0D4B ldr r3, .L25+12
- 478 0058 0393 str r3, [sp, #12]
- 355:Core/Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
- 479 .loc 1 355 3 is_stmt 1 view .LVU113
- 480 .loc 1 355 24 is_stmt 0 view .LVU114
- 481 005a 0127 movs r7, #1
- 482 005c 0497 str r7, [sp, #16]
- 356:Core/Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
- 483 .loc 1 356 3 is_stmt 1 view .LVU115
- 484 .loc 1 356 25 is_stmt 0 view .LVU116
- 485 005e 0226 movs r6, #2
- 486 0060 0596 str r6, [sp, #20]
- 357:Core/Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
- 487 .loc 1 357 3 is_stmt 1 view .LVU117
- 358:Core/Src/main.c **** LL_GPIO_Init(GPIOC, &GPIO_InitStruct);
- 488 .loc 1 358 3 view .LVU118
- 489 0062 03A9 add r1, sp, #12
- 490 0064 FFF7FEFF bl LL_GPIO_Init
- ARM GAS /tmp/ccBGIhL8.s page 152
- 491 .LVL31:
- 359:Core/Src/main.c ****
- 360:Core/Src/main.c **** /**/
- 361:Core/Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_1|LL_GPIO_PIN_2;
- 492 .loc 1 361 3 view .LVU119
- 493 .loc 1 361 23 is_stmt 0 view .LVU120
- 494 0068 40F20663 movw r3, #1542
- 495 006c 0393 str r3, [sp, #12]
- 362:Core/Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
- 496 .loc 1 362 3 is_stmt 1 view .LVU121
- 497 .loc 1 362 24 is_stmt 0 view .LVU122
- 498 006e 0497 str r7, [sp, #16]
- 363:Core/Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
- 499 .loc 1 363 3 is_stmt 1 view .LVU123
- 500 .loc 1 363 25 is_stmt 0 view .LVU124
- 501 0070 0596 str r6, [sp, #20]
- 364:Core/Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
- 502 .loc 1 364 3 is_stmt 1 view .LVU125
- 503 .loc 1 364 30 is_stmt 0 view .LVU126
- 504 0072 0694 str r4, [sp, #24]
- 365:Core/Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- 505 .loc 1 365 3 is_stmt 1 view .LVU127
- 506 0074 03A9 add r1, sp, #12
- 507 0076 2846 mov r0, r5
- 508 0078 FFF7FEFF bl LL_GPIO_Init
- 509 .LVL32:
- 366:Core/Src/main.c ****
- 367:Core/Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_2 */
- 368:Core/Src/main.c **** /* USER CODE END MX_GPIO_Init_2 */
- 369:Core/Src/main.c **** }
- 510 .loc 1 369 1 is_stmt 0 view .LVU128
- 511 007c 09B0 add sp, sp, #36
- 512 .LCFI11:
- 513 .cfi_def_cfa_offset 20
- 514 @ sp needed
- 515 007e F0BD pop {r4, r5, r6, r7, pc}
- 516 .L26:
- 517 .align 2
- 518 .L25:
- 519 0080 00100240 .word 1073876992
- 520 0084 00100140 .word 1073811456
- 521 0088 00080140 .word 1073809408
- 522 008c 20002004 .word 69206048
- 523 .cfi_endproc
- 524 .LFE660:
- 526 .section .text.LL_ADC_SetChannelSamplingTime,"ax",%progbits
- 527 .align 1
- 528 .syntax unified
- 529 .thumb
- 530 .thumb_func
- 532 LL_ADC_SetChannelSamplingTime:
- 533 .LVL33:
- 534 .LFB98:
- 2586:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2587:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 2588:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Get ADC group injected sequence: channel on the selected
- 2589:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * sequence rank.
- ARM GAS /tmp/ccBGIhL8.s page 153
- 2590:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Depending on devices and packages, some channels may not be available.
- 2591:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Refer to device datasheet for channels availability.
- 2592:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Usage of the returned channel number:
- 2593:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - To reinject this channel into another function LL_ADC_xxx:
- 2594:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * the returned channel number is only partly formatted on definition
- 2595:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
- 2596:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * with parts of literals LL_ADC_CHANNEL_x or using
- 2597:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
- 2598:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Then the selected literal LL_ADC_CHANNEL_x can be used
- 2599:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * as parameter for another function.
- 2600:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - To get the channel number in decimal format:
- 2601:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * process the returned value with the helper macro
- 2602:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
- 2603:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
- 2604:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
- 2605:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
- 2606:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
- 2607:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 2608:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param Rank This parameter can be one of the following values:
- 2609:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_RANK_1
- 2610:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_RANK_2
- 2611:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_RANK_3
- 2612:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_RANK_4
- 2613:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Returned value can be one of the following values:
- 2614:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_0
- 2615:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_1
- 2616:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_2
- 2617:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_3
- 2618:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_4
- 2619:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_5
- 2620:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_6
- 2621:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_7
- 2622:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_8
- 2623:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_9
- 2624:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_10
- 2625:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_11
- 2626:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_12
- 2627:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_13
- 2628:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_14
- 2629:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_15
- 2630:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_16
- 2631:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_17
- 2632:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- 2633:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- 2634:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** *
- 2635:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n
- 2636:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (1) For ADC channel read back from ADC register,
- 2637:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * comparison with internal channel parameter to be done
- 2638:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
- 2639:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 2640:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
- 2641:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 2642:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
- 2643:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2644:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->JSQR,
- 2645:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1
- 2646:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** >> (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))
- ARM GAS /tmp/ccBGIhL8.s page 154
- 2647:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** );
- 2648:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 2649:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2650:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 2651:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Set ADC group injected conversion trigger:
- 2652:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * independent or from ADC group regular.
- 2653:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note This mode can be used to extend number of data registers
- 2654:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * updated after one ADC conversion trigger and with data
- 2655:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * permanently kept (not erased by successive conversions of scan of
- 2656:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * ADC sequencer ranks), up to 5 data registers:
- 2657:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * 1 data register on ADC group regular, 4 data registers
- 2658:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * on ADC group injected.
- 2659:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note If ADC group injected injected trigger source is set to an
- 2660:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * external trigger, this feature must be must be set to
- 2661:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * independent trigger.
- 2662:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * ADC group injected automatic trigger is compliant only with
- 2663:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * group injected trigger source set to SW start, without any
- 2664:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * further action on ADC group injected conversion start or stop:
- 2665:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * in this case, ADC group injected is controlled only
- 2666:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * from ADC group regular.
- 2667:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note It is not possible to enable both ADC group injected
- 2668:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * auto-injected mode and sequencer discontinuous mode.
- 2669:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto
- 2670:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 2671:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param TrigAuto This parameter can be one of the following values:
- 2672:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
- 2673:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
- 2674:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval None
- 2675:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 2676:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
- 2677:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 2678:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);
- 2679:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 2680:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2681:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 2682:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Get ADC group injected conversion trigger:
- 2683:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * independent or from ADC group regular.
- 2684:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto
- 2685:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 2686:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Returned value can be one of the following values:
- 2687:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
- 2688:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
- 2689:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 2690:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
- 2691:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 2692:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));
- 2693:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 2694:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2695:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 2696:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Set ADC group injected offset.
- 2697:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note It sets:
- 2698:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - ADC group injected rank to which the offset programmed
- 2699:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * will be applied
- 2700:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * - Offset level (offset to be subtracted from the raw
- 2701:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * converted data).
- 2702:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Caution: Offset format is dependent to ADC resolution:
- 2703:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * offset has to be left-aligned on bit 11, the LSB (right bits)
- ARM GAS /tmp/ccBGIhL8.s page 155
- 2704:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * are set to 0.
- 2705:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Offset cannot be enabled or disabled.
- 2706:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * To emulate offset disabled, set an offset value equal to 0.
- 2707:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n
- 2708:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n
- 2709:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n
- 2710:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset
- 2711:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 2712:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param Rank This parameter can be one of the following values:
- 2713:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_RANK_1
- 2714:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_RANK_2
- 2715:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_RANK_3
- 2716:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_RANK_4
- 2717:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
- 2718:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval None
- 2719:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 2720:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
- 2721:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 2722:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGO
- 2723:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2724:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** MODIFY_REG(*preg,
- 2725:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ADC_JOFR1_JOFFSET1,
- 2726:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** OffsetLevel);
- 2727:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 2728:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2729:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 2730:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Get ADC group injected offset.
- 2731:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note It gives offset level (offset to be subtracted from the raw converted data).
- 2732:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Caution: Offset format is dependent to ADC resolution:
- 2733:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * offset has to be left-aligned on bit 11, the LSB (right bits)
- 2734:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * are set to 0.
- 2735:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n
- 2736:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n
- 2737:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n
- 2738:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset
- 2739:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 2740:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param Rank This parameter can be one of the following values:
- 2741:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_RANK_1
- 2742:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_RANK_2
- 2743:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_RANK_3
- 2744:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_INJ_RANK_4
- 2745:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
- 2746:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 2747:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
- 2748:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 2749:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGO
- 2750:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2751:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** return (uint32_t)(READ_BIT(*preg,
- 2752:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ADC_JOFR1_JOFFSET1)
- 2753:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** );
- 2754:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 2755:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2756:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 2757:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @}
- 2758:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 2759:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2760:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
- ARM GAS /tmp/ccBGIhL8.s page 156
- 2761:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @{
- 2762:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 2763:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2764:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /**
- 2765:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @brief Set sampling time of the selected ADC channel
- 2766:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Unit: ADC clock cycles.
- 2767:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note On this device, sampling time is on channel scope: independently
- 2768:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * of channel mapped on ADC group regular or injected.
- 2769:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note In case of internal channel (VrefInt, TempSensor, ...) to be
- 2770:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * converted:
- 2771:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * sampling time constraints must be respected (sampling time can be
- 2772:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * adjusted in function of ADC clock frequency and sampling time
- 2773:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * setting).
- 2774:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Refer to device datasheet for timings values (parameters TS_vrefint,
- 2775:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * TS_temp, ...).
- 2776:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note Conversion time is the addition of sampling time and processing time.
- 2777:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Refer to reference manual for ADC processing time of
- 2778:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * this STM32 series.
- 2779:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @note In case of ADC conversion of internal channel (VrefInt,
- 2780:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * temperature sensor, ...), a sampling time minimum value
- 2781:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * is required.
- 2782:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * Refer to device datasheet.
- 2783:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @rmtoll SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n
- 2784:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n
- 2785:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n
- 2786:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n
- 2787:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n
- 2788:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n
- 2789:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n
- 2790:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n
- 2791:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n
- 2792:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n
- 2793:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n
- 2794:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n
- 2795:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n
- 2796:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n
- 2797:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n
- 2798:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n
- 2799:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n
- 2800:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime
- 2801:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param ADCx ADC instance
- 2802:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param Channel This parameter can be one of the following values:
- 2803:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_0
- 2804:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_1
- 2805:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_2
- 2806:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_3
- 2807:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_4
- 2808:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_5
- 2809:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_6
- 2810:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_7
- 2811:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_8
- 2812:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_9
- 2813:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_10
- 2814:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_11
- 2815:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_12
- 2816:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_13
- 2817:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_14
- ARM GAS /tmp/ccBGIhL8.s page 157
- 2818:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_15
- 2819:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_16
- 2820:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_17
- 2821:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- 2822:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- 2823:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** *
- 2824:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * (1) On STM32F1, parameter available only on ADC instance: ADC1.
- 2825:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @param SamplingTime This parameter can be one of the following values:
- 2826:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
- 2827:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
- 2828:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
- 2829:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
- 2830:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
- 2831:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
- 2832:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
- 2833:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
- 2834:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** * @retval None
- 2835:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** */
- 2836:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t Sa
- 2837:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 535 .loc 3 2837 1 is_stmt 1 view -0
- 536 .cfi_startproc
- 537 @ args = 0, pretend = 0, frame = 0
- 538 @ frame_needed = 0, uses_anonymous_args = 0
- 539 .loc 3 2837 1 is_stmt 0 view .LVU130
- 540 0000 30B5 push {r4, r5, lr}
- 541 .LCFI12:
- 542 .cfi_def_cfa_offset 12
- 543 .cfi_offset 4, -12
- 544 .cfi_offset 5, -8
- 545 .cfi_offset 14, -4
- 2838:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Set bits with content of parameter "SamplingTime" with bits position */
- 2839:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* in register and register position depending on parameter "Channel". */
- 2840:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* Parameter "Channel" is used with masks because containing */
- 2841:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** /* other bits reserved for other purpose. */
- 2842:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMP
- 546 .loc 3 2842 3 is_stmt 1 view .LVU131
- 547 .loc 3 2842 25 is_stmt 0 view .LVU132
- 548 0002 0C30 adds r0, r0, #12
- 549 .LVL34:
- 550 .loc 3 2842 25 view .LVU133
- 551 0004 01F0007E and lr, r1, #33554432
- 552 .LVL35:
- 553 .LBB114:
- 554 .LBI114:
- 555 .file 7 "Drivers/CMSIS/Include/cmsis_gcc.h"
- 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
- 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h
- 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file
- 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4
- 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018
- 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/
- 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
- 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- 9:Drivers/CMSIS/Include/cmsis_gcc.h **** *
- 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0
- 11:Drivers/CMSIS/Include/cmsis_gcc.h **** *
- ARM GAS /tmp/ccBGIhL8.s page 158
- 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may
- 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License.
- 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at
- 15:Drivers/CMSIS/Include/cmsis_gcc.h **** *
- 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0
- 17:Drivers/CMSIS/Include/cmsis_gcc.h **** *
- 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software
- 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and
- 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License.
- 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 24:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
- 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
- 27:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
- 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
- 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
- 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
- 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
- 33:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
- 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
- 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0)
- 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 38:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
- 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM
- 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm
- 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE
- 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline
- 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE
- 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline
- 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE
- 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
- 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN
- 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__))
- 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED
- 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used))
- 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK
- 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak))
- 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED
- 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1)))
- 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT
- 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
- 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION
- 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1)))
- ARM GAS /tmp/ccBGIhL8.s page 159
- 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */
- 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
- 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
- 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
- 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; };
- 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
- 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
- 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE
- 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
- 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
- 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
- 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
- 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
- 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
- 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ
- 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
- 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
- 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
- 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
- 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
- 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add
- 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE
- 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
- 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
- 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
- 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
- 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
- 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
- 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ
- 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
- 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
- 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
- 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
- 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
- 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add
- 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED
- 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x)))
- 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT
- 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict
- 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 116:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 117:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */
- 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface
- 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
- 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{
- 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 123:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts
- ARM GAS /tmp/ccBGIhL8.s page 160
- 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
- 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
- 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
- 130:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory");
- 132:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 133:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 134:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts
- 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR.
- 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
- 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
- 141:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory");
- 143:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 144:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 145:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register
- 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register.
- 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value
- 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
- 152:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
- 154:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) );
- 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
- 157:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 158:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 159:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
- 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure)
- 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode.
- 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value
- 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
- 167:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
- 169:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
- 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
- 172:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 174:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 175:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register
- 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register.
- 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set
- 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
- 182:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- ARM GAS /tmp/ccBGIhL8.s page 161
- 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
- 184:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 185:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 186:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
- 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure)
- 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state.
- 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set
- 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
- 194:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
- 196:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 198:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 199:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register
- 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register.
- 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value
- 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
- 206:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
- 208:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
- 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
- 211:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 212:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 213:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register
- 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register.
- 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value
- 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
- 220:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
- 222:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) );
- 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
- 225:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 226:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 227:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register
- 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register.
- 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value
- 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
- 234:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
- 236:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
- 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
- 239:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- ARM GAS /tmp/ccBGIhL8.s page 162
- 240:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 241:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer
- 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP).
- 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value
- 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
- 248:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
- 250:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) );
- 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
- 253:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 254:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 255:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
- 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure)
- 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
- 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value
- 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
- 263:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
- 265:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
- 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
- 268:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 270:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 271:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer
- 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP).
- 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set
- 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
- 278:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
- 280:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 281:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 282:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
- 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure)
- 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
- 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set
- 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
- 290:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
- 292:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 294:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 295:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- ARM GAS /tmp/ccBGIhL8.s page 163
- 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer
- 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP).
- 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value
- 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
- 302:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
- 304:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) );
- 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
- 307:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 308:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 309:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
- 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure)
- 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
- 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value
- 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
- 317:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
- 319:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
- 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
- 322:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 324:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 325:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer
- 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP).
- 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set
- 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
- 332:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
- 334:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 335:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 336:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
- 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure)
- 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
- 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set
- 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
- 344:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
- 346:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 348:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 349:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
- 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure)
- 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
- ARM GAS /tmp/ccBGIhL8.s page 164
- 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value
- 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
- 357:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
- 359:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
- 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
- 362:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 363:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 364:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure)
- 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
- 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set
- 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
- 371:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
- 373:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 375:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 376:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask
- 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register.
- 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value
- 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
- 383:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
- 385:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
- 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
- 388:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 389:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 390:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
- 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure)
- 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg
- 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value
- 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
- 398:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
- 400:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
- 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
- 403:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 405:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 406:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask
- 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register.
- 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask
- ARM GAS /tmp/ccBGIhL8.s page 165
- 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
- 413:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 415:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 416:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 417:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
- 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure)
- 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
- 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask
- 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
- 425:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
- 427:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 429:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 430:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
- 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ
- 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
- 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
- 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void)
- 440:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory");
- 442:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 443:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 444:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ
- 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR.
- 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
- 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void)
- 451:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory");
- 453:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 454:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 455:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority
- 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register.
- 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value
- 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
- 462:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
- 464:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) );
- 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
- 467:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- ARM GAS /tmp/ccBGIhL8.s page 166
- 468:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 469:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
- 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure)
- 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state.
- 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value
- 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
- 477:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
- 479:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
- 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
- 482:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 484:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 485:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority
- 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register.
- 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set
- 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
- 492:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
- 494:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 495:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 496:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
- 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure)
- 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state.
- 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set
- 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
- 504:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
- 506:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 508:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 509:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition
- 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
- 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level.
- 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set
- 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
- 517:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
- 519:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 520:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 521:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask
- 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register.
- ARM GAS /tmp/ccBGIhL8.s page 167
- 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value
- 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
- 528:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
- 530:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
- 533:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 534:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 535:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
- 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure)
- 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state.
- 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value
- 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
- 543:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
- 545:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
- 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
- 548:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 550:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 551:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask
- 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register.
- 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set
- 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
- 558:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
- 560:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 561:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 562:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
- 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure)
- 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state.
- 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set
- 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
- 570:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
- 572:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 574:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
- 578:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 579:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
- ARM GAS /tmp/ccBGIhL8.s page 168
- 582:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit
- 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure
- 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode.
- 588:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
- 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value
- 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
- 593:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI
- 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U;
- 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
- 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
- 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) );
- 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
- 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 603:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 604:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
- 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure)
- 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always.
- 610:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in
- 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value
- 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
- 615:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
- 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI
- 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U;
- 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
- 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
- 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
- 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
- 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 624:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 626:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 627:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit
- 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure
- 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode.
- 633:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
- 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
- 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
- 638:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- ARM GAS /tmp/ccBGIhL8.s page 169
- 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI
- 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit;
- 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
- 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
- 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 646:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 647:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 648:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
- 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure)
- 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored.
- 654:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s
- 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
- 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
- 659:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
- 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI
- 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit;
- 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
- 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
- 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 666:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 668:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 669:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit
- 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure
- 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode.
- 675:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
- 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value
- 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
- 680:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI
- 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U;
- 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
- 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
- 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) );
- 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
- 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 690:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 691:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 692:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
- 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure)
- ARM GAS /tmp/ccBGIhL8.s page 170
- 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always.
- 698:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec
- 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value
- 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
- 703:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
- 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI
- 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U;
- 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
- 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
- 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
- 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
- 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 712:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 714:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 715:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit
- 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure
- 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode.
- 721:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
- 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
- 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
- 726:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI
- 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit;
- 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
- 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
- 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 734:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 735:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 736:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
- 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure)
- 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored.
- 742:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu
- 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set
- 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
- 747:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
- 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI
- 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit;
- 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
- 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
- ARM GAS /tmp/ccBGIhL8.s page 171
- 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 754:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 756:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
- 759:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 760:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR
- 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register.
- 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value
- 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
- 767:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
- 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr)
- 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
- 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
- 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
- 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr();
- 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
- 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
- 777:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
- 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
- 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
- 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U);
- 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 784:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 785:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 786:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR
- 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register.
- 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set
- 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
- 793:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
- 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr)
- 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
- 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
- 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
- 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr);
- 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
- 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
- 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
- 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr;
- 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 807:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 808:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 809:Drivers/CMSIS/Include/cmsis_gcc.h ****
- ARM GAS /tmp/ccBGIhL8.s page 172
- 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
- 811:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 812:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */
- 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
- 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions
- 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{
- 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 818:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
- 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l"
- 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */
- 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
- 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
- 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
- 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
- 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
- 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
- 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
- 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
- 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 831:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation
- 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes.
- 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop")
- 837:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt
- 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
- 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi")
- 843:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 844:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event
- 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter
- 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs.
- 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe")
- 851:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 852:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event
- 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev")
- 858:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 859:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier
- 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor,
- 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory,
- 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed.
- 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
- ARM GAS /tmp/ccBGIhL8.s page 173
- 867:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory");
- 869:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 870:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 871:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier
- 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier.
- 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete.
- 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
- 878:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory");
- 880:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 881:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 882:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier
- 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before
- 886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion.
- 887:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
- 889:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory");
- 891:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 892:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 893:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 894:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 895:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit)
- 896:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785
- 897:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse
- 898:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value
- 899:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
- 901:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
- 903:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value);
- 904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
- 905:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
- 906:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 907:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- 908:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
- 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 910:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 911:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 912:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 913:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 914:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit)
- 915:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes
- 916:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse
- 917:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value
- 918:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
- 920:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 921:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
- 922:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 923:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- ARM GAS /tmp/ccBGIhL8.s page 174
- 924:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
- 925:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 926:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 927:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 928:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 929:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit)
- 930:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam
- 931:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse
- 932:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value
- 933:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
- 935:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- 937:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value);
- 938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
- 939:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result;
- 940:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 941:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- 942:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
- 943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 944:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 945:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 946:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 947:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 948:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit)
- 949:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v
- 950:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate
- 951:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate
- 952:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value
- 953:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
- 955:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 956:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U;
- 957:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U)
- 958:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 959:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1;
- 960:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 961:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2));
- 962:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 963:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 964:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 965:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 966:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint
- 967:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state.
- 968:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula
- 969:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor.
- 970:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break
- 971:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- 972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value)
- 973:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 974:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 975:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
- 976:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value
- 977:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value.
- 978:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse
- 979:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value
- 980:Drivers/CMSIS/Include/cmsis_gcc.h **** */
- ARM GAS /tmp/ccBGIhL8.s page 175
- 981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
- 556 .loc 7 981 31 is_stmt 1 view .LVU134
- 557 .LBB115:
- 982:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 983:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
- 558 .loc 7 983 3 view .LVU135
- 984:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- 986:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- 987:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
- 988:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
- 559 .loc 7 988 4 view .LVU136
- 560 0008 4FF00073 mov r3, #33554432
- 561 .syntax unified
- 562 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
- 563 000c 93FAA3F3 rbit r3, r3
- 564 @ 0 "" 2
- 565 .LVL36:
- 989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
- 990:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
- 991:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 992:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */
- 993:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U)
- 994:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 995:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U;
- 996:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U;
- 997:Drivers/CMSIS/Include/cmsis_gcc.h **** s--;
- 998:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 999:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */
- 1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
- 1001:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
- 566 .loc 7 1001 3 view .LVU137
- 567 .loc 7 1001 3 is_stmt 0 view .LVU138
- 568 .thumb
- 569 .syntax unified
- 570 .LBE115:
- 571 .LBE114:
- 572 .loc 3 2842 25 discriminator 2 view .LVU139
- 573 0010 B3FA83F3 clz r3, r3
- 574 0014 2EFA03FE lsr lr, lr, r3
- 575 .LVL37:
- 2843:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 2844:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** MODIFY_REG(*preg,
- 576 .loc 3 2844 3 is_stmt 1 view .LVU140
- 577 0018 50F82E40 ldr r4, [r0, lr, lsl #2]
- 578 001c 01F0F871 and r1, r1, #32505856
- 579 .LVL38:
- 580 .LBB116:
- 581 .LBI116:
- 981:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 582 .loc 7 981 31 view .LVU141
- 583 .LBB117:
- 983:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 584 .loc 7 983 3 view .LVU142
- 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
- 585 .loc 7 988 4 view .LVU143
- 586 0020 4FF0F873 mov r3, #32505856
- ARM GAS /tmp/ccBGIhL8.s page 176
- 587 .syntax unified
- 588 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
- 589 0024 93FAA3FC rbit ip, r3
- 590 @ 0 "" 2
- 591 .LVL39:
- 592 .loc 7 1001 3 view .LVU144
- 593 .loc 7 1001 3 is_stmt 0 view .LVU145
- 594 .thumb
- 595 .syntax unified
- 596 .LBE117:
- 597 .LBE116:
- 598 .loc 3 2844 3 discriminator 2 view .LVU146
- 599 0028 BCFA8CFC clz ip, ip
- 600 002c 21FA0CFC lsr ip, r1, ip
- 601 0030 0725 movs r5, #7
- 602 0032 05FA0CFC lsl ip, r5, ip
- 603 0036 24EA0C0C bic ip, r4, ip
- 604 .LVL40:
- 605 .LBB118:
- 606 .LBI118:
- 981:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 607 .loc 7 981 31 is_stmt 1 view .LVU147
- 608 .LBB119:
- 983:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 609 .loc 7 983 3 view .LVU148
- 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
- 610 .loc 7 988 4 view .LVU149
- 611 .syntax unified
- 612 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
- 613 003a 93FAA3F3 rbit r3, r3
- 614 @ 0 "" 2
- 615 .LVL41:
- 616 .loc 7 1001 3 view .LVU150
- 617 .loc 7 1001 3 is_stmt 0 view .LVU151
- 618 .thumb
- 619 .syntax unified
- 620 .LBE119:
- 621 .LBE118:
- 622 .loc 3 2844 3 discriminator 4 view .LVU152
- 623 003e B3FA83F3 clz r3, r3
- 624 0042 D940 lsrs r1, r1, r3
- 625 0044 8A40 lsls r2, r2, r1
- 626 .LVL42:
- 627 .loc 3 2844 3 discriminator 4 view .LVU153
- 628 0046 4CEA0202 orr r2, ip, r2
- 629 004a 40F82E20 str r2, [r0, lr, lsl #2]
- 2845:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
- 2846:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
- 2847:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** }
- 630 .loc 3 2847 1 view .LVU154
- 631 004e 30BD pop {r4, r5, pc}
- 632 .cfi_endproc
- 633 .LFE98:
- 635 .section .text.MX_ADC1_Init,"ax",%progbits
- 636 .align 1
- 637 .syntax unified
- 638 .thumb
- ARM GAS /tmp/ccBGIhL8.s page 177
- 639 .thumb_func
- 641 MX_ADC1_Init:
- 642 .LFB657:
- 165:Core/Src/main.c ****
- 643 .loc 1 165 1 is_stmt 1 view -0
- 644 .cfi_startproc
- 645 @ args = 0, pretend = 0, frame = 80
- 646 @ frame_needed = 0, uses_anonymous_args = 0
- 647 0000 F0B5 push {r4, r5, r6, r7, lr}
- 648 .LCFI13:
- 649 .cfi_def_cfa_offset 20
- 650 .cfi_offset 4, -20
- 651 .cfi_offset 5, -16
- 652 .cfi_offset 6, -12
- 653 .cfi_offset 7, -8
- 654 .cfi_offset 14, -4
- 655 0002 95B0 sub sp, sp, #84
- 656 .LCFI14:
- 657 .cfi_def_cfa_offset 104
- 171:Core/Src/main.c **** LL_ADC_CommonInitTypeDef ADC_CommonInitStruct = {0};
- 658 .loc 1 171 3 view .LVU156
- 171:Core/Src/main.c **** LL_ADC_CommonInitTypeDef ADC_CommonInitStruct = {0};
- 659 .loc 1 171 22 is_stmt 0 view .LVU157
- 660 0004 0024 movs r4, #0
- 661 0006 1294 str r4, [sp, #72]
- 662 0008 1394 str r4, [sp, #76]
- 172:Core/Src/main.c **** LL_ADC_REG_InitTypeDef ADC_REG_InitStruct = {0};
- 663 .loc 1 172 3 is_stmt 1 view .LVU158
- 172:Core/Src/main.c **** LL_ADC_REG_InitTypeDef ADC_REG_InitStruct = {0};
- 664 .loc 1 172 28 is_stmt 0 view .LVU159
- 665 000a 1194 str r4, [sp, #68]
- 173:Core/Src/main.c **** LL_ADC_INJ_InitTypeDef ADC_INJ_InitStruct = {0};
- 666 .loc 1 173 3 is_stmt 1 view .LVU160
- 173:Core/Src/main.c **** LL_ADC_INJ_InitTypeDef ADC_INJ_InitStruct = {0};
- 667 .loc 1 173 26 is_stmt 0 view .LVU161
- 668 000c 0C94 str r4, [sp, #48]
- 669 000e 0D94 str r4, [sp, #52]
- 670 0010 0E94 str r4, [sp, #56]
- 671 0012 0F94 str r4, [sp, #60]
- 672 0014 1094 str r4, [sp, #64]
- 174:Core/Src/main.c ****
- 673 .loc 1 174 3 is_stmt 1 view .LVU162
- 174:Core/Src/main.c ****
- 674 .loc 1 174 26 is_stmt 0 view .LVU163
- 675 0016 0894 str r4, [sp, #32]
- 676 0018 0994 str r4, [sp, #36]
- 677 001a 0A94 str r4, [sp, #40]
- 678 001c 0B94 str r4, [sp, #44]
- 176:Core/Src/main.c ****
- 679 .loc 1 176 3 is_stmt 1 view .LVU164
- 176:Core/Src/main.c ****
- 680 .loc 1 176 23 is_stmt 0 view .LVU165
- 681 001e 0394 str r4, [sp, #12]
- 682 0020 0494 str r4, [sp, #16]
- 683 0022 0594 str r4, [sp, #20]
- 684 0024 0694 str r4, [sp, #24]
- 685 0026 0794 str r4, [sp, #28]
- ARM GAS /tmp/ccBGIhL8.s page 178
- 179:Core/Src/main.c ****
- 686 .loc 1 179 3 is_stmt 1 view .LVU166
- 687 .LVL43:
- 688 .LBB120:
- 689 .LBI120:
- 761:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** {
- 690 .loc 5 761 22 view .LVU167
- 691 .LBB121:
- 763:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs);
- 692 .loc 5 763 3 view .LVU168
- 764:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */
- 693 .loc 5 764 3 view .LVU169
- 694 0028 384B ldr r3, .L31
- 695 002a 9A69 ldr r2, [r3, #24]
- 696 002c 42F40072 orr r2, r2, #512
- 697 0030 9A61 str r2, [r3, #24]
- 766:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** (void)tmpreg;
- 698 .loc 5 766 3 view .LVU170
- 766:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** (void)tmpreg;
- 699 .loc 5 766 12 is_stmt 0 view .LVU171
- 700 0032 9A69 ldr r2, [r3, #24]
- 701 0034 02F40072 and r2, r2, #512
- 766:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** (void)tmpreg;
- 702 .loc 5 766 10 view .LVU172
- 703 0038 0292 str r2, [sp, #8]
- 704 .loc 5 767 3 is_stmt 1 view .LVU173
- 705 003a 029A ldr r2, [sp, #8]
- 706 .LVL44:
- 707 .loc 5 767 3 is_stmt 0 view .LVU174
- 708 .LBE121:
- 709 .LBE120:
- 181:Core/Src/main.c **** /**ADC1 GPIO Configuration
- 710 .loc 1 181 3 is_stmt 1 view .LVU175
- 711 .LBB122:
- 712 .LBI122:
- 761:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** {
- 713 .loc 5 761 22 view .LVU176
- 714 .LBB123:
- 763:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs);
- 715 .loc 5 763 3 view .LVU177
- 764:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */
- 716 .loc 5 764 3 view .LVU178
- 717 003c 9A69 ldr r2, [r3, #24]
- 718 003e 42F00402 orr r2, r2, #4
- 719 0042 9A61 str r2, [r3, #24]
- 766:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** (void)tmpreg;
- 720 .loc 5 766 3 view .LVU179
- 766:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** (void)tmpreg;
- 721 .loc 5 766 12 is_stmt 0 view .LVU180
- 722 0044 9B69 ldr r3, [r3, #24]
- 723 0046 03F00403 and r3, r3, #4
- 766:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** (void)tmpreg;
- 724 .loc 5 766 10 view .LVU181
- 725 004a 0193 str r3, [sp, #4]
- 726 .loc 5 767 3 is_stmt 1 view .LVU182
- 727 004c 019B ldr r3, [sp, #4]
- 728 .LVL45:
- ARM GAS /tmp/ccBGIhL8.s page 179
- 729 .loc 5 767 3 is_stmt 0 view .LVU183
- 730 .LBE123:
- 731 .LBE122:
- 186:Core/Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG;
- 732 .loc 1 186 3 is_stmt 1 view .LVU184
- 186:Core/Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG;
- 733 .loc 1 186 23 is_stmt 0 view .LVU185
- 734 004e 41F61803 movw r3, #6168
- 735 0052 0393 str r3, [sp, #12]
- 187:Core/Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- 736 .loc 1 187 3 is_stmt 1 view .LVU186
- 188:Core/Src/main.c ****
- 737 .loc 1 188 3 view .LVU187
- 738 0054 03A9 add r1, sp, #12
- 739 0056 2E48 ldr r0, .L31+4
- 740 0058 FFF7FEFF bl LL_GPIO_Init
- 741 .LVL46:
- 196:Core/Src/main.c **** ADC_InitStruct.SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE;
- 742 .loc 1 196 3 view .LVU188
- 196:Core/Src/main.c **** ADC_InitStruct.SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE;
- 743 .loc 1 196 32 is_stmt 0 view .LVU189
- 744 005c 1294 str r4, [sp, #72]
- 197:Core/Src/main.c **** LL_ADC_Init(ADC1, &ADC_InitStruct);
- 745 .loc 1 197 3 is_stmt 1 view .LVU190
- 197:Core/Src/main.c **** LL_ADC_Init(ADC1, &ADC_InitStruct);
- 746 .loc 1 197 37 is_stmt 0 view .LVU191
- 747 005e 4FF48073 mov r3, #256
- 748 0062 1393 str r3, [sp, #76]
- 198:Core/Src/main.c **** ADC_CommonInitStruct.Multimode = LL_ADC_MULTI_INDEPENDENT;
- 749 .loc 1 198 3 is_stmt 1 view .LVU192
- 750 0064 2B4D ldr r5, .L31+8
- 751 0066 12A9 add r1, sp, #72
- 752 0068 2846 mov r0, r5
- 753 006a FFF7FEFF bl LL_ADC_Init
- 754 .LVL47:
- 199:Core/Src/main.c **** LL_ADC_CommonInit(__LL_ADC_COMMON_INSTANCE(ADC1), &ADC_CommonInitStruct);
- 755 .loc 1 199 3 view .LVU193
- 199:Core/Src/main.c **** LL_ADC_CommonInit(__LL_ADC_COMMON_INSTANCE(ADC1), &ADC_CommonInitStruct);
- 756 .loc 1 199 34 is_stmt 0 view .LVU194
- 757 006e 1194 str r4, [sp, #68]
- 200:Core/Src/main.c **** ADC_REG_InitStruct.TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
- 758 .loc 1 200 3 is_stmt 1 view .LVU195
- 759 0070 11A9 add r1, sp, #68
- 760 0072 2846 mov r0, r5
- 761 0074 FFF7FEFF bl LL_ADC_CommonInit
- 762 .LVL48:
- 201:Core/Src/main.c **** ADC_REG_InitStruct.SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
- 763 .loc 1 201 3 view .LVU196
- 201:Core/Src/main.c **** ADC_REG_InitStruct.SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
- 764 .loc 1 201 36 is_stmt 0 view .LVU197
- 765 0078 4FF46023 mov r3, #917504
- 766 007c 0C93 str r3, [sp, #48]
- 202:Core/Src/main.c **** ADC_REG_InitStruct.SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
- 767 .loc 1 202 3 is_stmt 1 view .LVU198
- 202:Core/Src/main.c **** ADC_REG_InitStruct.SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
- 768 .loc 1 202 38 is_stmt 0 view .LVU199
- 769 007e 0D94 str r4, [sp, #52]
- ARM GAS /tmp/ccBGIhL8.s page 180
- 203:Core/Src/main.c **** ADC_REG_InitStruct.ContinuousMode = LL_ADC_REG_CONV_SINGLE;
- 770 .loc 1 203 3 is_stmt 1 view .LVU200
- 203:Core/Src/main.c **** ADC_REG_InitStruct.ContinuousMode = LL_ADC_REG_CONV_SINGLE;
- 771 .loc 1 203 39 is_stmt 0 view .LVU201
- 772 0080 0E94 str r4, [sp, #56]
- 204:Core/Src/main.c **** ADC_REG_InitStruct.DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
- 773 .loc 1 204 3 is_stmt 1 view .LVU202
- 204:Core/Src/main.c **** ADC_REG_InitStruct.DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
- 774 .loc 1 204 37 is_stmt 0 view .LVU203
- 775 0082 0F94 str r4, [sp, #60]
- 205:Core/Src/main.c **** LL_ADC_REG_Init(ADC1, &ADC_REG_InitStruct);
- 776 .loc 1 205 3 is_stmt 1 view .LVU204
- 205:Core/Src/main.c **** LL_ADC_REG_Init(ADC1, &ADC_REG_InitStruct);
- 777 .loc 1 205 34 is_stmt 0 view .LVU205
- 778 0084 1094 str r4, [sp, #64]
- 206:Core/Src/main.c **** ADC_INJ_InitStruct.TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
- 779 .loc 1 206 3 is_stmt 1 view .LVU206
- 780 0086 0CA9 add r1, sp, #48
- 781 0088 2846 mov r0, r5
- 782 008a FFF7FEFF bl LL_ADC_REG_Init
- 783 .LVL49:
- 207:Core/Src/main.c **** ADC_INJ_InitStruct.SequencerLength = LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS;
- 784 .loc 1 207 3 view .LVU207
- 207:Core/Src/main.c **** ADC_INJ_InitStruct.SequencerLength = LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS;
- 785 .loc 1 207 36 is_stmt 0 view .LVU208
- 786 008e 4FF4E043 mov r3, #28672
- 787 0092 0893 str r3, [sp, #32]
- 208:Core/Src/main.c **** ADC_INJ_InitStruct.SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
- 788 .loc 1 208 3 is_stmt 1 view .LVU209
- 208:Core/Src/main.c **** ADC_INJ_InitStruct.SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
- 789 .loc 1 208 38 is_stmt 0 view .LVU210
- 790 0094 4FF48013 mov r3, #1048576
- 791 0098 0993 str r3, [sp, #36]
- 209:Core/Src/main.c **** ADC_INJ_InitStruct.TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
- 792 .loc 1 209 3 is_stmt 1 view .LVU211
- 209:Core/Src/main.c **** ADC_INJ_InitStruct.TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
- 793 .loc 1 209 39 is_stmt 0 view .LVU212
- 794 009a 0A94 str r4, [sp, #40]
- 210:Core/Src/main.c **** LL_ADC_INJ_Init(ADC1, &ADC_INJ_InitStruct);
- 795 .loc 1 210 3 is_stmt 1 view .LVU213
- 210:Core/Src/main.c **** LL_ADC_INJ_Init(ADC1, &ADC_INJ_InitStruct);
- 796 .loc 1 210 31 is_stmt 0 view .LVU214
- 797 009c 0B94 str r4, [sp, #44]
- 211:Core/Src/main.c ****
- 798 .loc 1 211 3 is_stmt 1 view .LVU215
- 799 009e 08A9 add r1, sp, #32
- 800 00a0 2846 mov r0, r5
- 801 00a2 FFF7FEFF bl LL_ADC_INJ_Init
- 802 .LVL50:
- 215:Core/Src/main.c **** LL_ADC_SetChannelSamplingTime(ADC1, LL_ADC_CHANNEL_3, LL_ADC_SAMPLINGTIME_1CYCLE_5);
- 803 .loc 1 215 3 view .LVU216
- 804 00a6 1C4E ldr r6, .L31+12
- 805 00a8 3246 mov r2, r6
- 806 00aa 0121 movs r1, #1
- 807 00ac 2846 mov r0, r5
- 808 00ae FFF7FEFF bl LL_ADC_INJ_SetSequencerRanks
- 809 .LVL51:
- ARM GAS /tmp/ccBGIhL8.s page 181
- 216:Core/Src/main.c **** LL_ADC_INJ_SetOffset(ADC1, LL_ADC_INJ_RANK_1, 0);
- 810 .loc 1 216 3 view .LVU217
- 811 00b2 2246 mov r2, r4
- 812 00b4 3146 mov r1, r6
- 813 00b6 2846 mov r0, r5
- 814 00b8 FFF7FEFF bl LL_ADC_SetChannelSamplingTime
- 815 .LVL52:
- 217:Core/Src/main.c ****
- 816 .loc 1 217 3 view .LVU218
- 817 .LBB124:
- 818 .LBI124:
- 2720:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 819 .loc 3 2720 22 view .LVU219
- 820 .LBB125:
- 2722:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 821 .loc 3 2722 3 view .LVU220
- 822 .LBB126:
- 823 .LBI126:
- 981:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 824 .loc 7 981 31 view .LVU221
- 825 .LBB127:
- 983:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 826 .loc 7 983 3 view .LVU222
- 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
- 827 .loc 7 988 4 view .LVU223
- 828 00bc 4FF44056 mov r6, #12288
- 829 .syntax unified
- 830 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
- 831 00c0 96FAA6F3 rbit r3, r6
- 832 @ 0 "" 2
- 833 .LVL53:
- 834 .loc 7 1001 3 view .LVU224
- 835 .loc 7 1001 3 is_stmt 0 view .LVU225
- 836 .thumb
- 837 .syntax unified
- 838 .LBE127:
- 839 .LBE126:
- 2724:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ADC_JOFR1_JOFFSET1,
- 840 .loc 3 2724 3 is_stmt 1 view .LVU226
- 841 00c4 154A ldr r2, .L31+16
- 842 00c6 D2F81434 ldr r3, [r2, #1044]
- 843 00ca 6FF30B03 bfc r3, #0, #12
- 844 00ce C2F81434 str r3, [r2, #1044]
- 845 .LVL54:
- 2724:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ADC_JOFR1_JOFFSET1,
- 846 .loc 3 2724 3 is_stmt 0 view .LVU227
- 847 .LBE125:
- 848 .LBE124:
- 221:Core/Src/main.c **** LL_ADC_SetChannelSamplingTime(ADC1, LL_ADC_CHANNEL_4, LL_ADC_SAMPLINGTIME_1CYCLE_5);
- 849 .loc 1 221 3 is_stmt 1 view .LVU228
- 850 00d2 134F ldr r7, .L31+20
- 851 00d4 3A46 mov r2, r7
- 852 00d6 41F20211 movw r1, #4354
- 853 00da 2846 mov r0, r5
- 854 00dc FFF7FEFF bl LL_ADC_INJ_SetSequencerRanks
- 855 .LVL55:
- 222:Core/Src/main.c **** LL_ADC_INJ_SetOffset(ADC1, LL_ADC_INJ_RANK_2, 0);
- ARM GAS /tmp/ccBGIhL8.s page 182
- 856 .loc 1 222 3 view .LVU229
- 857 00e0 2246 mov r2, r4
- 858 00e2 3946 mov r1, r7
- 859 00e4 2846 mov r0, r5
- 860 00e6 FFF7FEFF bl LL_ADC_SetChannelSamplingTime
- 861 .LVL56:
- 223:Core/Src/main.c **** /* USER CODE BEGIN ADC1_Init 2 */
- 862 .loc 1 223 3 view .LVU230
- 863 .LBB128:
- 864 .LBI128:
- 2720:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** {
- 865 .loc 3 2720 22 view .LVU231
- 866 .LBB129:
- 2722:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 867 .loc 3 2722 3 view .LVU232
- 868 .LBB130:
- 869 .LBI130:
- 981:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 870 .loc 7 981 31 view .LVU233
- 871 .LBB131:
- 983:Drivers/CMSIS/Include/cmsis_gcc.h ****
- 872 .loc 7 983 3 view .LVU234
- 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
- 873 .loc 7 988 4 view .LVU235
- 874 .syntax unified
- 875 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
- 876 00ea 96FAA6F6 rbit r6, r6
- 877 @ 0 "" 2
- 878 .LVL57:
- 879 .loc 7 1001 3 view .LVU236
- 880 .loc 7 1001 3 is_stmt 0 view .LVU237
- 881 .thumb
- 882 .syntax unified
- 883 .LBE131:
- 884 .LBE130:
- 2722:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h ****
- 885 .loc 3 2722 25 discriminator 2 view .LVU238
- 886 00ee B6FA86F6 clz r6, r6
- 887 00f2 4FF48053 mov r3, #4096
- 888 00f6 F340 lsrs r3, r3, r6
- 889 00f8 0A49 ldr r1, .L31+24
- 890 .LVL58:
- 2724:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ADC_JOFR1_JOFFSET1,
- 891 .loc 3 2724 3 is_stmt 1 view .LVU239
- 892 00fa 51F82320 ldr r2, [r1, r3, lsl #2]
- 893 00fe 6FF30B02 bfc r2, #0, #12
- 894 0102 41F82320 str r2, [r1, r3, lsl #2]
- 895 .LVL59:
- 2724:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h **** ADC_JOFR1_JOFFSET1,
- 896 .loc 3 2724 3 is_stmt 0 view .LVU240
- 897 .LBE129:
- 898 .LBE128:
- 228:Core/Src/main.c ****
- 899 .loc 1 228 1 view .LVU241
- 900 0106 15B0 add sp, sp, #84
- 901 .LCFI15:
- 902 .cfi_def_cfa_offset 20
- ARM GAS /tmp/ccBGIhL8.s page 183
- 903 @ sp needed
- 904 0108 F0BD pop {r4, r5, r6, r7, pc}
- 905 .L32:
- 906 010a 00BF .align 2
- 907 .L31:
- 908 010c 00100240 .word 1073876992
- 909 0110 00080140 .word 1073809408
- 910 0114 00240140 .word 1073816576
- 911 0118 03009002 .word 42991619
- 912 011c 00200140 .word 1073815552
- 913 0120 0400C002 .word 46137348
- 914 0124 14240140 .word 1073816596
- 915 .cfi_endproc
- 916 .LFE657:
- 918 .section .text.MX_TIM1_Init,"ax",%progbits
- 919 .align 1
- 920 .syntax unified
- 921 .thumb
- 922 .thumb_func
- 924 MX_TIM1_Init:
- 925 .LFB658:
- 236:Core/Src/main.c ****
- 926 .loc 1 236 1 is_stmt 1 view -0
- 927 .cfi_startproc
- 928 @ args = 0, pretend = 0, frame = 104
- 929 @ frame_needed = 0, uses_anonymous_args = 0
- 930 0000 F0B5 push {r4, r5, r6, r7, lr}
- 931 .LCFI16:
- 932 .cfi_def_cfa_offset 20
- 933 .cfi_offset 4, -20
- 934 .cfi_offset 5, -16
- 935 .cfi_offset 6, -12
- 936 .cfi_offset 7, -8
- 937 .cfi_offset 14, -4
- 938 0002 9BB0 sub sp, sp, #108
- 939 .LCFI17:
- 940 .cfi_def_cfa_offset 128
- 242:Core/Src/main.c **** LL_TIM_OC_InitTypeDef TIM_OC_InitStruct = {0};
- 941 .loc 1 242 3 view .LVU243
- 242:Core/Src/main.c **** LL_TIM_OC_InitTypeDef TIM_OC_InitStruct = {0};
- 942 .loc 1 242 22 is_stmt 0 view .LVU244
- 943 0004 0024 movs r4, #0
- 944 0006 1594 str r4, [sp, #84]
- 945 0008 1694 str r4, [sp, #88]
- 946 000a 1794 str r4, [sp, #92]
- 947 000c 1894 str r4, [sp, #96]
- 948 000e 1994 str r4, [sp, #100]
- 243:Core/Src/main.c **** LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct = {0};
- 949 .loc 1 243 3 is_stmt 1 view .LVU245
- 243:Core/Src/main.c **** LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct = {0};
- 950 .loc 1 243 25 is_stmt 0 view .LVU246
- 951 0010 2025 movs r5, #32
- 952 0012 2A46 mov r2, r5
- 953 0014 2146 mov r1, r4
- 954 0016 0DA8 add r0, sp, #52
- 955 0018 FFF7FEFF bl memset
- 956 .LVL60:
- ARM GAS /tmp/ccBGIhL8.s page 184
- 244:Core/Src/main.c ****
- 957 .loc 1 244 3 is_stmt 1 view .LVU247
- 244:Core/Src/main.c ****
- 958 .loc 1 244 27 is_stmt 0 view .LVU248
- 959 001c 0794 str r4, [sp, #28]
- 960 001e 0894 str r4, [sp, #32]
- 961 0020 0994 str r4, [sp, #36]
- 962 0022 0A94 str r4, [sp, #40]
- 963 0024 0B94 str r4, [sp, #44]
- 964 0026 0C94 str r4, [sp, #48]
- 246:Core/Src/main.c ****
- 965 .loc 1 246 3 is_stmt 1 view .LVU249
- 246:Core/Src/main.c ****
- 966 .loc 1 246 23 is_stmt 0 view .LVU250
- 967 0028 0294 str r4, [sp, #8]
- 968 002a 0394 str r4, [sp, #12]
- 969 002c 0494 str r4, [sp, #16]
- 970 002e 0594 str r4, [sp, #20]
- 971 0030 0694 str r4, [sp, #24]
- 249:Core/Src/main.c ****
- 972 .loc 1 249 3 is_stmt 1 view .LVU251
- 973 .LVL61:
- 974 .LBB132:
- 975 .LBI132:
- 761:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** {
- 976 .loc 5 761 22 view .LVU252
- 977 .LBB133:
- 763:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs);
- 978 .loc 5 763 3 view .LVU253
- 764:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */
- 979 .loc 5 764 3 view .LVU254
- 980 0032 444E ldr r6, .L35
- 981 0034 B369 ldr r3, [r6, #24]
- 982 0036 43F40063 orr r3, r3, #2048
- 983 003a B361 str r3, [r6, #24]
- 766:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** (void)tmpreg;
- 984 .loc 5 766 3 view .LVU255
- 766:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** (void)tmpreg;
- 985 .loc 5 766 12 is_stmt 0 view .LVU256
- 986 003c B369 ldr r3, [r6, #24]
- 987 003e 03F40063 and r3, r3, #2048
- 766:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** (void)tmpreg;
- 988 .loc 5 766 10 view .LVU257
- 989 0042 0193 str r3, [sp, #4]
- 990 .loc 5 767 3 is_stmt 1 view .LVU258
- 991 0044 019B ldr r3, [sp, #4]
- 992 .LVL62:
- 993 .loc 5 767 3 is_stmt 0 view .LVU259
- 994 .LBE133:
- 995 .LBE132:
- 254:Core/Src/main.c ****
- 996 .loc 1 254 3 is_stmt 1 view .LVU260
- 997 .LBB134:
- 998 .LBI134:
- 999 .file 8 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h"
- 1:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 2:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** ******************************************************************************
- ARM GAS /tmp/ccBGIhL8.s page 185
- 3:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @file stm32f1xx_ll_dma.h
- 4:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @author MCD Application Team
- 5:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @brief Header file of DMA LL module.
- 6:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** ******************************************************************************
- 7:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @attention
- 8:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** *
- 9:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * Copyright (c) 2016 STMicroelectronics.
- 10:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * All rights reserved.
- 11:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** *
- 12:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * This software is licensed under terms that can be found in the LICENSE file in
- 13:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * the root directory of this software component.
- 14:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * If no LICENSE file comes with this software, it is provided AS-IS.
- 15:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** *
- 16:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** ******************************************************************************
- 17:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 18:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 19:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /* Define to prevent recursive inclusion -------------------------------------*/
- 20:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #ifndef __STM32F1xx_LL_DMA_H
- 21:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define __STM32F1xx_LL_DMA_H
- 22:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 23:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #ifdef __cplusplus
- 24:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** extern "C" {
- 25:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #endif
- 26:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 27:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /* Includes ------------------------------------------------------------------*/
- 28:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #include "stm32f1xx.h"
- 29:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 30:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /** @addtogroup STM32F1xx_LL_Driver
- 31:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @{
- 32:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 33:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 34:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #if defined (DMA1) || defined (DMA2)
- 35:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 36:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /** @defgroup DMA_LL DMA
- 37:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @{
- 38:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 39:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 40:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /* Private types -------------------------------------------------------------*/
- 41:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /* Private variables ---------------------------------------------------------*/
- 42:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /** @defgroup DMA_LL_Private_Variables DMA Private Variables
- 43:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @{
- 44:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 45:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
- 46:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** static const uint8_t CHANNEL_OFFSET_TAB[] =
- 47:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** {
- 48:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
- 49:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
- 50:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
- 51:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
- 52:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
- 53:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
- 54:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
- 55:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** };
- 56:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 57:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @}
- 58:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 59:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /* Private constants ---------------------------------------------------------*/
- ARM GAS /tmp/ccBGIhL8.s page 186
- 60:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /* Private macros ------------------------------------------------------------*/
- 61:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #if defined(USE_FULL_LL_DRIVER)
- 62:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /** @defgroup DMA_LL_Private_Macros DMA Private Macros
- 63:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @{
- 64:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 65:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 66:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @}
- 67:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 68:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #endif /*USE_FULL_LL_DRIVER*/
- 69:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 70:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /* Exported types ------------------------------------------------------------*/
- 71:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #if defined(USE_FULL_LL_DRIVER)
- 72:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
- 73:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @{
- 74:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 75:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** typedef struct
- 76:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** {
- 77:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
- 78:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** or as Source base address in case of memory to memory trans
- 79:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 80:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** This parameter must be a value between Min_Data = 0 and Max
- 81:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 82:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
- 83:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** or as Destination base address in case of memory to memory
- 84:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 85:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** This parameter must be a value between Min_Data = 0 and Max
- 86:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 87:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** uint32_t Direction; /*!< Specifies if the data will be transferred from memory to pe
- 88:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** from memory to memory or from peripheral to memory.
- 89:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_DIRECTION
- 90:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 91:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** This feature can be modified afterwards using unitary funct
- 92:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 93:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** uint32_t Mode; /*!< Specifies the normal or circular operation mode.
- 94:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MODE
- 95:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** @note: The circular buffer mode cannot be used if the memor
- 96:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** data transfer direction is configured on the selecte
- 97:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 98:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** This feature can be modified afterwards using unitary funct
- 99:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 100:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address
- 101:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** is incremented or not.
- 102:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PERIPH
- 103:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 104:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** This feature can be modified afterwards using unitary funct
- 105:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 106:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address
- 107:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** is incremented or not.
- 108:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MEMORY
- 109:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 110:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** This feature can be modified afterwards using unitary funct
- 111:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 112:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data
- 113:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** in case of memory to memory transfer direction.
- 114:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
- 115:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 116:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** This feature can be modified afterwards using unitary funct
- ARM GAS /tmp/ccBGIhL8.s page 187
- 117:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 118:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination dat
- 119:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** in case of memory to memory transfer direction.
- 120:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
- 121:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 122:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** This feature can be modified afterwards using unitary funct
- 123:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 124:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
- 125:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** The data unit is equal to the source buffer configuration s
- 126:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** or MemorySize parameters depending in the transfer directio
- 127:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** This parameter must be a value between Min_Data = 0 and Max
- 128:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 129:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** This feature can be modified afterwards using unitary funct
- 130:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 131:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** uint32_t Priority; /*!< Specifies the channel priority level.
- 132:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PRIORITY
- 133:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 134:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** This feature can be modified afterwards using unitary funct
- 135:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 136:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** } LL_DMA_InitTypeDef;
- 137:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 138:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @}
- 139:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 140:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #endif /*USE_FULL_LL_DRIVER*/
- 141:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 142:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /* Exported constants --------------------------------------------------------*/
- 143:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
- 144:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @{
- 145:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 146:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
- 147:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @brief Flags defines which can be used with LL_DMA_WriteReg function
- 148:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @{
- 149:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 150:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag
- 151:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete fl
- 152:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag
- 153:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag
- 154:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag
- 155:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete fl
- 156:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag
- 157:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag
- 158:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag
- 159:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete fl
- 160:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag
- 161:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag
- 162:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag
- 163:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete fl
- 164:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag
- 165:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag
- 166:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag
- 167:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete fl
- 168:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag
- 169:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag
- 170:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag
- 171:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete fl
- 172:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag
- 173:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag
- ARM GAS /tmp/ccBGIhL8.s page 188
- 174:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag
- 175:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete fl
- 176:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag
- 177:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag
- 178:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 179:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @}
- 180:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 181:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 182:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
- 183:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @brief Flags defines which can be used with LL_DMA_ReadReg function
- 184:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @{
- 185:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 186:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag
- 187:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete fl
- 188:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag
- 189:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag
- 190:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag
- 191:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete fl
- 192:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag
- 193:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag
- 194:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag
- 195:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete fl
- 196:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag
- 197:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag
- 198:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag
- 199:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete fl
- 200:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag
- 201:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag
- 202:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag
- 203:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete fl
- 204:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag
- 205:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag
- 206:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag
- 207:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete fl
- 208:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag
- 209:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag
- 210:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag
- 211:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete fl
- 212:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag
- 213:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag
- 214:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 215:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @}
- 216:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 217:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 218:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /** @defgroup DMA_LL_EC_IT IT Defines
- 219:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
- 220:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @{
- 221:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 222:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
- 223:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
- 224:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
- 225:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 226:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @}
- 227:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 228:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 229:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
- 230:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @{
- ARM GAS /tmp/ccBGIhL8.s page 189
- 231:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 232:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */
- 233:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */
- 234:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */
- 235:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */
- 236:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */
- 237:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */
- 238:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */
- 239:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #if defined(USE_FULL_LL_DRIVER)
- 240:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function
- 241:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #endif /*USE_FULL_LL_DRIVER*/
- 242:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 243:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @}
- 244:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 245:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 246:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
- 247:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @{
- 248:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 249:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory directi
- 250:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral directi
- 251:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction
- 252:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 253:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @}
- 254:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 255:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 256:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MODE Transfer mode
- 257:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @{
- 258:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 259:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode
- 260:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode
- 261:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 262:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @}
- 263:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 264:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 265:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
- 266:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @{
- 267:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 268:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode En
- 269:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Di
- 270:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 271:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @}
- 272:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 273:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 274:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
- 275:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @{
- 276:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 277:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable
- 278:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disabl
- 279:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 280:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @}
- 281:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 282:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 283:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
- 284:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @{
- 285:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 286:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment :
- 287:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment :
- ARM GAS /tmp/ccBGIhL8.s page 190
- 288:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment :
- 289:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 290:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @}
- 291:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 292:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 293:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
- 294:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @{
- 295:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 296:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte
- 297:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : Half
- 298:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word
- 299:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 300:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @}
- 301:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 302:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 303:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
- 304:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @{
- 305:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 306:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low *
- 307:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium *
- 308:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High *
- 309:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High *
- 310:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 311:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @}
- 312:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 313:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 314:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 315:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @}
- 316:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 317:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 318:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /* Exported macro ------------------------------------------------------------*/
- 319:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
- 320:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @{
- 321:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 322:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 323:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
- 324:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @{
- 325:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 326:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 327:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @brief Write a value in DMA register
- 328:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param __INSTANCE__ DMA Instance
- 329:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param __REG__ Register to be written
- 330:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param __VALUE__ Value to be written in the register
- 331:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @retval None
- 332:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 333:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE
- 334:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 335:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 336:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @brief Read a value in DMA register
- 337:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param __INSTANCE__ DMA Instance
- 338:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param __REG__ Register to be read
- 339:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @retval Register value
- 340:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 341:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
- 342:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 343:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @}
- 344:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- ARM GAS /tmp/ccBGIhL8.s page 191
- 345:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 346:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
- 347:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @{
- 348:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 349:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 350:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 351:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @brief Convert DMAx_Channely into DMAx
- 352:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param __CHANNEL_INSTANCE__ DMAx_Channely
- 353:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @retval DMAx
- 354:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 355:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #if defined(DMA2)
- 356:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
- 357:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
- 358:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #else
- 359:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
- 360:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #endif
- 361:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 362:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 363:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
- 364:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param __CHANNEL_INSTANCE__ DMAx_Channely
- 365:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @retval LL_DMA_CHANNEL_y
- 366:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 367:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #if defined (DMA2)
- 368:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
- 369:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
- 370:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
- 371:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
- 372:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
- 373:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
- 374:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
- 375:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
- 376:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
- 377:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
- 378:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
- 379:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
- 380:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** LL_DMA_CHANNEL_7)
- 381:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #else
- 382:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
- 383:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
- 384:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
- 385:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
- 386:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
- 387:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
- 388:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
- 389:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** LL_DMA_CHANNEL_7)
- 390:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #endif
- 391:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 392:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 393:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
- 394:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param __DMA_INSTANCE__ DMAx
- 395:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param __CHANNEL__ LL_DMA_CHANNEL_y
- 396:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @retval DMAx_Channely
- 397:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 398:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #if defined (DMA2)
- 399:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
- 400:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D
- 401:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D
- ARM GAS /tmp/ccBGIhL8.s page 192
- 402:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D
- 403:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D
- 404:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D
- 405:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D
- 406:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D
- 407:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D
- 408:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D
- 409:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D
- 410:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D
- 411:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** DMA1_Channel7)
- 412:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #else
- 413:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
- 414:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D
- 415:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D
- 416:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D
- 417:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D
- 418:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D
- 419:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_D
- 420:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** DMA1_Channel7)
- 421:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** #endif
- 422:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 423:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 424:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @}
- 425:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 426:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 427:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 428:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @}
- 429:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 430:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 431:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /* Exported functions --------------------------------------------------------*/
- 432:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
- 433:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @{
- 434:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 435:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 436:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /** @defgroup DMA_LL_EF_Configuration Configuration
- 437:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @{
- 438:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 439:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 440:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @brief Enable DMA channel.
- 441:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @rmtoll CCR EN LL_DMA_EnableChannel
- 442:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param DMAx DMAx Instance
- 443:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param Channel This parameter can be one of the following values:
- 444:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1
- 445:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2
- 446:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3
- 447:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4
- 448:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5
- 449:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6
- 450:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7
- 451:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @retval None
- 452:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 453:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
- 454:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** {
- 455:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))-
- 456:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** }
- 457:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 458:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- ARM GAS /tmp/ccBGIhL8.s page 193
- 459:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @brief Disable DMA channel.
- 460:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @rmtoll CCR EN LL_DMA_DisableChannel
- 461:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param DMAx DMAx Instance
- 462:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param Channel This parameter can be one of the following values:
- 463:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1
- 464:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2
- 465:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3
- 466:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4
- 467:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5
- 468:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6
- 469:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7
- 470:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @retval None
- 471:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 472:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
- 473:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** {
- 474:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U]))
- 475:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** }
- 476:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 477:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 478:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @brief Check if DMA channel is enabled or disabled.
- 479:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @rmtoll CCR EN LL_DMA_IsEnabledChannel
- 480:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param DMAx DMAx Instance
- 481:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param Channel This parameter can be one of the following values:
- 482:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1
- 483:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2
- 484:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3
- 485:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4
- 486:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5
- 487:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6
- 488:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7
- 489:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @retval State of bit (1 or 0).
- 490:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 491:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
- 492:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** {
- 493:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel
- 494:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** DMA_CCR_EN) == (DMA_CCR_EN));
- 495:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** }
- 496:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 497:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 498:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @brief Configure all parameters link to DMA transfer.
- 499:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
- 500:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * CCR MEM2MEM LL_DMA_ConfigTransfer\n
- 501:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * CCR CIRC LL_DMA_ConfigTransfer\n
- 502:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * CCR PINC LL_DMA_ConfigTransfer\n
- 503:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * CCR MINC LL_DMA_ConfigTransfer\n
- 504:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * CCR PSIZE LL_DMA_ConfigTransfer\n
- 505:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * CCR MSIZE LL_DMA_ConfigTransfer\n
- 506:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * CCR PL LL_DMA_ConfigTransfer
- 507:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param DMAx DMAx Instance
- 508:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param Channel This parameter can be one of the following values:
- 509:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1
- 510:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2
- 511:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3
- 512:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4
- 513:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5
- 514:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6
- 515:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7
- ARM GAS /tmp/ccBGIhL8.s page 194
- 516:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param Configuration This parameter must be a combination of all the following values:
- 517:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH o
- 518:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
- 519:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
- 520:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
- 521:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDAT
- 522:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDAT
- 523:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HI
- 524:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @retval None
- 525:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 526:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configurat
- 527:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** {
- 528:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])
- 529:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_P
- 530:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** Configuration);
- 531:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** }
- 532:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 533:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 534:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @brief Set Data transfer direction (read from peripheral or from memory).
- 535:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
- 536:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * CCR MEM2MEM LL_DMA_SetDataTransferDirection
- 537:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param DMAx DMAx Instance
- 538:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param Channel This parameter can be one of the following values:
- 539:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1
- 540:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2
- 541:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3
- 542:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4
- 543:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5
- 544:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6
- 545:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7
- 546:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param Direction This parameter can be one of the following values:
- 547:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
- 548:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
- 549:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
- 550:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @retval None
- 551:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 552:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t
- 1000 .loc 8 552 22 view .LVU261
- 1001 .LBB135:
- 553:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** {
- 554:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])
- 1002 .loc 8 554 3 view .LVU262
- 1003 0046 404B ldr r3, .L35+4
- 1004 0048 9A6D ldr r2, [r3, #88]
- 1005 004a 22F48042 bic r2, r2, #16384
- 1006 004e 22F01002 bic r2, r2, #16
- 1007 0052 42F01002 orr r2, r2, #16
- 1008 0056 9A65 str r2, [r3, #88]
- 1009 .LVL63:
- 1010 .loc 8 554 3 is_stmt 0 view .LVU263
- 1011 .LBE135:
- 1012 .LBE134:
- 256:Core/Src/main.c ****
- 1013 .loc 1 256 3 is_stmt 1 view .LVU264
- 1014 .LBB136:
- 1015 .LBI136:
- 555:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
- ARM GAS /tmp/ccBGIhL8.s page 195
- 556:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** }
- 557:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 558:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 559:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @brief Get Data transfer direction (read from peripheral or from memory).
- 560:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
- 561:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * CCR MEM2MEM LL_DMA_GetDataTransferDirection
- 562:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param DMAx DMAx Instance
- 563:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param Channel This parameter can be one of the following values:
- 564:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1
- 565:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2
- 566:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3
- 567:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4
- 568:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5
- 569:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6
- 570:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7
- 571:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @retval Returned value can be one of the following values:
- 572:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
- 573:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
- 574:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
- 575:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 576:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
- 577:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** {
- 578:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel
- 579:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** DMA_CCR_DIR | DMA_CCR_MEM2MEM));
- 580:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** }
- 581:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 582:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 583:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @brief Set DMA mode circular or normal.
- 584:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @note The circular buffer mode cannot be used if the memory-to-memory
- 585:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * data transfer is configured on the selected Channel.
- 586:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @rmtoll CCR CIRC LL_DMA_SetMode
- 587:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param DMAx DMAx Instance
- 588:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param Channel This parameter can be one of the following values:
- 589:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1
- 590:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2
- 591:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3
- 592:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4
- 593:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5
- 594:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6
- 595:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7
- 596:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param Mode This parameter can be one of the following values:
- 597:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_NORMAL
- 598:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_CIRCULAR
- 599:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @retval None
- 600:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 601:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
- 602:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** {
- 603:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])
- 604:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** Mode);
- 605:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** }
- 606:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 607:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 608:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @brief Get DMA mode circular or normal.
- 609:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @rmtoll CCR CIRC LL_DMA_GetMode
- 610:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param DMAx DMAx Instance
- 611:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param Channel This parameter can be one of the following values:
- 612:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1
- ARM GAS /tmp/ccBGIhL8.s page 196
- 613:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2
- 614:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3
- 615:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4
- 616:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5
- 617:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6
- 618:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7
- 619:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @retval Returned value can be one of the following values:
- 620:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_NORMAL
- 621:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_CIRCULAR
- 622:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 623:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
- 624:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** {
- 625:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel
- 626:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** DMA_CCR_CIRC));
- 627:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** }
- 628:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 629:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 630:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @brief Set Peripheral increment mode.
- 631:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
- 632:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param DMAx DMAx Instance
- 633:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param Channel This parameter can be one of the following values:
- 634:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1
- 635:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2
- 636:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3
- 637:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4
- 638:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5
- 639:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6
- 640:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7
- 641:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
- 642:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_INCREMENT
- 643:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_NOINCREMENT
- 644:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @retval None
- 645:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 646:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOr
- 647:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** {
- 648:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])
- 649:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** PeriphOrM2MSrcIncMode);
- 650:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** }
- 651:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 652:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 653:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @brief Get Peripheral increment mode.
- 654:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
- 655:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param DMAx DMAx Instance
- 656:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param Channel This parameter can be one of the following values:
- 657:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1
- 658:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2
- 659:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3
- 660:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4
- 661:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5
- 662:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6
- 663:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7
- 664:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @retval Returned value can be one of the following values:
- 665:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_INCREMENT
- 666:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_NOINCREMENT
- 667:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 668:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
- 669:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** {
- ARM GAS /tmp/ccBGIhL8.s page 197
- 670:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel
- 671:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** DMA_CCR_PINC));
- 672:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** }
- 673:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 674:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 675:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @brief Set Memory increment mode.
- 676:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
- 677:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param DMAx DMAx Instance
- 678:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param Channel This parameter can be one of the following values:
- 679:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1
- 680:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2
- 681:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3
- 682:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4
- 683:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5
- 684:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6
- 685:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7
- 686:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
- 687:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_INCREMENT
- 688:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_NOINCREMENT
- 689:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @retval None
- 690:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 691:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOr
- 692:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** {
- 693:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])
- 694:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** MemoryOrM2MDstIncMode);
- 695:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** }
- 696:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 697:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 698:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @brief Get Memory increment mode.
- 699:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
- 700:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param DMAx DMAx Instance
- 701:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param Channel This parameter can be one of the following values:
- 702:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1
- 703:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2
- 704:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3
- 705:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4
- 706:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5
- 707:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6
- 708:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7
- 709:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @retval Returned value can be one of the following values:
- 710:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_INCREMENT
- 711:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_NOINCREMENT
- 712:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 713:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
- 714:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** {
- 715:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel
- 716:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** DMA_CCR_MINC));
- 717:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** }
- 718:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 719:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 720:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @brief Set Peripheral size.
- 721:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
- 722:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param DMAx DMAx Instance
- 723:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param Channel This parameter can be one of the following values:
- 724:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1
- 725:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2
- 726:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3
- ARM GAS /tmp/ccBGIhL8.s page 198
- 727:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4
- 728:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5
- 729:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6
- 730:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7
- 731:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
- 732:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_BYTE
- 733:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
- 734:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_WORD
- 735:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @retval None
- 736:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 737:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2M
- 738:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** {
- 739:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])
- 740:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** PeriphOrM2MSrcDataSize);
- 741:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** }
- 742:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 743:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 744:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @brief Get Peripheral size.
- 745:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
- 746:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param DMAx DMAx Instance
- 747:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param Channel This parameter can be one of the following values:
- 748:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1
- 749:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2
- 750:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3
- 751:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4
- 752:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5
- 753:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6
- 754:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7
- 755:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @retval Returned value can be one of the following values:
- 756:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_BYTE
- 757:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
- 758:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_WORD
- 759:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 760:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
- 761:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** {
- 762:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel
- 763:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** DMA_CCR_PSIZE));
- 764:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** }
- 765:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 766:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 767:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @brief Set Memory size.
- 768:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
- 769:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param DMAx DMAx Instance
- 770:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param Channel This parameter can be one of the following values:
- 771:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1
- 772:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2
- 773:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3
- 774:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4
- 775:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5
- 776:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6
- 777:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7
- 778:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
- 779:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_BYTE
- 780:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
- 781:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_WORD
- 782:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @retval None
- 783:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- ARM GAS /tmp/ccBGIhL8.s page 199
- 784:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2M
- 785:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** {
- 786:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])
- 787:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** MemoryOrM2MDstDataSize);
- 788:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** }
- 789:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 790:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 791:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @brief Get Memory size.
- 792:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
- 793:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param DMAx DMAx Instance
- 794:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param Channel This parameter can be one of the following values:
- 795:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1
- 796:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2
- 797:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3
- 798:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4
- 799:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5
- 800:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6
- 801:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7
- 802:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @retval Returned value can be one of the following values:
- 803:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_BYTE
- 804:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
- 805:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_WORD
- 806:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 807:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
- 808:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** {
- 809:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel
- 810:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** DMA_CCR_MSIZE));
- 811:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** }
- 812:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h ****
- 813:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** /**
- 814:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @brief Set Channel priority level.
- 815:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
- 816:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param DMAx DMAx Instance
- 817:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param Channel This parameter can be one of the following values:
- 818:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1
- 819:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2
- 820:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3
- 821:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4
- 822:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5
- 823:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6
- 824:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7
- 825:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @param Priority This parameter can be one of the following values:
- 826:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_LOW
- 827:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_MEDIUM
- 828:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_HIGH
- 829:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_VERYHIGH
- 830:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** * @retval None
- 831:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** */
- 832:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t P
- 1016 .loc 8 832 22 view .LVU265
- 1017 .LBB137:
- 833:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** {
- 834:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])
- 1018 .loc 8 834 3 view .LVU266
- 1019 0058 9A6D ldr r2, [r3, #88]
- 1020 005a 22F44052 bic r2, r2, #12288
- 1021 005e 9A65 str r2, [r3, #88]
- ARM GAS /tmp/ccBGIhL8.s page 200
- 1022 .LVL64:
- 1023 .loc 8 834 3 is_stmt 0 view .LVU267
- 1024 .LBE137:
- 1025 .LBE136:
- 258:Core/Src/main.c ****
- 1026 .loc 1 258 3 is_stmt 1 view .LVU268
- 1027 .LBB138:
- 1028 .LBI138:
- 601:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** {
- 1029 .loc 8 601 22 view .LVU269
- 1030 .LBB139:
- 603:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** Mode);
- 1031 .loc 8 603 3 view .LVU270
- 1032 0060 9A6D ldr r2, [r3, #88]
- 1033 0062 22F02002 bic r2, r2, #32
- 1034 0066 9A65 str r2, [r3, #88]
- 1035 .LVL65:
- 603:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** Mode);
- 1036 .loc 8 603 3 is_stmt 0 view .LVU271
- 1037 .LBE139:
- 1038 .LBE138:
- 260:Core/Src/main.c ****
- 1039 .loc 1 260 3 is_stmt 1 view .LVU272
- 1040 .LBB140:
- 1041 .LBI140:
- 646:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** {
- 1042 .loc 8 646 22 view .LVU273
- 1043 .LBB141:
- 648:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** PeriphOrM2MSrcIncMode);
- 1044 .loc 8 648 3 view .LVU274
- 1045 0068 9A6D ldr r2, [r3, #88]
- 1046 006a 22F04002 bic r2, r2, #64
- 1047 006e 9A65 str r2, [r3, #88]
- 1048 .LVL66:
- 648:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** PeriphOrM2MSrcIncMode);
- 1049 .loc 8 648 3 is_stmt 0 view .LVU275
- 1050 .LBE141:
- 1051 .LBE140:
- 262:Core/Src/main.c ****
- 1052 .loc 1 262 3 is_stmt 1 view .LVU276
- 1053 .LBB142:
- 1054 .LBI142:
- 691:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** {
- 1055 .loc 8 691 22 view .LVU277
- 1056 .LBB143:
- 693:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** MemoryOrM2MDstIncMode);
- 1057 .loc 8 693 3 view .LVU278
- 1058 0070 9A6D ldr r2, [r3, #88]
- 1059 0072 42F08002 orr r2, r2, #128
- 1060 0076 9A65 str r2, [r3, #88]
- 1061 .LVL67:
- 693:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** MemoryOrM2MDstIncMode);
- 1062 .loc 8 693 3 is_stmt 0 view .LVU279
- 1063 .LBE143:
- 1064 .LBE142:
- 264:Core/Src/main.c ****
- 1065 .loc 1 264 3 is_stmt 1 view .LVU280
- ARM GAS /tmp/ccBGIhL8.s page 201
- 1066 .LBB144:
- 1067 .LBI144:
- 737:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** {
- 1068 .loc 8 737 22 view .LVU281
- 1069 .LBB145:
- 739:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** PeriphOrM2MSrcDataSize);
- 1070 .loc 8 739 3 view .LVU282
- 1071 0078 9A6D ldr r2, [r3, #88]
- 1072 007a 22F44072 bic r2, r2, #768
- 1073 007e 42F40072 orr r2, r2, #512
- 1074 0082 9A65 str r2, [r3, #88]
- 1075 .LVL68:
- 739:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** PeriphOrM2MSrcDataSize);
- 1076 .loc 8 739 3 is_stmt 0 view .LVU283
- 1077 .LBE145:
- 1078 .LBE144:
- 266:Core/Src/main.c ****
- 1079 .loc 1 266 3 is_stmt 1 view .LVU284
- 1080 .LBB146:
- 1081 .LBI146:
- 784:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** {
- 1082 .loc 8 784 22 view .LVU285
- 1083 .LBB147:
- 786:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** MemoryOrM2MDstDataSize);
- 1084 .loc 8 786 3 view .LVU286
- 1085 0084 9A6D ldr r2, [r3, #88]
- 1086 0086 22F44062 bic r2, r2, #3072
- 1087 008a 42F40062 orr r2, r2, #2048
- 1088 008e 9A65 str r2, [r3, #88]
- 1089 .LVL69:
- 786:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h **** MemoryOrM2MDstDataSize);
- 1090 .loc 8 786 3 is_stmt 0 view .LVU287
- 1091 .LBE147:
- 1092 .LBE146:
- 271:Core/Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_CENTER_DOWN;
- 1093 .loc 1 271 3 is_stmt 1 view .LVU288
- 271:Core/Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_CENTER_DOWN;
- 1094 .loc 1 271 28 is_stmt 0 view .LVU289
- 1095 0090 4FF49653 mov r3, #4800
- 1096 0094 ADF85430 strh r3, [sp, #84] @ movhi
- 272:Core/Src/main.c **** TIM_InitStruct.Autoreload = 100;
- 1097 .loc 1 272 3 is_stmt 1 view .LVU290
- 272:Core/Src/main.c **** TIM_InitStruct.Autoreload = 100;
- 1098 .loc 1 272 30 is_stmt 0 view .LVU291
- 1099 0098 1695 str r5, [sp, #88]
- 273:Core/Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
- 1100 .loc 1 273 3 is_stmt 1 view .LVU292
- 273:Core/Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
- 1101 .loc 1 273 29 is_stmt 0 view .LVU293
- 1102 009a 6423 movs r3, #100
- 1103 009c 1793 str r3, [sp, #92]
- 274:Core/Src/main.c **** TIM_InitStruct.RepetitionCounter = 1;
- 1104 .loc 1 274 3 is_stmt 1 view .LVU294
- 274:Core/Src/main.c **** TIM_InitStruct.RepetitionCounter = 1;
- 1105 .loc 1 274 32 is_stmt 0 view .LVU295
- 1106 009e 1894 str r4, [sp, #96]
- 275:Core/Src/main.c **** LL_TIM_Init(TIM1, &TIM_InitStruct);
- ARM GAS /tmp/ccBGIhL8.s page 202
- 1107 .loc 1 275 3 is_stmt 1 view .LVU296
- 275:Core/Src/main.c **** LL_TIM_Init(TIM1, &TIM_InitStruct);
- 1108 .loc 1 275 36 is_stmt 0 view .LVU297
- 1109 00a0 0127 movs r7, #1
- 1110 00a2 1997 str r7, [sp, #100]
- 276:Core/Src/main.c **** LL_TIM_DisableARRPreload(TIM1);
- 1111 .loc 1 276 3 is_stmt 1 view .LVU298
- 1112 00a4 294D ldr r5, .L35+8
- 1113 00a6 15A9 add r1, sp, #84
- 1114 00a8 2846 mov r0, r5
- 1115 00aa FFF7FEFF bl LL_TIM_Init
- 1116 .LVL70:
- 277:Core/Src/main.c **** LL_TIM_SetClockSource(TIM1, LL_TIM_CLOCKSOURCE_INTERNAL);
- 1117 .loc 1 277 3 view .LVU299
- 1118 .LBB148:
- 1119 .LBI148:
- 1245:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1120 .loc 4 1245 22 view .LVU300
- 1121 .LBB149:
- 1247:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1122 .loc 4 1247 3 view .LVU301
- 1123 00ae 2B68 ldr r3, [r5]
- 1124 00b0 23F08003 bic r3, r3, #128
- 1125 00b4 2B60 str r3, [r5]
- 1126 .LVL71:
- 1247:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1127 .loc 4 1247 3 is_stmt 0 view .LVU302
- 1128 .LBE149:
- 1129 .LBE148:
- 278:Core/Src/main.c **** TIM_OC_InitStruct.OCMode = LL_TIM_OCMODE_TOGGLE;
- 1130 .loc 1 278 3 is_stmt 1 view .LVU303
- 1131 .LBB150:
- 1132 .LBI150:
- 1851:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1852:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1853:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Indicates whether fast mode is enabled for the output channel.
- 1854:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
- 1855:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
- 1856:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
- 1857:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
- 1858:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1859:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Channel This parameter can be one of the following values:
- 1860:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- 1861:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- 1862:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 1863:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- 1864:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval State of bit (1 or 0).
- 1865:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1866:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
- 1867:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1868:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 1869:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC
- 1870:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
- 1871:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
- 1872:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1873:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1874:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- ARM GAS /tmp/ccBGIhL8.s page 203
- 1875:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
- 1876:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
- 1877:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
- 1878:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
- 1879:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 OC4PE LL_TIM_OC_EnablePreload
- 1880:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1881:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Channel This parameter can be one of the following values:
- 1882:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- 1883:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- 1884:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 1885:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- 1886:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1887:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1888:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
- 1889:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1890:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 1891:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
- 1892:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
- 1893:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1894:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1895:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1896:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
- 1897:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
- 1898:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
- 1899:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
- 1900:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 OC4PE LL_TIM_OC_DisablePreload
- 1901:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1902:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Channel This parameter can be one of the following values:
- 1903:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- 1904:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- 1905:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 1906:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- 1907:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1908:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1909:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
- 1910:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1911:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 1912:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
- 1913:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
- 1914:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1915:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1916:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1917:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channe
- 1918:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
- 1919:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
- 1920:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
- 1921:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
- 1922:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1923:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Channel This parameter can be one of the following values:
- 1924:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- 1925:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- 1926:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 1927:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- 1928:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval State of bit (1 or 0).
- 1929:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1930:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
- 1931:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- ARM GAS /tmp/ccBGIhL8.s page 204
- 1932:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 1933:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC
- 1934:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
- 1935:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
- 1936:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1937:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1938:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1939:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Enable clearing the output channel on an external event.
- 1940:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note This function can only be used in Output compare and PWM modes. It does not work in Force
- 1941:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
- 1942:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * or not a timer instance can clear the OCxREF signal on an external event.
- 1943:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
- 1944:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
- 1945:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
- 1946:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 OC4CE LL_TIM_OC_EnableClear
- 1947:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1948:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Channel This parameter can be one of the following values:
- 1949:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- 1950:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- 1951:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 1952:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- 1953:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1954:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1955:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
- 1956:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1957:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 1958:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
- 1959:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
- 1960:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1961:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1962:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1963:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Disable clearing the output channel on an external event.
- 1964:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
- 1965:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * or not a timer instance can clear the OCxREF signal on an external event.
- 1966:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
- 1967:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
- 1968:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
- 1969:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 OC4CE LL_TIM_OC_DisableClear
- 1970:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1971:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Channel This parameter can be one of the following values:
- 1972:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- 1973:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- 1974:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 1975:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- 1976:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 1977:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 1978:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
- 1979:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 1980:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 1981:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
- 1982:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
- 1983:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 1984:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 1985:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 1986:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Indicates clearing the output channel on an external event is enabled for the output ch
- 1987:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note This function enables clearing the output channel on an external event.
- 1988:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note This function can only be used in Output compare and PWM modes. It does not work in Force
- ARM GAS /tmp/ccBGIhL8.s page 205
- 1989:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
- 1990:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * or not a timer instance can clear the OCxREF signal on an external event.
- 1991:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
- 1992:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
- 1993:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
- 1994:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
- 1995:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 1996:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Channel This parameter can be one of the following values:
- 1997:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- 1998:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- 1999:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 2000:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- 2001:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval State of bit (1 or 0).
- 2002:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2003:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
- 2004:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2005:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 2006:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC
- 2007:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
- 2008:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
- 2009:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2010:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2011:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2012:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal an
- 2013:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * the Ocx and OCxN signals).
- 2014:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- 2015:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * dead-time insertion feature is supported by a timer instance.
- 2016:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
- 2017:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
- 2018:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2019:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param DeadTime between Min_Data=0 and Max_Data=255
- 2020:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 2021:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2022:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
- 2023:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2024:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
- 2025:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2026:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2027:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2028:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Set compare value for output channel 1 (TIMx_CCR1).
- 2029:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
- 2030:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * output channel 1 is supported by a timer instance.
- 2031:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
- 2032:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2033:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535
- 2034:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 2035:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2036:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
- 2037:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2038:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** WRITE_REG(TIMx->CCR1, CompareValue);
- 2039:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2040:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2041:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2042:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Set compare value for output channel 2 (TIMx_CCR2).
- 2043:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
- 2044:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * output channel 2 is supported by a timer instance.
- 2045:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
- ARM GAS /tmp/ccBGIhL8.s page 206
- 2046:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2047:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535
- 2048:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 2049:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2050:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
- 2051:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2052:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** WRITE_REG(TIMx->CCR2, CompareValue);
- 2053:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2054:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2055:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2056:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Set compare value for output channel 3 (TIMx_CCR3).
- 2057:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
- 2058:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * output channel is supported by a timer instance.
- 2059:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
- 2060:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2061:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535
- 2062:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 2063:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2064:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
- 2065:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2066:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** WRITE_REG(TIMx->CCR3, CompareValue);
- 2067:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2068:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2069:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2070:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Set compare value for output channel 4 (TIMx_CCR4).
- 2071:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
- 2072:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * output channel 4 is supported by a timer instance.
- 2073:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
- 2074:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2075:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535
- 2076:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 2077:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2078:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
- 2079:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2080:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** WRITE_REG(TIMx->CCR4, CompareValue);
- 2081:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2082:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2083:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2084:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR1) set for output channel 1.
- 2085:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
- 2086:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * output channel 1 is supported by a timer instance.
- 2087:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
- 2088:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2089:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
- 2090:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2091:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
- 2092:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2093:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR1));
- 2094:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2095:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2096:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2097:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR2) set for output channel 2.
- 2098:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
- 2099:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * output channel 2 is supported by a timer instance.
- 2100:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
- 2101:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2102:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
- ARM GAS /tmp/ccBGIhL8.s page 207
- 2103:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2104:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
- 2105:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2106:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR2));
- 2107:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2108:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2109:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2110:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR3) set for output channel 3.
- 2111:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
- 2112:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * output channel 3 is supported by a timer instance.
- 2113:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
- 2114:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2115:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
- 2116:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2117:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
- 2118:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2119:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR3));
- 2120:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2121:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2122:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2123:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR4) set for output channel 4.
- 2124:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
- 2125:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * output channel 4 is supported by a timer instance.
- 2126:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
- 2127:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2128:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
- 2129:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2130:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
- 2131:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2132:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR4));
- 2133:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2134:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2135:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2136:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 2137:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2138:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2139:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
- 2140:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 2141:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2142:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2143:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Configure input channel.
- 2144:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
- 2145:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR1 IC1PSC LL_TIM_IC_Config\n
- 2146:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR1 IC1F LL_TIM_IC_Config\n
- 2147:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_IC_Config\n
- 2148:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR1 IC2PSC LL_TIM_IC_Config\n
- 2149:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR1 IC2F LL_TIM_IC_Config\n
- 2150:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_IC_Config\n
- 2151:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 IC3PSC LL_TIM_IC_Config\n
- 2152:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 IC3F LL_TIM_IC_Config\n
- 2153:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_IC_Config\n
- 2154:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 IC4PSC LL_TIM_IC_Config\n
- 2155:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 IC4F LL_TIM_IC_Config\n
- 2156:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC1P LL_TIM_IC_Config\n
- 2157:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC1NP LL_TIM_IC_Config\n
- 2158:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC2P LL_TIM_IC_Config\n
- 2159:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC2NP LL_TIM_IC_Config\n
- ARM GAS /tmp/ccBGIhL8.s page 208
- 2160:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC3P LL_TIM_IC_Config\n
- 2161:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC3NP LL_TIM_IC_Config\n
- 2162:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC4P LL_TIM_IC_Config\n
- 2163:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2164:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Channel This parameter can be one of the following values:
- 2165:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- 2166:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- 2167:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 2168:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- 2169:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Configuration This parameter must be a combination of all the following values:
- 2170:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_
- 2171:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
- 2172:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
- 2173:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING
- 2174:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 2175:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2176:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
- 2177:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2178:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 2179:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
- 2180:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChanne
- 2181:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))
- 2182:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** << SHIFT_TAB_ICxx[iChannel]);
- 2183:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
- 2184:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
- 2185:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2186:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2187:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2188:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Set the active input.
- 2189:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
- 2190:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
- 2191:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
- 2192:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_IC_SetActiveInput
- 2193:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2194:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Channel This parameter can be one of the following values:
- 2195:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- 2196:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- 2197:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 2198:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- 2199:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param ICActiveInput This parameter can be one of the following values:
- 2200:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
- 2201:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
- 2202:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_TRC
- 2203:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 2204:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2205:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiv
- 2206:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2207:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 2208:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
- 2209:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT
- 2210:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2211:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2212:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2213:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Get the current active input.
- 2214:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
- 2215:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
- 2216:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
- ARM GAS /tmp/ccBGIhL8.s page 209
- 2217:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_IC_GetActiveInput
- 2218:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2219:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Channel This parameter can be one of the following values:
- 2220:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- 2221:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- 2222:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 2223:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- 2224:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval Returned value can be one of the following values:
- 2225:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
- 2226:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
- 2227:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_TRC
- 2228:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2229:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
- 2230:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2231:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 2232:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC
- 2233:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChann
- 2234:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2235:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2236:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2237:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Set the prescaler of input channel.
- 2238:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
- 2239:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
- 2240:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
- 2241:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
- 2242:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2243:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Channel This parameter can be one of the following values:
- 2244:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- 2245:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- 2246:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 2247:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- 2248:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param ICPrescaler This parameter can be one of the following values:
- 2249:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1
- 2250:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV2
- 2251:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV4
- 2252:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV8
- 2253:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 2254:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2255:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescal
- 2256:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2257:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 2258:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
- 2259:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT
- 2260:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2261:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2262:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2263:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Get the current prescaler value acting on an input channel.
- 2264:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
- 2265:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
- 2266:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
- 2267:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
- 2268:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2269:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Channel This parameter can be one of the following values:
- 2270:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- 2271:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- 2272:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 2273:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- ARM GAS /tmp/ccBGIhL8.s page 210
- 2274:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval Returned value can be one of the following values:
- 2275:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1
- 2276:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV2
- 2277:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV4
- 2278:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV8
- 2279:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2280:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
- 2281:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2282:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 2283:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC
- 2284:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iCha
- 2285:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2286:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2287:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2288:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Set the input filter duration.
- 2289:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
- 2290:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR1 IC2F LL_TIM_IC_SetFilter\n
- 2291:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 IC3F LL_TIM_IC_SetFilter\n
- 2292:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 IC4F LL_TIM_IC_SetFilter
- 2293:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2294:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Channel This parameter can be one of the following values:
- 2295:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- 2296:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- 2297:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 2298:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- 2299:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param ICFilter This parameter can be one of the following values:
- 2300:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1
- 2301:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
- 2302:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
- 2303:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
- 2304:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
- 2305:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
- 2306:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
- 2307:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
- 2308:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
- 2309:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
- 2310:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
- 2311:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
- 2312:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
- 2313:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
- 2314:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
- 2315:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
- 2316:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 2317:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2318:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
- 2319:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2320:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 2321:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC
- 2322:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_
- 2323:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2324:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2325:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2326:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Get the input filter duration.
- 2327:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
- 2328:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR1 IC2F LL_TIM_IC_GetFilter\n
- 2329:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 IC3F LL_TIM_IC_GetFilter\n
- 2330:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCMR2 IC4F LL_TIM_IC_GetFilter
- ARM GAS /tmp/ccBGIhL8.s page 211
- 2331:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2332:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Channel This parameter can be one of the following values:
- 2333:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- 2334:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- 2335:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 2336:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- 2337:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval Returned value can be one of the following values:
- 2338:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1
- 2339:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
- 2340:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
- 2341:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
- 2342:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
- 2343:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
- 2344:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
- 2345:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
- 2346:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
- 2347:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
- 2348:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
- 2349:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
- 2350:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
- 2351:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
- 2352:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
- 2353:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
- 2354:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2355:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
- 2356:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2357:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 2358:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC
- 2359:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChann
- 2360:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2361:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2362:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2363:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Set the input channel polarity.
- 2364:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
- 2365:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC1NP LL_TIM_IC_SetPolarity\n
- 2366:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC2P LL_TIM_IC_SetPolarity\n
- 2367:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC2NP LL_TIM_IC_SetPolarity\n
- 2368:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC3P LL_TIM_IC_SetPolarity\n
- 2369:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC3NP LL_TIM_IC_SetPolarity\n
- 2370:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC4P LL_TIM_IC_SetPolarity\n
- 2371:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2372:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Channel This parameter can be one of the following values:
- 2373:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- 2374:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- 2375:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 2376:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- 2377:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param ICPolarity This parameter can be one of the following values:
- 2378:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_RISING
- 2379:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_FALLING
- 2380:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 2381:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2382:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity
- 2383:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2384:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 2385:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
- 2386:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** ICPolarity << SHIFT_TAB_CCxP[iChannel]);
- 2387:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- ARM GAS /tmp/ccBGIhL8.s page 212
- 2388:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2389:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2390:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Get the current input channel polarity.
- 2391:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
- 2392:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC1NP LL_TIM_IC_GetPolarity\n
- 2393:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC2P LL_TIM_IC_GetPolarity\n
- 2394:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC2NP LL_TIM_IC_GetPolarity\n
- 2395:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC3P LL_TIM_IC_GetPolarity\n
- 2396:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC3NP LL_TIM_IC_GetPolarity\n
- 2397:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * CCER CC4P LL_TIM_IC_GetPolarity\n
- 2398:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2399:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param Channel This parameter can be one of the following values:
- 2400:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1
- 2401:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2
- 2402:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3
- 2403:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4
- 2404:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval Returned value can be one of the following values:
- 2405:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_RISING
- 2406:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_FALLING
- 2407:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2408:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
- 2409:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2410:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- 2411:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
- 2412:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** SHIFT_TAB_CCxP[iChannel]);
- 2413:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2414:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2415:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2416:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
- 2417:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
- 2418:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * a timer instance provides an XOR input.
- 2419:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
- 2420:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2421:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 2422:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2423:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
- 2424:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2425:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
- 2426:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2427:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2428:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2429:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
- 2430:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
- 2431:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * a timer instance provides an XOR input.
- 2432:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
- 2433:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2434:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 2435:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2436:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
- 2437:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2438:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
- 2439:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2440:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2441:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2442:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
- 2443:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
- 2444:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * a timer instance provides an XOR input.
- ARM GAS /tmp/ccBGIhL8.s page 213
- 2445:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
- 2446:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2447:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval State of bit (1 or 0).
- 2448:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2449:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
- 2450:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2451:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
- 2452:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2453:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2454:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2455:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Get captured value for input channel 1.
- 2456:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
- 2457:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * input channel 1 is supported by a timer instance.
- 2458:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
- 2459:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2460:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
- 2461:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2462:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
- 2463:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2464:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR1));
- 2465:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2466:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2467:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2468:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Get captured value for input channel 2.
- 2469:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
- 2470:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * input channel 2 is supported by a timer instance.
- 2471:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
- 2472:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2473:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
- 2474:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2475:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
- 2476:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2477:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR2));
- 2478:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2479:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2480:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2481:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Get captured value for input channel 3.
- 2482:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
- 2483:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * input channel 3 is supported by a timer instance.
- 2484:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
- 2485:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2486:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
- 2487:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2488:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
- 2489:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2490:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR3));
- 2491:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2492:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2493:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2494:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Get captured value for input channel 4.
- 2495:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
- 2496:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * input channel 4 is supported by a timer instance.
- 2497:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
- 2498:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2499:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
- 2500:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2501:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
- ARM GAS /tmp/ccBGIhL8.s page 214
- 2502:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2503:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR4));
- 2504:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2505:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2506:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2507:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 2508:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2509:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2510:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
- 2511:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 2512:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2513:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2514:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Enable external clock mode 2.
- 2515:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ET
- 2516:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
- 2517:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2.
- 2518:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
- 2519:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2520:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 2521:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2522:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
- 2523:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2524:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
- 2525:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2526:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2527:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2528:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Disable external clock mode 2.
- 2529:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
- 2530:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2.
- 2531:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
- 2532:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2533:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 2534:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2535:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
- 2536:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2537:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
- 2538:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2539:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2540:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2541:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Indicate whether external clock mode 2 is enabled.
- 2542:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
- 2543:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2.
- 2544:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
- 2545:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2546:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval State of bit (1 or 0).
- 2547:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2548:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
- 2549:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2550:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
- 2551:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2552:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2553:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2554:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Set the clock source of the counter clock.
- 2555:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note when selected clock source is external clock mode 1, the timer input
- 2556:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
- 2557:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * function. This timer input must be configured by calling
- 2558:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * the @ref LL_TIM_IC_Config() function.
- ARM GAS /tmp/ccBGIhL8.s page 215
- 2559:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
- 2560:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * whether or not a timer instance supports external clock mode1.
- 2561:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
- 2562:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2.
- 2563:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
- 2564:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * SMCR ECE LL_TIM_SetClockSource
- 2565:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2566:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param ClockSource This parameter can be one of the following values:
- 2567:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
- 2568:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
- 2569:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
- 2570:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 2571:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2572:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
- 1133 .loc 4 2572 22 view .LVU304
- 1134 .LBB151:
- 2573:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2574:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
- 1135 .loc 4 2574 3 view .LVU305
- 1136 00b6 AB68 ldr r3, [r5, #8]
- 1137 00b8 23F48043 bic r3, r3, #16384
- 1138 00bc 23F00703 bic r3, r3, #7
- 1139 00c0 AB60 str r3, [r5, #8]
- 1140 .LVL72:
- 1141 .loc 4 2574 3 is_stmt 0 view .LVU306
- 1142 .LBE151:
- 1143 .LBE150:
- 279:Core/Src/main.c **** TIM_OC_InitStruct.OCState = LL_TIM_OCSTATE_DISABLE;
- 1144 .loc 1 279 3 is_stmt 1 view .LVU307
- 279:Core/Src/main.c **** TIM_OC_InitStruct.OCState = LL_TIM_OCSTATE_DISABLE;
- 1145 .loc 1 279 28 is_stmt 0 view .LVU308
- 1146 00c2 3023 movs r3, #48
- 1147 00c4 0D93 str r3, [sp, #52]
- 280:Core/Src/main.c **** TIM_OC_InitStruct.OCNState = LL_TIM_OCSTATE_DISABLE;
- 1148 .loc 1 280 3 is_stmt 1 view .LVU309
- 280:Core/Src/main.c **** TIM_OC_InitStruct.OCNState = LL_TIM_OCSTATE_DISABLE;
- 1149 .loc 1 280 29 is_stmt 0 view .LVU310
- 1150 00c6 0E94 str r4, [sp, #56]
- 281:Core/Src/main.c **** TIM_OC_InitStruct.CompareValue = 70;
- 1151 .loc 1 281 3 is_stmt 1 view .LVU311
- 281:Core/Src/main.c **** TIM_OC_InitStruct.CompareValue = 70;
- 1152 .loc 1 281 30 is_stmt 0 view .LVU312
- 1153 00c8 0F94 str r4, [sp, #60]
- 282:Core/Src/main.c **** TIM_OC_InitStruct.OCPolarity = LL_TIM_OCPOLARITY_HIGH;
- 1154 .loc 1 282 3 is_stmt 1 view .LVU313
- 282:Core/Src/main.c **** TIM_OC_InitStruct.OCPolarity = LL_TIM_OCPOLARITY_HIGH;
- 1155 .loc 1 282 34 is_stmt 0 view .LVU314
- 1156 00ca 4623 movs r3, #70
- 1157 00cc 1093 str r3, [sp, #64]
- 283:Core/Src/main.c **** TIM_OC_InitStruct.OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
- 1158 .loc 1 283 3 is_stmt 1 view .LVU315
- 283:Core/Src/main.c **** TIM_OC_InitStruct.OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
- 1159 .loc 1 283 32 is_stmt 0 view .LVU316
- 1160 00ce 1194 str r4, [sp, #68]
- 284:Core/Src/main.c **** TIM_OC_InitStruct.OCIdleState = LL_TIM_OCIDLESTATE_LOW;
- 1161 .loc 1 284 3 is_stmt 1 view .LVU317
- 284:Core/Src/main.c **** TIM_OC_InitStruct.OCIdleState = LL_TIM_OCIDLESTATE_LOW;
- ARM GAS /tmp/ccBGIhL8.s page 216
- 1162 .loc 1 284 33 is_stmt 0 view .LVU318
- 1163 00d0 1294 str r4, [sp, #72]
- 285:Core/Src/main.c **** TIM_OC_InitStruct.OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
- 1164 .loc 1 285 3 is_stmt 1 view .LVU319
- 285:Core/Src/main.c **** TIM_OC_InitStruct.OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
- 1165 .loc 1 285 33 is_stmt 0 view .LVU320
- 1166 00d2 1394 str r4, [sp, #76]
- 286:Core/Src/main.c **** LL_TIM_OC_Init(TIM1, LL_TIM_CHANNEL_CH1, &TIM_OC_InitStruct);
- 1167 .loc 1 286 3 is_stmt 1 view .LVU321
- 286:Core/Src/main.c **** LL_TIM_OC_Init(TIM1, LL_TIM_CHANNEL_CH1, &TIM_OC_InitStruct);
- 1168 .loc 1 286 34 is_stmt 0 view .LVU322
- 1169 00d4 1494 str r4, [sp, #80]
- 287:Core/Src/main.c **** LL_TIM_OC_DisableFast(TIM1, LL_TIM_CHANNEL_CH1);
- 1170 .loc 1 287 3 is_stmt 1 view .LVU323
- 1171 00d6 0DAA add r2, sp, #52
- 1172 00d8 3946 mov r1, r7
- 1173 00da 2846 mov r0, r5
- 1174 00dc FFF7FEFF bl LL_TIM_OC_Init
- 1175 .LVL73:
- 288:Core/Src/main.c **** LL_TIM_SetTriggerOutput(TIM1, LL_TIM_TRGO_RESET);
- 1176 .loc 1 288 3 view .LVU324
- 1177 00e0 3946 mov r1, r7
- 1178 00e2 2846 mov r0, r5
- 1179 00e4 FFF7FEFF bl LL_TIM_OC_DisableFast
- 1180 .LVL74:
- 289:Core/Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM1);
- 1181 .loc 1 289 3 view .LVU325
- 1182 .LBB152:
- 1183 .LBI152:
- 2575:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2576:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2577:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2578:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Set the encoder interface mode.
- 2579:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
- 2580:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * whether or not a timer instance supports the encoder mode.
- 2581:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
- 2582:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2583:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param EncoderMode This parameter can be one of the following values:
- 2584:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
- 2585:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
- 2586:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
- 2587:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 2588:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2589:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
- 2590:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2591:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
- 2592:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2593:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2594:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2595:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @}
- 2596:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2597:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2598:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
- 2599:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @{
- 2600:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2601:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2602:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Set the trigger output (TRGO) used for timer synchronization .
- ARM GAS /tmp/ccBGIhL8.s page 217
- 2603:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
- 2604:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * whether or not a timer instance can operate as a master timer.
- 2605:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
- 2606:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2607:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TimerSynchronization This parameter can be one of the following values:
- 2608:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_RESET
- 2609:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_ENABLE
- 2610:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_UPDATE
- 2611:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_CC1IF
- 2612:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC1REF
- 2613:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC2REF
- 2614:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC3REF
- 2615:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC4REF
- 2616:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 2617:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2618:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
- 1184 .loc 4 2618 22 view .LVU326
- 1185 .LBB153:
- 2619:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2620:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
- 1186 .loc 4 2620 3 view .LVU327
- 1187 00e8 6B68 ldr r3, [r5, #4]
- 1188 00ea 23F07003 bic r3, r3, #112
- 1189 00ee 6B60 str r3, [r5, #4]
- 1190 .LVL75:
- 1191 .loc 4 2620 3 is_stmt 0 view .LVU328
- 1192 .LBE153:
- 1193 .LBE152:
- 290:Core/Src/main.c **** TIM_BDTRInitStruct.OSSRState = LL_TIM_OSSR_DISABLE;
- 1194 .loc 1 290 3 is_stmt 1 view .LVU329
- 1195 .LBB154:
- 1196 .LBI154:
- 2621:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2622:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2623:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2624:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Set the synchronization mode of a slave timer.
- 2625:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
- 2626:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * a timer instance can operate as a slave timer.
- 2627:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
- 2628:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2629:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param SlaveMode This parameter can be one of the following values:
- 2630:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_DISABLED
- 2631:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_RESET
- 2632:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_GATED
- 2633:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
- 2634:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 2635:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2636:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
- 2637:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2638:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
- 2639:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2640:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2641:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2642:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Set the selects the trigger input to be used to synchronize the counter.
- 2643:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
- 2644:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * a timer instance can operate as a slave timer.
- 2645:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll SMCR TS LL_TIM_SetTriggerInput
- ARM GAS /tmp/ccBGIhL8.s page 218
- 2646:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2647:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TriggerInput This parameter can be one of the following values:
- 2648:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR0
- 2649:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR1
- 2650:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR2
- 2651:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR3
- 2652:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_TS_TI1F_ED
- 2653:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_TS_TI1FP1
- 2654:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_TS_TI2FP2
- 2655:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ETRF
- 2656:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 2657:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2658:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
- 2659:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2660:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
- 2661:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2662:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2663:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2664:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Enable the Master/Slave mode.
- 2665:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
- 2666:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * a timer instance can operate as a slave timer.
- 2667:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
- 2668:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2669:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 2670:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2671:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
- 2672:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2673:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
- 2674:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** }
- 2675:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h ****
- 2676:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** /**
- 2677:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @brief Disable the Master/Slave mode.
- 2678:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
- 2679:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * a timer instance can operate as a slave timer.
- 2680:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
- 2681:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @param TIMx Timer instance
- 2682:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** * @retval None
- 2683:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** */
- 2684:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
- 1197 .loc 4 2684 22 view .LVU330
- 1198 .LBB155:
- 2685:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** {
- 2686:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h **** CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
- 1199 .loc 4 2686 3 view .LVU331
- 1200 00f0 AB68 ldr r3, [r5, #8]
- 1201 00f2 23F08003 bic r3, r3, #128
- 1202 00f6 AB60 str r3, [r5, #8]
- 1203 .LVL76:
- 1204 .loc 4 2686 3 is_stmt 0 view .LVU332
- 1205 .LBE155:
- 1206 .LBE154:
- 291:Core/Src/main.c **** TIM_BDTRInitStruct.OSSIState = LL_TIM_OSSI_DISABLE;
- 1207 .loc 1 291 3 is_stmt 1 view .LVU333
- 291:Core/Src/main.c **** TIM_BDTRInitStruct.OSSIState = LL_TIM_OSSI_DISABLE;
- 1208 .loc 1 291 32 is_stmt 0 view .LVU334
- 1209 00f8 0794 str r4, [sp, #28]
- 292:Core/Src/main.c **** TIM_BDTRInitStruct.LockLevel = LL_TIM_LOCKLEVEL_OFF;
- ARM GAS /tmp/ccBGIhL8.s page 219
- 1210 .loc 1 292 3 is_stmt 1 view .LVU335
- 292:Core/Src/main.c **** TIM_BDTRInitStruct.LockLevel = LL_TIM_LOCKLEVEL_OFF;
- 1211 .loc 1 292 32 is_stmt 0 view .LVU336
- 1212 00fa 0894 str r4, [sp, #32]
- 293:Core/Src/main.c **** TIM_BDTRInitStruct.DeadTime = 0;
- 1213 .loc 1 293 3 is_stmt 1 view .LVU337
- 293:Core/Src/main.c **** TIM_BDTRInitStruct.DeadTime = 0;
- 1214 .loc 1 293 32 is_stmt 0 view .LVU338
- 1215 00fc 0994 str r4, [sp, #36]
- 294:Core/Src/main.c **** TIM_BDTRInitStruct.BreakState = LL_TIM_BREAK_DISABLE;
- 1216 .loc 1 294 3 is_stmt 1 view .LVU339
- 294:Core/Src/main.c **** TIM_BDTRInitStruct.BreakState = LL_TIM_BREAK_DISABLE;
- 1217 .loc 1 294 31 is_stmt 0 view .LVU340
- 1218 00fe 8DF82840 strb r4, [sp, #40]
- 295:Core/Src/main.c **** TIM_BDTRInitStruct.BreakPolarity = LL_TIM_BREAK_POLARITY_HIGH;
- 1219 .loc 1 295 3 is_stmt 1 view .LVU341
- 295:Core/Src/main.c **** TIM_BDTRInitStruct.BreakPolarity = LL_TIM_BREAK_POLARITY_HIGH;
- 1220 .loc 1 295 33 is_stmt 0 view .LVU342
- 1221 0102 ADF82A40 strh r4, [sp, #42] @ movhi
- 296:Core/Src/main.c **** TIM_BDTRInitStruct.AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
- 1222 .loc 1 296 3 is_stmt 1 view .LVU343
- 296:Core/Src/main.c **** TIM_BDTRInitStruct.AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
- 1223 .loc 1 296 36 is_stmt 0 view .LVU344
- 1224 0106 4FF40053 mov r3, #8192
- 1225 010a 0B93 str r3, [sp, #44]
- 297:Core/Src/main.c **** LL_TIM_BDTR_Init(TIM1, &TIM_BDTRInitStruct);
- 1226 .loc 1 297 3 is_stmt 1 view .LVU345
- 297:Core/Src/main.c **** LL_TIM_BDTR_Init(TIM1, &TIM_BDTRInitStruct);
- 1227 .loc 1 297 38 is_stmt 0 view .LVU346
- 1228 010c 0C94 str r4, [sp, #48]
- 298:Core/Src/main.c **** /* USER CODE BEGIN TIM1_Init 2 */
- 1229 .loc 1 298 3 is_stmt 1 view .LVU347
- 1230 010e 07A9 add r1, sp, #28
- 1231 0110 2846 mov r0, r5
- 1232 0112 FFF7FEFF bl LL_TIM_BDTR_Init
- 1233 .LVL77:
- 302:Core/Src/main.c **** /**TIM1 GPIO Configuration
- 1234 .loc 1 302 3 view .LVU348
- 1235 .LBB156:
- 1236 .LBI156:
- 761:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** {
- 1237 .loc 5 761 22 view .LVU349
- 1238 .LBB157:
- 763:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs);
- 1239 .loc 5 763 3 view .LVU350
- 764:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */
- 1240 .loc 5 764 3 view .LVU351
- 1241 0116 B369 ldr r3, [r6, #24]
- 1242 0118 43F00403 orr r3, r3, #4
- 1243 011c B361 str r3, [r6, #24]
- 766:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** (void)tmpreg;
- 1244 .loc 5 766 3 view .LVU352
- 766:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** (void)tmpreg;
- 1245 .loc 5 766 12 is_stmt 0 view .LVU353
- 1246 011e B369 ldr r3, [r6, #24]
- 1247 0120 03F00403 and r3, r3, #4
- 766:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h **** (void)tmpreg;
- ARM GAS /tmp/ccBGIhL8.s page 220
- 1248 .loc 5 766 10 view .LVU354
- 1249 0124 0093 str r3, [sp]
- 1250 .loc 5 767 3 is_stmt 1 view .LVU355
- 1251 0126 009B ldr r3, [sp]
- 1252 .LVL78:
- 1253 .loc 5 767 3 is_stmt 0 view .LVU356
- 1254 .LBE157:
- 1255 .LBE156:
- 306:Core/Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
- 1256 .loc 1 306 3 is_stmt 1 view .LVU357
- 306:Core/Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
- 1257 .loc 1 306 23 is_stmt 0 view .LVU358
- 1258 0128 094B ldr r3, .L35+12
- 1259 012a 0293 str r3, [sp, #8]
- 307:Core/Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
- 1260 .loc 1 307 3 is_stmt 1 view .LVU359
- 307:Core/Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
- 1261 .loc 1 307 24 is_stmt 0 view .LVU360
- 1262 012c 0923 movs r3, #9
- 1263 012e 0393 str r3, [sp, #12]
- 308:Core/Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
- 1264 .loc 1 308 3 is_stmt 1 view .LVU361
- 308:Core/Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
- 1265 .loc 1 308 25 is_stmt 0 view .LVU362
- 1266 0130 0223 movs r3, #2
- 1267 0132 0493 str r3, [sp, #16]
- 309:Core/Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- 1268 .loc 1 309 3 is_stmt 1 view .LVU363
- 309:Core/Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- 1269 .loc 1 309 30 is_stmt 0 view .LVU364
- 1270 0134 0594 str r4, [sp, #20]
- 310:Core/Src/main.c ****
- 1271 .loc 1 310 3 is_stmt 1 view .LVU365
- 1272 0136 02A9 add r1, sp, #8
- 1273 0138 0648 ldr r0, .L35+16
- 1274 013a FFF7FEFF bl LL_GPIO_Init
- 1275 .LVL79:
- 312:Core/Src/main.c ****
- 1276 .loc 1 312 1 is_stmt 0 view .LVU366
- 1277 013e 1BB0 add sp, sp, #108
- 1278 .LCFI18:
- 1279 .cfi_def_cfa_offset 20
- 1280 @ sp needed
- 1281 0140 F0BD pop {r4, r5, r6, r7, pc}
- 1282 .L36:
- 1283 0142 00BF .align 2
- 1284 .L35:
- 1285 0144 00100240 .word 1073876992
- 1286 0148 00000240 .word 1073872896
- 1287 014c 002C0140 .word 1073818624
- 1288 0150 01000104 .word 67174401
- 1289 0154 00080140 .word 1073809408
- 1290 .cfi_endproc
- 1291 .LFE658:
- 1293 .section .text.Error_Handler,"ax",%progbits
- 1294 .align 1
- 1295 .global Error_Handler
- ARM GAS /tmp/ccBGIhL8.s page 221
- 1296 .syntax unified
- 1297 .thumb
- 1298 .thumb_func
- 1300 Error_Handler:
- 1301 .LFB661:
- 370:Core/Src/main.c ****
- 371:Core/Src/main.c **** /* USER CODE BEGIN 4 */
- 372:Core/Src/main.c ****
- 373:Core/Src/main.c **** /* USER CODE END 4 */
- 374:Core/Src/main.c ****
- 375:Core/Src/main.c **** /**
- 376:Core/Src/main.c **** * @brief This function is executed in case of error occurrence.
- 377:Core/Src/main.c **** * @retval None
- 378:Core/Src/main.c **** */
- 379:Core/Src/main.c **** void Error_Handler(void)
- 380:Core/Src/main.c **** {
- 1302 .loc 1 380 1 is_stmt 1 view -0
- 1303 .cfi_startproc
- 1304 @ Volatile: function does not return.
- 1305 @ args = 0, pretend = 0, frame = 0
- 1306 @ frame_needed = 0, uses_anonymous_args = 0
- 1307 @ link register save eliminated.
- 381:Core/Src/main.c **** /* USER CODE BEGIN Error_Handler_Debug */
- 382:Core/Src/main.c **** /* User can add his own implementation to report the HAL error return state */
- 383:Core/Src/main.c **** __disable_irq();
- 1308 .loc 1 383 3 view .LVU368
- 1309 .LBB158:
- 1310 .LBI158:
- 140:Drivers/CMSIS/Include/cmsis_gcc.h **** {
- 1311 .loc 7 140 27 view .LVU369
- 1312 .LBB159:
- 142:Drivers/CMSIS/Include/cmsis_gcc.h **** }
- 1313 .loc 7 142 3 view .LVU370
- 1314 .syntax unified
- 1315 @ 142 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
- 1316 0000 72B6 cpsid i
- 1317 @ 0 "" 2
- 1318 .thumb
- 1319 .syntax unified
- 1320 .L38:
- 1321 .LBE159:
- 1322 .LBE158:
- 384:Core/Src/main.c **** while (1)
- 1323 .loc 1 384 3 view .LVU371
- 385:Core/Src/main.c **** {
- 386:Core/Src/main.c **** }
- 1324 .loc 1 386 3 view .LVU372
- 384:Core/Src/main.c **** while (1)
- 1325 .loc 1 384 9 view .LVU373
- 1326 0002 FEE7 b .L38
- 1327 .cfi_endproc
- 1328 .LFE661:
- 1330 .section .text.SystemClock_Config,"ax",%progbits
- 1331 .align 1
- 1332 .global SystemClock_Config
- 1333 .syntax unified
- 1334 .thumb
- ARM GAS /tmp/ccBGIhL8.s page 222
- 1335 .thumb_func
- 1337 SystemClock_Config:
- 1338 .LFB656:
- 118:Core/Src/main.c **** LL_FLASH_SetLatency(LL_FLASH_LATENCY_1);
- 1339 .loc 1 118 1 view -0
- 1340 .cfi_startproc
- 1341 @ args = 0, pretend = 0, frame = 0
- 1342 @ frame_needed = 0, uses_anonymous_args = 0
- 1343 0000 08B5 push {r3, lr}
- 1344 .LCFI19:
- 1345 .cfi_def_cfa_offset 8
- 1346 .cfi_offset 3, -8
- 1347 .cfi_offset 14, -4
- 119:Core/Src/main.c **** while(LL_FLASH_GetLatency()!= LL_FLASH_LATENCY_1)
- 1348 .loc 1 119 3 view .LVU375
- 1349 .LVL80:
- 1350 .LBB160:
- 1351 .LBI160:
- 1352 .file 9 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h"
- 1:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /**
- 2:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** ******************************************************************************
- 3:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @file stm32f1xx_ll_system.h
- 4:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @author MCD Application Team
- 5:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @brief Header file of SYSTEM LL module.
- 6:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** *
- 7:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** ******************************************************************************
- 8:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @attention
- 9:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** *
- 10:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * Copyright (c) 2016 STMicroelectronics.
- 11:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * All rights reserved.
- 12:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** *
- 13:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * This software is licensed under terms that can be found in the LICENSE file
- 14:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * in the root directory of this software component.
- 15:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * If no LICENSE file comes with this software, it is provided AS-IS.
- 16:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** *
- 17:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** ******************************************************************************
- 18:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** @verbatim
- 19:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** ==============================================================================
- 20:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** ##### How to use this driver #####
- 21:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** ==============================================================================
- 22:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** [..]
- 23:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** The LL SYSTEM driver contains a set of generic APIs that can be
- 24:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** used by user:
- 25:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** (+) Some of the FLASH features need to be handled in the SYSTEM file.
- 26:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** (+) Access to DBGCMU registers
- 27:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** (+) Access to SYSCFG registers
- 28:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 29:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** @endverbatim
- 30:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** ******************************************************************************
- 31:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 32:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 33:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /* Define to prevent recursive inclusion -------------------------------------*/
- 34:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #ifndef __STM32F1xx_LL_SYSTEM_H
- 35:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define __STM32F1xx_LL_SYSTEM_H
- 36:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 37:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #ifdef __cplusplus
- 38:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** extern "C" {
- ARM GAS /tmp/ccBGIhL8.s page 223
- 39:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #endif
- 40:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 41:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /* Includes ------------------------------------------------------------------*/
- 42:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #include "stm32f1xx.h"
- 43:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 44:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /** @addtogroup STM32F1xx_LL_Driver
- 45:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @{
- 46:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 47:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 48:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #if defined (FLASH) || defined (DBGMCU)
- 49:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 50:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /** @defgroup SYSTEM_LL SYSTEM
- 51:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @{
- 52:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 53:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 54:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /* Private types -------------------------------------------------------------*/
- 55:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /* Private variables ---------------------------------------------------------*/
- 56:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 57:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /* Private constants ---------------------------------------------------------*/
- 58:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
- 59:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @{
- 60:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 61:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 62:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /**
- 63:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @}
- 64:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 65:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 66:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /* Private macros ------------------------------------------------------------*/
- 67:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 68:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /* Exported types ------------------------------------------------------------*/
- 69:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /* Exported constants --------------------------------------------------------*/
- 70:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
- 71:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @{
- 72:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 73:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 74:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 75:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 76:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
- 77:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @{
- 78:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 79:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRA
- 80:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRA
- 81:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRA
- 82:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRA
- 83:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRA
- 84:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /**
- 85:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @}
- 86:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 87:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 88:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
- 89:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @{
- 90:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 91:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP /*!< TIM2 counter stopp
- 92:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP /*!< TIM3 counter stopp
- 93:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP /*!< TIM4 counter stopp
- 94:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #if defined(DBGMCU_CR_DBG_TIM5_STOP)
- 95:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP /*!< TIM5 counter stopp
- ARM GAS /tmp/ccBGIhL8.s page 224
- 96:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #endif /* DBGMCU_CR_DBG_TIM5_STOP */
- 97:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #if defined(DBGMCU_CR_DBG_TIM6_STOP)
- 98:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP /*!< TIM6 counter stopp
- 99:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #endif /* DBGMCU_CR_DBG_TIM6_STOP */
- 100:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #if defined(DBGMCU_CR_DBG_TIM7_STOP)
- 101:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP /*!< TIM7 counter stopp
- 102:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #endif /* DBGMCU_CR_DBG_TIM7_STOP */
- 103:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #if defined(DBGMCU_CR_DBG_TIM12_STOP)
- 104:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP /*!< TIM12 counter stop
- 105:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #endif /* DBGMCU_CR_DBG_TIM12_STOP */
- 106:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #if defined(DBGMCU_CR_DBG_TIM13_STOP)
- 107:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP /*!< TIM13 counter stop
- 108:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #endif /* DBGMCU_CR_DBG_TIM13_STOP */
- 109:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #if defined(DBGMCU_CR_DBG_TIM14_STOP)
- 110:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP /*!< TIM14 counter stop
- 111:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #endif /* DBGMCU_CR_DBG_TIM14_STOP */
- 112:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP /*!< Debug Window Watch
- 113:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP /*!< Debug Independent
- 114:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout
- 115:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
- 116:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout
- 117:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #endif /* DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT */
- 118:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #if defined(DBGMCU_CR_DBG_CAN1_STOP)
- 119:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP /*!< CAN1 debug stopped
- 120:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #endif /* DBGMCU_CR_DBG_CAN1_STOP */
- 121:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #if defined(DBGMCU_CR_DBG_CAN2_STOP)
- 122:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP /*!< CAN2 debug stopped
- 123:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #endif /* DBGMCU_CR_DBG_CAN2_STOP */
- 124:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /**
- 125:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @}
- 126:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 127:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 128:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
- 129:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @{
- 130:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 131:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP /*!< TIM1 counter stopped when
- 132:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #if defined(DBGMCU_CR_DBG_TIM8_STOP)
- 133:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_CR_DBG_TIM8_STOP /*!< TIM8 counter stopped when
- 134:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #endif /* DBGMCU_CR_DBG_CAN1_STOP */
- 135:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #if defined(DBGMCU_CR_DBG_TIM9_STOP)
- 136:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP /*!< TIM9 counter stopped when
- 137:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #endif /* DBGMCU_CR_DBG_TIM9_STOP */
- 138:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #if defined(DBGMCU_CR_DBG_TIM10_STOP)
- 139:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP /*!< TIM10 counter stopped wh
- 140:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #endif /* DBGMCU_CR_DBG_TIM10_STOP */
- 141:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #if defined(DBGMCU_CR_DBG_TIM11_STOP)
- 142:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP /*!< TIM11 counter stopped wh
- 143:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #endif /* DBGMCU_CR_DBG_TIM11_STOP */
- 144:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #if defined(DBGMCU_CR_DBG_TIM15_STOP)
- 145:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP /*!< TIM15 counter stopped wh
- 146:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #endif /* DBGMCU_CR_DBG_TIM15_STOP */
- 147:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #if defined(DBGMCU_CR_DBG_TIM16_STOP)
- 148:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP /*!< TIM16 counter stopped wh
- 149:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #endif /* DBGMCU_CR_DBG_TIM16_STOP */
- 150:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #if defined(DBGMCU_CR_DBG_TIM17_STOP)
- 151:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP /*!< TIM17 counter stopped wh
- 152:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #endif /* DBGMCU_CR_DBG_TIM17_STOP */
- ARM GAS /tmp/ccBGIhL8.s page 225
- 153:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /**
- 154:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @}
- 155:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 156:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 157:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
- 158:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @{
- 159:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 160:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #if defined(FLASH_ACR_LATENCY)
- 161:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
- 162:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
- 163:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */
- 164:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #else
- 165:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #endif /* FLASH_ACR_LATENCY */
- 166:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /**
- 167:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @}
- 168:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 169:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 170:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /**
- 171:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @}
- 172:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 173:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 174:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /* Exported macro ------------------------------------------------------------*/
- 175:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 176:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /* Exported functions --------------------------------------------------------*/
- 177:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
- 178:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @{
- 179:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 180:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 181:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 182:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 183:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
- 184:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @{
- 185:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 186:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 187:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /**
- 188:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @brief Return the device identifier
- 189:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @note For Low Density devices, the device ID is 0x412
- 190:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @note For Medium Density devices, the device ID is 0x410
- 191:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @note For High Density devices, the device ID is 0x414
- 192:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @note For XL Density devices, the device ID is 0x430
- 193:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @note For Connectivity Line devices, the device ID is 0x418
- 194:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
- 195:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
- 196:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 197:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
- 198:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** {
- 199:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
- 200:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** }
- 201:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 202:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /**
- 203:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @brief Return the device revision identifier
- 204:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @note This field indicates the revision of the device.
- 205:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** For example, it is read as revA -> 0x1000,for Low Density devices
- 206:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** For example, it is read as revA -> 0x0000, revB -> 0x2000, revZ -> 0x2001, rev1,2,3,X or
- 207:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** For example, it is read as revA or 1 -> 0x1000, revZ -> 0x1001,rev1,2,3,X or Y -> 0x1003,
- 208:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** For example, it is read as revA or 1 -> 0x1003,for XL Density devices
- 209:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** For example, it is read as revA -> 0x1000, revZ -> 0x1001 for Connectivity line devices
- ARM GAS /tmp/ccBGIhL8.s page 226
- 210:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
- 211:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
- 212:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 213:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
- 214:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** {
- 215:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
- 216:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** }
- 217:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 218:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /**
- 219:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @brief Enable the Debug Module during SLEEP mode
- 220:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
- 221:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @retval None
- 222:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 223:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
- 224:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** {
- 225:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
- 226:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** }
- 227:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 228:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /**
- 229:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @brief Disable the Debug Module during SLEEP mode
- 230:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
- 231:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @retval None
- 232:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 233:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
- 234:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** {
- 235:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
- 236:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** }
- 237:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 238:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /**
- 239:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @brief Enable the Debug Module during STOP mode
- 240:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
- 241:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @retval None
- 242:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 243:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
- 244:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** {
- 245:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
- 246:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** }
- 247:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 248:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /**
- 249:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @brief Disable the Debug Module during STOP mode
- 250:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
- 251:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @retval None
- 252:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 253:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
- 254:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** {
- 255:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
- 256:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** }
- 257:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 258:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /**
- 259:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @brief Enable the Debug Module during STANDBY mode
- 260:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
- 261:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @retval None
- 262:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 263:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
- 264:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** {
- 265:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
- 266:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** }
- ARM GAS /tmp/ccBGIhL8.s page 227
- 267:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 268:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /**
- 269:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @brief Disable the Debug Module during STANDBY mode
- 270:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
- 271:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @retval None
- 272:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 273:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
- 274:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** {
- 275:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
- 276:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** }
- 277:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 278:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /**
- 279:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @brief Set Trace pin assignment control
- 280:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
- 281:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
- 282:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @param PinAssignment This parameter can be one of the following values:
- 283:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_TRACE_NONE
- 284:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_TRACE_ASYNCH
- 285:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
- 286:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
- 287:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
- 288:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @retval None
- 289:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 290:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
- 291:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** {
- 292:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
- 293:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** }
- 294:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 295:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /**
- 296:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @brief Get Trace pin assignment control
- 297:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
- 298:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
- 299:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @retval Returned value can be one of the following values:
- 300:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_TRACE_NONE
- 301:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_TRACE_ASYNCH
- 302:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
- 303:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
- 304:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
- 305:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 306:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
- 307:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** {
- 308:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
- 309:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** }
- 310:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 311:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /**
- 312:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @brief Freeze APB1 peripherals (group1 peripherals)
- 313:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- 314:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- 315:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- 316:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- 317:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- 318:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- 319:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- 320:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- 321:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- 322:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- 323:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- ARM GAS /tmp/ccBGIhL8.s page 228
- 324:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- 325:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- 326:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- 327:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- 328:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
- 329:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @param Periphs This parameter can be a combination of the following values:
- 330:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
- 331:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
- 332:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
- 333:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
- 334:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
- 335:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
- 336:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
- 337:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
- 338:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
- 339:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
- 340:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
- 341:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
- 342:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
- 343:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
- 344:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
- 345:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** *
- 346:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * (*) value not defined in all devices.
- 347:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @retval None
- 348:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 349:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
- 350:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** {
- 351:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** SET_BIT(DBGMCU->CR, Periphs);
- 352:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** }
- 353:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 354:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /**
- 355:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @brief Unfreeze APB1 peripherals (group1 peripherals)
- 356:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- 357:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- 358:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- 359:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- 360:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- 361:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- 362:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- 363:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- 364:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- 365:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- 366:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- 367:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- 368:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- 369:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- 370:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- 371:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
- 372:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @param Periphs This parameter can be a combination of the following values:
- 373:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
- 374:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
- 375:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
- 376:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
- 377:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
- 378:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
- 379:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
- 380:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
- ARM GAS /tmp/ccBGIhL8.s page 229
- 381:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
- 382:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
- 383:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
- 384:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
- 385:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
- 386:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
- 387:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
- 388:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
- 389:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** *
- 390:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * (*) value not defined in all devices.
- 391:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @retval None
- 392:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 393:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
- 394:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** {
- 395:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** CLEAR_BIT(DBGMCU->CR, Periphs);
- 396:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** }
- 397:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 398:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /**
- 399:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @brief Freeze APB2 peripherals
- 400:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- 401:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- 402:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- 403:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- 404:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- 405:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- 406:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- 407:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
- 408:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @param Periphs This parameter can be a combination of the following values:
- 409:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
- 410:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
- 411:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
- 412:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
- 413:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
- 414:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
- 415:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
- 416:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
- 417:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** *
- 418:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * (*) value not defined in all devices.
- 419:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @retval None
- 420:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 421:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
- 422:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** {
- 423:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** SET_BIT(DBGMCU->CR, Periphs);
- 424:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** }
- 425:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 426:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /**
- 427:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @brief Unfreeze APB2 peripherals
- 428:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- 429:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- 430:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- 431:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- 432:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- 433:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- 434:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- 435:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
- 436:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @param Periphs This parameter can be a combination of the following values:
- 437:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
- ARM GAS /tmp/ccBGIhL8.s page 230
- 438:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
- 439:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
- 440:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
- 441:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
- 442:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
- 443:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
- 444:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
- 445:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** *
- 446:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * (*) value not defined in all devices.
- 447:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @retval None
- 448:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 449:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
- 450:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** {
- 451:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** CLEAR_BIT(DBGMCU->CR, Periphs);
- 452:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** }
- 453:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /**
- 454:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @}
- 455:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 456:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 457:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** #if defined(FLASH_ACR_LATENCY)
- 458:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /** @defgroup SYSTEM_LL_EF_FLASH FLASH
- 459:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @{
- 460:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 461:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 462:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /**
- 463:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @brief Set FLASH Latency
- 464:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
- 465:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @param Latency This parameter can be one of the following values:
- 466:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_0
- 467:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_1
- 468:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_2
- 469:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @retval None
- 470:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 471:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
- 1353 .loc 9 471 22 view .LVU376
- 1354 .LBB161:
- 472:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** {
- 473:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
- 1355 .loc 9 473 3 view .LVU377
- 1356 0002 2B4A ldr r2, .L47
- 1357 0004 1368 ldr r3, [r2]
- 1358 0006 23F00703 bic r3, r3, #7
- 1359 000a 43F00103 orr r3, r3, #1
- 1360 000e 1360 str r3, [r2]
- 1361 .LVL81:
- 1362 .loc 9 473 3 is_stmt 0 view .LVU378
- 1363 .LBE161:
- 1364 .LBE160:
- 120:Core/Src/main.c **** {
- 1365 .loc 1 120 3 is_stmt 1 view .LVU379
- 1366 .L40:
- 122:Core/Src/main.c **** LL_RCC_HSE_Enable();
- 1367 .loc 1 122 3 view .LVU380
- 120:Core/Src/main.c **** {
- 1368 .loc 1 120 30 discriminator 1 view .LVU381
- 1369 .LBB162:
- 1370 .LBI162:
- ARM GAS /tmp/ccBGIhL8.s page 231
- 474:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** }
- 475:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h ****
- 476:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** /**
- 477:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @brief Get FLASH Latency
- 478:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
- 479:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @retval Returned value can be one of the following values:
- 480:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_0
- 481:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_1
- 482:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_2
- 483:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** */
- 484:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
- 1371 .loc 9 484 26 view .LVU382
- 1372 .LBB163:
- 485:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** {
- 486:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h **** return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
- 1373 .loc 9 486 3 view .LVU383
- 1374 .loc 9 486 21 is_stmt 0 view .LVU384
- 1375 0010 274B ldr r3, .L47
- 1376 0012 1B68 ldr r3, [r3]
- 1377 .loc 9 486 10 view .LVU385
- 1378 0014 03F00703 and r3, r3, #7
- 1379 .LBE163:
- 1380 .LBE162:
- 120:Core/Src/main.c **** {
- 1381 .loc 1 120 30 discriminator 1 view .LVU386
- 1382 0018 012B cmp r3, #1
- 1383 001a F9D1 bne .L40
- 123:Core/Src/main.c ****
- 1384 .loc 1 123 3 is_stmt 1 view .LVU387
- 1385 .LBB164:
- 1386 .LBI164:
- 1387 .file 10 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h"
- 1:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 2:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** ******************************************************************************
- 3:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @file stm32f1xx_ll_rcc.h
- 4:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @author MCD Application Team
- 5:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Header file of RCC LL module.
- 6:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** ******************************************************************************
- 7:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @attention
- 8:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** *
- 9:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * Copyright (c) 2016 STMicroelectronics.
- 10:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * All rights reserved.
- 11:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** *
- 12:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * This software is licensed under terms that can be found in the LICENSE file in
- 13:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * the root directory of this software component.
- 14:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * If no LICENSE file comes with this software, it is provided AS-IS.
- 15:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** ******************************************************************************
- 16:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 17:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 18:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /* Define to prevent recursive inclusion -------------------------------------*/
- 19:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #ifndef __STM32F1xx_LL_RCC_H
- 20:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define __STM32F1xx_LL_RCC_H
- 21:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 22:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #ifdef __cplusplus
- 23:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** extern "C" {
- 24:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif
- 25:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- ARM GAS /tmp/ccBGIhL8.s page 232
- 26:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /* Includes ------------------------------------------------------------------*/
- 27:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #include "stm32f1xx.h"
- 28:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 29:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @addtogroup STM32F1xx_LL_Driver
- 30:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 31:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 32:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 33:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(RCC)
- 34:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 35:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL RCC
- 36:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 37:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 38:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 39:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /* Private types -------------------------------------------------------------*/
- 40:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /* Private variables ---------------------------------------------------------*/
- 41:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /* Private constants ---------------------------------------------------------*/
- 42:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /* Private macros ------------------------------------------------------------*/
- 43:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER)
- 44:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_Private_Macros RCC Private Macros
- 45:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 46:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 47:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 48:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 49:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 50:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /*USE_FULL_LL_DRIVER*/
- 51:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /* Exported types ------------------------------------------------------------*/
- 52:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER)
- 53:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Types RCC Exported Types
- 54:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 55:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 56:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 57:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
- 58:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 59:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 60:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 61:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 62:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief RCC Clocks Frequency Structure
- 63:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 64:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** typedef struct
- 65:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 66:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
- 67:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
- 68:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
- 69:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
- 70:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** } LL_RCC_ClocksTypeDef;
- 71:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 72:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 73:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 74:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 75:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 76:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 77:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 78:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 79:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /* USE_FULL_LL_DRIVER */
- 80:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 81:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /* Exported constants --------------------------------------------------------*/
- 82:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
- ARM GAS /tmp/ccBGIhL8.s page 233
- 83:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 84:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 85:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 86:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
- 87:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Defines used to adapt values of different oscillators
- 88:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @note These values could be modified in the user environment according to
- 89:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * HW set-up.
- 90:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 91:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 92:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if !defined (HSE_VALUE)
- 93:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */
- 94:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /* HSE_VALUE */
- 95:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 96:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if !defined (HSI_VALUE)
- 97:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */
- 98:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /* HSI_VALUE */
- 99:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 100:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if !defined (LSE_VALUE)
- 101:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
- 102:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /* LSE_VALUE */
- 103:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 104:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if !defined (LSI_VALUE)
- 105:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LSI_VALUE 40000U /*!< Value of the LSI oscillator in Hz */
- 106:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /* LSI_VALUE */
- 107:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 108:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 109:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 110:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 111:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
- 112:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Flags defines which can be used with LL_RCC_WriteReg function
- 113:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 114:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 115:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */
- 116:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */
- 117:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */
- 118:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */
- 119:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */
- 120:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CIR_PLL3RDYC RCC_CIR_PLL3RDYC /*!< PLL3(PLLI2S) Ready Interrupt Cle
- 121:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CIR_PLL2RDYC RCC_CIR_PLL2RDYC /*!< PLL2 Ready Interrupt Clear */
- 122:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt
- 123:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 124:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 125:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 126:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 127:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
- 128:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Flags defines which can be used with LL_RCC_ReadReg function
- 129:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 130:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 131:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */
- 132:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */
- 133:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */
- 134:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */
- 135:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */
- 136:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CIR_PLL3RDYF RCC_CIR_PLL3RDYF /*!< PLL3(PLLI2S) Ready Interrupt fla
- 137:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CIR_PLL2RDYF RCC_CIR_PLL2RDYF /*!< PLL2 Ready Interrupt flag */
- 138:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt
- 139:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
- ARM GAS /tmp/ccBGIhL8.s page 234
- 140:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */
- 141:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
- 142:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag
- 143:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
- 144:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
- 145:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 146:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 147:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 148:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 149:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_IT IT Defines
- 150:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
- 151:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 152:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 153:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */
- 154:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */
- 155:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */
- 156:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */
- 157:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */
- 158:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE /*!< PLL3(PLLI2S) Ready Interrupt E
- 159:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE /*!< PLL2 Ready Interrupt Enable */
- 160:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 161:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 162:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 163:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 164:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(RCC_CFGR2_PREDIV2)
- 165:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_HSE_PREDIV2_DIV HSE PREDIV2 Division factor
- 166:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 167:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 168:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_HSE_PREDIV2_DIV_1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not di
- 169:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_HSE_PREDIV2_DIV_2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divide
- 170:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_HSE_PREDIV2_DIV_3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divide
- 171:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_HSE_PREDIV2_DIV_4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divide
- 172:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_HSE_PREDIV2_DIV_5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divide
- 173:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_HSE_PREDIV2_DIV_6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divide
- 174:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_HSE_PREDIV2_DIV_7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divide
- 175:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_HSE_PREDIV2_DIV_8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divide
- 176:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_HSE_PREDIV2_DIV_9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divide
- 177:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_HSE_PREDIV2_DIV_10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divide
- 178:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_HSE_PREDIV2_DIV_11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divide
- 179:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_HSE_PREDIV2_DIV_12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divide
- 180:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_HSE_PREDIV2_DIV_13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divide
- 181:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_HSE_PREDIV2_DIV_14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divide
- 182:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_HSE_PREDIV2_DIV_15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divide
- 183:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_HSE_PREDIV2_DIV_16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divide
- 184:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 185:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 186:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 187:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 188:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /* RCC_CFGR2_PREDIV2 */
- 189:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 190:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
- 191:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 192:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 193:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
- 194:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
- 195:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
- 196:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- ARM GAS /tmp/ccBGIhL8.s page 235
- 197:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 198:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 199:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 200:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
- 201:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 202:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 203:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
- 204:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
- 205:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
- 206:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 207:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 208:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 209:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 210:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
- 211:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 212:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 213:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
- 214:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
- 215:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
- 216:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
- 217:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
- 218:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
- 219:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
- 220:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
- 221:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
- 222:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 223:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 224:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 225:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 226:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
- 227:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 228:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 229:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
- 230:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
- 231:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
- 232:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
- 233:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
- 234:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 235:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 236:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 237:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 238:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
- 239:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 240:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 241:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
- 242:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
- 243:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
- 244:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
- 245:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
- 246:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 247:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 248:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 249:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 250:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
- 251:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 252:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 253:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK /*!< MCO output disabled, no c
- ARM GAS /tmp/ccBGIhL8.s page 236
- 254:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK /*!< SYSCLK selection as MCO s
- 255:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI /*!< HSI selection as MCO sour
- 256:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE /*!< HSE selection as MCO sour
- 257:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCO_PLLCLK_DIV2 /*!< PLL clock divided by 2*/
- 258:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(RCC_CFGR_MCO_PLL2CLK)
- 259:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_PLL2CLK RCC_CFGR_MCO_PLL2CLK /*!< PLL2 clock selected as MC
- 260:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /* RCC_CFGR_MCO_PLL2CLK */
- 261:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(RCC_CFGR_MCO_PLL3CLK_DIV2)
- 262:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 RCC_CFGR_MCO_PLL3CLK_DIV2 /*!< PLLI2S clock divided by 2
- 263:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /* RCC_CFGR_MCO_PLL3CLK_DIV2 */
- 264:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(RCC_CFGR_MCO_EXT_HSE)
- 265:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_EXT_HSE RCC_CFGR_MCO_EXT_HSE /*!< XT1 external 3-25 MHz osc
- 266:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /* RCC_CFGR_MCO_EXT_HSE */
- 267:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(RCC_CFGR_MCO_PLL3CLK)
- 268:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_PLLI2SCLK RCC_CFGR_MCO_PLL3CLK /*!< PLLI2S clock selected as
- 269:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /* RCC_CFGR_MCO_PLL3CLK */
- 270:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 271:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 272:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 273:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 274:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER)
- 275:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
- 276:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 277:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 278:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the periphera
- 279:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as ex
- 280:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 281:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 282:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 283:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /* USE_FULL_LL_DRIVER */
- 284:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 285:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(RCC_CFGR2_I2S2SRC)
- 286:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2S2CLKSOURCE Peripheral I2S clock source selection
- 287:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 288:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 289:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_I2S2_CLKSOURCE_SYSCLK RCC_CFGR2_I2S2SRC
- 290:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S2SRC | (RCC_CFGR2_I2S2SRC >> 16
- 291:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_I2S3_CLKSOURCE_SYSCLK RCC_CFGR2_I2S3SRC
- 292:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S3SRC | (RCC_CFGR2_I2S3SRC >> 16
- 293:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 294:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 295:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 296:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /* RCC_CFGR2_I2S2SRC */
- 297:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 298:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(USB_OTG_FS) || defined(USB)
- 299:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
- 300:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 301:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 302:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(RCC_CFGR_USBPRE)
- 303:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE /*!< PLL clock is not divided *
- 304:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 0x00000000U /*!< PLL clock is divided by 1.
- 305:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /*RCC_CFGR_USBPRE*/
- 306:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(RCC_CFGR_OTGFSPRE)
- 307:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE_PLL_DIV_2 RCC_CFGR_OTGFSPRE /*!< PLL clock is divided by 2
- 308:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE_PLL_DIV_3 0x00000000U /*!< PLL clock is divided by 3
- 309:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /*RCC_CFGR_OTGFSPRE*/
- 310:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- ARM GAS /tmp/ccBGIhL8.s page 237
- 311:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 312:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 313:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /* USB_OTG_FS || USB */
- 314:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 315:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_ADC_CLKSOURCE_PCLK2 Peripheral ADC clock source selection
- 316:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 317:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 318:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2 /*ADC prescaler PCLK2 divided by 2*/
- 319:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4 /*ADC prescaler PCLK2 divided by 4*/
- 320:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6 /*ADC prescaler PCLK2 divided by 6*/
- 321:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /*ADC prescaler PCLK2 divided by 8*/
- 322:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 323:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 324:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 325:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 326:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(RCC_CFGR2_I2S2SRC)
- 327:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2S2 Peripheral I2S get clock source
- 328:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 329:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 330:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_I2S2_CLKSOURCE RCC_CFGR2_I2S2SRC /*!< I2S2 Clock source selection
- 331:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_I2S3_CLKSOURCE RCC_CFGR2_I2S3SRC /*!< I2S3 Clock source selection
- 332:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 333:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 334:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 335:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 336:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /* RCC_CFGR2_I2S2SRC */
- 337:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 338:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(USB_OTG_FS) || defined(USB)
- 339:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
- 340:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 341:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 342:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE 0x00400000U /*!< USB Clock source selection */
- 343:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 344:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 345:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 346:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 347:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /* USB_OTG_FS || USB */
- 348:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 349:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
- 350:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 351:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 352:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE /*!< ADC Clock source selection */
- 353:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 354:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 355:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 356:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 357:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
- 358:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 359:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 360:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock
- 361:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used a
- 362:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used a
- 363:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divide
- 364:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 365:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 366:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 367:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- ARM GAS /tmp/ccBGIhL8.s page 238
- 368:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
- 369:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 370:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 371:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(RCC_CFGR_PLLMULL2)
- 372:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMULL2 /*!< PLL input clock*2 */
- 373:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /*RCC_CFGR_PLLMULL2*/
- 374:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(RCC_CFGR_PLLMULL3)
- 375:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMULL3 /*!< PLL input clock*3 */
- 376:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /*RCC_CFGR_PLLMULL3*/
- 377:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMULL4 /*!< PLL input clock*4 */
- 378:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMULL5 /*!< PLL input clock*5 */
- 379:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMULL6 /*!< PLL input clock*6 */
- 380:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMULL7 /*!< PLL input clock*7 */
- 381:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMULL8 /*!< PLL input clock*8 */
- 382:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMULL9 /*!< PLL input clock*9 */
- 383:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(RCC_CFGR_PLLMULL6_5)
- 384:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_6_5 RCC_CFGR_PLLMULL6_5 /*!< PLL input clock*6 */
- 385:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #else
- 386:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMULL10 /*!< PLL input clock*10 */
- 387:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMULL11 /*!< PLL input clock*11 */
- 388:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMULL12 /*!< PLL input clock*12 */
- 389:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMULL13 /*!< PLL input clock*13 */
- 390:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMULL14 /*!< PLL input clock*14 */
- 391:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMULL15 /*!< PLL input clock*15 */
- 392:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMULL16 /*!< PLL input clock*16 */
- 393:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /*RCC_CFGR_PLLMULL6_5*/
- 394:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 395:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 396:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 397:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 398:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
- 399:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 400:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 401:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSI_DIV_2 0x00000000U /*!< HSI
- 402:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE/
- 403:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(RCC_CFGR2_PREDIV1SRC)
- 404:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_PLL2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2
- 405:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /*RCC_CFGR2_PREDIV1SRC*/
- 406:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 407:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(RCC_CFGR2_PREDIV1)
- 408:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV1) /*!< HSE/1
- 409:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2) /*!< HSE/2
- 410:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3) /*!< HSE/3
- 411:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4) /*!< HSE/4
- 412:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5) /*!< HSE/5
- 413:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6) /*!< HSE/6
- 414:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7) /*!< HSE/7
- 415:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8) /*!< HSE/8
- 416:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9) /*!< HSE/9
- 417:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10) /*!< HSE/1
- 418:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11) /*!< HSE/1
- 419:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12) /*!< HSE/1
- 420:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13) /*!< HSE/1
- 421:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14) /*!< HSE/1
- 422:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15) /*!< HSE/1
- 423:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16) /*!< HSE/1
- 424:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(RCC_CFGR2_PREDIV1SRC)
- ARM GAS /tmp/ccBGIhL8.s page 239
- 425:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_PLL2_DIV_1 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV1 | RCC_CFGR2_PR
- 426:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_PLL2_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2 | RCC_CFGR2_PR
- 427:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_PLL2_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3 | RCC_CFGR2_PR
- 428:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_PLL2_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4 | RCC_CFGR2_PR
- 429:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_PLL2_DIV_5 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5 | RCC_CFGR2_PR
- 430:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_PLL2_DIV_6 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6 | RCC_CFGR2_PR
- 431:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_PLL2_DIV_7 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7 | RCC_CFGR2_PR
- 432:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_PLL2_DIV_8 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8 | RCC_CFGR2_PR
- 433:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_PLL2_DIV_9 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9 | RCC_CFGR2_PR
- 434:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_PLL2_DIV_10 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10 | RCC_CFGR2_P
- 435:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_PLL2_DIV_11 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11 | RCC_CFGR2_P
- 436:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_PLL2_DIV_12 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12 | RCC_CFGR2_P
- 437:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_PLL2_DIV_13 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13 | RCC_CFGR2_P
- 438:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_PLL2_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14 | RCC_CFGR2_P
- 439:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_PLL2_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15 | RCC_CFGR2_P
- 440:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_PLL2_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16 | RCC_CFGR2_P
- 441:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /*RCC_CFGR2_PREDIV1SRC*/
- 442:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #else
- 443:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC | 0x00000000U) /*!< HSE/1
- 444:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE) /*!< HSE/2
- 445:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /*RCC_CFGR2_PREDIV1*/
- 446:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 447:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 448:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 449:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 450:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor
- 451:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 452:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 453:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(RCC_CFGR2_PREDIV1)
- 454:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV1_DIV1 /*!< PREDIV1 input clock not di
- 455:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV1_DIV2 /*!< PREDIV1 input clock divide
- 456:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV1_DIV3 /*!< PREDIV1 input clock divide
- 457:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV1_DIV4 /*!< PREDIV1 input clock divide
- 458:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV1_DIV5 /*!< PREDIV1 input clock divide
- 459:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV1_DIV6 /*!< PREDIV1 input clock divide
- 460:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV1_DIV7 /*!< PREDIV1 input clock divide
- 461:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV1_DIV8 /*!< PREDIV1 input clock divide
- 462:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV1_DIV9 /*!< PREDIV1 input clock divide
- 463:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV1_DIV10 /*!< PREDIV1 input clock divide
- 464:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV1_DIV11 /*!< PREDIV1 input clock divide
- 465:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV1_DIV12 /*!< PREDIV1 input clock divide
- 466:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV1_DIV13 /*!< PREDIV1 input clock divide
- 467:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV1_DIV14 /*!< PREDIV1 input clock divide
- 468:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV1_DIV15 /*!< PREDIV1 input clock divide
- 469:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV1_DIV16 /*!< PREDIV1 input clock divide
- 470:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #else
- 471:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_1 0x00000000U /*!< HSE divider clock clock no
- 472:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PREDIV_DIV_2 RCC_CFGR_PLLXTPRE /*!< HSE divider clock divided
- 473:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /*RCC_CFGR2_PREDIV1*/
- 474:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 475:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 476:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 477:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 478:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(RCC_PLLI2S_SUPPORT)
- 479:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLI2S_MUL PLLI2S MUL
- 480:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 481:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- ARM GAS /tmp/ccBGIhL8.s page 240
- 482:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLI2S_MUL_8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */
- 483:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLI2S_MUL_9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */
- 484:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLI2S_MUL_10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */
- 485:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLI2S_MUL_11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */
- 486:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLI2S_MUL_12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */
- 487:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLI2S_MUL_13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */
- 488:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLI2S_MUL_14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */
- 489:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLI2S_MUL_16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */
- 490:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLLI2S_MUL_20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */
- 491:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 492:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 493:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 494:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 495:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /* RCC_PLLI2S_SUPPORT */
- 496:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 497:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(RCC_PLL2_SUPPORT)
- 498:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLL2_MUL PLL2 MUL
- 499:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 500:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 501:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLL2_MUL_8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */
- 502:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLL2_MUL_9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */
- 503:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLL2_MUL_10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */
- 504:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLL2_MUL_11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */
- 505:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLL2_MUL_12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */
- 506:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLL2_MUL_13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */
- 507:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLL2_MUL_14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */
- 508:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLL2_MUL_16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */
- 509:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_PLL2_MUL_20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */
- 510:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 511:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 512:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 513:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 514:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /* RCC_PLL2_SUPPORT */
- 515:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 516:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 517:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 518:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 519:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 520:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /* Exported macro ------------------------------------------------------------*/
- 521:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
- 522:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 523:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 524:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 525:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
- 526:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 527:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 528:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 529:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 530:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Write a value in RCC register
- 531:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param __REG__ Register to be written
- 532:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param __VALUE__ Value to be written in the register
- 533:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 534:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 535:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
- 536:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 537:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 538:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Read a value in RCC register
- ARM GAS /tmp/ccBGIhL8.s page 241
- 539:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param __REG__ Register to be read
- 540:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval Register value
- 541:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 542:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
- 543:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 544:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 545:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 546:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 547:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
- 548:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 549:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 550:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 551:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(RCC_CFGR_PLLMULL6_5)
- 552:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 553:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLCLK frequency
- 554:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref
- 555:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 / HSI div 2 / PLL2 div Pred
- 556:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param __PLLMUL__: This parameter can be one of the following values:
- 557:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_4
- 558:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_5
- 559:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_6
- 560:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_7
- 561:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_8
- 562:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_9
- 563:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_6_5
- 564:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval PLL clock frequency (in Hz)
- 565:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 566:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \
- 567:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** (((__PLLMUL__) != RCC_CFGR_PLLMULL6_5) ? \
- 568:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos) + 2U)
- 569:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** (((__INPUTFREQ__) * 13U) / 2U))
- 570:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 571:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #else
- 572:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 573:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLCLK frequency
- 574:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref
- 575:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 or div 2 / HSI div 2)
- 576:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param __PLLMUL__: This parameter can be one of the following values:
- 577:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_2
- 578:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_3
- 579:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_4
- 580:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_5
- 581:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_6
- 582:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_7
- 583:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_8
- 584:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_9
- 585:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_10
- 586:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_11
- 587:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_12
- 588:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_13
- 589:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_14
- 590:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_15
- 591:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_16
- 592:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval PLL clock frequency (in Hz)
- 593:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 594:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) ((__INPUTFREQ__) * (((__PLLMUL__) >> R
- 595:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /* RCC_CFGR_PLLMULL6_5 */
- ARM GAS /tmp/ccBGIhL8.s page 242
- 596:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 597:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(RCC_PLLI2S_SUPPORT)
- 598:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 599:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLI2S frequency
- 600:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLI2SCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLLI2S_GetMultiplicator (),
- 601:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param __INPUTFREQ__ PLLI2S Input frequency (based on HSE value)
- 602:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param __PLLI2SMUL__: This parameter can be one of the following values:
- 603:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2S_MUL_8
- 604:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2S_MUL_9
- 605:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2S_MUL_10
- 606:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2S_MUL_11
- 607:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2S_MUL_12
- 608:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2S_MUL_13
- 609:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2S_MUL_14
- 610:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2S_MUL_16
- 611:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2S_MUL_20
- 612:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param __PLLI2SDIV__: This parameter can be one of the following values:
- 613:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
- 614:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
- 615:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
- 616:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
- 617:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
- 618:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
- 619:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
- 620:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
- 621:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
- 622:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
- 623:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
- 624:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
- 625:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
- 626:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
- 627:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
- 628:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
- 629:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval PLLI2S clock frequency (in Hz)
- 630:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 631:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLI2SCLK_FREQ(__INPUTFREQ__, __PLLI2SMUL__, __PLLI2SDIV__) (((__INPUTFREQ__)
- 632:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /* RCC_PLLI2S_SUPPORT */
- 633:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 634:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(RCC_PLL2_SUPPORT)
- 635:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 636:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Helper macro to calculate the PLL2 frequency
- 637:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLL2CLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL2_GetMultiplicator (), @re
- 638:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL2 Input frequency (based on HSE value)
- 639:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param __PLL2MUL__: This parameter can be one of the following values:
- 640:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL2_MUL_8
- 641:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL2_MUL_9
- 642:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL2_MUL_10
- 643:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL2_MUL_11
- 644:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL2_MUL_12
- 645:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL2_MUL_13
- 646:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL2_MUL_14
- 647:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL2_MUL_16
- 648:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL2_MUL_20
- 649:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param __PLL2DIV__: This parameter can be one of the following values:
- 650:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
- 651:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
- 652:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
- ARM GAS /tmp/ccBGIhL8.s page 243
- 653:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
- 654:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
- 655:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
- 656:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
- 657:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
- 658:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
- 659:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
- 660:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
- 661:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
- 662:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
- 663:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
- 664:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
- 665:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
- 666:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval PLL2 clock frequency (in Hz)
- 667:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 668:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define __LL_RCC_CALC_PLL2CLK_FREQ(__INPUTFREQ__, __PLL2MUL__, __PLL2DIV__) (((__INPUTFREQ__) * (((
- 669:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /* RCC_PLL2_SUPPORT */
- 670:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 671:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 672:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Helper macro to calculate the HCLK frequency
- 673:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
- 674:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
- 675:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
- 676:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param __AHBPRESCALER__: This parameter can be one of the following values:
- 677:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_1
- 678:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_2
- 679:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_4
- 680:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_8
- 681:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_16
- 682:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_64
- 683:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_128
- 684:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_256
- 685:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_512
- 686:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval HCLK clock frequency (in Hz)
- 687:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 688:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTabl
- 689:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 690:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 691:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
- 692:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
- 693:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
- 694:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param __HCLKFREQ__ HCLK frequency
- 695:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param __APB1PRESCALER__: This parameter can be one of the following values:
- 696:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_1
- 697:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_2
- 698:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_4
- 699:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_8
- 700:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_16
- 701:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval PCLK1 clock frequency (in Hz)
- 702:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 703:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[
- 704:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 705:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 706:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
- 707:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler
- 708:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
- 709:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param __HCLKFREQ__ HCLK frequency
- ARM GAS /tmp/ccBGIhL8.s page 244
- 710:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param __APB2PRESCALER__: This parameter can be one of the following values:
- 711:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_1
- 712:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_2
- 713:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_4
- 714:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_8
- 715:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_16
- 716:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval PCLK2 clock frequency (in Hz)
- 717:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 718:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[
- 719:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 720:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 721:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 722:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 723:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 724:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 725:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 726:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 727:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 728:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /* Exported functions --------------------------------------------------------*/
- 729:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
- 730:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 731:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 732:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 733:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSE HSE
- 734:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 735:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 736:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 737:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 738:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Enable the Clock Security System.
- 739:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
- 740:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 741:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 742:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
- 743:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 744:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_CSSON);
- 745:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 746:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 747:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 748:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Enable HSE external oscillator (HSE Bypass)
- 749:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
- 750:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 751:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 752:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
- 753:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 754:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSEBYP);
- 755:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 756:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 757:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 758:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Disable HSE external oscillator (HSE Bypass)
- 759:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
- 760:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 761:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 762:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
- 763:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 764:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
- 765:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 766:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- ARM GAS /tmp/ccBGIhL8.s page 245
- 767:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 768:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Enable HSE crystal oscillator (HSE ON)
- 769:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CR HSEON LL_RCC_HSE_Enable
- 770:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 771:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 772:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_Enable(void)
- 1388 .loc 10 772 22 view .LVU388
- 1389 .LBB165:
- 773:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 774:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSEON);
- 1390 .loc 10 774 3 view .LVU389
- 1391 001c 254A ldr r2, .L47+4
- 1392 001e 1368 ldr r3, [r2]
- 1393 0020 43F48033 orr r3, r3, #65536
- 1394 0024 1360 str r3, [r2]
- 1395 .LBE165:
- 1396 .LBE164:
- 126:Core/Src/main.c **** {
- 1397 .loc 1 126 3 view .LVU390
- 1398 .L41:
- 129:Core/Src/main.c **** LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE_DIV_1, LL_RCC_PLL_MUL_6);
- 1399 .loc 1 129 3 view .LVU391
- 126:Core/Src/main.c **** {
- 1400 .loc 1 126 30 discriminator 1 view .LVU392
- 1401 .LBB166:
- 1402 .LBI166:
- 775:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 776:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 777:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 778:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Disable HSE crystal oscillator (HSE ON)
- 779:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CR HSEON LL_RCC_HSE_Disable
- 780:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 781:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 782:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_Disable(void)
- 783:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 784:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
- 785:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 786:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 787:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 788:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Check if HSE oscillator Ready
- 789:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
- 790:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval State of bit (1 or 0).
- 791:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 792:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
- 1403 .loc 10 792 26 view .LVU393
- 1404 .LBB167:
- 793:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 794:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
- 1405 .loc 10 794 3 view .LVU394
- 1406 .loc 10 794 11 is_stmt 0 view .LVU395
- 1407 0026 234B ldr r3, .L47+4
- 1408 0028 1B68 ldr r3, [r3]
- 1409 .LBE167:
- 1410 .LBE166:
- 126:Core/Src/main.c **** {
- 1411 .loc 1 126 30 discriminator 1 view .LVU396
- 1412 002a 13F4003F tst r3, #131072
- ARM GAS /tmp/ccBGIhL8.s page 246
- 1413 002e FAD0 beq .L41
- 130:Core/Src/main.c **** LL_RCC_PLL_Enable();
- 1414 .loc 1 130 3 is_stmt 1 view .LVU397
- 1415 .LVL82:
- 1416 .LBB168:
- 1417 .LBI168:
- 795:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 796:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 797:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(RCC_CFGR2_PREDIV2)
- 798:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 799:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Get PREDIV2 division factor
- 800:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CFGR2 PREDIV2 LL_RCC_HSE_GetPrediv2
- 801:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval Returned value can be one of the following values:
- 802:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
- 803:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
- 804:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
- 805:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
- 806:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
- 807:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
- 808:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
- 809:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
- 810:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
- 811:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
- 812:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
- 813:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
- 814:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
- 815:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
- 816:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
- 817:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
- 818:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 819:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSE_GetPrediv2(void)
- 820:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 821:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2));
- 822:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 823:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /* RCC_CFGR2_PREDIV2 */
- 824:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 825:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 826:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 827:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 828:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 829:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSI HSI
- 830:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 831:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 832:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 833:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 834:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Enable HSI oscillator
- 835:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CR HSION LL_RCC_HSI_Enable
- 836:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 837:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 838:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_Enable(void)
- 839:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 840:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSION);
- 841:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 842:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 843:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 844:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Disable HSI oscillator
- 845:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CR HSION LL_RCC_HSI_Disable
- ARM GAS /tmp/ccBGIhL8.s page 247
- 846:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 847:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 848:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_Disable(void)
- 849:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 850:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSION);
- 851:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 852:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 853:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 854:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Check if HSI clock is ready
- 855:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
- 856:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval State of bit (1 or 0).
- 857:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 858:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
- 859:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 860:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
- 861:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 862:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 863:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 864:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Get HSI Calibration value
- 865:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @note When HSITRIM is written, HSICAL is updated with the sum of
- 866:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * HSITRIM and the factory trim value
- 867:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
- 868:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
- 869:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 870:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
- 871:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 872:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
- 873:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 874:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 875:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 876:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Set HSI Calibration trimming
- 877:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @note user-programmable trimming value that is added to the HSICAL
- 878:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @note Default value is 16, which, when added to the HSICAL value,
- 879:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * should trim the HSI to 16 MHz +/- 1 %
- 880:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
- 881:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param Value between Min_Data = 0x00 and Max_Data = 0x1F
- 882:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 883:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 884:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
- 885:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 886:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
- 887:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 888:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 889:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 890:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Get HSI Calibration trimming
- 891:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
- 892:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0x1F
- 893:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 894:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
- 895:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 896:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
- 897:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 898:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 899:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 900:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 901:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 902:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- ARM GAS /tmp/ccBGIhL8.s page 248
- 903:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_LSE LSE
- 904:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 905:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 906:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 907:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 908:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Enable Low Speed External (LSE) crystal.
- 909:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
- 910:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 911:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 912:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_Enable(void)
- 913:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 914:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
- 915:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 916:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 917:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 918:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Disable Low Speed External (LSE) crystal.
- 919:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
- 920:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 921:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 922:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_Disable(void)
- 923:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 924:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
- 925:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 926:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 927:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 928:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Enable external clock source (LSE bypass).
- 929:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
- 930:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 931:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 932:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
- 933:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 934:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
- 935:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 936:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 937:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 938:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Disable external clock source (LSE bypass).
- 939:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
- 940:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 941:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 942:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
- 943:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 944:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
- 945:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 946:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 947:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 948:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Check if LSE oscillator Ready
- 949:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
- 950:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval State of bit (1 or 0).
- 951:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 952:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
- 953:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 954:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
- 955:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 956:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 957:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 958:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 959:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- ARM GAS /tmp/ccBGIhL8.s page 249
- 960:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 961:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_LSI LSI
- 962:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 963:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 964:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 965:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 966:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Enable LSI Oscillator
- 967:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CSR LSION LL_RCC_LSI_Enable
- 968:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 969:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 970:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSI_Enable(void)
- 971:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 972:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** SET_BIT(RCC->CSR, RCC_CSR_LSION);
- 973:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 974:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 975:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 976:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Disable LSI Oscillator
- 977:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CSR LSION LL_RCC_LSI_Disable
- 978:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 979:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 980:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSI_Disable(void)
- 981:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 982:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
- 983:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 984:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 985:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 986:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Check if LSI is Ready
- 987:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
- 988:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval State of bit (1 or 0).
- 989:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 990:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
- 991:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 992:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
- 993:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 994:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 995:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 996:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 997:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 998:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 999:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_System System
- 1000:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 1001:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1002:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1003:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1004:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Configure the system clock source
- 1005:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CFGR SW LL_RCC_SetSysClkSource
- 1006:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param Source This parameter can be one of the following values:
- 1007:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
- 1008:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
- 1009:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
- 1010:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 1011:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1012:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
- 1013:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1014:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
- 1015:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1016:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- ARM GAS /tmp/ccBGIhL8.s page 250
- 1017:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1018:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Get the system clock source
- 1019:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
- 1020:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval Returned value can be one of the following values:
- 1021:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
- 1022:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
- 1023:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
- 1024:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1025:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
- 1026:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1027:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
- 1028:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1029:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1030:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1031:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Set AHB prescaler
- 1032:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
- 1033:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param Prescaler This parameter can be one of the following values:
- 1034:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_1
- 1035:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_2
- 1036:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_4
- 1037:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_8
- 1038:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_16
- 1039:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_64
- 1040:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_128
- 1041:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_256
- 1042:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_512
- 1043:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 1044:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1045:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
- 1046:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1047:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
- 1048:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1049:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1050:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1051:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Set APB1 prescaler
- 1052:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
- 1053:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param Prescaler This parameter can be one of the following values:
- 1054:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_1
- 1055:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_2
- 1056:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_4
- 1057:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_8
- 1058:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_16
- 1059:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 1060:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1061:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
- 1062:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1063:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
- 1064:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1065:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1066:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1067:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Set APB2 prescaler
- 1068:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
- 1069:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param Prescaler This parameter can be one of the following values:
- 1070:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_1
- 1071:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_2
- 1072:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_4
- 1073:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_8
- ARM GAS /tmp/ccBGIhL8.s page 251
- 1074:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_16
- 1075:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 1076:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1077:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
- 1078:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1079:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
- 1080:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1081:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1082:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1083:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Get AHB prescaler
- 1084:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
- 1085:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval Returned value can be one of the following values:
- 1086:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_1
- 1087:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_2
- 1088:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_4
- 1089:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_8
- 1090:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_16
- 1091:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_64
- 1092:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_128
- 1093:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_256
- 1094:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_512
- 1095:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1096:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
- 1097:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1098:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
- 1099:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1100:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1101:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1102:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Get APB1 prescaler
- 1103:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
- 1104:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval Returned value can be one of the following values:
- 1105:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_1
- 1106:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_2
- 1107:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_4
- 1108:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_8
- 1109:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_16
- 1110:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1111:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
- 1112:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1113:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
- 1114:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1115:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1116:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1117:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Get APB2 prescaler
- 1118:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
- 1119:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval Returned value can be one of the following values:
- 1120:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_1
- 1121:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_2
- 1122:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_4
- 1123:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_8
- 1124:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_16
- 1125:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1126:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
- 1127:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1128:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
- 1129:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1130:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- ARM GAS /tmp/ccBGIhL8.s page 252
- 1131:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1132:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 1133:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1134:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1135:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_MCO MCO
- 1136:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 1137:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1138:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1139:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1140:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Configure MCOx
- 1141:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CFGR MCO LL_RCC_ConfigMCO
- 1142:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param MCOxSource This parameter can be one of the following values:
- 1143:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
- 1144:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
- 1145:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_HSI
- 1146:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_HSE
- 1147:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2
- 1148:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_PLL2CLK (*)
- 1149:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 (*)
- 1150:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_EXT_HSE (*)
- 1151:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK (*)
- 1152:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** *
- 1153:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * (*) value not defined in all devices
- 1154:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 1155:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1156:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource)
- 1157:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1158:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource);
- 1159:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1160:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1161:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1162:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 1163:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1164:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1165:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
- 1166:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 1167:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1168:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1169:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(RCC_CFGR2_I2S2SRC)
- 1170:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1171:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Configure I2Sx clock source
- 1172:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CFGR2 I2S2SRC LL_RCC_SetI2SClockSource\n
- 1173:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * CFGR2 I2S3SRC LL_RCC_SetI2SClockSource
- 1174:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param I2SxSource This parameter can be one of the following values:
- 1175:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK
- 1176:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO
- 1177:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK
- 1178:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO
- 1179:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 1180:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1181:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
- 1182:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1183:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR2, (I2SxSource & 0xFFFF0000U), (I2SxSource << 16U));
- 1184:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1185:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /* RCC_CFGR2_I2S2SRC */
- 1186:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1187:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(USB_OTG_FS) || defined(USB)
- ARM GAS /tmp/ccBGIhL8.s page 253
- 1188:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1189:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Configure USB clock source
- 1190:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CFGR OTGFSPRE LL_RCC_SetUSBClockSource\n
- 1191:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * CFGR USBPRE LL_RCC_SetUSBClockSource
- 1192:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param USBxSource This parameter can be one of the following values:
- 1193:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*)
- 1194:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*)
- 1195:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*)
- 1196:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*)
- 1197:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** *
- 1198:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * (*) value not defined in all devices
- 1199:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 1200:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1201:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
- 1202:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1203:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(RCC_CFGR_USBPRE)
- 1204:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, USBxSource);
- 1205:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #else /*RCC_CFGR_OTGFSPRE*/
- 1206:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, USBxSource);
- 1207:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /*RCC_CFGR_USBPRE*/
- 1208:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1209:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /* USB_OTG_FS || USB */
- 1210:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1211:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1212:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Configure ADC clock source
- 1213:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CFGR ADCPRE LL_RCC_SetADCClockSource
- 1214:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param ADCxSource This parameter can be one of the following values:
- 1215:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
- 1216:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
- 1217:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
- 1218:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
- 1219:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 1220:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1221:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
- 1222:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1223:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, ADCxSource);
- 1224:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1225:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1226:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(RCC_CFGR2_I2S2SRC)
- 1227:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1228:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Get I2Sx clock source
- 1229:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CFGR2 I2S2SRC LL_RCC_GetI2SClockSource\n
- 1230:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * CFGR2 I2S3SRC LL_RCC_GetI2SClockSource
- 1231:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param I2Sx This parameter can be one of the following values:
- 1232:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_I2S2_CLKSOURCE
- 1233:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_I2S3_CLKSOURCE
- 1234:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval Returned value can be one of the following values:
- 1235:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK
- 1236:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO
- 1237:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK
- 1238:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO
- 1239:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1240:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
- 1241:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1242:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR2, I2Sx) >> 16U | I2Sx);
- 1243:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1244:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /* RCC_CFGR2_I2S2SRC */
- ARM GAS /tmp/ccBGIhL8.s page 254
- 1245:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1246:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #if defined(USB_OTG_FS) || defined(USB)
- 1247:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1248:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Get USBx clock source
- 1249:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CFGR OTGFSPRE LL_RCC_GetUSBClockSource\n
- 1250:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * CFGR USBPRE LL_RCC_GetUSBClockSource
- 1251:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param USBx This parameter can be one of the following values:
- 1252:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE
- 1253:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval Returned value can be one of the following values:
- 1254:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*)
- 1255:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*)
- 1256:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*)
- 1257:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*)
- 1258:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** *
- 1259:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * (*) value not defined in all devices
- 1260:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1261:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
- 1262:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1263:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, USBx));
- 1264:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1265:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #endif /* USB_OTG_FS || USB */
- 1266:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1267:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1268:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Get ADCx clock source
- 1269:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CFGR ADCPRE LL_RCC_GetADCClockSource
- 1270:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param ADCx This parameter can be one of the following values:
- 1271:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_ADC_CLKSOURCE
- 1272:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval Returned value can be one of the following values:
- 1273:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
- 1274:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
- 1275:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
- 1276:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
- 1277:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1278:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
- 1279:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1280:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, ADCx));
- 1281:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1282:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1283:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1284:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 1285:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1286:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1287:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_RTC RTC
- 1288:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 1289:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1290:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1291:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1292:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Set RTC Clock Source
- 1293:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @note Once the RTC clock source has been selected, it cannot be changed any more unless
- 1294:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * the Backup domain is reset. The BDRST bit can be used to reset them.
- 1295:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
- 1296:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param Source This parameter can be one of the following values:
- 1297:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
- 1298:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
- 1299:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
- 1300:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128
- 1301:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- ARM GAS /tmp/ccBGIhL8.s page 255
- 1302:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1303:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
- 1304:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1305:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
- 1306:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1307:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1308:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1309:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Get RTC Clock Source
- 1310:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
- 1311:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval Returned value can be one of the following values:
- 1312:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
- 1313:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
- 1314:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
- 1315:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128
- 1316:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1317:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
- 1318:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1319:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
- 1320:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1321:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1322:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1323:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Enable RTC
- 1324:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
- 1325:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 1326:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1327:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_EnableRTC(void)
- 1328:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1329:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
- 1330:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1331:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1332:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1333:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Disable RTC
- 1334:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
- 1335:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 1336:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1337:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_DisableRTC(void)
- 1338:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1339:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
- 1340:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1341:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1342:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1343:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Check if RTC has been enabled or not
- 1344:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
- 1345:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval State of bit (1 or 0).
- 1346:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1347:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
- 1348:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1349:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
- 1350:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1351:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1352:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1353:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Force the Backup domain reset
- 1354:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
- 1355:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 1356:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1357:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
- 1358:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- ARM GAS /tmp/ccBGIhL8.s page 256
- 1359:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
- 1360:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1361:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1362:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1363:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Release the Backup domain reset
- 1364:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
- 1365:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 1366:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1367:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
- 1368:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1369:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
- 1370:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1371:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1372:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1373:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @}
- 1374:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1375:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1376:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_PLL PLL
- 1377:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @{
- 1378:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1379:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1380:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1381:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Enable PLL
- 1382:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CR PLLON LL_RCC_PLL_Enable
- 1383:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 1384:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1385:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_Enable(void)
- 1386:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1387:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_PLLON);
- 1388:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1389:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1390:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1391:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Disable PLL
- 1392:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @note Cannot be disabled if the PLL clock is used as the system clock
- 1393:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CR PLLON LL_RCC_PLL_Disable
- 1394:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 1395:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1396:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_Disable(void)
- 1397:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1398:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
- 1399:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1400:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1401:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1402:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Check if PLL Ready
- 1403:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
- 1404:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval State of bit (1 or 0).
- 1405:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1406:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
- 1407:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1408:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
- 1409:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1410:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h ****
- 1411:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** /**
- 1412:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @brief Configure PLL used for SYSCLK Domain
- 1413:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
- 1414:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * CFGR PLLXTPRE LL_RCC_PLL_ConfigDomain_SYS\n
- 1415:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * CFGR PLLMULL LL_RCC_PLL_ConfigDomain_SYS\n
- ARM GAS /tmp/ccBGIhL8.s page 257
- 1416:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * CFGR2 PREDIV1 LL_RCC_PLL_ConfigDomain_SYS\n
- 1417:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * CFGR2 PREDIV1SRC LL_RCC_PLL_ConfigDomain_SYS
- 1418:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param Source This parameter can be one of the following values:
- 1419:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
- 1420:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1
- 1421:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2 (*)
- 1422:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3 (*)
- 1423:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4 (*)
- 1424:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5 (*)
- 1425:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6 (*)
- 1426:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7 (*)
- 1427:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8 (*)
- 1428:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9 (*)
- 1429:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10 (*)
- 1430:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11 (*)
- 1431:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12 (*)
- 1432:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13 (*)
- 1433:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14 (*)
- 1434:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15 (*)
- 1435:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16 (*)
- 1436:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_1 (*)
- 1437:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_2 (*)
- 1438:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_3 (*)
- 1439:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_4 (*)
- 1440:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_5 (*)
- 1441:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_6 (*)
- 1442:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_7 (*)
- 1443:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_8 (*)
- 1444:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_9 (*)
- 1445:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_10 (*)
- 1446:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_11 (*)
- 1447:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_12 (*)
- 1448:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_13 (*)
- 1449:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_14 (*)
- 1450:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_15 (*)
- 1451:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_16 (*)
- 1452:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** *
- 1453:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * (*) value not defined in all devices
- 1454:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @param PLLMul This parameter can be one of the following values:
- 1455:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_2 (*)
- 1456:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_3 (*)
- 1457:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_4
- 1458:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_5
- 1459:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_6
- 1460:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_7
- 1461:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_8
- 1462:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_9
- 1463:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_6_5 (*)
- 1464:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_10 (*)
- 1465:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_11 (*)
- 1466:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_12 (*)
- 1467:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_13 (*)
- 1468:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_14 (*)
- 1469:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_15 (*)
- 1470:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @arg @ref LL_RCC_PLL_MUL_16 (*)
- 1471:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** *
- 1472:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * (*) value not defined in all devices
- ARM GAS /tmp/ccBGIhL8.s page 258
- 1473:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** * @retval None
- 1474:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** */
- 1475:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul)
- 1418 .loc 10 1475 22 view .LVU398
- 1419 .LBB169:
- 1476:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1477:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL,
- 1420 .loc 10 1477 3 view .LVU399
- 1421 0030 204A ldr r2, .L47+4
- 1422 0032 5368 ldr r3, [r2, #4]
- 1423 0034 23F47C13 bic r3, r3, #4128768
- 1424 0038 43F48813 orr r3, r3, #1114112
- 1425 003c 5360 str r3, [r2, #4]
- 1426 .LVL83:
- 1427 .loc 10 1477 3 is_stmt 0 view .LVU400
- 1428 .LBE169:
- 1429 .LBE168:
- 131:Core/Src/main.c ****
- 1430 .loc 1 131 3 is_stmt 1 view .LVU401
- 1431 .LBB170:
- 1432 .LBI170:
- 1385:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1433 .loc 10 1385 22 view .LVU402
- 1434 .LBB171:
- 1387:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1435 .loc 10 1387 3 view .LVU403
- 1436 003e 1368 ldr r3, [r2]
- 1437 0040 43F08073 orr r3, r3, #16777216
- 1438 0044 1360 str r3, [r2]
- 1439 .LBE171:
- 1440 .LBE170:
- 134:Core/Src/main.c **** {
- 1441 .loc 1 134 3 view .LVU404
- 1442 .L42:
- 137:Core/Src/main.c **** LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
- 1443 .loc 1 137 3 view .LVU405
- 134:Core/Src/main.c **** {
- 1444 .loc 1 134 30 discriminator 1 view .LVU406
- 1445 .LBB172:
- 1446 .LBI172:
- 1406:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1447 .loc 10 1406 26 view .LVU407
- 1448 .LBB173:
- 1408:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1449 .loc 10 1408 3 view .LVU408
- 1408:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1450 .loc 10 1408 11 is_stmt 0 view .LVU409
- 1451 0046 1B4B ldr r3, .L47+4
- 1452 0048 1B68 ldr r3, [r3]
- 1453 .LBE173:
- 1454 .LBE172:
- 134:Core/Src/main.c **** {
- 1455 .loc 1 134 30 discriminator 1 view .LVU410
- 1456 004a 13F0007F tst r3, #33554432
- 1457 004e FAD0 beq .L42
- 138:Core/Src/main.c **** LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2);
- 1458 .loc 1 138 3 is_stmt 1 view .LVU411
- ARM GAS /tmp/ccBGIhL8.s page 259
- 1459 .LVL84:
- 1460 .LBB174:
- 1461 .LBI174:
- 1045:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1462 .loc 10 1045 22 view .LVU412
- 1463 .LBB175:
- 1047:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1464 .loc 10 1047 3 view .LVU413
- 1465 0050 184B ldr r3, .L47+4
- 1466 0052 5A68 ldr r2, [r3, #4]
- 1467 0054 22F0F002 bic r2, r2, #240
- 1468 0058 5A60 str r2, [r3, #4]
- 1469 .LVL85:
- 1047:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1470 .loc 10 1047 3 is_stmt 0 view .LVU414
- 1471 .LBE175:
- 1472 .LBE174:
- 139:Core/Src/main.c **** LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
- 1473 .loc 1 139 3 is_stmt 1 view .LVU415
- 1474 .LBB176:
- 1475 .LBI176:
- 1061:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1476 .loc 10 1061 22 view .LVU416
- 1477 .LBB177:
- 1063:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1478 .loc 10 1063 3 view .LVU417
- 1479 005a 5A68 ldr r2, [r3, #4]
- 1480 005c 22F4E062 bic r2, r2, #1792
- 1481 0060 42F48062 orr r2, r2, #1024
- 1482 0064 5A60 str r2, [r3, #4]
- 1483 .LVL86:
- 1063:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1484 .loc 10 1063 3 is_stmt 0 view .LVU418
- 1485 .LBE177:
- 1486 .LBE176:
- 140:Core/Src/main.c **** LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
- 1487 .loc 1 140 3 is_stmt 1 view .LVU419
- 1488 .LBB178:
- 1489 .LBI178:
- 1077:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1490 .loc 10 1077 22 view .LVU420
- 1491 .LBB179:
- 1079:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1492 .loc 10 1079 3 view .LVU421
- 1493 0066 5A68 ldr r2, [r3, #4]
- 1494 0068 22F46052 bic r2, r2, #14336
- 1495 006c 5A60 str r2, [r3, #4]
- 1496 .LVL87:
- 1079:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1497 .loc 10 1079 3 is_stmt 0 view .LVU422
- 1498 .LBE179:
- 1499 .LBE178:
- 141:Core/Src/main.c ****
- 1500 .loc 1 141 3 is_stmt 1 view .LVU423
- 1501 .LBB180:
- 1502 .LBI180:
- 1012:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- ARM GAS /tmp/ccBGIhL8.s page 260
- 1503 .loc 10 1012 22 view .LVU424
- 1504 .LBB181:
- 1014:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1505 .loc 10 1014 3 view .LVU425
- 1506 006e 5A68 ldr r2, [r3, #4]
- 1507 0070 22F00302 bic r2, r2, #3
- 1508 0074 42F00202 orr r2, r2, #2
- 1509 0078 5A60 str r2, [r3, #4]
- 1510 .LVL88:
- 1014:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1511 .loc 10 1014 3 is_stmt 0 view .LVU426
- 1512 .LBE181:
- 1513 .LBE180:
- 144:Core/Src/main.c **** {
- 1514 .loc 1 144 3 is_stmt 1 view .LVU427
- 1515 .L43:
- 147:Core/Src/main.c **** LL_SetSystemCoreClock(48000000);
- 1516 .loc 1 147 3 view .LVU428
- 144:Core/Src/main.c **** {
- 1517 .loc 1 144 34 discriminator 1 view .LVU429
- 1518 .LBB182:
- 1519 .LBI182:
- 1025:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1520 .loc 10 1025 26 view .LVU430
- 1521 .LBB183:
- 1027:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1522 .loc 10 1027 3 view .LVU431
- 1027:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1523 .loc 10 1027 21 is_stmt 0 view .LVU432
- 1524 007a 0E4B ldr r3, .L47+4
- 1525 007c 5B68 ldr r3, [r3, #4]
- 1027:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1526 .loc 10 1027 10 view .LVU433
- 1527 007e 03F00C03 and r3, r3, #12
- 1528 .LBE183:
- 1529 .LBE182:
- 144:Core/Src/main.c **** {
- 1530 .loc 1 144 34 discriminator 1 view .LVU434
- 1531 0082 082B cmp r3, #8
- 1532 0084 F9D1 bne .L43
- 148:Core/Src/main.c ****
- 1533 .loc 1 148 3 is_stmt 1 view .LVU435
- 1534 0086 0C48 ldr r0, .L47+8
- 1535 0088 FFF7FEFF bl LL_SetSystemCoreClock
- 1536 .LVL89:
- 151:Core/Src/main.c **** {
- 1537 .loc 1 151 3 view .LVU436
- 151:Core/Src/main.c **** {
- 1538 .loc 1 151 7 is_stmt 0 view .LVU437
- 1539 008c 0F20 movs r0, #15
- 1540 008e FFF7FEFF bl HAL_InitTick
- 1541 .LVL90:
- 151:Core/Src/main.c **** {
- 1542 .loc 1 151 6 discriminator 1 view .LVU438
- 1543 0092 58B9 cbnz r0, .L46
- 155:Core/Src/main.c **** LL_RCC_SetUSBClockSource(LL_RCC_USB_CLKSOURCE_PLL);
- 1544 .loc 1 155 3 is_stmt 1 view .LVU439
- ARM GAS /tmp/ccBGIhL8.s page 261
- 1545 .LVL91:
- 1546 .LBB184:
- 1547 .LBI184:
- 1221:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1548 .loc 10 1221 22 view .LVU440
- 1549 .LBB185:
- 1223:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1550 .loc 10 1223 3 view .LVU441
- 1551 0094 074A ldr r2, .L47+4
- 1552 0096 5368 ldr r3, [r2, #4]
- 1553 0098 23F44043 bic r3, r3, #49152
- 1554 009c 43F48043 orr r3, r3, #16384
- 1555 00a0 5360 str r3, [r2, #4]
- 1556 .LVL92:
- 1223:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** }
- 1557 .loc 10 1223 3 is_stmt 0 view .LVU442
- 1558 .LBE185:
- 1559 .LBE184:
- 156:Core/Src/main.c **** }
- 1560 .loc 1 156 3 is_stmt 1 view .LVU443
- 1561 .LBB186:
- 1562 .LBI186:
- 1201:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** {
- 1563 .loc 10 1201 22 view .LVU444
- 1564 .LBB187:
- 1204:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #else /*RCC_CFGR_OTGFSPRE*/
- 1565 .loc 10 1204 3 view .LVU445
- 1566 00a2 5368 ldr r3, [r2, #4]
- 1567 00a4 43F48003 orr r3, r3, #4194304
- 1568 00a8 5360 str r3, [r2, #4]
- 1569 .LVL93:
- 1204:Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h **** #else /*RCC_CFGR_OTGFSPRE*/
- 1570 .loc 10 1204 3 is_stmt 0 view .LVU446
- 1571 .LBE187:
- 1572 .LBE186:
- 157:Core/Src/main.c ****
- 1573 .loc 1 157 1 view .LVU447
- 1574 00aa 08BD pop {r3, pc}
- 1575 .L46:
- 153:Core/Src/main.c **** }
- 1576 .loc 1 153 5 is_stmt 1 view .LVU448
- 1577 00ac FFF7FEFF bl Error_Handler
- 1578 .LVL94:
- 1579 .L48:
- 1580 .align 2
- 1581 .L47:
- 1582 00b0 00200240 .word 1073881088
- 1583 00b4 00100240 .word 1073876992
- 1584 00b8 006CDC02 .word 48000000
- 1585 .cfi_endproc
- 1586 .LFE656:
- 1588 .section .text.main,"ax",%progbits
- 1589 .align 1
- 1590 .global main
- 1591 .syntax unified
- 1592 .thumb
- 1593 .thumb_func
- ARM GAS /tmp/ccBGIhL8.s page 262
- 1595 main:
- 1596 .LFB655:
- 69:Core/Src/main.c **** /* USER CODE BEGIN 1 */
- 1597 .loc 1 69 1 view -0
- 1598 .cfi_startproc
- 1599 @ Volatile: function does not return.
- 1600 @ args = 0, pretend = 0, frame = 0
- 1601 @ frame_needed = 0, uses_anonymous_args = 0
- 1602 0000 08B5 push {r3, lr}
- 1603 .LCFI20:
- 1604 .cfi_def_cfa_offset 8
- 1605 .cfi_offset 3, -8
- 1606 .cfi_offset 14, -4
- 77:Core/Src/main.c ****
- 1607 .loc 1 77 3 view .LVU450
- 1608 0002 FFF7FEFF bl HAL_Init
- 1609 .LVL95:
- 84:Core/Src/main.c ****
- 1610 .loc 1 84 3 view .LVU451
- 1611 0006 FFF7FEFF bl SystemClock_Config
- 1612 .LVL96:
- 91:Core/Src/main.c **** MX_DMA_Init();
- 1613 .loc 1 91 3 view .LVU452
- 1614 000a FFF7FEFF bl MX_GPIO_Init
- 1615 .LVL97:
- 92:Core/Src/main.c **** MX_ADC1_Init();
- 1616 .loc 1 92 3 view .LVU453
- 1617 000e FFF7FEFF bl MX_DMA_Init
- 1618 .LVL98:
- 93:Core/Src/main.c **** MX_USB_DEVICE_Init();
- 1619 .loc 1 93 3 view .LVU454
- 1620 0012 FFF7FEFF bl MX_ADC1_Init
- 1621 .LVL99:
- 94:Core/Src/main.c **** MX_TIM1_Init();
- 1622 .loc 1 94 3 view .LVU455
- 1623 0016 FFF7FEFF bl MX_USB_DEVICE_Init
- 1624 .LVL100:
- 95:Core/Src/main.c **** /* USER CODE BEGIN 2 */
- 1625 .loc 1 95 3 view .LVU456
- 1626 001a FFF7FEFF bl MX_TIM1_Init
- 1627 .LVL101:
- 97:Core/Src/main.c **** LL_mDelay(500);
- 1628 .loc 1 97 3 view .LVU457
- 1629 001e FFF7FEFF bl PWM_init
- 1630 .LVL102:
- 98:Core/Src/main.c **** /* USER CODE END 2 */
- 1631 .loc 1 98 3 view .LVU458
- 1632 0022 4FF4FA70 mov r0, #500
- 1633 0026 FFF7FEFF bl LL_mDelay
- 1634 .LVL103:
- 1635 .L50:
- 103:Core/Src/main.c **** {
- 1636 .loc 1 103 3 view .LVU459
- 108:Core/Src/main.c **** }
- 1637 .loc 1 108 4 discriminator 1 view .LVU460
- 1638 002a 4FF4FA70 mov r0, #500
- 1639 002e FFF7FEFF bl LL_mDelay
- ARM GAS /tmp/ccBGIhL8.s page 263
- 1640 .LVL104:
- 103:Core/Src/main.c **** {
- 1641 .loc 1 103 9 view .LVU461
- 1642 0032 FAE7 b .L50
- 1643 .cfi_endproc
- 1644 .LFE655:
- 1646 .section .rodata.SHIFT_TAB_OCxx,"a"
- 1647 .align 2
- 1650 SHIFT_TAB_OCxx:
- 1651 0000 00000800 .ascii "\000\000\010\000\000\000\010"
- 1651 000008
- 1652 .section .rodata.OFFSET_TAB_CCMRx,"a"
- 1653 .align 2
- 1656 OFFSET_TAB_CCMRx:
- 1657 0000 00000000 .ascii "\000\000\000\000\004\004\004"
- 1657 040404
- 1658 .text
- 1659 .Letext0:
- 1660 .file 11 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h"
- 1661 .file 12 "/opt/gcc-arm/arm-none-eabi/include/machine/_default_types.h"
- 1662 .file 13 "/opt/gcc-arm/arm-none-eabi/include/sys/_stdint.h"
- 1663 .file 14 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h"
- 1664 .file 15 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h"
- 1665 .file 16 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h"
- 1666 .file 17 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_utils.h"
- 1667 .file 18 "Core/Inc/RFDAproto.h"
- 1668 .file 19 "USB_DEVICE/App/usb_device.h"
- 1669 .file 20 "<built-in>"
- ARM GAS /tmp/ccBGIhL8.s page 264
- DEFINED SYMBOLS
- *ABS*:00000000 main.c
- /tmp/ccBGIhL8.s:19 .text.NVIC_EncodePriority:00000000 $t
- /tmp/ccBGIhL8.s:24 .text.NVIC_EncodePriority:00000000 NVIC_EncodePriority
- /tmp/ccBGIhL8.s:87 .text.LL_ADC_INJ_SetSequencerRanks:00000000 $t
- /tmp/ccBGIhL8.s:92 .text.LL_ADC_INJ_SetSequencerRanks:00000000 LL_ADC_INJ_SetSequencerRanks
- /tmp/ccBGIhL8.s:144 .text.LL_TIM_OC_DisableFast:00000000 $t
- /tmp/ccBGIhL8.s:149 .text.LL_TIM_OC_DisableFast:00000000 LL_TIM_OC_DisableFast
- /tmp/ccBGIhL8.s:236 .text.LL_TIM_OC_DisableFast:0000005c $d
- /tmp/ccBGIhL8.s:1656 .rodata.OFFSET_TAB_CCMRx:00000000 OFFSET_TAB_CCMRx
- /tmp/ccBGIhL8.s:1650 .rodata.SHIFT_TAB_OCxx:00000000 SHIFT_TAB_OCxx
- /tmp/ccBGIhL8.s:242 .text.MX_DMA_Init:00000000 $t
- /tmp/ccBGIhL8.s:247 .text.MX_DMA_Init:00000000 MX_DMA_Init
- /tmp/ccBGIhL8.s:343 .text.MX_DMA_Init:00000040 $d
- /tmp/ccBGIhL8.s:350 .text.MX_GPIO_Init:00000000 $t
- /tmp/ccBGIhL8.s:355 .text.MX_GPIO_Init:00000000 MX_GPIO_Init
- /tmp/ccBGIhL8.s:519 .text.MX_GPIO_Init:00000080 $d
- /tmp/ccBGIhL8.s:527 .text.LL_ADC_SetChannelSamplingTime:00000000 $t
- /tmp/ccBGIhL8.s:532 .text.LL_ADC_SetChannelSamplingTime:00000000 LL_ADC_SetChannelSamplingTime
- /tmp/ccBGIhL8.s:636 .text.MX_ADC1_Init:00000000 $t
- /tmp/ccBGIhL8.s:641 .text.MX_ADC1_Init:00000000 MX_ADC1_Init
- /tmp/ccBGIhL8.s:908 .text.MX_ADC1_Init:0000010c $d
- /tmp/ccBGIhL8.s:919 .text.MX_TIM1_Init:00000000 $t
- /tmp/ccBGIhL8.s:924 .text.MX_TIM1_Init:00000000 MX_TIM1_Init
- /tmp/ccBGIhL8.s:1285 .text.MX_TIM1_Init:00000144 $d
- /tmp/ccBGIhL8.s:1294 .text.Error_Handler:00000000 $t
- /tmp/ccBGIhL8.s:1300 .text.Error_Handler:00000000 Error_Handler
- /tmp/ccBGIhL8.s:1331 .text.SystemClock_Config:00000000 $t
- /tmp/ccBGIhL8.s:1337 .text.SystemClock_Config:00000000 SystemClock_Config
- /tmp/ccBGIhL8.s:1582 .text.SystemClock_Config:000000b0 $d
- /tmp/ccBGIhL8.s:1589 .text.main:00000000 $t
- /tmp/ccBGIhL8.s:1595 .text.main:00000000 main
- /tmp/ccBGIhL8.s:1647 .rodata.SHIFT_TAB_OCxx:00000000 $d
- /tmp/ccBGIhL8.s:1653 .rodata.OFFSET_TAB_CCMRx:00000000 $d
- UNDEFINED SYMBOLS
- LL_GPIO_Init
- LL_ADC_Init
- LL_ADC_CommonInit
- LL_ADC_REG_Init
- LL_ADC_INJ_Init
- memset
- LL_TIM_Init
- LL_TIM_OC_Init
- LL_TIM_BDTR_Init
- LL_SetSystemCoreClock
- HAL_InitTick
- HAL_Init
- MX_USB_DEVICE_Init
- PWM_init
- LL_mDelay
|
