STM32_RFDA4005/build/stm32f1xx_hal_cortex.lst

ARM GAS  /tmp/ccMY5QHu.s 			page 1


   1              		.cpu cortex-m3
   2              		.arch armv7-m
   3              		.fpu softvfp
   4              		.eabi_attribute 20, 1
   5              		.eabi_attribute 21, 1
   6              		.eabi_attribute 23, 3
   7              		.eabi_attribute 24, 1
   8              		.eabi_attribute 25, 1
   9              		.eabi_attribute 26, 1
  10              		.eabi_attribute 30, 1
  11              		.eabi_attribute 34, 1
  12              		.eabi_attribute 18, 4
  13              		.file	"stm32f1xx_hal_cortex.c"
  14              		.text
  15              	.Ltext0:
  16              		.cfi_sections	.debug_frame
  17              		.section	.text.HAL_NVIC_SetPriorityGrouping,"ax",%progbits
  18              		.align	1
  19              		.global	HAL_NVIC_SetPriorityGrouping
  20              		.syntax unified
  21              		.thumb
  22              		.thumb_func
  24              	HAL_NVIC_SetPriorityGrouping:
  25              	.LVL0:
  26              	.LFB65:
  27              		.file 1 "Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c"
   1:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /**
   2:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   ******************************************************************************
   3:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @file    stm32f1xx_hal_cortex.c
   4:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @author  MCD Application Team
   5:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @brief   CORTEX HAL module driver.
   6:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *          This file provides firmware functions to manage the following 
   7:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *          functionalities of the CORTEX:
   8:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *           + Initialization and de-initialization functions
   9:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *           + Peripheral Control functions 
  10:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *
  11:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   @verbatim  
  12:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   ==============================================================================
  13:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****                         ##### How to use this driver #####
  14:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   ==============================================================================
  15:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
  16:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     [..]  
  17:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     *** How to configure Interrupts using CORTEX HAL driver ***
  18:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     ===========================================================
  19:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     [..]     
  20:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     This section provides functions allowing to configure the NVIC interrupts (IRQ).
  21:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     The Cortex-M3 exceptions are managed by CMSIS functions.
  22:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****    
  23:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
  24:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****         function according to the following table.
  25:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). 
  26:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
  27:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     (#) please refer to programming manual for details in how to configure priority. 
  28:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****       
  29:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****      -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. 
  30:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****          The pending IRQ priority will be managed only by the sub priority.
  31:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****    
ARM GAS  /tmp/ccMY5QHu.s 			page 2


  32:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****      -@- IRQ priority order (sorted by highest to lowest priority):
  33:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****         (+@) Lowest preemption priority
  34:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****         (+@) Lowest sub priority
  35:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****         (+@) Lowest hardware priority (IRQ number)
  36:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****  
  37:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     [..]  
  38:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     *** How to configure Systick using CORTEX HAL driver ***
  39:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     ========================================================
  40:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     [..]
  41:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     Setup SysTick Timer for time base.
  42:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****            
  43:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****    (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
  44:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****        is a CMSIS function that:
  45:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****         (++) Configures the SysTick Reload register with value passed as function parameter.
  46:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****         (++) Configures the SysTick IRQ priority to the lowest value 0x0F.
  47:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****         (++) Resets the SysTick Counter register.
  48:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****         (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
  49:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****         (++) Enables the SysTick Interrupt.
  50:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****         (++) Starts the SysTick Counter.
  51:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     
  52:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****    (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
  53:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****        __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
  54:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****        HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
  55:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****        inside the stm32f1xx_hal_cortex.h file.
  56:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
  57:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****    (+) You can change the SysTick IRQ priority by calling the
  58:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****        HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
  59:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****        call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS funct
  60:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
  61:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****    (+) To adjust the SysTick time base, use the following formula:
  62:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****                             
  63:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****        Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
  64:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****        (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
  65:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****        (++) Reload Value should not exceed 0xFFFFFF
  66:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****    
  67:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   @endverbatim
  68:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   ******************************************************************************
  69:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @attention
  70:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *
  71:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * Copyright (c) 2017 STMicroelectronics.
  72:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * All rights reserved.
  73:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *
  74:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * This software is licensed under terms that can be found in the LICENSE file in
  75:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * the root directory of this software component.
  76:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
  77:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *
  78:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   ******************************************************************************
  79:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   */
  80:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
  81:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Includes ------------------------------------------------------------------*/
  82:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** #include "stm32f1xx_hal.h"
  83:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
  84:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** @addtogroup STM32F1xx_HAL_Driver
  85:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @{
  86:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   */
  87:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
  88:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** @defgroup CORTEX CORTEX
ARM GAS  /tmp/ccMY5QHu.s 			page 3


  89:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @brief CORTEX HAL module driver
  90:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @{
  91:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   */
  92:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
  93:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** #ifdef HAL_CORTEX_MODULE_ENABLED
  94:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
  95:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Private types -------------------------------------------------------------*/
  96:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Private variables ---------------------------------------------------------*/
  97:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Private constants ---------------------------------------------------------*/
  98:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Private macros ------------------------------------------------------------*/
  99:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Private functions ---------------------------------------------------------*/
 100:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Exported functions --------------------------------------------------------*/
 101:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 102:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
 103:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @{
 104:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   */
 105:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 106:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 107:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
 108:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *  @brief    Initialization and Configuration functions 
 109:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *
 110:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** @verbatim    
 111:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   ==============================================================================
 112:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****               ##### Initialization and de-initialization functions #####
 113:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   ==============================================================================
 114:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     [..]
 115:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****       This section provides the CORTEX HAL driver functions allowing to configure Interrupts
 116:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****       Systick functionalities 
 117:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 118:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** @endverbatim
 119:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @{
 120:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   */
 121:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 122:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 123:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /**
 124:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @brief  Sets the priority grouping field (preemption priority and subpriority)
 125:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         using the required unlock sequence.
 126:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @param  PriorityGroup: The priority grouping bits length. 
 127:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         This parameter can be one of the following values:
 128:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
 129:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *                                    4 bits for subpriority
 130:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
 131:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *                                    3 bits for subpriority
 132:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
 133:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *                                    2 bits for subpriority
 134:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
 135:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *                                    1 bits for subpriority
 136:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
 137:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *                                    0 bits for subpriority
 138:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. 
 139:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         The pending IRQ priority will be managed only by the subpriority. 
 140:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @retval None
 141:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   */
 142:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
 143:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** {
  28              		.loc 1 143 1 view -0
  29              		.cfi_startproc
ARM GAS  /tmp/ccMY5QHu.s 			page 4


  30              		@ args = 0, pretend = 0, frame = 0
  31              		@ frame_needed = 0, uses_anonymous_args = 0
  32              		@ link register save eliminated.
 144:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   /* Check the parameters */
 145:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
  33              		.loc 1 145 3 view .LVU1
 146:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   
 147:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
 148:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   NVIC_SetPriorityGrouping(PriorityGroup);
  34              		.loc 1 148 3 view .LVU2
  35              	.LBB32:
  36              	.LBI32:
  37              		.file 2 "Drivers/CMSIS/Include/core_cm3.h"
   1:Drivers/CMSIS/Include/core_cm3.h **** /**************************************************************************//**
   2:Drivers/CMSIS/Include/core_cm3.h ****  * @file     core_cm3.h
   3:Drivers/CMSIS/Include/core_cm3.h ****  * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
   4:Drivers/CMSIS/Include/core_cm3.h ****  * @version  V5.0.8
   5:Drivers/CMSIS/Include/core_cm3.h ****  * @date     04. June 2018
   6:Drivers/CMSIS/Include/core_cm3.h ****  ******************************************************************************/
   7:Drivers/CMSIS/Include/core_cm3.h **** /*
   8:Drivers/CMSIS/Include/core_cm3.h ****  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
   9:Drivers/CMSIS/Include/core_cm3.h ****  *
  10:Drivers/CMSIS/Include/core_cm3.h ****  * SPDX-License-Identifier: Apache-2.0
  11:Drivers/CMSIS/Include/core_cm3.h ****  *
  12:Drivers/CMSIS/Include/core_cm3.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
  13:Drivers/CMSIS/Include/core_cm3.h ****  * not use this file except in compliance with the License.
  14:Drivers/CMSIS/Include/core_cm3.h ****  * You may obtain a copy of the License at
  15:Drivers/CMSIS/Include/core_cm3.h ****  *
  16:Drivers/CMSIS/Include/core_cm3.h ****  * www.apache.org/licenses/LICENSE-2.0
  17:Drivers/CMSIS/Include/core_cm3.h ****  *
  18:Drivers/CMSIS/Include/core_cm3.h ****  * Unless required by applicable law or agreed to in writing, software
  19:Drivers/CMSIS/Include/core_cm3.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20:Drivers/CMSIS/Include/core_cm3.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21:Drivers/CMSIS/Include/core_cm3.h ****  * See the License for the specific language governing permissions and
  22:Drivers/CMSIS/Include/core_cm3.h ****  * limitations under the License.
  23:Drivers/CMSIS/Include/core_cm3.h ****  */
  24:Drivers/CMSIS/Include/core_cm3.h **** 
  25:Drivers/CMSIS/Include/core_cm3.h **** #if   defined ( __ICCARM__ )
  26:Drivers/CMSIS/Include/core_cm3.h ****   #pragma system_include         /* treat file as system include file for MISRA check */
  27:Drivers/CMSIS/Include/core_cm3.h **** #elif defined (__clang__)
  28:Drivers/CMSIS/Include/core_cm3.h ****   #pragma clang system_header   /* treat file as system include file */
  29:Drivers/CMSIS/Include/core_cm3.h **** #endif
  30:Drivers/CMSIS/Include/core_cm3.h **** 
  31:Drivers/CMSIS/Include/core_cm3.h **** #ifndef __CORE_CM3_H_GENERIC
  32:Drivers/CMSIS/Include/core_cm3.h **** #define __CORE_CM3_H_GENERIC
  33:Drivers/CMSIS/Include/core_cm3.h **** 
  34:Drivers/CMSIS/Include/core_cm3.h **** #include <stdint.h>
  35:Drivers/CMSIS/Include/core_cm3.h **** 
  36:Drivers/CMSIS/Include/core_cm3.h **** #ifdef __cplusplus
  37:Drivers/CMSIS/Include/core_cm3.h ****  extern "C" {
  38:Drivers/CMSIS/Include/core_cm3.h **** #endif
  39:Drivers/CMSIS/Include/core_cm3.h **** 
  40:Drivers/CMSIS/Include/core_cm3.h **** /**
  41:Drivers/CMSIS/Include/core_cm3.h ****   \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
  42:Drivers/CMSIS/Include/core_cm3.h ****   CMSIS violates the following MISRA-C:2004 rules:
  43:Drivers/CMSIS/Include/core_cm3.h **** 
  44:Drivers/CMSIS/Include/core_cm3.h ****    \li Required Rule 8.5, object/function definition in header file.<br>
ARM GAS  /tmp/ccMY5QHu.s 			page 5


  45:Drivers/CMSIS/Include/core_cm3.h ****      Function definitions in header files are used to allow 'inlining'.
  46:Drivers/CMSIS/Include/core_cm3.h **** 
  47:Drivers/CMSIS/Include/core_cm3.h ****    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
  48:Drivers/CMSIS/Include/core_cm3.h ****      Unions are used for effective representation of core registers.
  49:Drivers/CMSIS/Include/core_cm3.h **** 
  50:Drivers/CMSIS/Include/core_cm3.h ****    \li Advisory Rule 19.7, Function-like macro defined.<br>
  51:Drivers/CMSIS/Include/core_cm3.h ****      Function-like macros are used to allow more efficient code.
  52:Drivers/CMSIS/Include/core_cm3.h ****  */
  53:Drivers/CMSIS/Include/core_cm3.h **** 
  54:Drivers/CMSIS/Include/core_cm3.h **** 
  55:Drivers/CMSIS/Include/core_cm3.h **** /*******************************************************************************
  56:Drivers/CMSIS/Include/core_cm3.h ****  *                 CMSIS definitions
  57:Drivers/CMSIS/Include/core_cm3.h ****  ******************************************************************************/
  58:Drivers/CMSIS/Include/core_cm3.h **** /**
  59:Drivers/CMSIS/Include/core_cm3.h ****   \ingroup Cortex_M3
  60:Drivers/CMSIS/Include/core_cm3.h ****   @{
  61:Drivers/CMSIS/Include/core_cm3.h ****  */
  62:Drivers/CMSIS/Include/core_cm3.h **** 
  63:Drivers/CMSIS/Include/core_cm3.h **** #include "cmsis_version.h"
  64:Drivers/CMSIS/Include/core_cm3.h **** 
  65:Drivers/CMSIS/Include/core_cm3.h **** /*  CMSIS CM3 definitions */
  66:Drivers/CMSIS/Include/core_cm3.h **** #define __CM3_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] C
  67:Drivers/CMSIS/Include/core_cm3.h **** #define __CM3_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  C
  68:Drivers/CMSIS/Include/core_cm3.h **** #define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
  69:Drivers/CMSIS/Include/core_cm3.h ****                                     __CM3_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL
  70:Drivers/CMSIS/Include/core_cm3.h **** 
  71:Drivers/CMSIS/Include/core_cm3.h **** #define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */
  72:Drivers/CMSIS/Include/core_cm3.h **** 
  73:Drivers/CMSIS/Include/core_cm3.h **** /** __FPU_USED indicates whether an FPU is used or not.
  74:Drivers/CMSIS/Include/core_cm3.h ****     This core does not support an FPU at all
  75:Drivers/CMSIS/Include/core_cm3.h **** */
  76:Drivers/CMSIS/Include/core_cm3.h **** #define __FPU_USED       0U
  77:Drivers/CMSIS/Include/core_cm3.h **** 
  78:Drivers/CMSIS/Include/core_cm3.h **** #if defined ( __CC_ARM )
  79:Drivers/CMSIS/Include/core_cm3.h ****   #if defined __TARGET_FPU_VFP
  80:Drivers/CMSIS/Include/core_cm3.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  81:Drivers/CMSIS/Include/core_cm3.h ****   #endif
  82:Drivers/CMSIS/Include/core_cm3.h **** 
  83:Drivers/CMSIS/Include/core_cm3.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  84:Drivers/CMSIS/Include/core_cm3.h ****   #if defined __ARM_PCS_VFP
  85:Drivers/CMSIS/Include/core_cm3.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  86:Drivers/CMSIS/Include/core_cm3.h ****   #endif
  87:Drivers/CMSIS/Include/core_cm3.h **** 
  88:Drivers/CMSIS/Include/core_cm3.h **** #elif defined ( __GNUC__ )
  89:Drivers/CMSIS/Include/core_cm3.h ****   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
  90:Drivers/CMSIS/Include/core_cm3.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  91:Drivers/CMSIS/Include/core_cm3.h ****   #endif
  92:Drivers/CMSIS/Include/core_cm3.h **** 
  93:Drivers/CMSIS/Include/core_cm3.h **** #elif defined ( __ICCARM__ )
  94:Drivers/CMSIS/Include/core_cm3.h ****   #if defined __ARMVFP__
  95:Drivers/CMSIS/Include/core_cm3.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  96:Drivers/CMSIS/Include/core_cm3.h ****   #endif
  97:Drivers/CMSIS/Include/core_cm3.h **** 
  98:Drivers/CMSIS/Include/core_cm3.h **** #elif defined ( __TI_ARM__ )
  99:Drivers/CMSIS/Include/core_cm3.h ****   #if defined __TI_VFP_SUPPORT__
 100:Drivers/CMSIS/Include/core_cm3.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
 101:Drivers/CMSIS/Include/core_cm3.h ****   #endif
ARM GAS  /tmp/ccMY5QHu.s 			page 6


 102:Drivers/CMSIS/Include/core_cm3.h **** 
 103:Drivers/CMSIS/Include/core_cm3.h **** #elif defined ( __TASKING__ )
 104:Drivers/CMSIS/Include/core_cm3.h ****   #if defined __FPU_VFP__
 105:Drivers/CMSIS/Include/core_cm3.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
 106:Drivers/CMSIS/Include/core_cm3.h ****   #endif
 107:Drivers/CMSIS/Include/core_cm3.h **** 
 108:Drivers/CMSIS/Include/core_cm3.h **** #elif defined ( __CSMC__ )
 109:Drivers/CMSIS/Include/core_cm3.h ****   #if ( __CSMC__ & 0x400U)
 110:Drivers/CMSIS/Include/core_cm3.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
 111:Drivers/CMSIS/Include/core_cm3.h ****   #endif
 112:Drivers/CMSIS/Include/core_cm3.h **** 
 113:Drivers/CMSIS/Include/core_cm3.h **** #endif
 114:Drivers/CMSIS/Include/core_cm3.h **** 
 115:Drivers/CMSIS/Include/core_cm3.h **** #include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
 116:Drivers/CMSIS/Include/core_cm3.h **** 
 117:Drivers/CMSIS/Include/core_cm3.h **** 
 118:Drivers/CMSIS/Include/core_cm3.h **** #ifdef __cplusplus
 119:Drivers/CMSIS/Include/core_cm3.h **** }
 120:Drivers/CMSIS/Include/core_cm3.h **** #endif
 121:Drivers/CMSIS/Include/core_cm3.h **** 
 122:Drivers/CMSIS/Include/core_cm3.h **** #endif /* __CORE_CM3_H_GENERIC */
 123:Drivers/CMSIS/Include/core_cm3.h **** 
 124:Drivers/CMSIS/Include/core_cm3.h **** #ifndef __CMSIS_GENERIC
 125:Drivers/CMSIS/Include/core_cm3.h **** 
 126:Drivers/CMSIS/Include/core_cm3.h **** #ifndef __CORE_CM3_H_DEPENDANT
 127:Drivers/CMSIS/Include/core_cm3.h **** #define __CORE_CM3_H_DEPENDANT
 128:Drivers/CMSIS/Include/core_cm3.h **** 
 129:Drivers/CMSIS/Include/core_cm3.h **** #ifdef __cplusplus
 130:Drivers/CMSIS/Include/core_cm3.h ****  extern "C" {
 131:Drivers/CMSIS/Include/core_cm3.h **** #endif
 132:Drivers/CMSIS/Include/core_cm3.h **** 
 133:Drivers/CMSIS/Include/core_cm3.h **** /* check device defines and use defaults */
 134:Drivers/CMSIS/Include/core_cm3.h **** #if defined __CHECK_DEVICE_DEFINES
 135:Drivers/CMSIS/Include/core_cm3.h ****   #ifndef __CM3_REV
 136:Drivers/CMSIS/Include/core_cm3.h ****     #define __CM3_REV               0x0200U
 137:Drivers/CMSIS/Include/core_cm3.h ****     #warning "__CM3_REV not defined in device header file; using default!"
 138:Drivers/CMSIS/Include/core_cm3.h ****   #endif
 139:Drivers/CMSIS/Include/core_cm3.h **** 
 140:Drivers/CMSIS/Include/core_cm3.h ****   #ifndef __MPU_PRESENT
 141:Drivers/CMSIS/Include/core_cm3.h ****     #define __MPU_PRESENT             0U
 142:Drivers/CMSIS/Include/core_cm3.h ****     #warning "__MPU_PRESENT not defined in device header file; using default!"
 143:Drivers/CMSIS/Include/core_cm3.h ****   #endif
 144:Drivers/CMSIS/Include/core_cm3.h **** 
 145:Drivers/CMSIS/Include/core_cm3.h ****   #ifndef __NVIC_PRIO_BITS
 146:Drivers/CMSIS/Include/core_cm3.h ****     #define __NVIC_PRIO_BITS          3U
 147:Drivers/CMSIS/Include/core_cm3.h ****     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
 148:Drivers/CMSIS/Include/core_cm3.h ****   #endif
 149:Drivers/CMSIS/Include/core_cm3.h **** 
 150:Drivers/CMSIS/Include/core_cm3.h ****   #ifndef __Vendor_SysTickConfig
 151:Drivers/CMSIS/Include/core_cm3.h ****     #define __Vendor_SysTickConfig    0U
 152:Drivers/CMSIS/Include/core_cm3.h ****     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
 153:Drivers/CMSIS/Include/core_cm3.h ****   #endif
 154:Drivers/CMSIS/Include/core_cm3.h **** #endif
 155:Drivers/CMSIS/Include/core_cm3.h **** 
 156:Drivers/CMSIS/Include/core_cm3.h **** /* IO definitions (access restrictions to peripheral registers) */
 157:Drivers/CMSIS/Include/core_cm3.h **** /**
 158:Drivers/CMSIS/Include/core_cm3.h ****     \defgroup CMSIS_glob_defs CMSIS Global Defines
ARM GAS  /tmp/ccMY5QHu.s 			page 7


 159:Drivers/CMSIS/Include/core_cm3.h **** 
 160:Drivers/CMSIS/Include/core_cm3.h ****     <strong>IO Type Qualifiers</strong> are used
 161:Drivers/CMSIS/Include/core_cm3.h ****     \li to specify the access to peripheral variables.
 162:Drivers/CMSIS/Include/core_cm3.h ****     \li for automatic generation of peripheral register debug information.
 163:Drivers/CMSIS/Include/core_cm3.h **** */
 164:Drivers/CMSIS/Include/core_cm3.h **** #ifdef __cplusplus
 165:Drivers/CMSIS/Include/core_cm3.h ****   #define   __I     volatile             /*!< Defines 'read only' permissions */
 166:Drivers/CMSIS/Include/core_cm3.h **** #else
 167:Drivers/CMSIS/Include/core_cm3.h ****   #define   __I     volatile const       /*!< Defines 'read only' permissions */
 168:Drivers/CMSIS/Include/core_cm3.h **** #endif
 169:Drivers/CMSIS/Include/core_cm3.h **** #define     __O     volatile             /*!< Defines 'write only' permissions */
 170:Drivers/CMSIS/Include/core_cm3.h **** #define     __IO    volatile             /*!< Defines 'read / write' permissions */
 171:Drivers/CMSIS/Include/core_cm3.h **** 
 172:Drivers/CMSIS/Include/core_cm3.h **** /* following defines should be used for structure members */
 173:Drivers/CMSIS/Include/core_cm3.h **** #define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
 174:Drivers/CMSIS/Include/core_cm3.h **** #define     __OM     volatile            /*! Defines 'write only' structure member permissions */
 175:Drivers/CMSIS/Include/core_cm3.h **** #define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
 176:Drivers/CMSIS/Include/core_cm3.h **** 
 177:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of group Cortex_M3 */
 178:Drivers/CMSIS/Include/core_cm3.h **** 
 179:Drivers/CMSIS/Include/core_cm3.h **** 
 180:Drivers/CMSIS/Include/core_cm3.h **** 
 181:Drivers/CMSIS/Include/core_cm3.h **** /*******************************************************************************
 182:Drivers/CMSIS/Include/core_cm3.h ****  *                 Register Abstraction
 183:Drivers/CMSIS/Include/core_cm3.h ****   Core Register contain:
 184:Drivers/CMSIS/Include/core_cm3.h ****   - Core Register
 185:Drivers/CMSIS/Include/core_cm3.h ****   - Core NVIC Register
 186:Drivers/CMSIS/Include/core_cm3.h ****   - Core SCB Register
 187:Drivers/CMSIS/Include/core_cm3.h ****   - Core SysTick Register
 188:Drivers/CMSIS/Include/core_cm3.h ****   - Core Debug Register
 189:Drivers/CMSIS/Include/core_cm3.h ****   - Core MPU Register
 190:Drivers/CMSIS/Include/core_cm3.h ****  ******************************************************************************/
 191:Drivers/CMSIS/Include/core_cm3.h **** /**
 192:Drivers/CMSIS/Include/core_cm3.h ****   \defgroup CMSIS_core_register Defines and Type Definitions
 193:Drivers/CMSIS/Include/core_cm3.h ****   \brief Type definitions and defines for Cortex-M processor based devices.
 194:Drivers/CMSIS/Include/core_cm3.h **** */
 195:Drivers/CMSIS/Include/core_cm3.h **** 
 196:Drivers/CMSIS/Include/core_cm3.h **** /**
 197:Drivers/CMSIS/Include/core_cm3.h ****   \ingroup    CMSIS_core_register
 198:Drivers/CMSIS/Include/core_cm3.h ****   \defgroup   CMSIS_CORE  Status and Control Registers
 199:Drivers/CMSIS/Include/core_cm3.h ****   \brief      Core Register type definitions.
 200:Drivers/CMSIS/Include/core_cm3.h ****   @{
 201:Drivers/CMSIS/Include/core_cm3.h ****  */
 202:Drivers/CMSIS/Include/core_cm3.h **** 
 203:Drivers/CMSIS/Include/core_cm3.h **** /**
 204:Drivers/CMSIS/Include/core_cm3.h ****   \brief  Union type to access the Application Program Status Register (APSR).
 205:Drivers/CMSIS/Include/core_cm3.h ****  */
 206:Drivers/CMSIS/Include/core_cm3.h **** typedef union
 207:Drivers/CMSIS/Include/core_cm3.h **** {
 208:Drivers/CMSIS/Include/core_cm3.h ****   struct
 209:Drivers/CMSIS/Include/core_cm3.h ****   {
 210:Drivers/CMSIS/Include/core_cm3.h ****     uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
 211:Drivers/CMSIS/Include/core_cm3.h ****     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
 212:Drivers/CMSIS/Include/core_cm3.h ****     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
 213:Drivers/CMSIS/Include/core_cm3.h ****     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
 214:Drivers/CMSIS/Include/core_cm3.h ****     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
 215:Drivers/CMSIS/Include/core_cm3.h ****     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
ARM GAS  /tmp/ccMY5QHu.s 			page 8


 216:Drivers/CMSIS/Include/core_cm3.h ****   } b;                                   /*!< Structure used for bit  access */
 217:Drivers/CMSIS/Include/core_cm3.h ****   uint32_t w;                            /*!< Type      used for word access */
 218:Drivers/CMSIS/Include/core_cm3.h **** } APSR_Type;
 219:Drivers/CMSIS/Include/core_cm3.h **** 
 220:Drivers/CMSIS/Include/core_cm3.h **** /* APSR Register Definitions */
 221:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_N_Pos                         31U                                            /*!< APSR
 222:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR
 223:Drivers/CMSIS/Include/core_cm3.h **** 
 224:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_Z_Pos                         30U                                            /*!< APSR
 225:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR
 226:Drivers/CMSIS/Include/core_cm3.h **** 
 227:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_C_Pos                         29U                                            /*!< APSR
 228:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR
 229:Drivers/CMSIS/Include/core_cm3.h **** 
 230:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_V_Pos                         28U                                            /*!< APSR
 231:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR
 232:Drivers/CMSIS/Include/core_cm3.h **** 
 233:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_Q_Pos                         27U                                            /*!< APSR
 234:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR
 235:Drivers/CMSIS/Include/core_cm3.h **** 
 236:Drivers/CMSIS/Include/core_cm3.h **** 
 237:Drivers/CMSIS/Include/core_cm3.h **** /**
 238:Drivers/CMSIS/Include/core_cm3.h ****   \brief  Union type to access the Interrupt Program Status Register (IPSR).
 239:Drivers/CMSIS/Include/core_cm3.h ****  */
 240:Drivers/CMSIS/Include/core_cm3.h **** typedef union
 241:Drivers/CMSIS/Include/core_cm3.h **** {
 242:Drivers/CMSIS/Include/core_cm3.h ****   struct
 243:Drivers/CMSIS/Include/core_cm3.h ****   {
 244:Drivers/CMSIS/Include/core_cm3.h ****     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
 245:Drivers/CMSIS/Include/core_cm3.h ****     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
 246:Drivers/CMSIS/Include/core_cm3.h ****   } b;                                   /*!< Structure used for bit  access */
 247:Drivers/CMSIS/Include/core_cm3.h ****   uint32_t w;                            /*!< Type      used for word access */
 248:Drivers/CMSIS/Include/core_cm3.h **** } IPSR_Type;
 249:Drivers/CMSIS/Include/core_cm3.h **** 
 250:Drivers/CMSIS/Include/core_cm3.h **** /* IPSR Register Definitions */
 251:Drivers/CMSIS/Include/core_cm3.h **** #define IPSR_ISR_Pos                        0U                                            /*!< IPSR
 252:Drivers/CMSIS/Include/core_cm3.h **** #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR
 253:Drivers/CMSIS/Include/core_cm3.h **** 
 254:Drivers/CMSIS/Include/core_cm3.h **** 
 255:Drivers/CMSIS/Include/core_cm3.h **** /**
 256:Drivers/CMSIS/Include/core_cm3.h ****   \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
 257:Drivers/CMSIS/Include/core_cm3.h ****  */
 258:Drivers/CMSIS/Include/core_cm3.h **** typedef union
 259:Drivers/CMSIS/Include/core_cm3.h **** {
 260:Drivers/CMSIS/Include/core_cm3.h ****   struct
 261:Drivers/CMSIS/Include/core_cm3.h ****   {
 262:Drivers/CMSIS/Include/core_cm3.h ****     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
 263:Drivers/CMSIS/Include/core_cm3.h ****     uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
 264:Drivers/CMSIS/Include/core_cm3.h ****     uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
 265:Drivers/CMSIS/Include/core_cm3.h ****     uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
 266:Drivers/CMSIS/Include/core_cm3.h ****     uint32_t T:1;                        /*!< bit:     24  Thumb bit */
 267:Drivers/CMSIS/Include/core_cm3.h ****     uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
 268:Drivers/CMSIS/Include/core_cm3.h ****     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
 269:Drivers/CMSIS/Include/core_cm3.h ****     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
 270:Drivers/CMSIS/Include/core_cm3.h ****     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
 271:Drivers/CMSIS/Include/core_cm3.h ****     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
 272:Drivers/CMSIS/Include/core_cm3.h ****     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
ARM GAS  /tmp/ccMY5QHu.s 			page 9


 273:Drivers/CMSIS/Include/core_cm3.h ****   } b;                                   /*!< Structure used for bit  access */
 274:Drivers/CMSIS/Include/core_cm3.h ****   uint32_t w;                            /*!< Type      used for word access */
 275:Drivers/CMSIS/Include/core_cm3.h **** } xPSR_Type;
 276:Drivers/CMSIS/Include/core_cm3.h **** 
 277:Drivers/CMSIS/Include/core_cm3.h **** /* xPSR Register Definitions */
 278:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_N_Pos                         31U                                            /*!< xPSR
 279:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR
 280:Drivers/CMSIS/Include/core_cm3.h **** 
 281:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_Z_Pos                         30U                                            /*!< xPSR
 282:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR
 283:Drivers/CMSIS/Include/core_cm3.h **** 
 284:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_C_Pos                         29U                                            /*!< xPSR
 285:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR
 286:Drivers/CMSIS/Include/core_cm3.h **** 
 287:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_V_Pos                         28U                                            /*!< xPSR
 288:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR
 289:Drivers/CMSIS/Include/core_cm3.h **** 
 290:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_Q_Pos                         27U                                            /*!< xPSR
 291:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR
 292:Drivers/CMSIS/Include/core_cm3.h **** 
 293:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR
 294:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR
 295:Drivers/CMSIS/Include/core_cm3.h **** 
 296:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_T_Pos                         24U                                            /*!< xPSR
 297:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR
 298:Drivers/CMSIS/Include/core_cm3.h **** 
 299:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR
 300:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR
 301:Drivers/CMSIS/Include/core_cm3.h **** 
 302:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_ISR_Pos                        0U                                            /*!< xPSR
 303:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR
 304:Drivers/CMSIS/Include/core_cm3.h **** 
 305:Drivers/CMSIS/Include/core_cm3.h **** 
 306:Drivers/CMSIS/Include/core_cm3.h **** /**
 307:Drivers/CMSIS/Include/core_cm3.h ****   \brief  Union type to access the Control Registers (CONTROL).
 308:Drivers/CMSIS/Include/core_cm3.h ****  */
 309:Drivers/CMSIS/Include/core_cm3.h **** typedef union
 310:Drivers/CMSIS/Include/core_cm3.h **** {
 311:Drivers/CMSIS/Include/core_cm3.h ****   struct
 312:Drivers/CMSIS/Include/core_cm3.h ****   {
 313:Drivers/CMSIS/Include/core_cm3.h ****     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
 314:Drivers/CMSIS/Include/core_cm3.h ****     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
 315:Drivers/CMSIS/Include/core_cm3.h ****     uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
 316:Drivers/CMSIS/Include/core_cm3.h ****   } b;                                   /*!< Structure used for bit  access */
 317:Drivers/CMSIS/Include/core_cm3.h ****   uint32_t w;                            /*!< Type      used for word access */
 318:Drivers/CMSIS/Include/core_cm3.h **** } CONTROL_Type;
 319:Drivers/CMSIS/Include/core_cm3.h **** 
 320:Drivers/CMSIS/Include/core_cm3.h **** /* CONTROL Register Definitions */
 321:Drivers/CMSIS/Include/core_cm3.h **** #define CONTROL_SPSEL_Pos                   1U                                            /*!< CONT
 322:Drivers/CMSIS/Include/core_cm3.h **** #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONT
 323:Drivers/CMSIS/Include/core_cm3.h **** 
 324:Drivers/CMSIS/Include/core_cm3.h **** #define CONTROL_nPRIV_Pos                   0U                                            /*!< CONT
 325:Drivers/CMSIS/Include/core_cm3.h **** #define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONT
 326:Drivers/CMSIS/Include/core_cm3.h **** 
 327:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of group CMSIS_CORE */
 328:Drivers/CMSIS/Include/core_cm3.h **** 
 329:Drivers/CMSIS/Include/core_cm3.h **** 
ARM GAS  /tmp/ccMY5QHu.s 			page 10


 330:Drivers/CMSIS/Include/core_cm3.h **** /**
 331:Drivers/CMSIS/Include/core_cm3.h ****   \ingroup    CMSIS_core_register
 332:Drivers/CMSIS/Include/core_cm3.h ****   \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
 333:Drivers/CMSIS/Include/core_cm3.h ****   \brief      Type definitions for the NVIC Registers
 334:Drivers/CMSIS/Include/core_cm3.h ****   @{
 335:Drivers/CMSIS/Include/core_cm3.h ****  */
 336:Drivers/CMSIS/Include/core_cm3.h **** 
 337:Drivers/CMSIS/Include/core_cm3.h **** /**
 338:Drivers/CMSIS/Include/core_cm3.h ****   \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
 339:Drivers/CMSIS/Include/core_cm3.h ****  */
 340:Drivers/CMSIS/Include/core_cm3.h **** typedef struct
 341:Drivers/CMSIS/Include/core_cm3.h **** {
 342:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
 343:Drivers/CMSIS/Include/core_cm3.h ****         uint32_t RESERVED0[24U];
 344:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register 
 345:Drivers/CMSIS/Include/core_cm3.h ****         uint32_t RSERVED1[24U];
 346:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register *
 347:Drivers/CMSIS/Include/core_cm3.h ****         uint32_t RESERVED2[24U];
 348:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register
 349:Drivers/CMSIS/Include/core_cm3.h ****         uint32_t RESERVED3[24U];
 350:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
 351:Drivers/CMSIS/Include/core_cm3.h ****         uint32_t RESERVED4[56U];
 352:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bi
 353:Drivers/CMSIS/Include/core_cm3.h ****         uint32_t RESERVED5[644U];
 354:Drivers/CMSIS/Include/core_cm3.h ****   __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Regis
 355:Drivers/CMSIS/Include/core_cm3.h **** }  NVIC_Type;
 356:Drivers/CMSIS/Include/core_cm3.h **** 
 357:Drivers/CMSIS/Include/core_cm3.h **** /* Software Triggered Interrupt Register Definitions */
 358:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: I
 359:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: I
 360:Drivers/CMSIS/Include/core_cm3.h **** 
 361:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of group CMSIS_NVIC */
 362:Drivers/CMSIS/Include/core_cm3.h **** 
 363:Drivers/CMSIS/Include/core_cm3.h **** 
 364:Drivers/CMSIS/Include/core_cm3.h **** /**
 365:Drivers/CMSIS/Include/core_cm3.h ****   \ingroup  CMSIS_core_register
 366:Drivers/CMSIS/Include/core_cm3.h ****   \defgroup CMSIS_SCB     System Control Block (SCB)
 367:Drivers/CMSIS/Include/core_cm3.h ****   \brief    Type definitions for the System Control Block Registers
 368:Drivers/CMSIS/Include/core_cm3.h ****   @{
 369:Drivers/CMSIS/Include/core_cm3.h ****  */
 370:Drivers/CMSIS/Include/core_cm3.h **** 
 371:Drivers/CMSIS/Include/core_cm3.h **** /**
 372:Drivers/CMSIS/Include/core_cm3.h ****   \brief  Structure type to access the System Control Block (SCB).
 373:Drivers/CMSIS/Include/core_cm3.h ****  */
 374:Drivers/CMSIS/Include/core_cm3.h **** typedef struct
 375:Drivers/CMSIS/Include/core_cm3.h **** {
 376:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
 377:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Regi
 378:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
 379:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset 
 380:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
 381:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register *
 382:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registe
 383:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State
 384:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Regist
 385:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
 386:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
ARM GAS  /tmp/ccMY5QHu.s 			page 11


 387:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register
 388:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
 389:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register 
 390:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
 391:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
 392:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
 393:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
 394:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Regis
 395:Drivers/CMSIS/Include/core_cm3.h ****         uint32_t RESERVED0[5U];
 396:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Regis
 397:Drivers/CMSIS/Include/core_cm3.h **** } SCB_Type;
 398:Drivers/CMSIS/Include/core_cm3.h **** 
 399:Drivers/CMSIS/Include/core_cm3.h **** /* SCB CPUID Register Definitions */
 400:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB 
 401:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB 
 402:Drivers/CMSIS/Include/core_cm3.h **** 
 403:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB 
 404:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB 
 405:Drivers/CMSIS/Include/core_cm3.h **** 
 406:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB 
 407:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB 
 408:Drivers/CMSIS/Include/core_cm3.h **** 
 409:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB 
 410:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB 
 411:Drivers/CMSIS/Include/core_cm3.h **** 
 412:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB 
 413:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB 
 414:Drivers/CMSIS/Include/core_cm3.h **** 
 415:Drivers/CMSIS/Include/core_cm3.h **** /* SCB Interrupt Control State Register Definitions */
 416:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB 
 417:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB 
 418:Drivers/CMSIS/Include/core_cm3.h **** 
 419:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB 
 420:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB 
 421:Drivers/CMSIS/Include/core_cm3.h **** 
 422:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB 
 423:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB 
 424:Drivers/CMSIS/Include/core_cm3.h **** 
 425:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB 
 426:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB 
 427:Drivers/CMSIS/Include/core_cm3.h **** 
 428:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB 
 429:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB 
 430:Drivers/CMSIS/Include/core_cm3.h **** 
 431:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB 
 432:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB 
 433:Drivers/CMSIS/Include/core_cm3.h **** 
 434:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB 
 435:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB 
 436:Drivers/CMSIS/Include/core_cm3.h **** 
 437:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB 
 438:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB 
 439:Drivers/CMSIS/Include/core_cm3.h **** 
 440:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB 
 441:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB 
 442:Drivers/CMSIS/Include/core_cm3.h **** 
 443:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB 
ARM GAS  /tmp/ccMY5QHu.s 			page 12


 444:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB 
 445:Drivers/CMSIS/Include/core_cm3.h **** 
 446:Drivers/CMSIS/Include/core_cm3.h **** /* SCB Vector Table Offset Register Definitions */
 447:Drivers/CMSIS/Include/core_cm3.h **** #if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */
 448:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB 
 449:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB 
 450:Drivers/CMSIS/Include/core_cm3.h **** 
 451:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB 
 452:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB 
 453:Drivers/CMSIS/Include/core_cm3.h **** #else
 454:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB 
 455:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB 
 456:Drivers/CMSIS/Include/core_cm3.h **** #endif
 457:Drivers/CMSIS/Include/core_cm3.h **** 
 458:Drivers/CMSIS/Include/core_cm3.h **** /* SCB Application Interrupt and Reset Control Register Definitions */
 459:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB 
 460:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB 
 461:Drivers/CMSIS/Include/core_cm3.h **** 
 462:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB 
 463:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB 
 464:Drivers/CMSIS/Include/core_cm3.h **** 
 465:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB 
 466:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB 
 467:Drivers/CMSIS/Include/core_cm3.h **** 
 468:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB 
 469:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB 
 470:Drivers/CMSIS/Include/core_cm3.h **** 
 471:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB 
 472:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB 
 473:Drivers/CMSIS/Include/core_cm3.h **** 
 474:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB 
 475:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB 
 476:Drivers/CMSIS/Include/core_cm3.h **** 
 477:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB 
 478:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB 
 479:Drivers/CMSIS/Include/core_cm3.h **** 
 480:Drivers/CMSIS/Include/core_cm3.h **** /* SCB System Control Register Definitions */
 481:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB 
 482:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB 
 483:Drivers/CMSIS/Include/core_cm3.h **** 
 484:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB 
 485:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB 
 486:Drivers/CMSIS/Include/core_cm3.h **** 
 487:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB 
 488:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB 
 489:Drivers/CMSIS/Include/core_cm3.h **** 
 490:Drivers/CMSIS/Include/core_cm3.h **** /* SCB Configuration Control Register Definitions */
 491:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB 
 492:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB 
 493:Drivers/CMSIS/Include/core_cm3.h **** 
 494:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB 
 495:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB 
 496:Drivers/CMSIS/Include/core_cm3.h **** 
 497:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB 
 498:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB 
 499:Drivers/CMSIS/Include/core_cm3.h **** 
 500:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB 
ARM GAS  /tmp/ccMY5QHu.s 			page 13


 501:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB 
 502:Drivers/CMSIS/Include/core_cm3.h **** 
 503:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB 
 504:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB 
 505:Drivers/CMSIS/Include/core_cm3.h **** 
 506:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB 
 507:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB 
 508:Drivers/CMSIS/Include/core_cm3.h **** 
 509:Drivers/CMSIS/Include/core_cm3.h **** /* SCB System Handler Control and State Register Definitions */
 510:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB 
 511:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB 
 512:Drivers/CMSIS/Include/core_cm3.h **** 
 513:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB 
 514:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB 
 515:Drivers/CMSIS/Include/core_cm3.h **** 
 516:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB 
 517:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB 
 518:Drivers/CMSIS/Include/core_cm3.h **** 
 519:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB 
 520:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB 
 521:Drivers/CMSIS/Include/core_cm3.h **** 
 522:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB 
 523:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB 
 524:Drivers/CMSIS/Include/core_cm3.h **** 
 525:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB 
 526:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB 
 527:Drivers/CMSIS/Include/core_cm3.h **** 
 528:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB 
 529:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB 
 530:Drivers/CMSIS/Include/core_cm3.h **** 
 531:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB 
 532:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB 
 533:Drivers/CMSIS/Include/core_cm3.h **** 
 534:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB 
 535:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB 
 536:Drivers/CMSIS/Include/core_cm3.h **** 
 537:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB 
 538:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB 
 539:Drivers/CMSIS/Include/core_cm3.h **** 
 540:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB 
 541:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB 
 542:Drivers/CMSIS/Include/core_cm3.h **** 
 543:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB 
 544:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB 
 545:Drivers/CMSIS/Include/core_cm3.h **** 
 546:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB 
 547:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB 
 548:Drivers/CMSIS/Include/core_cm3.h **** 
 549:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB 
 550:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB 
 551:Drivers/CMSIS/Include/core_cm3.h **** 
 552:Drivers/CMSIS/Include/core_cm3.h **** /* SCB Configurable Fault Status Register Definitions */
 553:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB 
 554:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB 
 555:Drivers/CMSIS/Include/core_cm3.h **** 
 556:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB 
 557:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB 
ARM GAS  /tmp/ccMY5QHu.s 			page 14


 558:Drivers/CMSIS/Include/core_cm3.h **** 
 559:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB 
 560:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB 
 561:Drivers/CMSIS/Include/core_cm3.h **** 
 562:Drivers/CMSIS/Include/core_cm3.h **** /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
 563:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB 
 564:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB 
 565:Drivers/CMSIS/Include/core_cm3.h **** 
 566:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB 
 567:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB 
 568:Drivers/CMSIS/Include/core_cm3.h **** 
 569:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB 
 570:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB 
 571:Drivers/CMSIS/Include/core_cm3.h **** 
 572:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB 
 573:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB 
 574:Drivers/CMSIS/Include/core_cm3.h **** 
 575:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB 
 576:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB 
 577:Drivers/CMSIS/Include/core_cm3.h **** 
 578:Drivers/CMSIS/Include/core_cm3.h **** /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
 579:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB 
 580:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB 
 581:Drivers/CMSIS/Include/core_cm3.h **** 
 582:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB 
 583:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB 
 584:Drivers/CMSIS/Include/core_cm3.h **** 
 585:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB 
 586:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB 
 587:Drivers/CMSIS/Include/core_cm3.h **** 
 588:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB 
 589:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB 
 590:Drivers/CMSIS/Include/core_cm3.h **** 
 591:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB 
 592:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB 
 593:Drivers/CMSIS/Include/core_cm3.h **** 
 594:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB 
 595:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB 
 596:Drivers/CMSIS/Include/core_cm3.h **** 
 597:Drivers/CMSIS/Include/core_cm3.h **** /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
 598:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB 
 599:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB 
 600:Drivers/CMSIS/Include/core_cm3.h **** 
 601:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB 
 602:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB 
 603:Drivers/CMSIS/Include/core_cm3.h **** 
 604:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB 
 605:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB 
 606:Drivers/CMSIS/Include/core_cm3.h **** 
 607:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB 
 608:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB 
 609:Drivers/CMSIS/Include/core_cm3.h **** 
 610:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB 
 611:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB 
 612:Drivers/CMSIS/Include/core_cm3.h **** 
 613:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB 
 614:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB 
ARM GAS  /tmp/ccMY5QHu.s 			page 15


 615:Drivers/CMSIS/Include/core_cm3.h **** 
 616:Drivers/CMSIS/Include/core_cm3.h **** /* SCB Hard Fault Status Register Definitions */
 617:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB 
 618:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB 
 619:Drivers/CMSIS/Include/core_cm3.h **** 
 620:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB 
 621:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB 
 622:Drivers/CMSIS/Include/core_cm3.h **** 
 623:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB 
 624:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB 
 625:Drivers/CMSIS/Include/core_cm3.h **** 
 626:Drivers/CMSIS/Include/core_cm3.h **** /* SCB Debug Fault Status Register Definitions */
 627:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB 
 628:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB 
 629:Drivers/CMSIS/Include/core_cm3.h **** 
 630:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB 
 631:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB 
 632:Drivers/CMSIS/Include/core_cm3.h **** 
 633:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB 
 634:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB 
 635:Drivers/CMSIS/Include/core_cm3.h **** 
 636:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB 
 637:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB 
 638:Drivers/CMSIS/Include/core_cm3.h **** 
 639:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB 
 640:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB 
 641:Drivers/CMSIS/Include/core_cm3.h **** 
 642:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of group CMSIS_SCB */
 643:Drivers/CMSIS/Include/core_cm3.h **** 
 644:Drivers/CMSIS/Include/core_cm3.h **** 
 645:Drivers/CMSIS/Include/core_cm3.h **** /**
 646:Drivers/CMSIS/Include/core_cm3.h ****   \ingroup  CMSIS_core_register
 647:Drivers/CMSIS/Include/core_cm3.h ****   \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
 648:Drivers/CMSIS/Include/core_cm3.h ****   \brief    Type definitions for the System Control and ID Register not in the SCB
 649:Drivers/CMSIS/Include/core_cm3.h ****   @{
 650:Drivers/CMSIS/Include/core_cm3.h ****  */
 651:Drivers/CMSIS/Include/core_cm3.h **** 
 652:Drivers/CMSIS/Include/core_cm3.h **** /**
 653:Drivers/CMSIS/Include/core_cm3.h ****   \brief  Structure type to access the System Control and ID Register not in the SCB.
 654:Drivers/CMSIS/Include/core_cm3.h ****  */
 655:Drivers/CMSIS/Include/core_cm3.h **** typedef struct
 656:Drivers/CMSIS/Include/core_cm3.h **** {
 657:Drivers/CMSIS/Include/core_cm3.h ****         uint32_t RESERVED0[1U];
 658:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Regist
 659:Drivers/CMSIS/Include/core_cm3.h **** #if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
 660:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
 661:Drivers/CMSIS/Include/core_cm3.h **** #else
 662:Drivers/CMSIS/Include/core_cm3.h ****         uint32_t RESERVED1[1U];
 663:Drivers/CMSIS/Include/core_cm3.h **** #endif
 664:Drivers/CMSIS/Include/core_cm3.h **** } SCnSCB_Type;
 665:Drivers/CMSIS/Include/core_cm3.h **** 
 666:Drivers/CMSIS/Include/core_cm3.h **** /* Interrupt Controller Type Register Definitions */
 667:Drivers/CMSIS/Include/core_cm3.h **** #define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: I
 668:Drivers/CMSIS/Include/core_cm3.h **** #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: I
 669:Drivers/CMSIS/Include/core_cm3.h **** 
 670:Drivers/CMSIS/Include/core_cm3.h **** /* Auxiliary Control Register Definitions */
 671:Drivers/CMSIS/Include/core_cm3.h **** 
ARM GAS  /tmp/ccMY5QHu.s 			page 16


 672:Drivers/CMSIS/Include/core_cm3.h **** #define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: 
 673:Drivers/CMSIS/Include/core_cm3.h **** #define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: 
 674:Drivers/CMSIS/Include/core_cm3.h **** 
 675:Drivers/CMSIS/Include/core_cm3.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: 
 676:Drivers/CMSIS/Include/core_cm3.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: 
 677:Drivers/CMSIS/Include/core_cm3.h **** 
 678:Drivers/CMSIS/Include/core_cm3.h **** #define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: 
 679:Drivers/CMSIS/Include/core_cm3.h **** #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: 
 680:Drivers/CMSIS/Include/core_cm3.h **** 
 681:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of group CMSIS_SCnotSCB */
 682:Drivers/CMSIS/Include/core_cm3.h **** 
 683:Drivers/CMSIS/Include/core_cm3.h **** 
 684:Drivers/CMSIS/Include/core_cm3.h **** /**
 685:Drivers/CMSIS/Include/core_cm3.h ****   \ingroup  CMSIS_core_register
 686:Drivers/CMSIS/Include/core_cm3.h ****   \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
 687:Drivers/CMSIS/Include/core_cm3.h ****   \brief    Type definitions for the System Timer Registers.
 688:Drivers/CMSIS/Include/core_cm3.h ****   @{
 689:Drivers/CMSIS/Include/core_cm3.h ****  */
 690:Drivers/CMSIS/Include/core_cm3.h **** 
 691:Drivers/CMSIS/Include/core_cm3.h **** /**
 692:Drivers/CMSIS/Include/core_cm3.h ****   \brief  Structure type to access the System Timer (SysTick).
 693:Drivers/CMSIS/Include/core_cm3.h ****  */
 694:Drivers/CMSIS/Include/core_cm3.h **** typedef struct
 695:Drivers/CMSIS/Include/core_cm3.h **** {
 696:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Regis
 697:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
 698:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register *
 699:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
 700:Drivers/CMSIS/Include/core_cm3.h **** } SysTick_Type;
 701:Drivers/CMSIS/Include/core_cm3.h **** 
 702:Drivers/CMSIS/Include/core_cm3.h **** /* SysTick Control / Status Register Definitions */
 703:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysT
 704:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysT
 705:Drivers/CMSIS/Include/core_cm3.h **** 
 706:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysT
 707:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysT
 708:Drivers/CMSIS/Include/core_cm3.h **** 
 709:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysT
 710:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysT
 711:Drivers/CMSIS/Include/core_cm3.h **** 
 712:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysT
 713:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysT
 714:Drivers/CMSIS/Include/core_cm3.h **** 
 715:Drivers/CMSIS/Include/core_cm3.h **** /* SysTick Reload Register Definitions */
 716:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysT
 717:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysT
 718:Drivers/CMSIS/Include/core_cm3.h **** 
 719:Drivers/CMSIS/Include/core_cm3.h **** /* SysTick Current Register Definitions */
 720:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysT
 721:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysT
 722:Drivers/CMSIS/Include/core_cm3.h **** 
 723:Drivers/CMSIS/Include/core_cm3.h **** /* SysTick Calibration Register Definitions */
 724:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysT
 725:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysT
 726:Drivers/CMSIS/Include/core_cm3.h **** 
 727:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysT
 728:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysT
ARM GAS  /tmp/ccMY5QHu.s 			page 17


 729:Drivers/CMSIS/Include/core_cm3.h **** 
 730:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysT
 731:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysT
 732:Drivers/CMSIS/Include/core_cm3.h **** 
 733:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of group CMSIS_SysTick */
 734:Drivers/CMSIS/Include/core_cm3.h **** 
 735:Drivers/CMSIS/Include/core_cm3.h **** 
 736:Drivers/CMSIS/Include/core_cm3.h **** /**
 737:Drivers/CMSIS/Include/core_cm3.h ****   \ingroup  CMSIS_core_register
 738:Drivers/CMSIS/Include/core_cm3.h ****   \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
 739:Drivers/CMSIS/Include/core_cm3.h ****   \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
 740:Drivers/CMSIS/Include/core_cm3.h ****   @{
 741:Drivers/CMSIS/Include/core_cm3.h ****  */
 742:Drivers/CMSIS/Include/core_cm3.h **** 
 743:Drivers/CMSIS/Include/core_cm3.h **** /**
 744:Drivers/CMSIS/Include/core_cm3.h ****   \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
 745:Drivers/CMSIS/Include/core_cm3.h ****  */
 746:Drivers/CMSIS/Include/core_cm3.h **** typedef struct
 747:Drivers/CMSIS/Include/core_cm3.h **** {
 748:Drivers/CMSIS/Include/core_cm3.h ****   __OM  union
 749:Drivers/CMSIS/Include/core_cm3.h ****   {
 750:Drivers/CMSIS/Include/core_cm3.h ****     __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
 751:Drivers/CMSIS/Include/core_cm3.h ****     __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
 752:Drivers/CMSIS/Include/core_cm3.h ****     __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
 753:Drivers/CMSIS/Include/core_cm3.h ****   }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
 754:Drivers/CMSIS/Include/core_cm3.h ****         uint32_t RESERVED0[864U];
 755:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
 756:Drivers/CMSIS/Include/core_cm3.h ****         uint32_t RESERVED1[15U];
 757:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
 758:Drivers/CMSIS/Include/core_cm3.h ****         uint32_t RESERVED2[15U];
 759:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
 760:Drivers/CMSIS/Include/core_cm3.h ****         uint32_t RESERVED3[29U];
 761:Drivers/CMSIS/Include/core_cm3.h ****   __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register *
 762:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
 763:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Reg
 764:Drivers/CMSIS/Include/core_cm3.h ****         uint32_t RESERVED4[43U];
 765:Drivers/CMSIS/Include/core_cm3.h ****   __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
 766:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
 767:Drivers/CMSIS/Include/core_cm3.h ****         uint32_t RESERVED5[6U];
 768:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Re
 769:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Re
 770:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Re
 771:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Re
 772:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Re
 773:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Re
 774:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Re
 775:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Re
 776:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Re
 777:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Re
 778:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Re
 779:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Re
 780:Drivers/CMSIS/Include/core_cm3.h **** } ITM_Type;
 781:Drivers/CMSIS/Include/core_cm3.h **** 
 782:Drivers/CMSIS/Include/core_cm3.h **** /* ITM Trace Privilege Register Definitions */
 783:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM 
 784:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM 
 785:Drivers/CMSIS/Include/core_cm3.h **** 
ARM GAS  /tmp/ccMY5QHu.s 			page 18


 786:Drivers/CMSIS/Include/core_cm3.h **** /* ITM Trace Control Register Definitions */
 787:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM 
 788:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM 
 789:Drivers/CMSIS/Include/core_cm3.h **** 
 790:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM 
 791:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM 
 792:Drivers/CMSIS/Include/core_cm3.h **** 
 793:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM 
 794:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM 
 795:Drivers/CMSIS/Include/core_cm3.h **** 
 796:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM 
 797:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM 
 798:Drivers/CMSIS/Include/core_cm3.h **** 
 799:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM 
 800:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM 
 801:Drivers/CMSIS/Include/core_cm3.h **** 
 802:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM 
 803:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM 
 804:Drivers/CMSIS/Include/core_cm3.h **** 
 805:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM 
 806:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM 
 807:Drivers/CMSIS/Include/core_cm3.h **** 
 808:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM 
 809:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM 
 810:Drivers/CMSIS/Include/core_cm3.h **** 
 811:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM 
 812:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM 
 813:Drivers/CMSIS/Include/core_cm3.h **** 
 814:Drivers/CMSIS/Include/core_cm3.h **** /* ITM Integration Write Register Definitions */
 815:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM 
 816:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM 
 817:Drivers/CMSIS/Include/core_cm3.h **** 
 818:Drivers/CMSIS/Include/core_cm3.h **** /* ITM Integration Read Register Definitions */
 819:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM 
 820:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM 
 821:Drivers/CMSIS/Include/core_cm3.h **** 
 822:Drivers/CMSIS/Include/core_cm3.h **** /* ITM Integration Mode Control Register Definitions */
 823:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM 
 824:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM 
 825:Drivers/CMSIS/Include/core_cm3.h **** 
 826:Drivers/CMSIS/Include/core_cm3.h **** /* ITM Lock Status Register Definitions */
 827:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM 
 828:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM 
 829:Drivers/CMSIS/Include/core_cm3.h **** 
 830:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_LSR_Access_Pos                  1U                                            /*!< ITM 
 831:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM 
 832:Drivers/CMSIS/Include/core_cm3.h **** 
 833:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_LSR_Present_Pos                 0U                                            /*!< ITM 
 834:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM 
 835:Drivers/CMSIS/Include/core_cm3.h **** 
 836:Drivers/CMSIS/Include/core_cm3.h **** /*@}*/ /* end of group CMSIS_ITM */
 837:Drivers/CMSIS/Include/core_cm3.h **** 
 838:Drivers/CMSIS/Include/core_cm3.h **** 
 839:Drivers/CMSIS/Include/core_cm3.h **** /**
 840:Drivers/CMSIS/Include/core_cm3.h ****   \ingroup  CMSIS_core_register
 841:Drivers/CMSIS/Include/core_cm3.h ****   \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
 842:Drivers/CMSIS/Include/core_cm3.h ****   \brief    Type definitions for the Data Watchpoint and Trace (DWT)
ARM GAS  /tmp/ccMY5QHu.s 			page 19


 843:Drivers/CMSIS/Include/core_cm3.h ****   @{
 844:Drivers/CMSIS/Include/core_cm3.h ****  */
 845:Drivers/CMSIS/Include/core_cm3.h **** 
 846:Drivers/CMSIS/Include/core_cm3.h **** /**
 847:Drivers/CMSIS/Include/core_cm3.h ****   \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
 848:Drivers/CMSIS/Include/core_cm3.h ****  */
 849:Drivers/CMSIS/Include/core_cm3.h **** typedef struct
 850:Drivers/CMSIS/Include/core_cm3.h **** {
 851:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
 852:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
 853:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
 854:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Registe
 855:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
 856:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
 857:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Registe
 858:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register 
 859:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
 860:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
 861:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
 862:Drivers/CMSIS/Include/core_cm3.h ****         uint32_t RESERVED0[1U];
 863:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
 864:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
 865:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
 866:Drivers/CMSIS/Include/core_cm3.h ****         uint32_t RESERVED1[1U];
 867:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
 868:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
 869:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
 870:Drivers/CMSIS/Include/core_cm3.h ****         uint32_t RESERVED2[1U];
 871:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
 872:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
 873:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
 874:Drivers/CMSIS/Include/core_cm3.h **** } DWT_Type;
 875:Drivers/CMSIS/Include/core_cm3.h **** 
 876:Drivers/CMSIS/Include/core_cm3.h **** /* DWT Control Register Definitions */
 877:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTR
 878:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTR
 879:Drivers/CMSIS/Include/core_cm3.h **** 
 880:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTR
 881:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTR
 882:Drivers/CMSIS/Include/core_cm3.h **** 
 883:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTR
 884:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTR
 885:Drivers/CMSIS/Include/core_cm3.h **** 
 886:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTR
 887:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTR
 888:Drivers/CMSIS/Include/core_cm3.h **** 
 889:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTR
 890:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTR
 891:Drivers/CMSIS/Include/core_cm3.h **** 
 892:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTR
 893:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTR
 894:Drivers/CMSIS/Include/core_cm3.h **** 
 895:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTR
 896:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTR
 897:Drivers/CMSIS/Include/core_cm3.h **** 
 898:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTR
 899:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTR
ARM GAS  /tmp/ccMY5QHu.s 			page 20


 900:Drivers/CMSIS/Include/core_cm3.h **** 
 901:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTR
 902:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTR
 903:Drivers/CMSIS/Include/core_cm3.h **** 
 904:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTR
 905:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTR
 906:Drivers/CMSIS/Include/core_cm3.h **** 
 907:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTR
 908:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTR
 909:Drivers/CMSIS/Include/core_cm3.h **** 
 910:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTR
 911:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTR
 912:Drivers/CMSIS/Include/core_cm3.h **** 
 913:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTR
 914:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTR
 915:Drivers/CMSIS/Include/core_cm3.h **** 
 916:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTR
 917:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTR
 918:Drivers/CMSIS/Include/core_cm3.h **** 
 919:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTR
 920:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTR
 921:Drivers/CMSIS/Include/core_cm3.h **** 
 922:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTR
 923:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTR
 924:Drivers/CMSIS/Include/core_cm3.h **** 
 925:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTR
 926:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTR
 927:Drivers/CMSIS/Include/core_cm3.h **** 
 928:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTR
 929:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTR
 930:Drivers/CMSIS/Include/core_cm3.h **** 
 931:Drivers/CMSIS/Include/core_cm3.h **** /* DWT CPI Count Register Definitions */
 932:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPI
 933:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPI
 934:Drivers/CMSIS/Include/core_cm3.h **** 
 935:Drivers/CMSIS/Include/core_cm3.h **** /* DWT Exception Overhead Count Register Definitions */
 936:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXC
 937:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXC
 938:Drivers/CMSIS/Include/core_cm3.h **** 
 939:Drivers/CMSIS/Include/core_cm3.h **** /* DWT Sleep Count Register Definitions */
 940:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLE
 941:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLE
 942:Drivers/CMSIS/Include/core_cm3.h **** 
 943:Drivers/CMSIS/Include/core_cm3.h **** /* DWT LSU Count Register Definitions */
 944:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSU
 945:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSU
 946:Drivers/CMSIS/Include/core_cm3.h **** 
 947:Drivers/CMSIS/Include/core_cm3.h **** /* DWT Folded-instruction Count Register Definitions */
 948:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOL
 949:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOL
 950:Drivers/CMSIS/Include/core_cm3.h **** 
 951:Drivers/CMSIS/Include/core_cm3.h **** /* DWT Comparator Mask Register Definitions */
 952:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MAS
 953:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MAS
 954:Drivers/CMSIS/Include/core_cm3.h **** 
 955:Drivers/CMSIS/Include/core_cm3.h **** /* DWT Comparator Function Register Definitions */
 956:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUN
ARM GAS  /tmp/ccMY5QHu.s 			page 21


 957:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUN
 958:Drivers/CMSIS/Include/core_cm3.h **** 
 959:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUN
 960:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUN
 961:Drivers/CMSIS/Include/core_cm3.h **** 
 962:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUN
 963:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUN
 964:Drivers/CMSIS/Include/core_cm3.h **** 
 965:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUN
 966:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUN
 967:Drivers/CMSIS/Include/core_cm3.h **** 
 968:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUN
 969:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUN
 970:Drivers/CMSIS/Include/core_cm3.h **** 
 971:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUN
 972:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUN
 973:Drivers/CMSIS/Include/core_cm3.h **** 
 974:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUN
 975:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUN
 976:Drivers/CMSIS/Include/core_cm3.h **** 
 977:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUN
 978:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUN
 979:Drivers/CMSIS/Include/core_cm3.h **** 
 980:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUN
 981:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUN
 982:Drivers/CMSIS/Include/core_cm3.h **** 
 983:Drivers/CMSIS/Include/core_cm3.h **** /*@}*/ /* end of group CMSIS_DWT */
 984:Drivers/CMSIS/Include/core_cm3.h **** 
 985:Drivers/CMSIS/Include/core_cm3.h **** 
 986:Drivers/CMSIS/Include/core_cm3.h **** /**
 987:Drivers/CMSIS/Include/core_cm3.h ****   \ingroup  CMSIS_core_register
 988:Drivers/CMSIS/Include/core_cm3.h ****   \defgroup CMSIS_TPI     Trace Port Interface (TPI)
 989:Drivers/CMSIS/Include/core_cm3.h ****   \brief    Type definitions for the Trace Port Interface (TPI)
 990:Drivers/CMSIS/Include/core_cm3.h ****   @{
 991:Drivers/CMSIS/Include/core_cm3.h ****  */
 992:Drivers/CMSIS/Include/core_cm3.h **** 
 993:Drivers/CMSIS/Include/core_cm3.h **** /**
 994:Drivers/CMSIS/Include/core_cm3.h ****   \brief  Structure type to access the Trace Port Interface Register (TPI).
 995:Drivers/CMSIS/Include/core_cm3.h ****  */
 996:Drivers/CMSIS/Include/core_cm3.h **** typedef struct
 997:Drivers/CMSIS/Include/core_cm3.h **** {
 998:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Reg
 999:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Regis
1000:Drivers/CMSIS/Include/core_cm3.h ****         uint32_t RESERVED0[2U];
1001:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Reg
1002:Drivers/CMSIS/Include/core_cm3.h ****         uint32_t RESERVED1[55U];
1003:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register *
1004:Drivers/CMSIS/Include/core_cm3.h ****         uint32_t RESERVED2[131U];
1005:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Regis
1006:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Regi
1007:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counte
1008:Drivers/CMSIS/Include/core_cm3.h ****         uint32_t RESERVED3[759U];
1009:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
1010:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
1011:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
1012:Drivers/CMSIS/Include/core_cm3.h ****         uint32_t RESERVED4[1U];
1013:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
ARM GAS  /tmp/ccMY5QHu.s 			page 22


1014:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
1015:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
1016:Drivers/CMSIS/Include/core_cm3.h ****         uint32_t RESERVED5[39U];
1017:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
1018:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
1019:Drivers/CMSIS/Include/core_cm3.h ****         uint32_t RESERVED7[8U];
1020:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
1021:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
1022:Drivers/CMSIS/Include/core_cm3.h **** } TPI_Type;
1023:Drivers/CMSIS/Include/core_cm3.h **** 
1024:Drivers/CMSIS/Include/core_cm3.h **** /* TPI Asynchronous Clock Prescaler Register Definitions */
1025:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACP
1026:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACP
1027:Drivers/CMSIS/Include/core_cm3.h **** 
1028:Drivers/CMSIS/Include/core_cm3.h **** /* TPI Selected Pin Protocol Register Definitions */
1029:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPP
1030:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPP
1031:Drivers/CMSIS/Include/core_cm3.h **** 
1032:Drivers/CMSIS/Include/core_cm3.h **** /* TPI Formatter and Flush Status Register Definitions */
1033:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFS
1034:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFS
1035:Drivers/CMSIS/Include/core_cm3.h **** 
1036:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFS
1037:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFS
1038:Drivers/CMSIS/Include/core_cm3.h **** 
1039:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFS
1040:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFS
1041:Drivers/CMSIS/Include/core_cm3.h **** 
1042:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFS
1043:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFS
1044:Drivers/CMSIS/Include/core_cm3.h **** 
1045:Drivers/CMSIS/Include/core_cm3.h **** /* TPI Formatter and Flush Control Register Definitions */
1046:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFC
1047:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFC
1048:Drivers/CMSIS/Include/core_cm3.h **** 
1049:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFC
1050:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFC
1051:Drivers/CMSIS/Include/core_cm3.h **** 
1052:Drivers/CMSIS/Include/core_cm3.h **** /* TPI TRIGGER Register Definitions */
1053:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRI
1054:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRI
1055:Drivers/CMSIS/Include/core_cm3.h **** 
1056:Drivers/CMSIS/Include/core_cm3.h **** /* TPI Integration ETM Data Register Definitions (FIFO0) */
1057:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIF
1058:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIF
1059:Drivers/CMSIS/Include/core_cm3.h **** 
1060:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIF
1061:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIF
1062:Drivers/CMSIS/Include/core_cm3.h **** 
1063:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIF
1064:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIF
1065:Drivers/CMSIS/Include/core_cm3.h **** 
1066:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIF
1067:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIF
1068:Drivers/CMSIS/Include/core_cm3.h **** 
1069:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIF
1070:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIF
ARM GAS  /tmp/ccMY5QHu.s 			page 23


1071:Drivers/CMSIS/Include/core_cm3.h **** 
1072:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIF
1073:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIF
1074:Drivers/CMSIS/Include/core_cm3.h **** 
1075:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIF
1076:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIF
1077:Drivers/CMSIS/Include/core_cm3.h **** 
1078:Drivers/CMSIS/Include/core_cm3.h **** /* TPI ITATBCTR2 Register Definitions */
1079:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITA
1080:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITA
1081:Drivers/CMSIS/Include/core_cm3.h **** 
1082:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITA
1083:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITA
1084:Drivers/CMSIS/Include/core_cm3.h **** 
1085:Drivers/CMSIS/Include/core_cm3.h **** /* TPI Integration ITM Data Register Definitions (FIFO1) */
1086:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIF
1087:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIF
1088:Drivers/CMSIS/Include/core_cm3.h **** 
1089:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIF
1090:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIF
1091:Drivers/CMSIS/Include/core_cm3.h **** 
1092:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIF
1093:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIF
1094:Drivers/CMSIS/Include/core_cm3.h **** 
1095:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIF
1096:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIF
1097:Drivers/CMSIS/Include/core_cm3.h **** 
1098:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIF
1099:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIF
1100:Drivers/CMSIS/Include/core_cm3.h **** 
1101:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIF
1102:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIF
1103:Drivers/CMSIS/Include/core_cm3.h **** 
1104:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIF
1105:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIF
1106:Drivers/CMSIS/Include/core_cm3.h **** 
1107:Drivers/CMSIS/Include/core_cm3.h **** /* TPI ITATBCTR0 Register Definitions */
1108:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITA
1109:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITA
1110:Drivers/CMSIS/Include/core_cm3.h **** 
1111:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITA
1112:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITA
1113:Drivers/CMSIS/Include/core_cm3.h **** 
1114:Drivers/CMSIS/Include/core_cm3.h **** /* TPI Integration Mode Control Register Definitions */
1115:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITC
1116:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITC
1117:Drivers/CMSIS/Include/core_cm3.h **** 
1118:Drivers/CMSIS/Include/core_cm3.h **** /* TPI DEVID Register Definitions */
1119:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEV
1120:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEV
1121:Drivers/CMSIS/Include/core_cm3.h **** 
1122:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEV
1123:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEV
1124:Drivers/CMSIS/Include/core_cm3.h **** 
1125:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEV
1126:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEV
1127:Drivers/CMSIS/Include/core_cm3.h **** 
ARM GAS  /tmp/ccMY5QHu.s 			page 24


1128:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEV
1129:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEV
1130:Drivers/CMSIS/Include/core_cm3.h **** 
1131:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEV
1132:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEV
1133:Drivers/CMSIS/Include/core_cm3.h **** 
1134:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEV
1135:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEV
1136:Drivers/CMSIS/Include/core_cm3.h **** 
1137:Drivers/CMSIS/Include/core_cm3.h **** /* TPI DEVTYPE Register Definitions */
1138:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEV
1139:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEV
1140:Drivers/CMSIS/Include/core_cm3.h **** 
1141:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEV
1142:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEV
1143:Drivers/CMSIS/Include/core_cm3.h **** 
1144:Drivers/CMSIS/Include/core_cm3.h **** /*@}*/ /* end of group CMSIS_TPI */
1145:Drivers/CMSIS/Include/core_cm3.h **** 
1146:Drivers/CMSIS/Include/core_cm3.h **** 
1147:Drivers/CMSIS/Include/core_cm3.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1148:Drivers/CMSIS/Include/core_cm3.h **** /**
1149:Drivers/CMSIS/Include/core_cm3.h ****   \ingroup  CMSIS_core_register
1150:Drivers/CMSIS/Include/core_cm3.h ****   \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
1151:Drivers/CMSIS/Include/core_cm3.h ****   \brief    Type definitions for the Memory Protection Unit (MPU)
1152:Drivers/CMSIS/Include/core_cm3.h ****   @{
1153:Drivers/CMSIS/Include/core_cm3.h ****  */
1154:Drivers/CMSIS/Include/core_cm3.h **** 
1155:Drivers/CMSIS/Include/core_cm3.h **** /**
1156:Drivers/CMSIS/Include/core_cm3.h ****   \brief  Structure type to access the Memory Protection Unit (MPU).
1157:Drivers/CMSIS/Include/core_cm3.h ****  */
1158:Drivers/CMSIS/Include/core_cm3.h **** typedef struct
1159:Drivers/CMSIS/Include/core_cm3.h **** {
1160:Drivers/CMSIS/Include/core_cm3.h ****   __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
1161:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
1162:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
1163:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register
1164:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Re
1165:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address 
1166:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and
1167:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address 
1168:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and
1169:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address 
1170:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and
1171:Drivers/CMSIS/Include/core_cm3.h **** } MPU_Type;
1172:Drivers/CMSIS/Include/core_cm3.h **** 
1173:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_TYPE_RALIASES                  4U
1174:Drivers/CMSIS/Include/core_cm3.h **** 
1175:Drivers/CMSIS/Include/core_cm3.h **** /* MPU Type Register Definitions */
1176:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU 
1177:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU 
1178:Drivers/CMSIS/Include/core_cm3.h **** 
1179:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU 
1180:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU 
1181:Drivers/CMSIS/Include/core_cm3.h **** 
1182:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU 
1183:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU 
1184:Drivers/CMSIS/Include/core_cm3.h **** 
ARM GAS  /tmp/ccMY5QHu.s 			page 25


1185:Drivers/CMSIS/Include/core_cm3.h **** /* MPU Control Register Definitions */
1186:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU 
1187:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU 
1188:Drivers/CMSIS/Include/core_cm3.h **** 
1189:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU 
1190:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU 
1191:Drivers/CMSIS/Include/core_cm3.h **** 
1192:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU 
1193:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU 
1194:Drivers/CMSIS/Include/core_cm3.h **** 
1195:Drivers/CMSIS/Include/core_cm3.h **** /* MPU Region Number Register Definitions */
1196:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU 
1197:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU 
1198:Drivers/CMSIS/Include/core_cm3.h **** 
1199:Drivers/CMSIS/Include/core_cm3.h **** /* MPU Region Base Address Register Definitions */
1200:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU 
1201:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU 
1202:Drivers/CMSIS/Include/core_cm3.h **** 
1203:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU 
1204:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU 
1205:Drivers/CMSIS/Include/core_cm3.h **** 
1206:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU 
1207:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU 
1208:Drivers/CMSIS/Include/core_cm3.h **** 
1209:Drivers/CMSIS/Include/core_cm3.h **** /* MPU Region Attribute and Size Register Definitions */
1210:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU 
1211:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU 
1212:Drivers/CMSIS/Include/core_cm3.h **** 
1213:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_XN_Pos                    28U                                            /*!< MPU 
1214:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU 
1215:Drivers/CMSIS/Include/core_cm3.h **** 
1216:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_AP_Pos                    24U                                            /*!< MPU 
1217:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU 
1218:Drivers/CMSIS/Include/core_cm3.h **** 
1219:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU 
1220:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU 
1221:Drivers/CMSIS/Include/core_cm3.h **** 
1222:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_S_Pos                     18U                                            /*!< MPU 
1223:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU 
1224:Drivers/CMSIS/Include/core_cm3.h **** 
1225:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_C_Pos                     17U                                            /*!< MPU 
1226:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU 
1227:Drivers/CMSIS/Include/core_cm3.h **** 
1228:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_B_Pos                     16U                                            /*!< MPU 
1229:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU 
1230:Drivers/CMSIS/Include/core_cm3.h **** 
1231:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU 
1232:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU 
1233:Drivers/CMSIS/Include/core_cm3.h **** 
1234:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU 
1235:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU 
1236:Drivers/CMSIS/Include/core_cm3.h **** 
1237:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU 
1238:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU 
1239:Drivers/CMSIS/Include/core_cm3.h **** 
1240:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of group CMSIS_MPU */
1241:Drivers/CMSIS/Include/core_cm3.h **** #endif
ARM GAS  /tmp/ccMY5QHu.s 			page 26


1242:Drivers/CMSIS/Include/core_cm3.h **** 
1243:Drivers/CMSIS/Include/core_cm3.h **** 
1244:Drivers/CMSIS/Include/core_cm3.h **** /**
1245:Drivers/CMSIS/Include/core_cm3.h ****   \ingroup  CMSIS_core_register
1246:Drivers/CMSIS/Include/core_cm3.h ****   \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
1247:Drivers/CMSIS/Include/core_cm3.h ****   \brief    Type definitions for the Core Debug Registers
1248:Drivers/CMSIS/Include/core_cm3.h ****   @{
1249:Drivers/CMSIS/Include/core_cm3.h ****  */
1250:Drivers/CMSIS/Include/core_cm3.h **** 
1251:Drivers/CMSIS/Include/core_cm3.h **** /**
1252:Drivers/CMSIS/Include/core_cm3.h ****   \brief  Structure type to access the Core Debug Register (CoreDebug).
1253:Drivers/CMSIS/Include/core_cm3.h ****  */
1254:Drivers/CMSIS/Include/core_cm3.h **** typedef struct
1255:Drivers/CMSIS/Include/core_cm3.h **** {
1256:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status
1257:Drivers/CMSIS/Include/core_cm3.h ****   __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Reg
1258:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Registe
1259:Drivers/CMSIS/Include/core_cm3.h ****   __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Cont
1260:Drivers/CMSIS/Include/core_cm3.h **** } CoreDebug_Type;
1261:Drivers/CMSIS/Include/core_cm3.h **** 
1262:Drivers/CMSIS/Include/core_cm3.h **** /* Debug Halting Control and Status Register Definitions */
1263:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< Core
1264:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< Core
1265:Drivers/CMSIS/Include/core_cm3.h **** 
1266:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< Core
1267:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< Core
1268:Drivers/CMSIS/Include/core_cm3.h **** 
1269:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< Core
1270:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< Core
1271:Drivers/CMSIS/Include/core_cm3.h **** 
1272:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< Core
1273:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< Core
1274:Drivers/CMSIS/Include/core_cm3.h **** 
1275:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< Core
1276:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< Core
1277:Drivers/CMSIS/Include/core_cm3.h **** 
1278:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< Core
1279:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< Core
1280:Drivers/CMSIS/Include/core_cm3.h **** 
1281:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< Core
1282:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< Core
1283:Drivers/CMSIS/Include/core_cm3.h **** 
1284:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< Core
1285:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< Core
1286:Drivers/CMSIS/Include/core_cm3.h **** 
1287:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< Core
1288:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< Core
1289:Drivers/CMSIS/Include/core_cm3.h **** 
1290:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< Core
1291:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< Core
1292:Drivers/CMSIS/Include/core_cm3.h **** 
1293:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< Core
1294:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< Core
1295:Drivers/CMSIS/Include/core_cm3.h **** 
1296:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< Core
1297:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< Core
1298:Drivers/CMSIS/Include/core_cm3.h **** 
ARM GAS  /tmp/ccMY5QHu.s 			page 27


1299:Drivers/CMSIS/Include/core_cm3.h **** /* Debug Core Register Selector Register Definitions */
1300:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< Core
1301:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< Core
1302:Drivers/CMSIS/Include/core_cm3.h **** 
1303:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< Core
1304:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< Core
1305:Drivers/CMSIS/Include/core_cm3.h **** 
1306:Drivers/CMSIS/Include/core_cm3.h **** /* Debug Exception and Monitor Control Register Definitions */
1307:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< Core
1308:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< Core
1309:Drivers/CMSIS/Include/core_cm3.h **** 
1310:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< Core
1311:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< Core
1312:Drivers/CMSIS/Include/core_cm3.h **** 
1313:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< Core
1314:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< Core
1315:Drivers/CMSIS/Include/core_cm3.h **** 
1316:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< Core
1317:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< Core
1318:Drivers/CMSIS/Include/core_cm3.h **** 
1319:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< Core
1320:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< Core
1321:Drivers/CMSIS/Include/core_cm3.h **** 
1322:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< Core
1323:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< Core
1324:Drivers/CMSIS/Include/core_cm3.h **** 
1325:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< Core
1326:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< Core
1327:Drivers/CMSIS/Include/core_cm3.h **** 
1328:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< Core
1329:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< Core
1330:Drivers/CMSIS/Include/core_cm3.h **** 
1331:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< Core
1332:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< Core
1333:Drivers/CMSIS/Include/core_cm3.h **** 
1334:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< Core
1335:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< Core
1336:Drivers/CMSIS/Include/core_cm3.h **** 
1337:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< Core
1338:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< Core
1339:Drivers/CMSIS/Include/core_cm3.h **** 
1340:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< Core
1341:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< Core
1342:Drivers/CMSIS/Include/core_cm3.h **** 
1343:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< Core
1344:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< Core
1345:Drivers/CMSIS/Include/core_cm3.h **** 
1346:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of group CMSIS_CoreDebug */
1347:Drivers/CMSIS/Include/core_cm3.h **** 
1348:Drivers/CMSIS/Include/core_cm3.h **** 
1349:Drivers/CMSIS/Include/core_cm3.h **** /**
1350:Drivers/CMSIS/Include/core_cm3.h ****   \ingroup    CMSIS_core_register
1351:Drivers/CMSIS/Include/core_cm3.h ****   \defgroup   CMSIS_core_bitfield     Core register bit field macros
1352:Drivers/CMSIS/Include/core_cm3.h ****   \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1353:Drivers/CMSIS/Include/core_cm3.h ****   @{
1354:Drivers/CMSIS/Include/core_cm3.h ****  */
1355:Drivers/CMSIS/Include/core_cm3.h **** 
ARM GAS  /tmp/ccMY5QHu.s 			page 28


1356:Drivers/CMSIS/Include/core_cm3.h **** /**
1357:Drivers/CMSIS/Include/core_cm3.h ****   \brief   Mask and shift a bit field value for use in a register bit range.
1358:Drivers/CMSIS/Include/core_cm3.h ****   \param[in] field  Name of the register bit field.
1359:Drivers/CMSIS/Include/core_cm3.h ****   \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
1360:Drivers/CMSIS/Include/core_cm3.h ****   \return           Masked and shifted value.
1361:Drivers/CMSIS/Include/core_cm3.h **** */
1362:Drivers/CMSIS/Include/core_cm3.h **** #define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1363:Drivers/CMSIS/Include/core_cm3.h **** 
1364:Drivers/CMSIS/Include/core_cm3.h **** /**
1365:Drivers/CMSIS/Include/core_cm3.h ****   \brief     Mask and shift a register value to extract a bit filed value.
1366:Drivers/CMSIS/Include/core_cm3.h ****   \param[in] field  Name of the register bit field.
1367:Drivers/CMSIS/Include/core_cm3.h ****   \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
1368:Drivers/CMSIS/Include/core_cm3.h ****   \return           Masked and shifted bit field value.
1369:Drivers/CMSIS/Include/core_cm3.h **** */
1370:Drivers/CMSIS/Include/core_cm3.h **** #define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1371:Drivers/CMSIS/Include/core_cm3.h **** 
1372:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of group CMSIS_core_bitfield */
1373:Drivers/CMSIS/Include/core_cm3.h **** 
1374:Drivers/CMSIS/Include/core_cm3.h **** 
1375:Drivers/CMSIS/Include/core_cm3.h **** /**
1376:Drivers/CMSIS/Include/core_cm3.h ****   \ingroup    CMSIS_core_register
1377:Drivers/CMSIS/Include/core_cm3.h ****   \defgroup   CMSIS_core_base     Core Definitions
1378:Drivers/CMSIS/Include/core_cm3.h ****   \brief      Definitions for base addresses, unions, and structures.
1379:Drivers/CMSIS/Include/core_cm3.h ****   @{
1380:Drivers/CMSIS/Include/core_cm3.h ****  */
1381:Drivers/CMSIS/Include/core_cm3.h **** 
1382:Drivers/CMSIS/Include/core_cm3.h **** /* Memory mapping of Core Hardware */
1383:Drivers/CMSIS/Include/core_cm3.h **** #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Bas
1384:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
1385:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
1386:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
1387:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address 
1388:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
1389:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
1390:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Bas
1391:Drivers/CMSIS/Include/core_cm3.h **** 
1392:Drivers/CMSIS/Include/core_cm3.h **** #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register 
1393:Drivers/CMSIS/Include/core_cm3.h **** #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct
1394:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration st
1395:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struc
1396:Drivers/CMSIS/Include/core_cm3.h **** #define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct
1397:Drivers/CMSIS/Include/core_cm3.h **** #define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct
1398:Drivers/CMSIS/Include/core_cm3.h **** #define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct
1399:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration
1400:Drivers/CMSIS/Include/core_cm3.h **** 
1401:Drivers/CMSIS/Include/core_cm3.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1402:Drivers/CMSIS/Include/core_cm3.h ****   #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit *
1403:Drivers/CMSIS/Include/core_cm3.h ****   #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit *
1404:Drivers/CMSIS/Include/core_cm3.h **** #endif
1405:Drivers/CMSIS/Include/core_cm3.h **** 
1406:Drivers/CMSIS/Include/core_cm3.h **** /*@} */
1407:Drivers/CMSIS/Include/core_cm3.h **** 
1408:Drivers/CMSIS/Include/core_cm3.h **** 
1409:Drivers/CMSIS/Include/core_cm3.h **** 
1410:Drivers/CMSIS/Include/core_cm3.h **** /*******************************************************************************
1411:Drivers/CMSIS/Include/core_cm3.h ****  *                Hardware Abstraction Layer
1412:Drivers/CMSIS/Include/core_cm3.h ****   Core Function Interface contains:
ARM GAS  /tmp/ccMY5QHu.s 			page 29


1413:Drivers/CMSIS/Include/core_cm3.h ****   - Core NVIC Functions
1414:Drivers/CMSIS/Include/core_cm3.h ****   - Core SysTick Functions
1415:Drivers/CMSIS/Include/core_cm3.h ****   - Core Debug Functions
1416:Drivers/CMSIS/Include/core_cm3.h ****   - Core Register Access Functions
1417:Drivers/CMSIS/Include/core_cm3.h ****  ******************************************************************************/
1418:Drivers/CMSIS/Include/core_cm3.h **** /**
1419:Drivers/CMSIS/Include/core_cm3.h ****   \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1420:Drivers/CMSIS/Include/core_cm3.h **** */
1421:Drivers/CMSIS/Include/core_cm3.h **** 
1422:Drivers/CMSIS/Include/core_cm3.h **** 
1423:Drivers/CMSIS/Include/core_cm3.h **** 
1424:Drivers/CMSIS/Include/core_cm3.h **** /* ##########################   NVIC functions  #################################### */
1425:Drivers/CMSIS/Include/core_cm3.h **** /**
1426:Drivers/CMSIS/Include/core_cm3.h ****   \ingroup  CMSIS_Core_FunctionInterface
1427:Drivers/CMSIS/Include/core_cm3.h ****   \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1428:Drivers/CMSIS/Include/core_cm3.h ****   \brief    Functions that manage interrupts and exceptions via the NVIC.
1429:Drivers/CMSIS/Include/core_cm3.h ****   @{
1430:Drivers/CMSIS/Include/core_cm3.h ****  */
1431:Drivers/CMSIS/Include/core_cm3.h **** 
1432:Drivers/CMSIS/Include/core_cm3.h **** #ifdef CMSIS_NVIC_VIRTUAL
1433:Drivers/CMSIS/Include/core_cm3.h ****   #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1434:Drivers/CMSIS/Include/core_cm3.h ****     #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1435:Drivers/CMSIS/Include/core_cm3.h ****   #endif
1436:Drivers/CMSIS/Include/core_cm3.h ****   #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1437:Drivers/CMSIS/Include/core_cm3.h **** #else
1438:Drivers/CMSIS/Include/core_cm3.h ****   #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
1439:Drivers/CMSIS/Include/core_cm3.h ****   #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
1440:Drivers/CMSIS/Include/core_cm3.h ****   #define NVIC_EnableIRQ              __NVIC_EnableIRQ
1441:Drivers/CMSIS/Include/core_cm3.h ****   #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
1442:Drivers/CMSIS/Include/core_cm3.h ****   #define NVIC_DisableIRQ             __NVIC_DisableIRQ
1443:Drivers/CMSIS/Include/core_cm3.h ****   #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
1444:Drivers/CMSIS/Include/core_cm3.h ****   #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
1445:Drivers/CMSIS/Include/core_cm3.h ****   #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
1446:Drivers/CMSIS/Include/core_cm3.h ****   #define NVIC_GetActive              __NVIC_GetActive
1447:Drivers/CMSIS/Include/core_cm3.h ****   #define NVIC_SetPriority            __NVIC_SetPriority
1448:Drivers/CMSIS/Include/core_cm3.h ****   #define NVIC_GetPriority            __NVIC_GetPriority
1449:Drivers/CMSIS/Include/core_cm3.h ****   #define NVIC_SystemReset            __NVIC_SystemReset
1450:Drivers/CMSIS/Include/core_cm3.h **** #endif /* CMSIS_NVIC_VIRTUAL */
1451:Drivers/CMSIS/Include/core_cm3.h **** 
1452:Drivers/CMSIS/Include/core_cm3.h **** #ifdef CMSIS_VECTAB_VIRTUAL
1453:Drivers/CMSIS/Include/core_cm3.h ****   #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1454:Drivers/CMSIS/Include/core_cm3.h ****    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1455:Drivers/CMSIS/Include/core_cm3.h ****   #endif
1456:Drivers/CMSIS/Include/core_cm3.h ****   #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1457:Drivers/CMSIS/Include/core_cm3.h **** #else
1458:Drivers/CMSIS/Include/core_cm3.h ****   #define NVIC_SetVector              __NVIC_SetVector
1459:Drivers/CMSIS/Include/core_cm3.h ****   #define NVIC_GetVector              __NVIC_GetVector
1460:Drivers/CMSIS/Include/core_cm3.h **** #endif  /* (CMSIS_VECTAB_VIRTUAL) */
1461:Drivers/CMSIS/Include/core_cm3.h **** 
1462:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_USER_IRQ_OFFSET          16
1463:Drivers/CMSIS/Include/core_cm3.h **** 
1464:Drivers/CMSIS/Include/core_cm3.h **** 
1465:Drivers/CMSIS/Include/core_cm3.h **** /* The following EXC_RETURN values are saved the LR on exception entry */
1466:Drivers/CMSIS/Include/core_cm3.h **** #define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after ret
1467:Drivers/CMSIS/Include/core_cm3.h **** #define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after retu
1468:Drivers/CMSIS/Include/core_cm3.h **** #define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after retu
1469:Drivers/CMSIS/Include/core_cm3.h **** 
ARM GAS  /tmp/ccMY5QHu.s 			page 30


1470:Drivers/CMSIS/Include/core_cm3.h **** 
1471:Drivers/CMSIS/Include/core_cm3.h **** /**
1472:Drivers/CMSIS/Include/core_cm3.h ****   \brief   Set Priority Grouping
1473:Drivers/CMSIS/Include/core_cm3.h ****   \details Sets the priority grouping field using the required unlock sequence.
1474:Drivers/CMSIS/Include/core_cm3.h ****            The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1475:Drivers/CMSIS/Include/core_cm3.h ****            Only values from 0..7 are used.
1476:Drivers/CMSIS/Include/core_cm3.h ****            In case of a conflict between priority grouping and available
1477:Drivers/CMSIS/Include/core_cm3.h ****            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1478:Drivers/CMSIS/Include/core_cm3.h ****   \param [in]      PriorityGroup  Priority grouping field.
1479:Drivers/CMSIS/Include/core_cm3.h ****  */
1480:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
  38              		.loc 2 1480 22 view .LVU3
  39              	.LBB33:
1481:Drivers/CMSIS/Include/core_cm3.h **** {
1482:Drivers/CMSIS/Include/core_cm3.h ****   uint32_t reg_value;
  40              		.loc 2 1482 3 view .LVU4
1483:Drivers/CMSIS/Include/core_cm3.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 a
  41              		.loc 2 1483 3 view .LVU5
1484:Drivers/CMSIS/Include/core_cm3.h **** 
1485:Drivers/CMSIS/Include/core_cm3.h ****   reg_value  =  SCB->AIRCR;                                                   /* read old register 
  42              		.loc 2 1485 3 view .LVU6
  43              		.loc 2 1485 14 is_stmt 0 view .LVU7
  44 0000 074A     		ldr	r2, .L2
  45 0002 D368     		ldr	r3, [r2, #12]
  46              	.LVL1:
1486:Drivers/CMSIS/Include/core_cm3.h ****   reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan
  47              		.loc 2 1486 3 is_stmt 1 view .LVU8
  48              		.loc 2 1486 13 is_stmt 0 view .LVU9
  49 0004 23F4E063 		bic	r3, r3, #1792
  50              	.LVL2:
  51              		.loc 2 1486 13 view .LVU10
  52 0008 1B04     		lsls	r3, r3, #16
  53 000a 1B0C     		lsrs	r3, r3, #16
  54              	.LVL3:
1487:Drivers/CMSIS/Include/core_cm3.h ****   reg_value  =  (reg_value                                   |
  55              		.loc 2 1487 3 is_stmt 1 view .LVU11
1488:Drivers/CMSIS/Include/core_cm3.h ****                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1489:Drivers/CMSIS/Include/core_cm3.h ****                 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key a
  56              		.loc 2 1489 35 is_stmt 0 view .LVU12
  57 000c 0002     		lsls	r0, r0, #8
  58              	.LVL4:
  59              		.loc 2 1489 35 view .LVU13
  60 000e 00F4E060 		and	r0, r0, #1792
1488:Drivers/CMSIS/Include/core_cm3.h ****                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
  61              		.loc 2 1488 62 view .LVU14
  62 0012 0343     		orrs	r3, r3, r0
  63              	.LVL5:
1487:Drivers/CMSIS/Include/core_cm3.h ****   reg_value  =  (reg_value                                   |
  64              		.loc 2 1487 14 view .LVU15
  65 0014 43F0BF63 		orr	r3, r3, #100139008
  66 0018 43F40033 		orr	r3, r3, #131072
  67              	.LVL6:
1490:Drivers/CMSIS/Include/core_cm3.h ****   SCB->AIRCR =  reg_value;
  68              		.loc 2 1490 3 is_stmt 1 view .LVU16
  69              		.loc 2 1490 14 is_stmt 0 view .LVU17
  70 001c D360     		str	r3, [r2, #12]
  71              	.LVL7:
ARM GAS  /tmp/ccMY5QHu.s 			page 31


  72              		.loc 2 1490 14 view .LVU18
  73              	.LBE33:
  74              	.LBE32:
 149:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** }
  75              		.loc 1 149 1 view .LVU19
  76 001e 7047     		bx	lr
  77              	.L3:
  78              		.align	2
  79              	.L2:
  80 0020 00ED00E0 		.word	-536810240
  81              		.cfi_endproc
  82              	.LFE65:
  84              		.section	.text.HAL_NVIC_SetPriority,"ax",%progbits
  85              		.align	1
  86              		.global	HAL_NVIC_SetPriority
  87              		.syntax unified
  88              		.thumb
  89              		.thumb_func
  91              	HAL_NVIC_SetPriority:
  92              	.LVL8:
  93              	.LFB66:
 150:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 151:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /**
 152:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @brief  Sets the priority of an interrupt.
 153:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @param  IRQn: External interrupt number.
 154:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
 155:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
 156:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @param  PreemptPriority: The preemption priority for the IRQn channel.
 157:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         This parameter can be a value between 0 and 15
 158:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         A lower priority value indicates a higher priority 
 159:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @param  SubPriority: the subpriority level for the IRQ channel.
 160:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         This parameter can be a value between 0 and 15
 161:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         A lower priority value indicates a higher priority.          
 162:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @retval None
 163:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   */
 164:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
 165:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** { 
  94              		.loc 1 165 1 is_stmt 1 view -0
  95              		.cfi_startproc
  96              		@ args = 0, pretend = 0, frame = 0
  97              		@ frame_needed = 0, uses_anonymous_args = 0
  98              		.loc 1 165 1 is_stmt 0 view .LVU21
  99 0000 00B5     		push	{lr}
 100              	.LCFI0:
 101              		.cfi_def_cfa_offset 4
 102              		.cfi_offset 14, -4
 166:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   uint32_t prioritygroup = 0x00U;
 103              		.loc 1 166 3 is_stmt 1 view .LVU22
 104              	.LVL9:
 167:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   
 168:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   /* Check the parameters */
 169:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
 105              		.loc 1 169 3 view .LVU23
 170:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
 106              		.loc 1 170 3 view .LVU24
 171:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   
 172:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   prioritygroup = NVIC_GetPriorityGrouping();
ARM GAS  /tmp/ccMY5QHu.s 			page 32


 107              		.loc 1 172 3 view .LVU25
 108              	.LBB40:
 109              	.LBI40:
1491:Drivers/CMSIS/Include/core_cm3.h **** }
1492:Drivers/CMSIS/Include/core_cm3.h **** 
1493:Drivers/CMSIS/Include/core_cm3.h **** 
1494:Drivers/CMSIS/Include/core_cm3.h **** /**
1495:Drivers/CMSIS/Include/core_cm3.h ****   \brief   Get Priority Grouping
1496:Drivers/CMSIS/Include/core_cm3.h ****   \details Reads the priority grouping field from the NVIC Interrupt Controller.
1497:Drivers/CMSIS/Include/core_cm3.h ****   \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1498:Drivers/CMSIS/Include/core_cm3.h ****  */
1499:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
 110              		.loc 2 1499 26 view .LVU26
 111              	.LBB41:
1500:Drivers/CMSIS/Include/core_cm3.h **** {
1501:Drivers/CMSIS/Include/core_cm3.h ****   return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 112              		.loc 2 1501 3 view .LVU27
 113              		.loc 2 1501 26 is_stmt 0 view .LVU28
 114 0002 194B     		ldr	r3, .L10
 115 0004 DB68     		ldr	r3, [r3, #12]
 116              		.loc 2 1501 11 view .LVU29
 117 0006 C3F30223 		ubfx	r3, r3, #8, #3
 118              	.LVL10:
 119              		.loc 2 1501 11 view .LVU30
 120              	.LBE41:
 121              	.LBE40:
 173:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   
 174:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
 122              		.loc 1 174 3 is_stmt 1 view .LVU31
 123              	.LBB42:
 124              	.LBI42:
1502:Drivers/CMSIS/Include/core_cm3.h **** }
1503:Drivers/CMSIS/Include/core_cm3.h **** 
1504:Drivers/CMSIS/Include/core_cm3.h **** 
1505:Drivers/CMSIS/Include/core_cm3.h **** /**
1506:Drivers/CMSIS/Include/core_cm3.h ****   \brief   Enable Interrupt
1507:Drivers/CMSIS/Include/core_cm3.h ****   \details Enables a device specific interrupt in the NVIC interrupt controller.
1508:Drivers/CMSIS/Include/core_cm3.h ****   \param [in]      IRQn  Device specific interrupt number.
1509:Drivers/CMSIS/Include/core_cm3.h ****   \note    IRQn must not be negative.
1510:Drivers/CMSIS/Include/core_cm3.h ****  */
1511:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1512:Drivers/CMSIS/Include/core_cm3.h **** {
1513:Drivers/CMSIS/Include/core_cm3.h ****   if ((int32_t)(IRQn) >= 0)
1514:Drivers/CMSIS/Include/core_cm3.h ****   {
1515:Drivers/CMSIS/Include/core_cm3.h ****     NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1516:Drivers/CMSIS/Include/core_cm3.h ****   }
1517:Drivers/CMSIS/Include/core_cm3.h **** }
1518:Drivers/CMSIS/Include/core_cm3.h **** 
1519:Drivers/CMSIS/Include/core_cm3.h **** 
1520:Drivers/CMSIS/Include/core_cm3.h **** /**
1521:Drivers/CMSIS/Include/core_cm3.h ****   \brief   Get Interrupt Enable status
1522:Drivers/CMSIS/Include/core_cm3.h ****   \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
1523:Drivers/CMSIS/Include/core_cm3.h ****   \param [in]      IRQn  Device specific interrupt number.
1524:Drivers/CMSIS/Include/core_cm3.h ****   \return             0  Interrupt is not enabled.
1525:Drivers/CMSIS/Include/core_cm3.h ****   \return             1  Interrupt is enabled.
1526:Drivers/CMSIS/Include/core_cm3.h ****   \note    IRQn must not be negative.
1527:Drivers/CMSIS/Include/core_cm3.h ****  */
ARM GAS  /tmp/ccMY5QHu.s 			page 33


1528:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1529:Drivers/CMSIS/Include/core_cm3.h **** {
1530:Drivers/CMSIS/Include/core_cm3.h ****   if ((int32_t)(IRQn) >= 0)
1531:Drivers/CMSIS/Include/core_cm3.h ****   {
1532:Drivers/CMSIS/Include/core_cm3.h ****     return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL)
1533:Drivers/CMSIS/Include/core_cm3.h ****   }
1534:Drivers/CMSIS/Include/core_cm3.h ****   else
1535:Drivers/CMSIS/Include/core_cm3.h ****   {
1536:Drivers/CMSIS/Include/core_cm3.h ****     return(0U);
1537:Drivers/CMSIS/Include/core_cm3.h ****   }
1538:Drivers/CMSIS/Include/core_cm3.h **** }
1539:Drivers/CMSIS/Include/core_cm3.h **** 
1540:Drivers/CMSIS/Include/core_cm3.h **** 
1541:Drivers/CMSIS/Include/core_cm3.h **** /**
1542:Drivers/CMSIS/Include/core_cm3.h ****   \brief   Disable Interrupt
1543:Drivers/CMSIS/Include/core_cm3.h ****   \details Disables a device specific interrupt in the NVIC interrupt controller.
1544:Drivers/CMSIS/Include/core_cm3.h ****   \param [in]      IRQn  Device specific interrupt number.
1545:Drivers/CMSIS/Include/core_cm3.h ****   \note    IRQn must not be negative.
1546:Drivers/CMSIS/Include/core_cm3.h ****  */
1547:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1548:Drivers/CMSIS/Include/core_cm3.h **** {
1549:Drivers/CMSIS/Include/core_cm3.h ****   if ((int32_t)(IRQn) >= 0)
1550:Drivers/CMSIS/Include/core_cm3.h ****   {
1551:Drivers/CMSIS/Include/core_cm3.h ****     NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1552:Drivers/CMSIS/Include/core_cm3.h ****     __DSB();
1553:Drivers/CMSIS/Include/core_cm3.h ****     __ISB();
1554:Drivers/CMSIS/Include/core_cm3.h ****   }
1555:Drivers/CMSIS/Include/core_cm3.h **** }
1556:Drivers/CMSIS/Include/core_cm3.h **** 
1557:Drivers/CMSIS/Include/core_cm3.h **** 
1558:Drivers/CMSIS/Include/core_cm3.h **** /**
1559:Drivers/CMSIS/Include/core_cm3.h ****   \brief   Get Pending Interrupt
1560:Drivers/CMSIS/Include/core_cm3.h ****   \details Reads the NVIC pending register and returns the pending bit for the specified device spe
1561:Drivers/CMSIS/Include/core_cm3.h ****   \param [in]      IRQn  Device specific interrupt number.
1562:Drivers/CMSIS/Include/core_cm3.h ****   \return             0  Interrupt status is not pending.
1563:Drivers/CMSIS/Include/core_cm3.h ****   \return             1  Interrupt status is pending.
1564:Drivers/CMSIS/Include/core_cm3.h ****   \note    IRQn must not be negative.
1565:Drivers/CMSIS/Include/core_cm3.h ****  */
1566:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1567:Drivers/CMSIS/Include/core_cm3.h **** {
1568:Drivers/CMSIS/Include/core_cm3.h ****   if ((int32_t)(IRQn) >= 0)
1569:Drivers/CMSIS/Include/core_cm3.h ****   {
1570:Drivers/CMSIS/Include/core_cm3.h ****     return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL)
1571:Drivers/CMSIS/Include/core_cm3.h ****   }
1572:Drivers/CMSIS/Include/core_cm3.h ****   else
1573:Drivers/CMSIS/Include/core_cm3.h ****   {
1574:Drivers/CMSIS/Include/core_cm3.h ****     return(0U);
1575:Drivers/CMSIS/Include/core_cm3.h ****   }
1576:Drivers/CMSIS/Include/core_cm3.h **** }
1577:Drivers/CMSIS/Include/core_cm3.h **** 
1578:Drivers/CMSIS/Include/core_cm3.h **** 
1579:Drivers/CMSIS/Include/core_cm3.h **** /**
1580:Drivers/CMSIS/Include/core_cm3.h ****   \brief   Set Pending Interrupt
1581:Drivers/CMSIS/Include/core_cm3.h ****   \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
1582:Drivers/CMSIS/Include/core_cm3.h ****   \param [in]      IRQn  Device specific interrupt number.
1583:Drivers/CMSIS/Include/core_cm3.h ****   \note    IRQn must not be negative.
1584:Drivers/CMSIS/Include/core_cm3.h ****  */
ARM GAS  /tmp/ccMY5QHu.s 			page 34


1585:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1586:Drivers/CMSIS/Include/core_cm3.h **** {
1587:Drivers/CMSIS/Include/core_cm3.h ****   if ((int32_t)(IRQn) >= 0)
1588:Drivers/CMSIS/Include/core_cm3.h ****   {
1589:Drivers/CMSIS/Include/core_cm3.h ****     NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1590:Drivers/CMSIS/Include/core_cm3.h ****   }
1591:Drivers/CMSIS/Include/core_cm3.h **** }
1592:Drivers/CMSIS/Include/core_cm3.h **** 
1593:Drivers/CMSIS/Include/core_cm3.h **** 
1594:Drivers/CMSIS/Include/core_cm3.h **** /**
1595:Drivers/CMSIS/Include/core_cm3.h ****   \brief   Clear Pending Interrupt
1596:Drivers/CMSIS/Include/core_cm3.h ****   \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
1597:Drivers/CMSIS/Include/core_cm3.h ****   \param [in]      IRQn  Device specific interrupt number.
1598:Drivers/CMSIS/Include/core_cm3.h ****   \note    IRQn must not be negative.
1599:Drivers/CMSIS/Include/core_cm3.h ****  */
1600:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1601:Drivers/CMSIS/Include/core_cm3.h **** {
1602:Drivers/CMSIS/Include/core_cm3.h ****   if ((int32_t)(IRQn) >= 0)
1603:Drivers/CMSIS/Include/core_cm3.h ****   {
1604:Drivers/CMSIS/Include/core_cm3.h ****     NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1605:Drivers/CMSIS/Include/core_cm3.h ****   }
1606:Drivers/CMSIS/Include/core_cm3.h **** }
1607:Drivers/CMSIS/Include/core_cm3.h **** 
1608:Drivers/CMSIS/Include/core_cm3.h **** 
1609:Drivers/CMSIS/Include/core_cm3.h **** /**
1610:Drivers/CMSIS/Include/core_cm3.h ****   \brief   Get Active Interrupt
1611:Drivers/CMSIS/Include/core_cm3.h ****   \details Reads the active register in the NVIC and returns the active bit for the device specific
1612:Drivers/CMSIS/Include/core_cm3.h ****   \param [in]      IRQn  Device specific interrupt number.
1613:Drivers/CMSIS/Include/core_cm3.h ****   \return             0  Interrupt status is not active.
1614:Drivers/CMSIS/Include/core_cm3.h ****   \return             1  Interrupt status is active.
1615:Drivers/CMSIS/Include/core_cm3.h ****   \note    IRQn must not be negative.
1616:Drivers/CMSIS/Include/core_cm3.h ****  */
1617:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
1618:Drivers/CMSIS/Include/core_cm3.h **** {
1619:Drivers/CMSIS/Include/core_cm3.h ****   if ((int32_t)(IRQn) >= 0)
1620:Drivers/CMSIS/Include/core_cm3.h ****   {
1621:Drivers/CMSIS/Include/core_cm3.h ****     return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL)
1622:Drivers/CMSIS/Include/core_cm3.h ****   }
1623:Drivers/CMSIS/Include/core_cm3.h ****   else
1624:Drivers/CMSIS/Include/core_cm3.h ****   {
1625:Drivers/CMSIS/Include/core_cm3.h ****     return(0U);
1626:Drivers/CMSIS/Include/core_cm3.h ****   }
1627:Drivers/CMSIS/Include/core_cm3.h **** }
1628:Drivers/CMSIS/Include/core_cm3.h **** 
1629:Drivers/CMSIS/Include/core_cm3.h **** 
1630:Drivers/CMSIS/Include/core_cm3.h **** /**
1631:Drivers/CMSIS/Include/core_cm3.h ****   \brief   Set Interrupt Priority
1632:Drivers/CMSIS/Include/core_cm3.h ****   \details Sets the priority of a device specific interrupt or a processor exception.
1633:Drivers/CMSIS/Include/core_cm3.h ****            The interrupt number can be positive to specify a device specific interrupt,
1634:Drivers/CMSIS/Include/core_cm3.h ****            or negative to specify a processor exception.
1635:Drivers/CMSIS/Include/core_cm3.h ****   \param [in]      IRQn  Interrupt number.
1636:Drivers/CMSIS/Include/core_cm3.h ****   \param [in]  priority  Priority to set.
1637:Drivers/CMSIS/Include/core_cm3.h ****   \note    The priority cannot be set for every processor exception.
1638:Drivers/CMSIS/Include/core_cm3.h ****  */
1639:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1640:Drivers/CMSIS/Include/core_cm3.h **** {
1641:Drivers/CMSIS/Include/core_cm3.h ****   if ((int32_t)(IRQn) >= 0)
ARM GAS  /tmp/ccMY5QHu.s 			page 35


1642:Drivers/CMSIS/Include/core_cm3.h ****   {
1643:Drivers/CMSIS/Include/core_cm3.h ****     NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (u
1644:Drivers/CMSIS/Include/core_cm3.h ****   }
1645:Drivers/CMSIS/Include/core_cm3.h ****   else
1646:Drivers/CMSIS/Include/core_cm3.h ****   {
1647:Drivers/CMSIS/Include/core_cm3.h ****     SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (u
1648:Drivers/CMSIS/Include/core_cm3.h ****   }
1649:Drivers/CMSIS/Include/core_cm3.h **** }
1650:Drivers/CMSIS/Include/core_cm3.h **** 
1651:Drivers/CMSIS/Include/core_cm3.h **** 
1652:Drivers/CMSIS/Include/core_cm3.h **** /**
1653:Drivers/CMSIS/Include/core_cm3.h ****   \brief   Get Interrupt Priority
1654:Drivers/CMSIS/Include/core_cm3.h ****   \details Reads the priority of a device specific interrupt or a processor exception.
1655:Drivers/CMSIS/Include/core_cm3.h ****            The interrupt number can be positive to specify a device specific interrupt,
1656:Drivers/CMSIS/Include/core_cm3.h ****            or negative to specify a processor exception.
1657:Drivers/CMSIS/Include/core_cm3.h ****   \param [in]   IRQn  Interrupt number.
1658:Drivers/CMSIS/Include/core_cm3.h ****   \return             Interrupt Priority.
1659:Drivers/CMSIS/Include/core_cm3.h ****                       Value is aligned automatically to the implemented priority bits of the microc
1660:Drivers/CMSIS/Include/core_cm3.h ****  */
1661:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
1662:Drivers/CMSIS/Include/core_cm3.h **** {
1663:Drivers/CMSIS/Include/core_cm3.h **** 
1664:Drivers/CMSIS/Include/core_cm3.h ****   if ((int32_t)(IRQn) >= 0)
1665:Drivers/CMSIS/Include/core_cm3.h ****   {
1666:Drivers/CMSIS/Include/core_cm3.h ****     return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
1667:Drivers/CMSIS/Include/core_cm3.h ****   }
1668:Drivers/CMSIS/Include/core_cm3.h ****   else
1669:Drivers/CMSIS/Include/core_cm3.h ****   {
1670:Drivers/CMSIS/Include/core_cm3.h ****     return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
1671:Drivers/CMSIS/Include/core_cm3.h ****   }
1672:Drivers/CMSIS/Include/core_cm3.h **** }
1673:Drivers/CMSIS/Include/core_cm3.h **** 
1674:Drivers/CMSIS/Include/core_cm3.h **** 
1675:Drivers/CMSIS/Include/core_cm3.h **** /**
1676:Drivers/CMSIS/Include/core_cm3.h ****   \brief   Encode Priority
1677:Drivers/CMSIS/Include/core_cm3.h ****   \details Encodes the priority for an interrupt with the given priority group,
1678:Drivers/CMSIS/Include/core_cm3.h ****            preemptive priority value, and subpriority value.
1679:Drivers/CMSIS/Include/core_cm3.h ****            In case of a conflict between priority grouping and available
1680:Drivers/CMSIS/Include/core_cm3.h ****            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1681:Drivers/CMSIS/Include/core_cm3.h ****   \param [in]     PriorityGroup  Used priority group.
1682:Drivers/CMSIS/Include/core_cm3.h ****   \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
1683:Drivers/CMSIS/Include/core_cm3.h ****   \param [in]       SubPriority  Subpriority value (starting from 0).
1684:Drivers/CMSIS/Include/core_cm3.h ****   \return                        Encoded priority. Value can be used in the function \ref NVIC_SetP
1685:Drivers/CMSIS/Include/core_cm3.h ****  */
1686:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin
 125              		.loc 2 1686 26 view .LVU32
 126              	.LBB43:
1687:Drivers/CMSIS/Include/core_cm3.h **** {
1688:Drivers/CMSIS/Include/core_cm3.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used   
 127              		.loc 2 1688 3 view .LVU33
1689:Drivers/CMSIS/Include/core_cm3.h ****   uint32_t PreemptPriorityBits;
 128              		.loc 2 1689 3 view .LVU34
1690:Drivers/CMSIS/Include/core_cm3.h ****   uint32_t SubPriorityBits;
 129              		.loc 2 1690 3 view .LVU35
1691:Drivers/CMSIS/Include/core_cm3.h **** 
1692:Drivers/CMSIS/Include/core_cm3.h ****   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV
 130              		.loc 2 1692 3 view .LVU36
ARM GAS  /tmp/ccMY5QHu.s 			page 36


 131              		.loc 2 1692 31 is_stmt 0 view .LVU37
 132 000a C3F1070C 		rsb	ip, r3, #7
 133              		.loc 2 1692 23 view .LVU38
 134 000e BCF1040F 		cmp	ip, #4
 135 0012 28BF     		it	cs
 136 0014 4FF0040C 		movcs	ip, #4
 137              	.LVL11:
1693:Drivers/CMSIS/Include/core_cm3.h ****   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
 138              		.loc 2 1693 3 is_stmt 1 view .LVU39
 139              		.loc 2 1693 44 is_stmt 0 view .LVU40
 140 0018 03F1040E 		add	lr, r3, #4
 141              		.loc 2 1693 109 view .LVU41
 142 001c BEF1060F 		cmp	lr, #6
 143 0020 18D9     		bls	.L8
 144 0022 033B     		subs	r3, r3, #3
 145              	.LVL12:
 146              	.L5:
1694:Drivers/CMSIS/Include/core_cm3.h **** 
1695:Drivers/CMSIS/Include/core_cm3.h ****   return (
 147              		.loc 2 1695 3 is_stmt 1 view .LVU42
1696:Drivers/CMSIS/Include/core_cm3.h ****            ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits
 148              		.loc 2 1696 30 is_stmt 0 view .LVU43
 149 0024 4FF0FF3E 		mov	lr, #-1
 150              	.LVL13:
 151              		.loc 2 1696 30 view .LVU44
 152 0028 0EFA0CFC 		lsl	ip, lr, ip
 153              	.LVL14:
 154              		.loc 2 1696 30 view .LVU45
 155 002c 21EA0C01 		bic	r1, r1, ip
 156              	.LVL15:
 157              		.loc 2 1696 82 view .LVU46
 158 0030 9940     		lsls	r1, r1, r3
1697:Drivers/CMSIS/Include/core_cm3.h ****            ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 159              		.loc 2 1697 30 view .LVU47
 160 0032 0EFA03F3 		lsl	r3, lr, r3
 161              	.LVL16:
 162              		.loc 2 1697 30 view .LVU48
 163 0036 22EA0303 		bic	r3, r2, r3
1696:Drivers/CMSIS/Include/core_cm3.h ****            ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits
 164              		.loc 2 1696 102 view .LVU49
 165 003a 1943     		orrs	r1, r1, r3
 166              	.LVL17:
1696:Drivers/CMSIS/Include/core_cm3.h ****            ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits
 167              		.loc 2 1696 102 view .LVU50
 168              	.LBE43:
 169              	.LBE42:
 170              	.LBB45:
 171              	.LBI45:
1639:Drivers/CMSIS/Include/core_cm3.h **** {
 172              		.loc 2 1639 22 is_stmt 1 view .LVU51
 173              	.LBB46:
1641:Drivers/CMSIS/Include/core_cm3.h ****   {
 174              		.loc 2 1641 3 view .LVU52
1641:Drivers/CMSIS/Include/core_cm3.h ****   {
 175              		.loc 2 1641 6 is_stmt 0 view .LVU53
 176 003c 0028     		cmp	r0, #0
 177 003e 0BDB     		blt	.L6
ARM GAS  /tmp/ccMY5QHu.s 			page 37


1643:Drivers/CMSIS/Include/core_cm3.h ****   }
 178              		.loc 2 1643 5 is_stmt 1 view .LVU54
1643:Drivers/CMSIS/Include/core_cm3.h ****   }
 179              		.loc 2 1643 48 is_stmt 0 view .LVU55
 180 0040 0901     		lsls	r1, r1, #4
 181              	.LVL18:
1643:Drivers/CMSIS/Include/core_cm3.h ****   }
 182              		.loc 2 1643 48 view .LVU56
 183 0042 C9B2     		uxtb	r1, r1
1643:Drivers/CMSIS/Include/core_cm3.h ****   }
 184              		.loc 2 1643 46 view .LVU57
 185 0044 00F16040 		add	r0, r0, #-536870912
 186              	.LVL19:
1643:Drivers/CMSIS/Include/core_cm3.h ****   }
 187              		.loc 2 1643 46 view .LVU58
 188 0048 00F56140 		add	r0, r0, #57600
 189 004c 80F80013 		strb	r1, [r0, #768]
 190              	.LVL20:
 191              	.L4:
1643:Drivers/CMSIS/Include/core_cm3.h ****   }
 192              		.loc 2 1643 46 view .LVU59
 193              	.LBE46:
 194              	.LBE45:
 175:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** }
 195              		.loc 1 175 1 view .LVU60
 196 0050 5DF804FB 		ldr	pc, [sp], #4
 197              	.LVL21:
 198              	.L8:
 199              	.LBB48:
 200              	.LBB44:
1693:Drivers/CMSIS/Include/core_cm3.h **** 
 201              		.loc 2 1693 109 view .LVU61
 202 0054 0023     		movs	r3, #0
 203              	.LVL22:
1693:Drivers/CMSIS/Include/core_cm3.h **** 
 204              		.loc 2 1693 109 view .LVU62
 205 0056 E5E7     		b	.L5
 206              	.LVL23:
 207              	.L6:
1693:Drivers/CMSIS/Include/core_cm3.h **** 
 208              		.loc 2 1693 109 view .LVU63
 209              	.LBE44:
 210              	.LBE48:
 211              	.LBB49:
 212              	.LBB47:
1647:Drivers/CMSIS/Include/core_cm3.h ****   }
 213              		.loc 2 1647 5 is_stmt 1 view .LVU64
1647:Drivers/CMSIS/Include/core_cm3.h ****   }
 214              		.loc 2 1647 32 is_stmt 0 view .LVU65
 215 0058 00F00F00 		and	r0, r0, #15
 216              	.LVL24:
1647:Drivers/CMSIS/Include/core_cm3.h ****   }
 217              		.loc 2 1647 48 view .LVU66
 218 005c 0901     		lsls	r1, r1, #4
 219              	.LVL25:
1647:Drivers/CMSIS/Include/core_cm3.h ****   }
 220              		.loc 2 1647 48 view .LVU67
ARM GAS  /tmp/ccMY5QHu.s 			page 38


 221 005e C9B2     		uxtb	r1, r1
1647:Drivers/CMSIS/Include/core_cm3.h ****   }
 222              		.loc 2 1647 46 view .LVU68
 223 0060 024B     		ldr	r3, .L10+4
 224 0062 1954     		strb	r1, [r3, r0]
 225              	.LVL26:
1647:Drivers/CMSIS/Include/core_cm3.h ****   }
 226              		.loc 2 1647 46 view .LVU69
 227              	.LBE47:
 228              	.LBE49:
 229              		.loc 1 175 1 view .LVU70
 230 0064 F4E7     		b	.L4
 231              	.L11:
 232 0066 00BF     		.align	2
 233              	.L10:
 234 0068 00ED00E0 		.word	-536810240
 235 006c 14ED00E0 		.word	-536810220
 236              		.cfi_endproc
 237              	.LFE66:
 239              		.section	.text.HAL_NVIC_EnableIRQ,"ax",%progbits
 240              		.align	1
 241              		.global	HAL_NVIC_EnableIRQ
 242              		.syntax unified
 243              		.thumb
 244              		.thumb_func
 246              	HAL_NVIC_EnableIRQ:
 247              	.LVL27:
 248              	.LFB67:
 176:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 177:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /**
 178:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
 179:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
 180:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         function should be called before. 
 181:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @param  IRQn External interrupt number.
 182:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
 183:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
 184:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @retval None
 185:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   */
 186:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
 187:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** {
 249              		.loc 1 187 1 is_stmt 1 view -0
 250              		.cfi_startproc
 251              		@ args = 0, pretend = 0, frame = 0
 252              		@ frame_needed = 0, uses_anonymous_args = 0
 253              		@ link register save eliminated.
 188:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   /* Check the parameters */
 189:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
 254              		.loc 1 189 3 view .LVU72
 190:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 191:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   /* Enable interrupt */
 192:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   NVIC_EnableIRQ(IRQn);
 255              		.loc 1 192 3 view .LVU73
 256              	.LBB50:
 257              	.LBI50:
1511:Drivers/CMSIS/Include/core_cm3.h **** {
 258              		.loc 2 1511 22 view .LVU74
 259              	.LBB51:
ARM GAS  /tmp/ccMY5QHu.s 			page 39


1513:Drivers/CMSIS/Include/core_cm3.h ****   {
 260              		.loc 2 1513 3 view .LVU75
1513:Drivers/CMSIS/Include/core_cm3.h ****   {
 261              		.loc 2 1513 6 is_stmt 0 view .LVU76
 262 0000 0028     		cmp	r0, #0
 263              	.LVL28:
1513:Drivers/CMSIS/Include/core_cm3.h ****   {
 264              		.loc 2 1513 6 view .LVU77
 265 0002 07DB     		blt	.L12
1515:Drivers/CMSIS/Include/core_cm3.h ****   }
 266              		.loc 2 1515 5 is_stmt 1 view .LVU78
1515:Drivers/CMSIS/Include/core_cm3.h ****   }
 267              		.loc 2 1515 81 is_stmt 0 view .LVU79
 268 0004 00F01F02 		and	r2, r0, #31
1515:Drivers/CMSIS/Include/core_cm3.h ****   }
 269              		.loc 2 1515 34 view .LVU80
 270 0008 4009     		lsrs	r0, r0, #5
1515:Drivers/CMSIS/Include/core_cm3.h ****   }
 271              		.loc 2 1515 45 view .LVU81
 272 000a 0123     		movs	r3, #1
 273 000c 9340     		lsls	r3, r3, r2
1515:Drivers/CMSIS/Include/core_cm3.h ****   }
 274              		.loc 2 1515 43 view .LVU82
 275 000e 024A     		ldr	r2, .L14
 276 0010 42F82030 		str	r3, [r2, r0, lsl #2]
 277              	.LVL29:
 278              	.L12:
1515:Drivers/CMSIS/Include/core_cm3.h ****   }
 279              		.loc 2 1515 43 view .LVU83
 280              	.LBE51:
 281              	.LBE50:
 193:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** }
 282              		.loc 1 193 1 view .LVU84
 283 0014 7047     		bx	lr
 284              	.L15:
 285 0016 00BF     		.align	2
 286              	.L14:
 287 0018 00E100E0 		.word	-536813312
 288              		.cfi_endproc
 289              	.LFE67:
 291              		.section	.text.HAL_NVIC_DisableIRQ,"ax",%progbits
 292              		.align	1
 293              		.global	HAL_NVIC_DisableIRQ
 294              		.syntax unified
 295              		.thumb
 296              		.thumb_func
 298              	HAL_NVIC_DisableIRQ:
 299              	.LVL30:
 300              	.LFB68:
 194:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 195:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /**
 196:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
 197:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @param  IRQn External interrupt number.
 198:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
 199:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
 200:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @retval None
 201:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   */
ARM GAS  /tmp/ccMY5QHu.s 			page 40


 202:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
 203:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** {
 301              		.loc 1 203 1 is_stmt 1 view -0
 302              		.cfi_startproc
 303              		@ args = 0, pretend = 0, frame = 0
 304              		@ frame_needed = 0, uses_anonymous_args = 0
 305              		@ link register save eliminated.
 204:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   /* Check the parameters */
 205:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
 306              		.loc 1 205 3 view .LVU86
 206:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 207:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   /* Disable interrupt */
 208:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   NVIC_DisableIRQ(IRQn);
 307              		.loc 1 208 3 view .LVU87
 308              	.LBB58:
 309              	.LBI58:
1547:Drivers/CMSIS/Include/core_cm3.h **** {
 310              		.loc 2 1547 22 view .LVU88
 311              	.LBB59:
1549:Drivers/CMSIS/Include/core_cm3.h ****   {
 312              		.loc 2 1549 3 view .LVU89
1549:Drivers/CMSIS/Include/core_cm3.h ****   {
 313              		.loc 2 1549 6 is_stmt 0 view .LVU90
 314 0000 0028     		cmp	r0, #0
 315              	.LVL31:
1549:Drivers/CMSIS/Include/core_cm3.h ****   {
 316              		.loc 2 1549 6 view .LVU91
 317 0002 0CDB     		blt	.L16
1551:Drivers/CMSIS/Include/core_cm3.h ****     __DSB();
 318              		.loc 2 1551 5 is_stmt 1 view .LVU92
1551:Drivers/CMSIS/Include/core_cm3.h ****     __DSB();
 319              		.loc 2 1551 81 is_stmt 0 view .LVU93
 320 0004 00F01F02 		and	r2, r0, #31
1551:Drivers/CMSIS/Include/core_cm3.h ****     __DSB();
 321              		.loc 2 1551 34 view .LVU94
 322 0008 4009     		lsrs	r0, r0, #5
1551:Drivers/CMSIS/Include/core_cm3.h ****     __DSB();
 323              		.loc 2 1551 45 view .LVU95
 324 000a 0123     		movs	r3, #1
 325 000c 9340     		lsls	r3, r3, r2
1551:Drivers/CMSIS/Include/core_cm3.h ****     __DSB();
 326              		.loc 2 1551 43 view .LVU96
 327 000e 2030     		adds	r0, r0, #32
 328 0010 034A     		ldr	r2, .L18
 329 0012 42F82030 		str	r3, [r2, r0, lsl #2]
1552:Drivers/CMSIS/Include/core_cm3.h ****     __ISB();
 330              		.loc 2 1552 5 is_stmt 1 view .LVU97
 331              	.LBB60:
 332              	.LBI60:
 333              		.file 3 "Drivers/CMSIS/Include/cmsis_gcc.h"
   1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
   2:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @file     cmsis_gcc.h
   3:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
   4:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @version  V5.0.4
   5:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @date     09. April 2018
   6:Drivers/CMSIS/Include/cmsis_gcc.h ****  ******************************************************************************/
   7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
ARM GAS  /tmp/ccMY5QHu.s 			page 41


   8:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
   9:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
  10:Drivers/CMSIS/Include/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
  11:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
  12:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
  13:Drivers/CMSIS/Include/cmsis_gcc.h ****  * not use this file except in compliance with the License.
  14:Drivers/CMSIS/Include/cmsis_gcc.h ****  * You may obtain a copy of the License at
  15:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
  16:Drivers/CMSIS/Include/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
  17:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
  18:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
  19:Drivers/CMSIS/Include/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20:Drivers/CMSIS/Include/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21:Drivers/CMSIS/Include/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
  22:Drivers/CMSIS/Include/cmsis_gcc.h ****  * limitations under the License.
  23:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
  24:Drivers/CMSIS/Include/cmsis_gcc.h **** 
  25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
  26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
  27:Drivers/CMSIS/Include/cmsis_gcc.h **** 
  28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
  29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
  30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
  31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
  32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
  33:Drivers/CMSIS/Include/cmsis_gcc.h **** 
  34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
  35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
  36:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __has_builtin(x) (0)
  37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  38:Drivers/CMSIS/Include/cmsis_gcc.h **** 
  39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
  40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ASM
  41:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ASM                                  __asm
  42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __INLINE
  44:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __INLINE                               inline
  45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
  47:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
  48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE                 
  50:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
  51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif                                           
  52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __NO_RETURN
  53:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
  54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __USED
  56:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
  57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __WEAK
  59:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
  60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED
  62:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
  63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
ARM GAS  /tmp/ccMY5QHu.s 			page 42


  65:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
  66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_UNION
  68:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
  69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
  71:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
  72:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  73:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  74:Drivers/CMSIS/Include/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
  75:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  76:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
  77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
  79:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
  80:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  81:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  82:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
  83:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  84:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
  85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
  87:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
  88:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  89:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  90:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
  91:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  92:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
  93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
  95:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
  96:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  97:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  98:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
  99:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 100:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
 103:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
 104:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
 105:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
 106:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
 107:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 108:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ALIGNED
 111:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __RESTRICT
 114:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 116:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 117:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
 120:Drivers/CMSIS/Include/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
 121:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
ARM GAS  /tmp/ccMY5QHu.s 			page 43


 122:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 125:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
 126:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
 127:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 128:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
 130:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 131:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
 132:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 133:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 136:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
 137:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
 138:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 139:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
 141:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 142:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
 143:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 144:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 145:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 147:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register
 148:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the Control Register.
 149:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Control Register value
 150:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
 152:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 153:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 154:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 155:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control" : "=r" (result) );
 156:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 157:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 158:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 159:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 162:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register (non-secure)
 163:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the non-secure Control Register when in secure mode.
 164:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               non-secure Control Register value
 165:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
 167:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 168:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 169:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 170:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
 171:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 172:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 174:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 175:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 177:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register
 178:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the Control Register.
ARM GAS  /tmp/ccMY5QHu.s 			page 44


 179:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
 180:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
 182:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 183:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
 184:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 185:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 186:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 189:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register (non-secure)
 190:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the non-secure Control Register when in secure state.
 191:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
 192:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
 194:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 195:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
 196:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 198:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 199:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 201:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get IPSR Register
 202:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the IPSR Register.
 203:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               IPSR Register value
 204:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
 206:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 207:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 208:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 209:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 210:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 211:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 212:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 213:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 215:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get APSR Register
 216:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the APSR Register.
 217:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               APSR Register value
 218:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
 220:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 221:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 222:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 223:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
 224:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 225:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 226:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 227:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 229:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get xPSR Register
 230:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the xPSR Register.
 231:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               xPSR Register value
 232:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
 234:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 235:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
ARM GAS  /tmp/ccMY5QHu.s 			page 45


 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 237:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
 238:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 239:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 240:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 241:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 243:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer
 244:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer (PSP).
 245:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
 246:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
 248:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 249:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 250:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 251:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp"  : "=r" (result) );
 252:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 253:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 254:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 255:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 258:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer (non-secure)
 259:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
 260:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
 261:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
 263:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 264:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 265:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 266:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
 267:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 268:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 270:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 271:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 273:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer
 274:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer (PSP).
 275:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
 276:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
 278:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 279:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
 280:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 281:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 282:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 285:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
 286:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
 287:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
 288:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
 290:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 291:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
 292:Drivers/CMSIS/Include/cmsis_gcc.h **** }
ARM GAS  /tmp/ccMY5QHu.s 			page 46


 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 294:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 295:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 297:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer
 298:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer (MSP).
 299:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
 300:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
 302:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 303:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 304:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 305:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp" : "=r" (result) );
 306:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 307:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 308:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 309:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 312:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer (non-secure)
 313:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
 314:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
 315:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
 317:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 318:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 319:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 320:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
 321:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 322:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 324:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 325:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 327:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer
 328:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer (MSP).
 329:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
 330:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
 332:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 333:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
 334:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 335:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 336:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 339:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer (non-secure)
 340:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
 341:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
 342:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
 344:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 345:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
 346:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 348:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 349:Drivers/CMSIS/Include/cmsis_gcc.h **** 
ARM GAS  /tmp/ccMY5QHu.s 			page 47


 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 352:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Stack Pointer (non-secure)
 353:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
 354:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               SP Register value
 355:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
 357:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 358:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 359:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 360:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
 361:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 362:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 363:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 364:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 366:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Stack Pointer (non-secure)
 367:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
 368:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfStack  Stack Pointer value to set
 369:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
 371:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 372:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
 373:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 375:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 378:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask
 379:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the priority mask bit from the Priority Mask Register.
 380:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
 381:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
 383:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 384:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 385:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 386:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
 387:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 388:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 389:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 390:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 393:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask (non-secure)
 394:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg
 395:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
 396:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
 398:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 399:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 400:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 401:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
 402:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 403:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 405:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 406:Drivers/CMSIS/Include/cmsis_gcc.h **** 
ARM GAS  /tmp/ccMY5QHu.s 			page 48


 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 408:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask
 409:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Priority Mask Register.
 410:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
 411:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
 413:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 414:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
 415:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 416:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 417:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 420:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask (non-secure)
 421:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
 422:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
 423:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
 425:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 426:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
 427:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 429:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 430:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 432:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 433:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 435:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable FIQ
 436:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
 437:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 438:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void)
 440:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 441:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie f" : : : "memory");
 442:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 443:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 444:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 446:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable FIQ
 447:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables FIQ interrupts by setting the F-bit in the CPSR.
 448:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 449:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void)
 451:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 452:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid f" : : : "memory");
 453:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 454:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 455:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 457:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority
 458:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Base Priority register.
 459:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
 460:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
 462:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 463:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
ARM GAS  /tmp/ccMY5QHu.s 			page 49


 464:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 465:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri" : "=r" (result) );
 466:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 467:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 468:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 469:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 472:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority (non-secure)
 473:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Base Priority register when in secure state.
 474:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
 475:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
 477:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 478:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 479:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 480:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
 481:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 482:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 485:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 487:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority
 488:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register.
 489:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
 490:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
 492:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 493:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
 494:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 495:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 499:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority (non-secure)
 500:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Base Priority register when in secure state.
 501:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
 502:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
 504:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 505:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
 506:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 508:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 509:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 511:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority with condition
 512:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
 513:Drivers/CMSIS/Include/cmsis_gcc.h ****            or the new value increases the BASEPRI priority level.
 514:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
 515:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
 517:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 518:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
 519:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 520:Drivers/CMSIS/Include/cmsis_gcc.h **** 
ARM GAS  /tmp/ccMY5QHu.s 			page 50


 521:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 523:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask
 524:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Fault Mask register.
 525:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
 526:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
 528:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 529:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 530:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 531:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
 532:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 533:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 534:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 538:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask (non-secure)
 539:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Fault Mask register when in secure state.
 540:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
 541:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
 543:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 544:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 545:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 546:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
 547:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 548:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 550:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 551:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 553:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask
 554:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Fault Mask register.
 555:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
 556:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
 558:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 559:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
 560:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 561:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 565:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask (non-secure)
 566:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Fault Mask register when in secure state.
 567:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
 568:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
 570:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 571:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
 572:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 574:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 576:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 577:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
ARM GAS  /tmp/ccMY5QHu.s 			page 51


 578:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 579:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 581:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
 582:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 584:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit
 585:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
 586:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
 587:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
 588:Drivers/CMSIS/Include/cmsis_gcc.h ****   
 589:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
 590:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
 591:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
 593:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
 595:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
 596:Drivers/CMSIS/Include/cmsis_gcc.h ****     // without main extensions, the non-secure PSPLIM is RAZ/WI
 597:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 599:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 600:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
 601:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 603:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 604:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 607:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit (non-secure)
 608:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
 609:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
 610:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 611:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in
 612:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
 613:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
 615:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
 617:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
 618:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 620:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 621:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
 622:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 624:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 626:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 627:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 629:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer Limit
 630:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
 631:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
 632:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
 633:Drivers/CMSIS/Include/cmsis_gcc.h ****   
 634:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
ARM GAS  /tmp/ccMY5QHu.s 			page 52


 635:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
 636:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
 638:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
 640:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
 641:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
 642:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 644:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 646:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 647:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 648:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 651:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
 652:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
 653:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
 654:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 655:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s
 656:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
 657:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
 659:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
 661:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
 662:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 664:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 666:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 668:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 669:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 671:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit
 672:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
 673:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
 674:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
 675:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 676:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
 677:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
 678:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
 680:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
 682:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
 683:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
 684:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 686:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 687:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim" : "=r" (result) );
 688:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 690:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 691:Drivers/CMSIS/Include/cmsis_gcc.h **** 
ARM GAS  /tmp/ccMY5QHu.s 			page 53


 692:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 695:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit (non-secure)
 696:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
 697:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
 698:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 699:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec
 700:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
 701:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
 703:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
 705:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
 706:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 708:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 709:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
 710:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 712:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 714:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 715:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 717:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit
 718:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
 719:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
 720:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
 721:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 722:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
 723:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
 724:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
 726:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
 728:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
 729:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
 730:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 732:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 734:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 739:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit (non-secure)
 740:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
 741:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
 742:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 743:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu
 744:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
 745:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
 747:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
ARM GAS  /tmp/ccMY5QHu.s 			page 54


 749:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
 750:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 752:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 754:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 756:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 758:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
 759:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 760:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 762:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get FPSCR
 763:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Floating Point Status/Control register.
 764:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Floating Point Status/Control register value
 765:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
 767:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
 769:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) 
 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
 773:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
 774:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_arm_get_fpscr();
 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 776:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 777:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 778:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
 779:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 782:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(0U);
 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 784:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 785:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 786:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 788:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set FPSCR
 789:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Floating Point Status/Control register.
 790:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    fpscr  Floating Point Status/Control value to set
 791:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
 793:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
 795:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr)
 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
 799:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
 800:Drivers/CMSIS/Include/cmsis_gcc.h ****   __builtin_arm_set_fpscr(fpscr);
 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 802:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 805:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)fpscr;
ARM GAS  /tmp/ccMY5QHu.s 			page 55


 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 807:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 808:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 809:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
 811:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 812:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
 815:Drivers/CMSIS/Include/cmsis_gcc.h ****   Access to dedicated instructions
 816:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */
 818:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
 820:Drivers/CMSIS/Include/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
 821:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 831:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 833:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   No Operation
 834:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
 835:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP()                             __ASM volatile ("nop")
 837:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 839:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Interrupt
 840:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
 841:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI()                             __ASM volatile ("wfi")
 843:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 844:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 846:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Event
 847:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
 848:Drivers/CMSIS/Include/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
 849:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe")
 851:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 854:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Send Event
 855:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
 856:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV()                             __ASM volatile ("sev")
 858:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 859:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 861:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
 862:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
ARM GAS  /tmp/ccMY5QHu.s 			page 56


 863:Drivers/CMSIS/Include/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
 864:Drivers/CMSIS/Include/cmsis_gcc.h ****            after the instruction has been completed.
 865:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
 867:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 868:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
 869:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 870:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 871:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 873:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
 874:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
 875:Drivers/CMSIS/Include/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
 876:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
 334              		.loc 3 877 27 view .LVU98
 335              	.LBB61:
 878:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 879:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
 336              		.loc 3 879 3 view .LVU99
 337              		.syntax unified
 338              	@ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 339 0016 BFF34F8F 		dsb 0xF
 340              	@ 0 "" 2
 341              		.thumb
 342              		.syntax unified
 343              	.LBE61:
 344              	.LBE60:
1553:Drivers/CMSIS/Include/core_cm3.h ****   }
 345              		.loc 2 1553 5 view .LVU100
 346              	.LBB62:
 347              	.LBI62:
 866:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 348              		.loc 3 866 27 view .LVU101
 349              	.LBB63:
 868:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 350              		.loc 3 868 3 view .LVU102
 351              		.syntax unified
 352              	@ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 353 001a BFF36F8F 		isb 0xF
 354              	@ 0 "" 2
 355              	.LVL32:
 356              		.thumb
 357              		.syntax unified
 358              	.L16:
 868:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 359              		.loc 3 868 3 is_stmt 0 view .LVU103
 360              	.LBE63:
 361              	.LBE62:
 362              	.LBE59:
 363              	.LBE58:
 209:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** }
 364              		.loc 1 209 1 view .LVU104
 365 001e 7047     		bx	lr
 366              	.L19:
 367              		.align	2
 368              	.L18:
ARM GAS  /tmp/ccMY5QHu.s 			page 57


 369 0020 00E100E0 		.word	-536813312
 370              		.cfi_endproc
 371              	.LFE68:
 373              		.section	.text.HAL_NVIC_SystemReset,"ax",%progbits
 374              		.align	1
 375              		.global	HAL_NVIC_SystemReset
 376              		.syntax unified
 377              		.thumb
 378              		.thumb_func
 380              	HAL_NVIC_SystemReset:
 381              	.LFB69:
 210:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 211:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /**
 212:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @brief  Initiates a system reset request to reset the MCU.
 213:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @retval None
 214:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   */
 215:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** void HAL_NVIC_SystemReset(void)
 216:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** {
 382              		.loc 1 216 1 is_stmt 1 view -0
 383              		.cfi_startproc
 384              		@ Volatile: function does not return.
 385              		@ args = 0, pretend = 0, frame = 0
 386              		@ frame_needed = 0, uses_anonymous_args = 0
 387              		@ link register save eliminated.
 217:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   /* System Reset */
 218:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   NVIC_SystemReset();
 388              		.loc 1 218 3 view .LVU106
 389              	.LBB70:
 390              	.LBI70:
1698:Drivers/CMSIS/Include/core_cm3.h ****          );
1699:Drivers/CMSIS/Include/core_cm3.h **** }
1700:Drivers/CMSIS/Include/core_cm3.h **** 
1701:Drivers/CMSIS/Include/core_cm3.h **** 
1702:Drivers/CMSIS/Include/core_cm3.h **** /**
1703:Drivers/CMSIS/Include/core_cm3.h ****   \brief   Decode Priority
1704:Drivers/CMSIS/Include/core_cm3.h ****   \details Decodes an interrupt priority value with a given priority group to
1705:Drivers/CMSIS/Include/core_cm3.h ****            preemptive priority value and subpriority value.
1706:Drivers/CMSIS/Include/core_cm3.h ****            In case of a conflict between priority grouping and available
1707:Drivers/CMSIS/Include/core_cm3.h ****            priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1708:Drivers/CMSIS/Include/core_cm3.h ****   \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC
1709:Drivers/CMSIS/Include/core_cm3.h ****   \param [in]     PriorityGroup  Used priority group.
1710:Drivers/CMSIS/Include/core_cm3.h ****   \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
1711:Drivers/CMSIS/Include/core_cm3.h ****   \param [out]     pSubPriority  Subpriority value (starting from 0).
1712:Drivers/CMSIS/Include/core_cm3.h ****  */
1713:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* cons
1714:Drivers/CMSIS/Include/core_cm3.h **** {
1715:Drivers/CMSIS/Include/core_cm3.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used   
1716:Drivers/CMSIS/Include/core_cm3.h ****   uint32_t PreemptPriorityBits;
1717:Drivers/CMSIS/Include/core_cm3.h ****   uint32_t SubPriorityBits;
1718:Drivers/CMSIS/Include/core_cm3.h **** 
1719:Drivers/CMSIS/Include/core_cm3.h ****   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV
1720:Drivers/CMSIS/Include/core_cm3.h ****   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
1721:Drivers/CMSIS/Include/core_cm3.h **** 
1722:Drivers/CMSIS/Include/core_cm3.h ****   *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1
1723:Drivers/CMSIS/Include/core_cm3.h ****   *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1
1724:Drivers/CMSIS/Include/core_cm3.h **** }
1725:Drivers/CMSIS/Include/core_cm3.h **** 
ARM GAS  /tmp/ccMY5QHu.s 			page 58


1726:Drivers/CMSIS/Include/core_cm3.h **** 
1727:Drivers/CMSIS/Include/core_cm3.h **** /**
1728:Drivers/CMSIS/Include/core_cm3.h ****   \brief   Set Interrupt Vector
1729:Drivers/CMSIS/Include/core_cm3.h ****   \details Sets an interrupt vector in SRAM based interrupt vector table.
1730:Drivers/CMSIS/Include/core_cm3.h ****            The interrupt number can be positive to specify a device specific interrupt,
1731:Drivers/CMSIS/Include/core_cm3.h ****            or negative to specify a processor exception.
1732:Drivers/CMSIS/Include/core_cm3.h ****            VTOR must been relocated to SRAM before.
1733:Drivers/CMSIS/Include/core_cm3.h ****   \param [in]   IRQn      Interrupt number
1734:Drivers/CMSIS/Include/core_cm3.h ****   \param [in]   vector    Address of interrupt handler function
1735:Drivers/CMSIS/Include/core_cm3.h ****  */
1736:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
1737:Drivers/CMSIS/Include/core_cm3.h **** {
1738:Drivers/CMSIS/Include/core_cm3.h ****   uint32_t *vectors = (uint32_t *)SCB->VTOR;
1739:Drivers/CMSIS/Include/core_cm3.h ****   vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
1740:Drivers/CMSIS/Include/core_cm3.h **** }
1741:Drivers/CMSIS/Include/core_cm3.h **** 
1742:Drivers/CMSIS/Include/core_cm3.h **** 
1743:Drivers/CMSIS/Include/core_cm3.h **** /**
1744:Drivers/CMSIS/Include/core_cm3.h ****   \brief   Get Interrupt Vector
1745:Drivers/CMSIS/Include/core_cm3.h ****   \details Reads an interrupt vector from interrupt vector table.
1746:Drivers/CMSIS/Include/core_cm3.h ****            The interrupt number can be positive to specify a device specific interrupt,
1747:Drivers/CMSIS/Include/core_cm3.h ****            or negative to specify a processor exception.
1748:Drivers/CMSIS/Include/core_cm3.h ****   \param [in]   IRQn      Interrupt number.
1749:Drivers/CMSIS/Include/core_cm3.h ****   \return                 Address of interrupt handler function
1750:Drivers/CMSIS/Include/core_cm3.h ****  */
1751:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
1752:Drivers/CMSIS/Include/core_cm3.h **** {
1753:Drivers/CMSIS/Include/core_cm3.h ****   uint32_t *vectors = (uint32_t *)SCB->VTOR;
1754:Drivers/CMSIS/Include/core_cm3.h ****   return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
1755:Drivers/CMSIS/Include/core_cm3.h **** }
1756:Drivers/CMSIS/Include/core_cm3.h **** 
1757:Drivers/CMSIS/Include/core_cm3.h **** 
1758:Drivers/CMSIS/Include/core_cm3.h **** /**
1759:Drivers/CMSIS/Include/core_cm3.h ****   \brief   System Reset
1760:Drivers/CMSIS/Include/core_cm3.h ****   \details Initiates a system reset request to reset the MCU.
1761:Drivers/CMSIS/Include/core_cm3.h ****  */
1762:Drivers/CMSIS/Include/core_cm3.h **** __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
 391              		.loc 2 1762 34 view .LVU107
 392              	.LBB71:
1763:Drivers/CMSIS/Include/core_cm3.h **** {
1764:Drivers/CMSIS/Include/core_cm3.h ****   __DSB();                                                          /* Ensure all outstanding memor
 393              		.loc 2 1764 3 view .LVU108
 394              	.LBB72:
 395              	.LBI72:
 877:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 396              		.loc 3 877 27 view .LVU109
 397              	.LBB73:
 398              		.loc 3 879 3 view .LVU110
 399              		.syntax unified
 400              	@ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 401 0000 BFF34F8F 		dsb 0xF
 402              	@ 0 "" 2
 403              		.thumb
 404              		.syntax unified
 405              	.LBE73:
 406              	.LBE72:
1765:Drivers/CMSIS/Include/core_cm3.h ****                                                                        buffered write are completed
ARM GAS  /tmp/ccMY5QHu.s 			page 59


1766:Drivers/CMSIS/Include/core_cm3.h ****   SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
 407              		.loc 2 1766 3 view .LVU111
1767:Drivers/CMSIS/Include/core_cm3.h ****                            (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
 408              		.loc 2 1767 32 is_stmt 0 view .LVU112
 409 0004 0549     		ldr	r1, .L22
 410 0006 CA68     		ldr	r2, [r1, #12]
 411              		.loc 2 1767 40 view .LVU113
 412 0008 02F4E062 		and	r2, r2, #1792
1766:Drivers/CMSIS/Include/core_cm3.h ****                            (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
 413              		.loc 2 1766 17 view .LVU114
 414 000c 044B     		ldr	r3, .L22+4
 415 000e 1343     		orrs	r3, r3, r2
1766:Drivers/CMSIS/Include/core_cm3.h ****                            (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
 416              		.loc 2 1766 15 view .LVU115
 417 0010 CB60     		str	r3, [r1, #12]
1768:Drivers/CMSIS/Include/core_cm3.h ****                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchange
1769:Drivers/CMSIS/Include/core_cm3.h ****   __DSB();                                                          /* Ensure completion of memory 
 418              		.loc 2 1769 3 is_stmt 1 view .LVU116
 419              	.LBB74:
 420              	.LBI74:
 877:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 421              		.loc 3 877 27 view .LVU117
 422              	.LBB75:
 423              		.loc 3 879 3 view .LVU118
 424              		.syntax unified
 425              	@ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 426 0012 BFF34F8F 		dsb 0xF
 427              	@ 0 "" 2
 428              		.thumb
 429              		.syntax unified
 430              	.L21:
 431              	.LBE75:
 432              	.LBE74:
1770:Drivers/CMSIS/Include/core_cm3.h **** 
1771:Drivers/CMSIS/Include/core_cm3.h ****   for(;;)                                                           /* wait until reset */
 433              		.loc 2 1771 3 view .LVU119
1772:Drivers/CMSIS/Include/core_cm3.h ****   {
1773:Drivers/CMSIS/Include/core_cm3.h ****     __NOP();
 434              		.loc 2 1773 5 view .LVU120
 435              		.syntax unified
 436              	@ 1773 "Drivers/CMSIS/Include/core_cm3.h" 1
 437 0016 00BF     		nop
 438              	@ 0 "" 2
1771:Drivers/CMSIS/Include/core_cm3.h ****   {
 439              		.loc 2 1771 8 view .LVU121
 440              		.thumb
 441              		.syntax unified
 442 0018 FDE7     		b	.L21
 443              	.L23:
 444 001a 00BF     		.align	2
 445              	.L22:
 446 001c 00ED00E0 		.word	-536810240
 447 0020 0400FA05 		.word	100270084
 448              	.LBE71:
 449              	.LBE70:
 450              		.cfi_endproc
 451              	.LFE69:
ARM GAS  /tmp/ccMY5QHu.s 			page 60


 453              		.section	.text.HAL_SYSTICK_Config,"ax",%progbits
 454              		.align	1
 455              		.global	HAL_SYSTICK_Config
 456              		.syntax unified
 457              		.thumb
 458              		.thumb_func
 460              	HAL_SYSTICK_Config:
 461              	.LVL33:
 462              	.LFB70:
 219:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** }
 220:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 221:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /**
 222:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
 223:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         Counter is in free running mode to generate periodic interrupts.
 224:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
 225:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @retval status:  - 0  Function succeeded.
 226:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *                  - 1  Function failed.
 227:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   */
 228:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
 229:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** {
 463              		.loc 1 229 1 view -0
 464              		.cfi_startproc
 465              		@ args = 0, pretend = 0, frame = 0
 466              		@ frame_needed = 0, uses_anonymous_args = 0
 467              		@ link register save eliminated.
 230:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****    return SysTick_Config(TicksNumb);
 468              		.loc 1 230 4 view .LVU123
 469              	.LBB76:
 470              	.LBI76:
1774:Drivers/CMSIS/Include/core_cm3.h ****   }
1775:Drivers/CMSIS/Include/core_cm3.h **** }
1776:Drivers/CMSIS/Include/core_cm3.h **** 
1777:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of CMSIS_Core_NVICFunctions */
1778:Drivers/CMSIS/Include/core_cm3.h **** 
1779:Drivers/CMSIS/Include/core_cm3.h **** /* ##########################  MPU functions  #################################### */
1780:Drivers/CMSIS/Include/core_cm3.h **** 
1781:Drivers/CMSIS/Include/core_cm3.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1782:Drivers/CMSIS/Include/core_cm3.h **** 
1783:Drivers/CMSIS/Include/core_cm3.h **** #include "mpu_armv7.h"
1784:Drivers/CMSIS/Include/core_cm3.h **** 
1785:Drivers/CMSIS/Include/core_cm3.h **** #endif
1786:Drivers/CMSIS/Include/core_cm3.h **** 
1787:Drivers/CMSIS/Include/core_cm3.h **** /* ##########################  FPU functions  #################################### */
1788:Drivers/CMSIS/Include/core_cm3.h **** /**
1789:Drivers/CMSIS/Include/core_cm3.h ****   \ingroup  CMSIS_Core_FunctionInterface
1790:Drivers/CMSIS/Include/core_cm3.h ****   \defgroup CMSIS_Core_FpuFunctions FPU Functions
1791:Drivers/CMSIS/Include/core_cm3.h ****   \brief    Function that provides FPU type.
1792:Drivers/CMSIS/Include/core_cm3.h ****   @{
1793:Drivers/CMSIS/Include/core_cm3.h ****  */
1794:Drivers/CMSIS/Include/core_cm3.h **** 
1795:Drivers/CMSIS/Include/core_cm3.h **** /**
1796:Drivers/CMSIS/Include/core_cm3.h ****   \brief   get FPU type
1797:Drivers/CMSIS/Include/core_cm3.h ****   \details returns the FPU type
1798:Drivers/CMSIS/Include/core_cm3.h ****   \returns
1799:Drivers/CMSIS/Include/core_cm3.h ****    - \b  0: No FPU
1800:Drivers/CMSIS/Include/core_cm3.h ****    - \b  1: Single precision FPU
1801:Drivers/CMSIS/Include/core_cm3.h ****    - \b  2: Double + Single precision FPU
ARM GAS  /tmp/ccMY5QHu.s 			page 61


1802:Drivers/CMSIS/Include/core_cm3.h ****  */
1803:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE uint32_t SCB_GetFPUType(void)
1804:Drivers/CMSIS/Include/core_cm3.h **** {
1805:Drivers/CMSIS/Include/core_cm3.h ****     return 0U;           /* No FPU */
1806:Drivers/CMSIS/Include/core_cm3.h **** }
1807:Drivers/CMSIS/Include/core_cm3.h **** 
1808:Drivers/CMSIS/Include/core_cm3.h **** 
1809:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of CMSIS_Core_FpuFunctions */
1810:Drivers/CMSIS/Include/core_cm3.h **** 
1811:Drivers/CMSIS/Include/core_cm3.h **** 
1812:Drivers/CMSIS/Include/core_cm3.h **** 
1813:Drivers/CMSIS/Include/core_cm3.h **** /* ##################################    SysTick function  ########################################
1814:Drivers/CMSIS/Include/core_cm3.h **** /**
1815:Drivers/CMSIS/Include/core_cm3.h ****   \ingroup  CMSIS_Core_FunctionInterface
1816:Drivers/CMSIS/Include/core_cm3.h ****   \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1817:Drivers/CMSIS/Include/core_cm3.h ****   \brief    Functions that configure the System.
1818:Drivers/CMSIS/Include/core_cm3.h ****   @{
1819:Drivers/CMSIS/Include/core_cm3.h ****  */
1820:Drivers/CMSIS/Include/core_cm3.h **** 
1821:Drivers/CMSIS/Include/core_cm3.h **** #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
1822:Drivers/CMSIS/Include/core_cm3.h **** 
1823:Drivers/CMSIS/Include/core_cm3.h **** /**
1824:Drivers/CMSIS/Include/core_cm3.h ****   \brief   System Tick Configuration
1825:Drivers/CMSIS/Include/core_cm3.h ****   \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
1826:Drivers/CMSIS/Include/core_cm3.h ****            Counter is in free running mode to generate periodic interrupts.
1827:Drivers/CMSIS/Include/core_cm3.h ****   \param [in]  ticks  Number of ticks between two interrupts.
1828:Drivers/CMSIS/Include/core_cm3.h ****   \return          0  Function succeeded.
1829:Drivers/CMSIS/Include/core_cm3.h ****   \return          1  Function failed.
1830:Drivers/CMSIS/Include/core_cm3.h ****   \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1831:Drivers/CMSIS/Include/core_cm3.h ****            function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.
1832:Drivers/CMSIS/Include/core_cm3.h ****            must contain a vendor-specific implementation of this function.
1833:Drivers/CMSIS/Include/core_cm3.h ****  */
1834:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 471              		.loc 2 1834 26 view .LVU124
 472              	.LBB77:
1835:Drivers/CMSIS/Include/core_cm3.h **** {
1836:Drivers/CMSIS/Include/core_cm3.h ****   if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
 473              		.loc 2 1836 3 view .LVU125
 474              		.loc 2 1836 14 is_stmt 0 view .LVU126
 475 0000 0138     		subs	r0, r0, #1
 476              	.LVL34:
 477              		.loc 2 1836 6 view .LVU127
 478 0002 B0F1807F 		cmp	r0, #16777216
 479 0006 0BD2     		bcs	.L26
1837:Drivers/CMSIS/Include/core_cm3.h ****   {
1838:Drivers/CMSIS/Include/core_cm3.h ****     return (1UL);                                                   /* Reload value impossible */
1839:Drivers/CMSIS/Include/core_cm3.h ****   }
1840:Drivers/CMSIS/Include/core_cm3.h **** 
1841:Drivers/CMSIS/Include/core_cm3.h ****   SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 480              		.loc 2 1841 3 is_stmt 1 view .LVU128
 481              		.loc 2 1841 18 is_stmt 0 view .LVU129
 482 0008 4FF0E023 		mov	r3, #-536813568
 483 000c 5861     		str	r0, [r3, #20]
1842:Drivers/CMSIS/Include/core_cm3.h ****   NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Int
 484              		.loc 2 1842 3 is_stmt 1 view .LVU130
 485              	.LVL35:
 486              	.LBB78:
ARM GAS  /tmp/ccMY5QHu.s 			page 62


 487              	.LBI78:
1639:Drivers/CMSIS/Include/core_cm3.h **** {
 488              		.loc 2 1639 22 view .LVU131
 489              	.LBB79:
1641:Drivers/CMSIS/Include/core_cm3.h ****   {
 490              		.loc 2 1641 3 view .LVU132
1647:Drivers/CMSIS/Include/core_cm3.h ****   }
 491              		.loc 2 1647 5 view .LVU133
1647:Drivers/CMSIS/Include/core_cm3.h ****   }
 492              		.loc 2 1647 46 is_stmt 0 view .LVU134
 493 000e 054A     		ldr	r2, .L27
 494 0010 F021     		movs	r1, #240
 495 0012 82F82310 		strb	r1, [r2, #35]
 496              	.LVL36:
1647:Drivers/CMSIS/Include/core_cm3.h ****   }
 497              		.loc 2 1647 46 view .LVU135
 498              	.LBE79:
 499              	.LBE78:
1843:Drivers/CMSIS/Include/core_cm3.h ****   SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Val
 500              		.loc 2 1843 3 is_stmt 1 view .LVU136
 501              		.loc 2 1843 18 is_stmt 0 view .LVU137
 502 0016 0020     		movs	r0, #0
 503              	.LVL37:
 504              		.loc 2 1843 18 view .LVU138
 505 0018 9861     		str	r0, [r3, #24]
1844:Drivers/CMSIS/Include/core_cm3.h ****   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 506              		.loc 2 1844 3 is_stmt 1 view .LVU139
 507              		.loc 2 1844 18 is_stmt 0 view .LVU140
 508 001a 0722     		movs	r2, #7
 509 001c 1A61     		str	r2, [r3, #16]
1845:Drivers/CMSIS/Include/core_cm3.h ****                    SysTick_CTRL_TICKINT_Msk   |
1846:Drivers/CMSIS/Include/core_cm3.h ****                    SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTi
1847:Drivers/CMSIS/Include/core_cm3.h ****   return (0UL);                                                     /* Function successful */
 510              		.loc 2 1847 3 is_stmt 1 view .LVU141
 511              		.loc 2 1847 10 is_stmt 0 view .LVU142
 512 001e 7047     		bx	lr
 513              	.L26:
1838:Drivers/CMSIS/Include/core_cm3.h ****   }
 514              		.loc 2 1838 12 view .LVU143
 515 0020 0120     		movs	r0, #1
 516              	.LVL38:
1838:Drivers/CMSIS/Include/core_cm3.h ****   }
 517              		.loc 2 1838 12 view .LVU144
 518              	.LBE77:
 519              	.LBE76:
 231:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** }
 520              		.loc 1 231 1 view .LVU145
 521 0022 7047     		bx	lr
 522              	.L28:
 523              		.align	2
 524              	.L27:
 525 0024 00ED00E0 		.word	-536810240
 526              		.cfi_endproc
 527              	.LFE70:
 529              		.section	.text.HAL_NVIC_GetPriorityGrouping,"ax",%progbits
 530              		.align	1
 531              		.global	HAL_NVIC_GetPriorityGrouping
ARM GAS  /tmp/ccMY5QHu.s 			page 63


 532              		.syntax unified
 533              		.thumb
 534              		.thumb_func
 536              	HAL_NVIC_GetPriorityGrouping:
 537              	.LFB71:
 232:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /**
 233:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @}
 234:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   */
 235:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 236:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
 237:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *  @brief   Cortex control functions 
 238:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *
 239:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** @verbatim   
 240:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   ==============================================================================
 241:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****                       ##### Peripheral Control functions #####
 242:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   ==============================================================================
 243:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     [..]
 244:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****       This subsection provides a set of functions allowing to control the CORTEX
 245:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****       (NVIC, SYSTICK, MPU) functionalities. 
 246:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****  
 247:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****       
 248:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** @endverbatim
 249:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @{
 250:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   */
 251:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 252:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** #if (__MPU_PRESENT == 1U)
 253:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /**
 254:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @brief  Disables the MPU
 255:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @retval None
 256:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   */
 257:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** void HAL_MPU_Disable(void)
 258:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** {
 259:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   /* Make sure outstanding transfers are done */
 260:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   __DMB();
 261:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 262:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   /* Disable fault exceptions */
 263:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
 264:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   
 265:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   /* Disable the MPU and clear the control register*/
 266:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   MPU->CTRL = 0U;
 267:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** }
 268:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 269:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /**
 270:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @brief  Enable the MPU.
 271:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @param  MPU_Control: Specifies the control mode of the MPU during hard fault, 
 272:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *          NMI, FAULTMASK and privileged access to the default memory 
 273:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *          This parameter can be one of the following values:
 274:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *            @arg MPU_HFNMI_PRIVDEF_NONE
 275:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *            @arg MPU_HARDFAULT_NMI
 276:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *            @arg MPU_PRIVILEGED_DEFAULT
 277:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *            @arg MPU_HFNMI_PRIVDEF
 278:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @retval None
 279:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   */
 280:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** void HAL_MPU_Enable(uint32_t MPU_Control)
 281:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** {
 282:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   /* Enable the MPU */
 283:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
ARM GAS  /tmp/ccMY5QHu.s 			page 64


 284:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   
 285:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   /* Enable fault exceptions */
 286:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
 287:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   
 288:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   /* Ensure MPU setting take effects */
 289:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   __DSB();
 290:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   __ISB();
 291:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** }
 292:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 293:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /**
 294:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @brief  Initializes and configures the Region and the memory to be protected.
 295:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @param  MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
 296:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *                the initialization and configuration information.
 297:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @retval None
 298:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   */
 299:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
 300:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** {
 301:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   /* Check the parameters */
 302:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
 303:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
 304:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 305:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   /* Set the Region number */
 306:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   MPU->RNR = MPU_Init->Number;
 307:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 308:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   if ((MPU_Init->Enable) != RESET)
 309:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   {
 310:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     /* Check the parameters */
 311:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
 312:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
 313:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
 314:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
 315:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
 316:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
 317:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
 318:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
 319:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     
 320:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     MPU->RBAR = MPU_Init->BaseAddress;
 321:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
 322:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
 323:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
 324:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
 325:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
 326:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
 327:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
 328:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
 329:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
 330:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   }
 331:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   else
 332:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   {
 333:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     MPU->RBAR = 0x00U;
 334:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     MPU->RASR = 0x00U;
 335:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   }
 336:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** }
 337:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** #endif /* __MPU_PRESENT */
 338:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 339:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /**
 340:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.
ARM GAS  /tmp/ccMY5QHu.s 			page 65


 341:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
 342:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   */
 343:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPriorityGrouping(void)
 344:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** {
 538              		.loc 1 344 1 is_stmt 1 view -0
 539              		.cfi_startproc
 540              		@ args = 0, pretend = 0, frame = 0
 541              		@ frame_needed = 0, uses_anonymous_args = 0
 542              		@ link register save eliminated.
 345:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   /* Get the PRIGROUP[10:8] field value */
 346:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   return NVIC_GetPriorityGrouping();
 543              		.loc 1 346 3 view .LVU147
 544              	.LBB80:
 545              	.LBI80:
1499:Drivers/CMSIS/Include/core_cm3.h **** {
 546              		.loc 2 1499 26 view .LVU148
 547              	.LBB81:
1501:Drivers/CMSIS/Include/core_cm3.h **** }
 548              		.loc 2 1501 3 view .LVU149
1501:Drivers/CMSIS/Include/core_cm3.h **** }
 549              		.loc 2 1501 26 is_stmt 0 view .LVU150
 550 0000 024B     		ldr	r3, .L30
 551 0002 D868     		ldr	r0, [r3, #12]
 552              	.LBE81:
 553              	.LBE80:
 347:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** }
 554              		.loc 1 347 1 view .LVU151
 555 0004 C0F30220 		ubfx	r0, r0, #8, #3
 556 0008 7047     		bx	lr
 557              	.L31:
 558 000a 00BF     		.align	2
 559              	.L30:
 560 000c 00ED00E0 		.word	-536810240
 561              		.cfi_endproc
 562              	.LFE71:
 564              		.section	.text.HAL_NVIC_GetPriority,"ax",%progbits
 565              		.align	1
 566              		.global	HAL_NVIC_GetPriority
 567              		.syntax unified
 568              		.thumb
 569              		.thumb_func
 571              	HAL_NVIC_GetPriority:
 572              	.LVL39:
 573              	.LFB72:
 348:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 349:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /**
 350:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @brief  Gets the priority of an interrupt.
 351:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @param  IRQn: External interrupt number.
 352:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
 353:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
 354:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @param   PriorityGroup: the priority grouping bits length.
 355:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         This parameter can be one of the following values:
 356:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *           @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
 357:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *                                      4 bits for subpriority
 358:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *           @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
 359:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *                                      3 bits for subpriority
 360:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *           @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
ARM GAS  /tmp/ccMY5QHu.s 			page 66


 361:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *                                      2 bits for subpriority
 362:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *           @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
 363:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *                                      1 bits for subpriority
 364:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *           @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
 365:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *                                      0 bits for subpriority
 366:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @param  pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
 367:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @param  pSubPriority: Pointer on the Subpriority value (starting from 0).
 368:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @retval None
 369:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   */
 370:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint3
 371:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** {
 574              		.loc 1 371 1 is_stmt 1 view -0
 575              		.cfi_startproc
 576              		@ args = 0, pretend = 0, frame = 0
 577              		@ frame_needed = 0, uses_anonymous_args = 0
 578              		.loc 1 371 1 is_stmt 0 view .LVU153
 579 0000 10B5     		push	{r4, lr}
 580              	.LCFI1:
 581              		.cfi_def_cfa_offset 8
 582              		.cfi_offset 4, -8
 583              		.cfi_offset 14, -4
 372:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   /* Check the parameters */
 373:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
 584              		.loc 1 373 3 is_stmt 1 view .LVU154
 374:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****  /* Get priority for Cortex-M system or device specific interrupts */
 375:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
 585              		.loc 1 375 3 view .LVU155
 586              	.LVL40:
 587              	.LBB86:
 588              	.LBI86:
1661:Drivers/CMSIS/Include/core_cm3.h **** {
 589              		.loc 2 1661 26 view .LVU156
 590              	.LBB87:
1664:Drivers/CMSIS/Include/core_cm3.h ****   {
 591              		.loc 2 1664 3 view .LVU157
1664:Drivers/CMSIS/Include/core_cm3.h ****   {
 592              		.loc 2 1664 6 is_stmt 0 view .LVU158
 593 0002 0028     		cmp	r0, #0
 594              	.LVL41:
1664:Drivers/CMSIS/Include/core_cm3.h ****   {
 595              		.loc 2 1664 6 view .LVU159
 596 0004 22DB     		blt	.L33
1666:Drivers/CMSIS/Include/core_cm3.h ****   }
 597              		.loc 2 1666 5 is_stmt 1 view .LVU160
1666:Drivers/CMSIS/Include/core_cm3.h ****   }
 598              		.loc 2 1666 31 is_stmt 0 view .LVU161
 599 0006 00F16040 		add	r0, r0, #-536870912
 600 000a 00F56140 		add	r0, r0, #57600
 601 000e 90F80003 		ldrb	r0, [r0, #768]	@ zero_extendqisi2
1666:Drivers/CMSIS/Include/core_cm3.h ****   }
 602              		.loc 2 1666 64 view .LVU162
 603 0012 0009     		lsrs	r0, r0, #4
 604              	.L34:
 605              	.LVL42:
1666:Drivers/CMSIS/Include/core_cm3.h ****   }
 606              		.loc 2 1666 64 view .LVU163
 607              	.LBE87:
ARM GAS  /tmp/ccMY5QHu.s 			page 67


 608              	.LBE86:
 609              	.LBB89:
 610              	.LBI89:
1713:Drivers/CMSIS/Include/core_cm3.h **** {
 611              		.loc 2 1713 22 is_stmt 1 view .LVU164
 612              	.LBB90:
1715:Drivers/CMSIS/Include/core_cm3.h ****   uint32_t PreemptPriorityBits;
 613              		.loc 2 1715 3 view .LVU165
1715:Drivers/CMSIS/Include/core_cm3.h ****   uint32_t PreemptPriorityBits;
 614              		.loc 2 1715 12 is_stmt 0 view .LVU166
 615 0014 01F00701 		and	r1, r1, #7
 616              	.LVL43:
1716:Drivers/CMSIS/Include/core_cm3.h ****   uint32_t SubPriorityBits;
 617              		.loc 2 1716 3 is_stmt 1 view .LVU167
1717:Drivers/CMSIS/Include/core_cm3.h **** 
 618              		.loc 2 1717 3 view .LVU168
1719:Drivers/CMSIS/Include/core_cm3.h ****   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
 619              		.loc 2 1719 3 view .LVU169
1719:Drivers/CMSIS/Include/core_cm3.h ****   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
 620              		.loc 2 1719 31 is_stmt 0 view .LVU170
 621 0018 C1F1070C 		rsb	ip, r1, #7
1719:Drivers/CMSIS/Include/core_cm3.h ****   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
 622              		.loc 2 1719 23 view .LVU171
 623 001c BCF1040F 		cmp	ip, #4
 624 0020 28BF     		it	cs
 625 0022 4FF0040C 		movcs	ip, #4
 626              	.LVL44:
1720:Drivers/CMSIS/Include/core_cm3.h **** 
 627              		.loc 2 1720 3 is_stmt 1 view .LVU172
1720:Drivers/CMSIS/Include/core_cm3.h **** 
 628              		.loc 2 1720 44 is_stmt 0 view .LVU173
 629 0026 0C1D     		adds	r4, r1, #4
1720:Drivers/CMSIS/Include/core_cm3.h **** 
 630              		.loc 2 1720 109 view .LVU174
 631 0028 062C     		cmp	r4, #6
 632 002a 15D9     		bls	.L36
 633 002c 0339     		subs	r1, r1, #3
 634              	.LVL45:
 635              	.L35:
1722:Drivers/CMSIS/Include/core_cm3.h ****   *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1
 636              		.loc 2 1722 3 is_stmt 1 view .LVU175
1722:Drivers/CMSIS/Include/core_cm3.h ****   *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1
 637              		.loc 2 1722 33 is_stmt 0 view .LVU176
 638 002e 20FA01F4 		lsr	r4, r0, r1
 639              	.LVL46:
1722:Drivers/CMSIS/Include/core_cm3.h ****   *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1
 640              		.loc 2 1722 53 view .LVU177
 641 0032 4FF0FF3E 		mov	lr, #-1
 642 0036 0EFA0CFC 		lsl	ip, lr, ip
 643              	.LVL47:
1722:Drivers/CMSIS/Include/core_cm3.h ****   *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1
 644              		.loc 2 1722 53 view .LVU178
 645 003a 24EA0C04 		bic	r4, r4, ip
1722:Drivers/CMSIS/Include/core_cm3.h ****   *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1
 646              		.loc 2 1722 21 view .LVU179
 647 003e 1460     		str	r4, [r2]
1723:Drivers/CMSIS/Include/core_cm3.h **** }
ARM GAS  /tmp/ccMY5QHu.s 			page 68


 648              		.loc 2 1723 3 is_stmt 1 view .LVU180
1723:Drivers/CMSIS/Include/core_cm3.h **** }
 649              		.loc 2 1723 53 is_stmt 0 view .LVU181
 650 0040 0EFA01F1 		lsl	r1, lr, r1
 651              	.LVL48:
1723:Drivers/CMSIS/Include/core_cm3.h **** }
 652              		.loc 2 1723 53 view .LVU182
 653 0044 20EA0100 		bic	r0, r0, r1
 654              	.LVL49:
1723:Drivers/CMSIS/Include/core_cm3.h **** }
 655              		.loc 2 1723 21 view .LVU183
 656 0048 1860     		str	r0, [r3]
 657              	.LVL50:
1723:Drivers/CMSIS/Include/core_cm3.h **** }
 658              		.loc 2 1723 21 view .LVU184
 659              	.LBE90:
 660              	.LBE89:
 376:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** }
 661              		.loc 1 376 1 view .LVU185
 662 004a 10BD     		pop	{r4, pc}
 663              	.LVL51:
 664              	.L33:
 665              	.LBB92:
 666              	.LBB88:
1670:Drivers/CMSIS/Include/core_cm3.h ****   }
 667              		.loc 2 1670 5 is_stmt 1 view .LVU186
1670:Drivers/CMSIS/Include/core_cm3.h ****   }
 668              		.loc 2 1670 50 is_stmt 0 view .LVU187
 669 004c 00F00F00 		and	r0, r0, #15
1670:Drivers/CMSIS/Include/core_cm3.h ****   }
 670              		.loc 2 1670 31 view .LVU188
 671 0050 024C     		ldr	r4, .L38
 672 0052 205C     		ldrb	r0, [r4, r0]	@ zero_extendqisi2
1670:Drivers/CMSIS/Include/core_cm3.h ****   }
 673              		.loc 2 1670 64 view .LVU189
 674 0054 0009     		lsrs	r0, r0, #4
 675 0056 DDE7     		b	.L34
 676              	.LVL52:
 677              	.L36:
1670:Drivers/CMSIS/Include/core_cm3.h ****   }
 678              		.loc 2 1670 64 view .LVU190
 679              	.LBE88:
 680              	.LBE92:
 681              	.LBB93:
 682              	.LBB91:
1720:Drivers/CMSIS/Include/core_cm3.h **** 
 683              		.loc 2 1720 109 view .LVU191
 684 0058 0021     		movs	r1, #0
 685              	.LVL53:
1720:Drivers/CMSIS/Include/core_cm3.h **** 
 686              		.loc 2 1720 109 view .LVU192
 687 005a E8E7     		b	.L35
 688              	.L39:
 689              		.align	2
 690              	.L38:
 691 005c 14ED00E0 		.word	-536810220
 692              	.LBE91:
ARM GAS  /tmp/ccMY5QHu.s 			page 69


 693              	.LBE93:
 694              		.cfi_endproc
 695              	.LFE72:
 697              		.section	.text.HAL_NVIC_SetPendingIRQ,"ax",%progbits
 698              		.align	1
 699              		.global	HAL_NVIC_SetPendingIRQ
 700              		.syntax unified
 701              		.thumb
 702              		.thumb_func
 704              	HAL_NVIC_SetPendingIRQ:
 705              	.LVL54:
 706              	.LFB73:
 377:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 378:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /**
 379:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @brief  Sets Pending bit of an external interrupt.
 380:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @param  IRQn External interrupt number
 381:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
 382:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
 383:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @retval None
 384:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   */
 385:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
 386:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** {
 707              		.loc 1 386 1 is_stmt 1 view -0
 708              		.cfi_startproc
 709              		@ args = 0, pretend = 0, frame = 0
 710              		@ frame_needed = 0, uses_anonymous_args = 0
 711              		@ link register save eliminated.
 387:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   /* Check the parameters */
 388:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
 712              		.loc 1 388 3 view .LVU194
 389:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   
 390:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   /* Set interrupt pending */
 391:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   NVIC_SetPendingIRQ(IRQn);
 713              		.loc 1 391 3 view .LVU195
 714              	.LBB94:
 715              	.LBI94:
1585:Drivers/CMSIS/Include/core_cm3.h **** {
 716              		.loc 2 1585 22 view .LVU196
 717              	.LBB95:
1587:Drivers/CMSIS/Include/core_cm3.h ****   {
 718              		.loc 2 1587 3 view .LVU197
1587:Drivers/CMSIS/Include/core_cm3.h ****   {
 719              		.loc 2 1587 6 is_stmt 0 view .LVU198
 720 0000 0028     		cmp	r0, #0
 721              	.LVL55:
1587:Drivers/CMSIS/Include/core_cm3.h ****   {
 722              		.loc 2 1587 6 view .LVU199
 723 0002 08DB     		blt	.L40
1589:Drivers/CMSIS/Include/core_cm3.h ****   }
 724              		.loc 2 1589 5 is_stmt 1 view .LVU200
1589:Drivers/CMSIS/Include/core_cm3.h ****   }
 725              		.loc 2 1589 81 is_stmt 0 view .LVU201
 726 0004 00F01F02 		and	r2, r0, #31
1589:Drivers/CMSIS/Include/core_cm3.h ****   }
 727              		.loc 2 1589 34 view .LVU202
 728 0008 4009     		lsrs	r0, r0, #5
1589:Drivers/CMSIS/Include/core_cm3.h ****   }
ARM GAS  /tmp/ccMY5QHu.s 			page 70


 729              		.loc 2 1589 45 view .LVU203
 730 000a 0123     		movs	r3, #1
 731 000c 9340     		lsls	r3, r3, r2
1589:Drivers/CMSIS/Include/core_cm3.h ****   }
 732              		.loc 2 1589 43 view .LVU204
 733 000e 4030     		adds	r0, r0, #64
 734 0010 014A     		ldr	r2, .L42
 735 0012 42F82030 		str	r3, [r2, r0, lsl #2]
 736              	.LVL56:
 737              	.L40:
1589:Drivers/CMSIS/Include/core_cm3.h ****   }
 738              		.loc 2 1589 43 view .LVU205
 739              	.LBE95:
 740              	.LBE94:
 392:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** }
 741              		.loc 1 392 1 view .LVU206
 742 0016 7047     		bx	lr
 743              	.L43:
 744              		.align	2
 745              	.L42:
 746 0018 00E100E0 		.word	-536813312
 747              		.cfi_endproc
 748              	.LFE73:
 750              		.section	.text.HAL_NVIC_GetPendingIRQ,"ax",%progbits
 751              		.align	1
 752              		.global	HAL_NVIC_GetPendingIRQ
 753              		.syntax unified
 754              		.thumb
 755              		.thumb_func
 757              	HAL_NVIC_GetPendingIRQ:
 758              	.LVL57:
 759              	.LFB74:
 393:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 394:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /**
 395:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @brief  Gets Pending Interrupt (reads the pending register in the NVIC 
 396:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         and returns the pending bit for the specified interrupt).
 397:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @param  IRQn External interrupt number.
 398:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
 399:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
 400:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @retval status: - 0  Interrupt status is not pending.
 401:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *                 - 1  Interrupt status is pending.
 402:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   */
 403:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
 404:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** {
 760              		.loc 1 404 1 is_stmt 1 view -0
 761              		.cfi_startproc
 762              		@ args = 0, pretend = 0, frame = 0
 763              		@ frame_needed = 0, uses_anonymous_args = 0
 764              		@ link register save eliminated.
 405:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   /* Check the parameters */
 406:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
 765              		.loc 1 406 3 view .LVU208
 407:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 408:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   /* Return 1 if pending else 0 */
 409:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   return NVIC_GetPendingIRQ(IRQn);
 766              		.loc 1 409 3 view .LVU209
 767              	.LBB96:
ARM GAS  /tmp/ccMY5QHu.s 			page 71


 768              	.LBI96:
1566:Drivers/CMSIS/Include/core_cm3.h **** {
 769              		.loc 2 1566 26 view .LVU210
 770              	.LBB97:
1568:Drivers/CMSIS/Include/core_cm3.h ****   {
 771              		.loc 2 1568 3 view .LVU211
1568:Drivers/CMSIS/Include/core_cm3.h ****   {
 772              		.loc 2 1568 6 is_stmt 0 view .LVU212
 773 0000 0028     		cmp	r0, #0
 774              	.LVL58:
1568:Drivers/CMSIS/Include/core_cm3.h ****   {
 775              		.loc 2 1568 6 view .LVU213
 776 0002 0BDB     		blt	.L46
1570:Drivers/CMSIS/Include/core_cm3.h ****   }
 777              		.loc 2 1570 5 is_stmt 1 view .LVU214
1570:Drivers/CMSIS/Include/core_cm3.h ****   }
 778              		.loc 2 1570 54 is_stmt 0 view .LVU215
 779 0004 4309     		lsrs	r3, r0, #5
1570:Drivers/CMSIS/Include/core_cm3.h ****   }
 780              		.loc 2 1570 35 view .LVU216
 781 0006 4033     		adds	r3, r3, #64
 782 0008 054A     		ldr	r2, .L47
 783 000a 52F82330 		ldr	r3, [r2, r3, lsl #2]
1570:Drivers/CMSIS/Include/core_cm3.h ****   }
 784              		.loc 2 1570 91 view .LVU217
 785 000e 00F01F00 		and	r0, r0, #31
1570:Drivers/CMSIS/Include/core_cm3.h ****   }
 786              		.loc 2 1570 103 view .LVU218
 787 0012 23FA00F0 		lsr	r0, r3, r0
1570:Drivers/CMSIS/Include/core_cm3.h ****   }
 788              		.loc 2 1570 12 view .LVU219
 789 0016 00F00100 		and	r0, r0, #1
 790 001a 7047     		bx	lr
 791              	.L46:
1574:Drivers/CMSIS/Include/core_cm3.h ****   }
 792              		.loc 2 1574 11 view .LVU220
 793 001c 0020     		movs	r0, #0
 794              	.LVL59:
1574:Drivers/CMSIS/Include/core_cm3.h ****   }
 795              		.loc 2 1574 11 view .LVU221
 796              	.LBE97:
 797              	.LBE96:
 410:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** }
 798              		.loc 1 410 1 view .LVU222
 799 001e 7047     		bx	lr
 800              	.L48:
 801              		.align	2
 802              	.L47:
 803 0020 00E100E0 		.word	-536813312
 804              		.cfi_endproc
 805              	.LFE74:
 807              		.section	.text.HAL_NVIC_ClearPendingIRQ,"ax",%progbits
 808              		.align	1
 809              		.global	HAL_NVIC_ClearPendingIRQ
 810              		.syntax unified
 811              		.thumb
 812              		.thumb_func
ARM GAS  /tmp/ccMY5QHu.s 			page 72


 814              	HAL_NVIC_ClearPendingIRQ:
 815              	.LVL60:
 816              	.LFB75:
 411:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 412:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /**
 413:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @brief  Clears the pending bit of an external interrupt.
 414:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @param  IRQn External interrupt number.
 415:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
 416:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
 417:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @retval None
 418:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   */
 419:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 420:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** {
 817              		.loc 1 420 1 is_stmt 1 view -0
 818              		.cfi_startproc
 819              		@ args = 0, pretend = 0, frame = 0
 820              		@ frame_needed = 0, uses_anonymous_args = 0
 821              		@ link register save eliminated.
 421:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   /* Check the parameters */
 422:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
 822              		.loc 1 422 3 view .LVU224
 423:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 424:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   /* Clear pending interrupt */
 425:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   NVIC_ClearPendingIRQ(IRQn);
 823              		.loc 1 425 3 view .LVU225
 824              	.LBB98:
 825              	.LBI98:
1600:Drivers/CMSIS/Include/core_cm3.h **** {
 826              		.loc 2 1600 22 view .LVU226
 827              	.LBB99:
1602:Drivers/CMSIS/Include/core_cm3.h ****   {
 828              		.loc 2 1602 3 view .LVU227
1602:Drivers/CMSIS/Include/core_cm3.h ****   {
 829              		.loc 2 1602 6 is_stmt 0 view .LVU228
 830 0000 0028     		cmp	r0, #0
 831              	.LVL61:
1602:Drivers/CMSIS/Include/core_cm3.h ****   {
 832              		.loc 2 1602 6 view .LVU229
 833 0002 08DB     		blt	.L49
1604:Drivers/CMSIS/Include/core_cm3.h ****   }
 834              		.loc 2 1604 5 is_stmt 1 view .LVU230
1604:Drivers/CMSIS/Include/core_cm3.h ****   }
 835              		.loc 2 1604 81 is_stmt 0 view .LVU231
 836 0004 00F01F02 		and	r2, r0, #31
1604:Drivers/CMSIS/Include/core_cm3.h ****   }
 837              		.loc 2 1604 34 view .LVU232
 838 0008 4009     		lsrs	r0, r0, #5
1604:Drivers/CMSIS/Include/core_cm3.h ****   }
 839              		.loc 2 1604 45 view .LVU233
 840 000a 0123     		movs	r3, #1
 841 000c 9340     		lsls	r3, r3, r2
1604:Drivers/CMSIS/Include/core_cm3.h ****   }
 842              		.loc 2 1604 43 view .LVU234
 843 000e 6030     		adds	r0, r0, #96
 844 0010 014A     		ldr	r2, .L51
 845 0012 42F82030 		str	r3, [r2, r0, lsl #2]
 846              	.LVL62:
ARM GAS  /tmp/ccMY5QHu.s 			page 73


 847              	.L49:
1604:Drivers/CMSIS/Include/core_cm3.h ****   }
 848              		.loc 2 1604 43 view .LVU235
 849              	.LBE99:
 850              	.LBE98:
 426:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** }
 851              		.loc 1 426 1 view .LVU236
 852 0016 7047     		bx	lr
 853              	.L52:
 854              		.align	2
 855              	.L51:
 856 0018 00E100E0 		.word	-536813312
 857              		.cfi_endproc
 858              	.LFE75:
 860              		.section	.text.HAL_NVIC_GetActive,"ax",%progbits
 861              		.align	1
 862              		.global	HAL_NVIC_GetActive
 863              		.syntax unified
 864              		.thumb
 865              		.thumb_func
 867              	HAL_NVIC_GetActive:
 868              	.LVL63:
 869              	.LFB76:
 427:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 428:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /**
 429:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
 430:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @param IRQn External interrupt number
 431:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
 432:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
 433:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @retval status: - 0  Interrupt status is not pending.
 434:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *                 - 1  Interrupt status is pending.
 435:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   */
 436:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
 437:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** {
 870              		.loc 1 437 1 is_stmt 1 view -0
 871              		.cfi_startproc
 872              		@ args = 0, pretend = 0, frame = 0
 873              		@ frame_needed = 0, uses_anonymous_args = 0
 874              		@ link register save eliminated.
 438:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   /* Check the parameters */
 439:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
 875              		.loc 1 439 3 view .LVU238
 440:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 441:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   /* Return 1 if active else 0 */
 442:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   return NVIC_GetActive(IRQn);
 876              		.loc 1 442 3 view .LVU239
 877              	.LBB100:
 878              	.LBI100:
1617:Drivers/CMSIS/Include/core_cm3.h **** {
 879              		.loc 2 1617 26 view .LVU240
 880              	.LBB101:
1619:Drivers/CMSIS/Include/core_cm3.h ****   {
 881              		.loc 2 1619 3 view .LVU241
1619:Drivers/CMSIS/Include/core_cm3.h ****   {
 882              		.loc 2 1619 6 is_stmt 0 view .LVU242
 883 0000 0028     		cmp	r0, #0
 884              	.LVL64:
ARM GAS  /tmp/ccMY5QHu.s 			page 74


1619:Drivers/CMSIS/Include/core_cm3.h ****   {
 885              		.loc 2 1619 6 view .LVU243
 886 0002 0BDB     		blt	.L55
1621:Drivers/CMSIS/Include/core_cm3.h ****   }
 887              		.loc 2 1621 5 is_stmt 1 view .LVU244
1621:Drivers/CMSIS/Include/core_cm3.h ****   }
 888              		.loc 2 1621 54 is_stmt 0 view .LVU245
 889 0004 4309     		lsrs	r3, r0, #5
1621:Drivers/CMSIS/Include/core_cm3.h ****   }
 890              		.loc 2 1621 35 view .LVU246
 891 0006 8033     		adds	r3, r3, #128
 892 0008 054A     		ldr	r2, .L56
 893 000a 52F82330 		ldr	r3, [r2, r3, lsl #2]
1621:Drivers/CMSIS/Include/core_cm3.h ****   }
 894              		.loc 2 1621 91 view .LVU247
 895 000e 00F01F00 		and	r0, r0, #31
1621:Drivers/CMSIS/Include/core_cm3.h ****   }
 896              		.loc 2 1621 103 view .LVU248
 897 0012 23FA00F0 		lsr	r0, r3, r0
1621:Drivers/CMSIS/Include/core_cm3.h ****   }
 898              		.loc 2 1621 12 view .LVU249
 899 0016 00F00100 		and	r0, r0, #1
 900 001a 7047     		bx	lr
 901              	.L55:
1625:Drivers/CMSIS/Include/core_cm3.h ****   }
 902              		.loc 2 1625 11 view .LVU250
 903 001c 0020     		movs	r0, #0
 904              	.LVL65:
1625:Drivers/CMSIS/Include/core_cm3.h ****   }
 905              		.loc 2 1625 11 view .LVU251
 906              	.LBE101:
 907              	.LBE100:
 443:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** }
 908              		.loc 1 443 1 view .LVU252
 909 001e 7047     		bx	lr
 910              	.L57:
 911              		.align	2
 912              	.L56:
 913 0020 00E100E0 		.word	-536813312
 914              		.cfi_endproc
 915              	.LFE76:
 917              		.section	.text.HAL_SYSTICK_CLKSourceConfig,"ax",%progbits
 918              		.align	1
 919              		.global	HAL_SYSTICK_CLKSourceConfig
 920              		.syntax unified
 921              		.thumb
 922              		.thumb_func
 924              	HAL_SYSTICK_CLKSourceConfig:
 925              	.LVL66:
 926              	.LFB77:
 444:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 445:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /**
 446:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @brief  Configures the SysTick clock source.
 447:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @param  CLKSource: specifies the SysTick clock source.
 448:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *         This parameter can be one of the following values:
 449:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock 
 450:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
ARM GAS  /tmp/ccMY5QHu.s 			page 75


 451:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @retval None
 452:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   */
 453:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
 454:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** {
 927              		.loc 1 454 1 is_stmt 1 view -0
 928              		.cfi_startproc
 929              		@ args = 0, pretend = 0, frame = 0
 930              		@ frame_needed = 0, uses_anonymous_args = 0
 931              		@ link register save eliminated.
 455:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   /* Check the parameters */
 456:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
 932              		.loc 1 456 3 view .LVU254
 457:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
 933              		.loc 1 457 3 view .LVU255
 934              		.loc 1 457 6 is_stmt 0 view .LVU256
 935 0000 0428     		cmp	r0, #4
 936 0002 06D0     		beq	.L61
 458:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   {
 459:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
 460:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   }
 461:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   else
 462:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   {
 463:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****     SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
 937              		.loc 1 463 5 is_stmt 1 view .LVU257
 938              		.loc 1 463 19 is_stmt 0 view .LVU258
 939 0004 4FF0E022 		mov	r2, #-536813568
 940 0008 1369     		ldr	r3, [r2, #16]
 941 000a 23F00403 		bic	r3, r3, #4
 942 000e 1361     		str	r3, [r2, #16]
 464:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   }
 465:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** }
 943              		.loc 1 465 1 view .LVU259
 944 0010 7047     		bx	lr
 945              	.L61:
 459:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   }
 946              		.loc 1 459 5 is_stmt 1 view .LVU260
 459:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   }
 947              		.loc 1 459 19 is_stmt 0 view .LVU261
 948 0012 4FF0E022 		mov	r2, #-536813568
 949 0016 1369     		ldr	r3, [r2, #16]
 950 0018 43F00403 		orr	r3, r3, #4
 951 001c 1361     		str	r3, [r2, #16]
 952 001e 7047     		bx	lr
 953              		.cfi_endproc
 954              	.LFE77:
 956              		.section	.text.HAL_SYSTICK_Callback,"ax",%progbits
 957              		.align	1
 958              		.weak	HAL_SYSTICK_Callback
 959              		.syntax unified
 960              		.thumb
 961              		.thumb_func
 963              	HAL_SYSTICK_Callback:
 964              	.LFB79:
 466:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 467:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /**
 468:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @brief  This function handles SYSTICK interrupt request.
 469:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @retval None
ARM GAS  /tmp/ccMY5QHu.s 			page 76


 470:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   */
 471:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** void HAL_SYSTICK_IRQHandler(void)
 472:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** {
 473:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   HAL_SYSTICK_Callback();
 474:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** }
 475:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 476:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /**
 477:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @brief  SYSTICK callback.
 478:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   * @retval None
 479:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   */
 480:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** __weak void HAL_SYSTICK_Callback(void)
 481:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** {
 965              		.loc 1 481 1 is_stmt 1 view -0
 966              		.cfi_startproc
 967              		@ args = 0, pretend = 0, frame = 0
 968              		@ frame_needed = 0, uses_anonymous_args = 0
 969              		@ link register save eliminated.
 482:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   /* NOTE : This function Should not be modified, when the callback is needed,
 483:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****             the HAL_SYSTICK_Callback could be implemented in the user file
 484:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****    */
 485:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** }
 970              		.loc 1 485 1 view .LVU263
 971 0000 7047     		bx	lr
 972              		.cfi_endproc
 973              	.LFE79:
 975              		.section	.text.HAL_SYSTICK_IRQHandler,"ax",%progbits
 976              		.align	1
 977              		.global	HAL_SYSTICK_IRQHandler
 978              		.syntax unified
 979              		.thumb
 980              		.thumb_func
 982              	HAL_SYSTICK_IRQHandler:
 983              	.LFB78:
 472:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ****   HAL_SYSTICK_Callback();
 984              		.loc 1 472 1 view -0
 985              		.cfi_startproc
 986              		@ args = 0, pretend = 0, frame = 0
 987              		@ frame_needed = 0, uses_anonymous_args = 0
 988 0000 08B5     		push	{r3, lr}
 989              	.LCFI2:
 990              		.cfi_def_cfa_offset 8
 991              		.cfi_offset 3, -8
 992              		.cfi_offset 14, -4
 473:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** }
 993              		.loc 1 473 3 view .LVU265
 994 0002 FFF7FEFF 		bl	HAL_SYSTICK_Callback
 995              	.LVL67:
 474:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** 
 996              		.loc 1 474 1 is_stmt 0 view .LVU266
 997 0006 08BD     		pop	{r3, pc}
 998              		.cfi_endproc
 999              	.LFE78:
 1001              		.text
 1002              	.Letext0:
 1003              		.file 4 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h"
 1004              		.file 5 "/opt/gcc-arm/arm-none-eabi/include/machine/_default_types.h"
 1005              		.file 6 "/opt/gcc-arm/arm-none-eabi/include/sys/_stdint.h"
ARM GAS  /tmp/ccMY5QHu.s 			page 77


ARM GAS  /tmp/ccMY5QHu.s 			page 78


DEFINED SYMBOLS
                            *ABS*:0000000000000000 stm32f1xx_hal_cortex.c
     /tmp/ccMY5QHu.s:18     .text.HAL_NVIC_SetPriorityGrouping:0000000000000000 $t
     /tmp/ccMY5QHu.s:24     .text.HAL_NVIC_SetPriorityGrouping:0000000000000000 HAL_NVIC_SetPriorityGrouping
     /tmp/ccMY5QHu.s:80     .text.HAL_NVIC_SetPriorityGrouping:0000000000000020 $d
     /tmp/ccMY5QHu.s:85     .text.HAL_NVIC_SetPriority:0000000000000000 $t
     /tmp/ccMY5QHu.s:91     .text.HAL_NVIC_SetPriority:0000000000000000 HAL_NVIC_SetPriority
     /tmp/ccMY5QHu.s:234    .text.HAL_NVIC_SetPriority:0000000000000068 $d
     /tmp/ccMY5QHu.s:240    .text.HAL_NVIC_EnableIRQ:0000000000000000 $t
     /tmp/ccMY5QHu.s:246    .text.HAL_NVIC_EnableIRQ:0000000000000000 HAL_NVIC_EnableIRQ
     /tmp/ccMY5QHu.s:287    .text.HAL_NVIC_EnableIRQ:0000000000000018 $d
     /tmp/ccMY5QHu.s:292    .text.HAL_NVIC_DisableIRQ:0000000000000000 $t
     /tmp/ccMY5QHu.s:298    .text.HAL_NVIC_DisableIRQ:0000000000000000 HAL_NVIC_DisableIRQ
     /tmp/ccMY5QHu.s:369    .text.HAL_NVIC_DisableIRQ:0000000000000020 $d
     /tmp/ccMY5QHu.s:374    .text.HAL_NVIC_SystemReset:0000000000000000 $t
     /tmp/ccMY5QHu.s:380    .text.HAL_NVIC_SystemReset:0000000000000000 HAL_NVIC_SystemReset
     /tmp/ccMY5QHu.s:446    .text.HAL_NVIC_SystemReset:000000000000001c $d
     /tmp/ccMY5QHu.s:454    .text.HAL_SYSTICK_Config:0000000000000000 $t
     /tmp/ccMY5QHu.s:460    .text.HAL_SYSTICK_Config:0000000000000000 HAL_SYSTICK_Config
     /tmp/ccMY5QHu.s:525    .text.HAL_SYSTICK_Config:0000000000000024 $d
     /tmp/ccMY5QHu.s:530    .text.HAL_NVIC_GetPriorityGrouping:0000000000000000 $t
     /tmp/ccMY5QHu.s:536    .text.HAL_NVIC_GetPriorityGrouping:0000000000000000 HAL_NVIC_GetPriorityGrouping
     /tmp/ccMY5QHu.s:560    .text.HAL_NVIC_GetPriorityGrouping:000000000000000c $d
     /tmp/ccMY5QHu.s:565    .text.HAL_NVIC_GetPriority:0000000000000000 $t
     /tmp/ccMY5QHu.s:571    .text.HAL_NVIC_GetPriority:0000000000000000 HAL_NVIC_GetPriority
     /tmp/ccMY5QHu.s:691    .text.HAL_NVIC_GetPriority:000000000000005c $d
     /tmp/ccMY5QHu.s:698    .text.HAL_NVIC_SetPendingIRQ:0000000000000000 $t
     /tmp/ccMY5QHu.s:704    .text.HAL_NVIC_SetPendingIRQ:0000000000000000 HAL_NVIC_SetPendingIRQ
     /tmp/ccMY5QHu.s:746    .text.HAL_NVIC_SetPendingIRQ:0000000000000018 $d
     /tmp/ccMY5QHu.s:751    .text.HAL_NVIC_GetPendingIRQ:0000000000000000 $t
     /tmp/ccMY5QHu.s:757    .text.HAL_NVIC_GetPendingIRQ:0000000000000000 HAL_NVIC_GetPendingIRQ
     /tmp/ccMY5QHu.s:803    .text.HAL_NVIC_GetPendingIRQ:0000000000000020 $d
     /tmp/ccMY5QHu.s:808    .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 $t
     /tmp/ccMY5QHu.s:814    .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 HAL_NVIC_ClearPendingIRQ
     /tmp/ccMY5QHu.s:856    .text.HAL_NVIC_ClearPendingIRQ:0000000000000018 $d
     /tmp/ccMY5QHu.s:861    .text.HAL_NVIC_GetActive:0000000000000000 $t
     /tmp/ccMY5QHu.s:867    .text.HAL_NVIC_GetActive:0000000000000000 HAL_NVIC_GetActive
     /tmp/ccMY5QHu.s:913    .text.HAL_NVIC_GetActive:0000000000000020 $d
     /tmp/ccMY5QHu.s:918    .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 $t
     /tmp/ccMY5QHu.s:924    .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 HAL_SYSTICK_CLKSourceConfig
     /tmp/ccMY5QHu.s:957    .text.HAL_SYSTICK_Callback:0000000000000000 $t
     /tmp/ccMY5QHu.s:963    .text.HAL_SYSTICK_Callback:0000000000000000 HAL_SYSTICK_Callback
     /tmp/ccMY5QHu.s:976    .text.HAL_SYSTICK_IRQHandler:0000000000000000 $t
     /tmp/ccMY5QHu.s:982    .text.HAL_SYSTICK_IRQHandler:0000000000000000 HAL_SYSTICK_IRQHandler

NO UNDEFINED SYMBOLS