stm32f1xx_hal_msp.lst 9.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205
  1. ARM GAS /tmp/cceKT6G3.s page 1
  2. 1 .cpu cortex-m3
  3. 2 .arch armv7-m
  4. 3 .fpu softvfp
  5. 4 .eabi_attribute 20, 1
  6. 5 .eabi_attribute 21, 1
  7. 6 .eabi_attribute 23, 3
  8. 7 .eabi_attribute 24, 1
  9. 8 .eabi_attribute 25, 1
  10. 9 .eabi_attribute 26, 1
  11. 10 .eabi_attribute 30, 1
  12. 11 .eabi_attribute 34, 1
  13. 12 .eabi_attribute 18, 4
  14. 13 .file "stm32f1xx_hal_msp.c"
  15. 14 .text
  16. 15 .Ltext0:
  17. 16 .cfi_sections .debug_frame
  18. 17 .section .text.HAL_MspInit,"ax",%progbits
  19. 18 .align 1
  20. 19 .global HAL_MspInit
  21. 20 .syntax unified
  22. 21 .thumb
  23. 22 .thumb_func
  24. 24 HAL_MspInit:
  25. 25 .LFB652:
  26. 26 .file 1 "Core/Src/stm32f1xx_hal_msp.c"
  27. 1:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN Header */
  28. 2:Core/Src/stm32f1xx_hal_msp.c **** /**
  29. 3:Core/Src/stm32f1xx_hal_msp.c **** ******************************************************************************
  30. 4:Core/Src/stm32f1xx_hal_msp.c **** * @file stm32f1xx_hal_msp.c
  31. 5:Core/Src/stm32f1xx_hal_msp.c **** * @brief This file provides code for the MSP Initialization
  32. 6:Core/Src/stm32f1xx_hal_msp.c **** * and de-Initialization codes.
  33. 7:Core/Src/stm32f1xx_hal_msp.c **** ******************************************************************************
  34. 8:Core/Src/stm32f1xx_hal_msp.c **** * @attention
  35. 9:Core/Src/stm32f1xx_hal_msp.c **** *
  36. 10:Core/Src/stm32f1xx_hal_msp.c **** * Copyright (c) 2024 STMicroelectronics.
  37. 11:Core/Src/stm32f1xx_hal_msp.c **** * All rights reserved.
  38. 12:Core/Src/stm32f1xx_hal_msp.c **** *
  39. 13:Core/Src/stm32f1xx_hal_msp.c **** * This software is licensed under terms that can be found in the LICENSE file
  40. 14:Core/Src/stm32f1xx_hal_msp.c **** * in the root directory of this software component.
  41. 15:Core/Src/stm32f1xx_hal_msp.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
  42. 16:Core/Src/stm32f1xx_hal_msp.c **** *
  43. 17:Core/Src/stm32f1xx_hal_msp.c **** ******************************************************************************
  44. 18:Core/Src/stm32f1xx_hal_msp.c **** */
  45. 19:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END Header */
  46. 20:Core/Src/stm32f1xx_hal_msp.c ****
  47. 21:Core/Src/stm32f1xx_hal_msp.c **** /* Includes ------------------------------------------------------------------*/
  48. 22:Core/Src/stm32f1xx_hal_msp.c **** #include "main.h"
  49. 23:Core/Src/stm32f1xx_hal_msp.c ****
  50. 24:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN Includes */
  51. 25:Core/Src/stm32f1xx_hal_msp.c ****
  52. 26:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END Includes */
  53. 27:Core/Src/stm32f1xx_hal_msp.c ****
  54. 28:Core/Src/stm32f1xx_hal_msp.c **** /* Private typedef -----------------------------------------------------------*/
  55. 29:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN TD */
  56. 30:Core/Src/stm32f1xx_hal_msp.c ****
  57. 31:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END TD */
  58. 32:Core/Src/stm32f1xx_hal_msp.c ****
  59. ARM GAS /tmp/cceKT6G3.s page 2
  60. 33:Core/Src/stm32f1xx_hal_msp.c **** /* Private define ------------------------------------------------------------*/
  61. 34:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN Define */
  62. 35:Core/Src/stm32f1xx_hal_msp.c ****
  63. 36:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END Define */
  64. 37:Core/Src/stm32f1xx_hal_msp.c ****
  65. 38:Core/Src/stm32f1xx_hal_msp.c **** /* Private macro -------------------------------------------------------------*/
  66. 39:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN Macro */
  67. 40:Core/Src/stm32f1xx_hal_msp.c ****
  68. 41:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END Macro */
  69. 42:Core/Src/stm32f1xx_hal_msp.c ****
  70. 43:Core/Src/stm32f1xx_hal_msp.c **** /* Private variables ---------------------------------------------------------*/
  71. 44:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN PV */
  72. 45:Core/Src/stm32f1xx_hal_msp.c ****
  73. 46:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END PV */
  74. 47:Core/Src/stm32f1xx_hal_msp.c ****
  75. 48:Core/Src/stm32f1xx_hal_msp.c **** /* Private function prototypes -----------------------------------------------*/
  76. 49:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN PFP */
  77. 50:Core/Src/stm32f1xx_hal_msp.c ****
  78. 51:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END PFP */
  79. 52:Core/Src/stm32f1xx_hal_msp.c ****
  80. 53:Core/Src/stm32f1xx_hal_msp.c **** /* External functions --------------------------------------------------------*/
  81. 54:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN ExternalFunctions */
  82. 55:Core/Src/stm32f1xx_hal_msp.c ****
  83. 56:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END ExternalFunctions */
  84. 57:Core/Src/stm32f1xx_hal_msp.c ****
  85. 58:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN 0 */
  86. 59:Core/Src/stm32f1xx_hal_msp.c ****
  87. 60:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END 0 */
  88. 61:Core/Src/stm32f1xx_hal_msp.c **** /**
  89. 62:Core/Src/stm32f1xx_hal_msp.c **** * Initializes the Global MSP.
  90. 63:Core/Src/stm32f1xx_hal_msp.c **** */
  91. 64:Core/Src/stm32f1xx_hal_msp.c **** void HAL_MspInit(void)
  92. 65:Core/Src/stm32f1xx_hal_msp.c **** {
  93. 27 .loc 1 65 1 view -0
  94. 28 .cfi_startproc
  95. 29 @ args = 0, pretend = 0, frame = 8
  96. 30 @ frame_needed = 0, uses_anonymous_args = 0
  97. 31 @ link register save eliminated.
  98. 32 0000 82B0 sub sp, sp, #8
  99. 33 .LCFI0:
  100. 34 .cfi_def_cfa_offset 8
  101. 66:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN MspInit 0 */
  102. 67:Core/Src/stm32f1xx_hal_msp.c ****
  103. 68:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END MspInit 0 */
  104. 69:Core/Src/stm32f1xx_hal_msp.c ****
  105. 70:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_AFIO_CLK_ENABLE();
  106. 35 .loc 1 70 3 view .LVU1
  107. 36 .LBB2:
  108. 37 .loc 1 70 3 view .LVU2
  109. 38 .loc 1 70 3 view .LVU3
  110. 39 0002 0E4B ldr r3, .L3
  111. 40 0004 9A69 ldr r2, [r3, #24]
  112. 41 0006 42F00102 orr r2, r2, #1
  113. 42 000a 9A61 str r2, [r3, #24]
  114. 43 .loc 1 70 3 view .LVU4
  115. 44 000c 9A69 ldr r2, [r3, #24]
  116. 45 000e 02F00102 and r2, r2, #1
  117. ARM GAS /tmp/cceKT6G3.s page 3
  118. 46 0012 0092 str r2, [sp]
  119. 47 .loc 1 70 3 view .LVU5
  120. 48 0014 009A ldr r2, [sp]
  121. 49 .LBE2:
  122. 50 .loc 1 70 3 view .LVU6
  123. 71:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_PWR_CLK_ENABLE();
  124. 51 .loc 1 71 3 view .LVU7
  125. 52 .LBB3:
  126. 53 .loc 1 71 3 view .LVU8
  127. 54 .loc 1 71 3 view .LVU9
  128. 55 0016 DA69 ldr r2, [r3, #28]
  129. 56 0018 42F08052 orr r2, r2, #268435456
  130. 57 001c DA61 str r2, [r3, #28]
  131. 58 .loc 1 71 3 view .LVU10
  132. 59 001e DB69 ldr r3, [r3, #28]
  133. 60 0020 03F08053 and r3, r3, #268435456
  134. 61 0024 0193 str r3, [sp, #4]
  135. 62 .loc 1 71 3 view .LVU11
  136. 63 0026 019B ldr r3, [sp, #4]
  137. 64 .LBE3:
  138. 65 .loc 1 71 3 view .LVU12
  139. 72:Core/Src/stm32f1xx_hal_msp.c ****
  140. 73:Core/Src/stm32f1xx_hal_msp.c **** /* System interrupt init*/
  141. 74:Core/Src/stm32f1xx_hal_msp.c ****
  142. 75:Core/Src/stm32f1xx_hal_msp.c **** /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
  143. 76:Core/Src/stm32f1xx_hal_msp.c **** */
  144. 77:Core/Src/stm32f1xx_hal_msp.c **** __HAL_AFIO_REMAP_SWJ_NOJTAG();
  145. 66 .loc 1 77 3 view .LVU13
  146. 67 .LBB4:
  147. 68 .loc 1 77 3 view .LVU14
  148. 69 0028 054A ldr r2, .L3+4
  149. 70 002a 5368 ldr r3, [r2, #4]
  150. 71 .LVL0:
  151. 72 .loc 1 77 3 view .LVU15
  152. 73 002c 23F0E063 bic r3, r3, #117440512
  153. 74 .LVL1:
  154. 75 .loc 1 77 3 view .LVU16
  155. 76 0030 43F00073 orr r3, r3, #33554432
  156. 77 .LVL2:
  157. 78 .loc 1 77 3 view .LVU17
  158. 79 0034 5360 str r3, [r2, #4]
  159. 80 .LBE4:
  160. 81 .loc 1 77 3 view .LVU18
  161. 78:Core/Src/stm32f1xx_hal_msp.c ****
  162. 79:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN MspInit 1 */
  163. 80:Core/Src/stm32f1xx_hal_msp.c ****
  164. 81:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END MspInit 1 */
  165. 82:Core/Src/stm32f1xx_hal_msp.c **** }
  166. 82 .loc 1 82 1 is_stmt 0 view .LVU19
  167. 83 0036 02B0 add sp, sp, #8
  168. 84 .LCFI1:
  169. 85 .cfi_def_cfa_offset 0
  170. 86 @ sp needed
  171. 87 0038 7047 bx lr
  172. 88 .L4:
  173. 89 003a 00BF .align 2
  174. 90 .L3:
  175. ARM GAS /tmp/cceKT6G3.s page 4
  176. 91 003c 00100240 .word 1073876992
  177. 92 0040 00000140 .word 1073807360
  178. 93 .cfi_endproc
  179. 94 .LFE652:
  180. 96 .text
  181. 97 .Letext0:
  182. 98 .file 2 "/opt/gcc-arm/arm-none-eabi/include/machine/_default_types.h"
  183. 99 .file 3 "/opt/gcc-arm/arm-none-eabi/include/sys/_stdint.h"
  184. 100 .file 4 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h"
  185. 101 .file 5 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h"
  186. 102 .file 6 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h"
  187. ARM GAS /tmp/cceKT6G3.s page 5
  188. DEFINED SYMBOLS
  189. *ABS*:0000000000000000 stm32f1xx_hal_msp.c
  190. /tmp/cceKT6G3.s:18 .text.HAL_MspInit:0000000000000000 $t
  191. /tmp/cceKT6G3.s:24 .text.HAL_MspInit:0000000000000000 HAL_MspInit
  192. /tmp/cceKT6G3.s:91 .text.HAL_MspInit:000000000000003c $d
  193. NO UNDEFINED SYMBOLS