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@@ -0,0 +1,110 @@
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+Protel Design System Design Rule Check
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+PCB File : C:\Users\vladi\Nextcloud\ÍÖÔÌ\06. Òåõíè÷åñêàÿ äîêóìåíòàöèÿ\02. Ýëåêòðîíèêà è ýëåêòðèêà\cap_test_unit\cap_test_unit\PCB1.PcbDoc
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+Date : 01.07.2024
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+Time : 10:57:13
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+
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+Processing Rule : Clearance Constraint (Gap=0.254mm) (All),(All)
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+Rule Violations :0
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+
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+Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
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+Rule Violations :0
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+
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+Processing Rule : Un-Routed Net Constraint ( (All) )
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+Rule Violations :0
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+
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+Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
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+Rule Violations :0
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+
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+Processing Rule : Width Constraint (Min=0.254mm) (Max=2.54mm) (Preferred=0.254mm) (All)
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+Rule Violations :0
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+
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+Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
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+Rule Violations :0
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+
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+Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
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+Rule Violations :0
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+
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+Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
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+Rule Violations :0
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+
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+Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
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+Rule Violations :0
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+
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+Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.007mm < 0.254mm) Between Arc (159.766mm,28.448mm) on Top Overlay And Pad XP2-2(160.655mm,27.94mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.007mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C1-1(165.608mm,36.576mm) on Top Layer And Track (166.116mm,35.814mm)(166.624mm,35.814mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C1-1(165.608mm,36.576mm) on Top Layer And Track (166.116mm,37.338mm)(166.624mm,37.338mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C1-2(167.196mm,36.576mm) on Top Layer And Track (166.116mm,35.814mm)(166.624mm,35.814mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C1-2(167.196mm,36.576mm) on Top Layer And Track (166.116mm,37.338mm)(166.624mm,37.338mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C2-1(162.243mm,32.004mm) on Top Layer And Track (162.75mm,31.242mm)(163.258mm,31.242mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C2-1(162.243mm,32.004mm) on Top Layer And Track (162.75mm,31.242mm)(163.258mm,31.242mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C2-1(162.243mm,32.004mm) on Top Layer And Track (162.75mm,32.766mm)(163.258mm,32.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C2-1(162.243mm,32.004mm) on Top Layer And Track (162.814mm,32.766mm)(163.322mm,32.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C2-2(163.83mm,32.004mm) on Top Layer And Track (162.75mm,31.242mm)(163.258mm,31.242mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C2-2(163.83mm,32.004mm) on Top Layer And Track (162.75mm,31.242mm)(163.258mm,31.242mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C2-2(163.83mm,32.004mm) on Top Layer And Track (162.75mm,32.766mm)(163.258mm,32.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C2-2(163.83mm,32.004mm) on Top Layer And Track (162.814mm,32.766mm)(163.322mm,32.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C3-1(162.243mm,30.48mm) on Top Layer And Track (162.75mm,29.718mm)(163.258mm,29.718mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C3-1(162.243mm,30.48mm) on Top Layer And Track (162.75mm,31.242mm)(163.258mm,31.242mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C3-1(162.243mm,30.48mm) on Top Layer And Track (162.75mm,31.242mm)(163.258mm,31.242mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C3-2(163.83mm,30.48mm) on Top Layer And Track (162.75mm,29.718mm)(163.258mm,29.718mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C3-2(163.83mm,30.48mm) on Top Layer And Track (162.75mm,31.242mm)(163.258mm,31.242mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C3-2(163.83mm,30.48mm) on Top Layer And Track (162.75mm,31.242mm)(163.258mm,31.242mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C4-1(175.832mm,32.766mm) on Top Layer And Track (174.815mm,32.004mm)(175.323mm,32.004mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C4-1(175.832mm,32.766mm) on Top Layer And Track (174.815mm,33.528mm)(175.323mm,33.528mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C4-1(175.832mm,32.766mm) on Top Layer And Track (174.815mm,33.528mm)(175.323mm,33.528mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C4-2(174.244mm,32.766mm) on Top Layer And Track (174.815mm,32.004mm)(175.323mm,32.004mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C4-2(174.244mm,32.766mm) on Top Layer And Track (174.815mm,33.528mm)(175.323mm,33.528mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C4-2(174.244mm,32.766mm) on Top Layer And Track (174.815mm,33.528mm)(175.323mm,33.528mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C5-1(175.832mm,34.29mm) on Top Layer And Track (174.815mm,33.528mm)(175.323mm,33.528mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C5-1(175.832mm,34.29mm) on Top Layer And Track (174.815mm,33.528mm)(175.323mm,33.528mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C5-1(175.832mm,34.29mm) on Top Layer And Track (174.815mm,35.052mm)(175.323mm,35.052mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C5-2(174.244mm,34.29mm) on Top Layer And Track (174.815mm,33.528mm)(175.323mm,33.528mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C5-2(174.244mm,34.29mm) on Top Layer And Track (174.815mm,33.528mm)(175.323mm,33.528mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C5-2(174.244mm,34.29mm) on Top Layer And Track (174.815mm,35.052mm)(175.323mm,35.052mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-1(171.622mm,30.607mm) on Top Layer And Track (170.51mm,30.062mm)(170.51mm,34.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-1(171.622mm,30.607mm) on Top Layer And Track (170.86mm,29.932mm)(172.385mm,29.932mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-2(171.622mm,31.877mm) on Top Layer And Track (170.51mm,30.062mm)(170.51mm,34.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-3(171.622mm,33.147mm) on Top Layer And Track (170.51mm,30.062mm)(170.51mm,34.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-4(171.622mm,34.417mm) on Top Layer And Track (170.51mm,30.062mm)(170.51mm,34.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-5(166.198mm,34.417mm) on Top Layer And Track (167.31mm,30.062mm)(167.31mm,34.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-6(166.198mm,33.147mm) on Top Layer And Track (167.31mm,30.062mm)(167.31mm,34.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-7(166.198mm,31.877mm) on Top Layer And Track (167.31mm,30.062mm)(167.31mm,34.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-8(166.198mm,30.607mm) on Top Layer And Track (167.31mm,30.062mm)(167.31mm,34.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R1-1(175.768mm,30.226mm) on Top Layer And Track (174.752mm,29.464mm)(175.26mm,29.464mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R1-1(175.768mm,30.226mm) on Top Layer And Track (174.752mm,30.988mm)(175.26mm,30.988mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R1-2(174.18mm,30.226mm) on Top Layer And Track (174.752mm,29.464mm)(175.26mm,29.464mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R1-2(174.18mm,30.226mm) on Top Layer And Track (174.752mm,30.988mm)(175.26mm,30.988mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R2-1(171.196mm,36.576mm) on Top Layer And Track (171.704mm,35.814mm)(172.212mm,35.814mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R2-1(171.196mm,36.576mm) on Top Layer And Track (171.704mm,37.338mm)(172.212mm,37.338mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R2-2(172.784mm,36.576mm) on Top Layer And Track (171.704mm,35.814mm)(172.212mm,35.814mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R2-2(172.784mm,36.576mm) on Top Layer And Track (171.704mm,37.338mm)(172.212mm,37.338mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R3-1(163.83mm,35.052mm) on Top Layer And Track (162.814mm,34.29mm)(163.322mm,34.29mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R3-1(163.83mm,35.052mm) on Top Layer And Track (162.814mm,34.29mm)(163.322mm,34.29mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R3-1(163.83mm,35.052mm) on Top Layer And Track (162.814mm,35.814mm)(163.322mm,35.814mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R3-2(162.243mm,35.052mm) on Top Layer And Track (162.814mm,34.29mm)(163.322mm,34.29mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R3-2(162.243mm,35.052mm) on Top Layer And Track (162.814mm,34.29mm)(163.322mm,34.29mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R3-2(162.243mm,35.052mm) on Top Layer And Track (162.814mm,35.814mm)(163.322mm,35.814mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R4-1(163.83mm,33.528mm) on Top Layer And Track (162.75mm,32.766mm)(163.258mm,32.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R4-1(163.83mm,33.528mm) on Top Layer And Track (162.814mm,32.766mm)(163.322mm,32.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R4-1(163.83mm,33.528mm) on Top Layer And Track (162.814mm,34.29mm)(163.322mm,34.29mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R4-1(163.83mm,33.528mm) on Top Layer And Track (162.814mm,34.29mm)(163.322mm,34.29mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R4-2(162.243mm,33.528mm) on Top Layer And Track (162.75mm,32.766mm)(163.258mm,32.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R4-2(162.243mm,33.528mm) on Top Layer And Track (162.814mm,32.766mm)(163.322mm,32.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R4-2(162.243mm,33.528mm) on Top Layer And Track (162.814mm,34.29mm)(163.322mm,34.29mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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+ Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R4-2(162.243mm,33.528mm) on Top Layer And Track (162.814mm,34.29mm)(163.322mm,34.29mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
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+Rule Violations :62
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+
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+Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All)
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+Rule Violations :0
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+
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+Processing Rule : Net Antennae (Tolerance=0mm) (All)
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+Rule Violations :0
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+
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+Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
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+Rule Violations :0
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+
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+
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+Violations Detected : 62
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+Waived Violations : 0
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+Time Elapsed : 00:00:01
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vladik411413