cap_plate added, вырезы под винты сделал, лого, шелкографию добавил

cap_plate/Project Logs for cap_plate/PCB2 PCB ECO 01.07.2024 13-11-34.LOG

@@ -0,0 +1,35 @@
+Added Component: Designator=C?(K50-98-63V-1500uF)
+Added Component: Designator=C?(K50-104-63V-2200uF)
+Added Component: Designator=R?(SQP 5W2)
+Added Component: Designator=R?(SQP 5W2)
+Added Component: Designator=XP?(DG3005002P1200AH)
+Add component (AddParameter): Name = "Arrow Part Number"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Arrow Price/Stock"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Datasheet Link"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Height"; Value = "12.6mm"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Manufacturer_Name"; Value = "Degson"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Manufacturer_Part_Number"; Value = "DG300-5.0-02P-12-00A(H)"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Mouser Part Number"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Mouser Price/Stock"; Value = ""; VariantName = "[No Variations]"
+Added Component: Designator=XP?(DG3005002P1200AH)
+Add component (AddParameter): Name = "Arrow Part Number"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Arrow Price/Stock"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Datasheet Link"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Height"; Value = "12.6mm"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Manufacturer_Name"; Value = "Degson"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Manufacturer_Part_Number"; Value = "DG300-5.0-02P-12-00A(H)"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Mouser Part Number"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Mouser Price/Stock"; Value = ""; VariantName = "[No Variations]"
+Added Pin To Net: NetName=GND Pin=C?-1
+Added Pin To Net: NetName=GND Pin=C?-1
+Added Pin To Net: NetName=GND Pin=XP?-2
+Added Pin To Net: NetName=GND Pin=XP?-2
+Added Net: Name=GND
+Added Pin To Net: NetName=NetC?_2 Pin=C?-2
+Added Pin To Net: NetName=NetC?_2 Pin=R?-1
+Added Net: Name=NetC?_2
+Added Pin To Net: NetName=NetR?_2 Pin=R?-2
+Added Pin To Net: NetName=NetR?_2 Pin=XP?-1
+Added Net: Name=NetR?_2
+Added Class: Name=Sheet3
+Added Room: Name=Sheet3

cap_plate/Project Logs for cap_plate/PCB2 PCB ECO 01.07.2024 13-12-44.LOG

@@ -0,0 +1,46 @@
+Added Component: Designator=C1(K50-104-63V-2200uF)
+Added Component: Designator=C2(K50-98-63V-1500uF)
+Added Component: Designator=R1(SQP 5W2)
+Added Component: Designator=R2(SQP 5W2)
+Added Component: Designator=XP1(DG3005002P1200AH)
+Add component (AddParameter): Name = "Arrow Part Number"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Arrow Price/Stock"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Datasheet Link"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Height"; Value = "12.6mm"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Manufacturer_Name"; Value = "Degson"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Manufacturer_Part_Number"; Value = "DG300-5.0-02P-12-00A(H)"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Mouser Part Number"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Mouser Price/Stock"; Value = ""; VariantName = "[No Variations]"
+Added Component: Designator=XP2(DG3005002P1200AH)
+Add component (AddParameter): Name = "Arrow Part Number"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Arrow Price/Stock"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Datasheet Link"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Height"; Value = "12.6mm"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Manufacturer_Name"; Value = "Degson"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Manufacturer_Part_Number"; Value = "DG300-5.0-02P-12-00A(H)"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Mouser Part Number"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Mouser Price/Stock"; Value = ""; VariantName = "[No Variations]"
+Added Pin To Net: NetName=GND Pin=C1-1
+Added Pin To Net: NetName=GND Pin=C2-1
+Added Pin To Net: NetName=GND Pin=XP1-2
+Added Pin To Net: NetName=GND Pin=XP2-2
+Added Net: Name=GND
+Added Pin To Net: NetName=NetC1_2 Pin=C1-2
+Added Pin To Net: NetName=NetC1_2 Pin=R2-1
+Added Net: Name=NetC1_2
+Added Pin To Net: NetName=NetC2_2 Pin=C2-2
+Added Pin To Net: NetName=NetC2_2 Pin=R1-1
+Added Net: Name=NetC2_2
+Added Pin To Net: NetName=NetR1_2 Pin=R1-2
+Added Pin To Net: NetName=NetR1_2 Pin=XP2-1
+Added Net: Name=NetR1_2
+Added Pin To Net: NetName=NetR2_2 Pin=R2-2
+Added Pin To Net: NetName=NetR2_2 Pin=XP1-1
+Added Net: Name=NetR2_2
+Added Member To Class: ClassName=Sheet3 Member=Component C1 2200uF
+Added Member To Class: ClassName=Sheet3 Member=Component C2 1500uF
+Added Member To Class: ClassName=Sheet3 Member=Component R1 2 Îì
+Added Member To Class: ClassName=Sheet3 Member=Component R2 2 Îì
+Added Member To Class: ClassName=Sheet3 Member=Component XP1 DG300-5.0-02P-12-00A_H_
+Added Member To Class: ClassName=Sheet3 Member=Component XP2 DG300-5.0-02P-12-00A_H_
+Added Room: Name=Sheet3

cap_plate/Project Logs for cap_plate/PCB2 PCB ECO 01.07.2024 13-20-06.LOG

@@ -0,0 +1,9 @@
+Removed Pin From Net: NetName=NetR2_2 Pin=XP1-1
+Removed Pin From Net: NetName=GND Pin=XP1-2
+Removed Pin From Net: NetName=NetR1_2 Pin=XP2-1
+Removed Pin From Net: NetName=GND Pin=XP2-2
+Added Pin To Net: NetName=GND Pin=XP1-1
+Added Pin To Net: NetName=NetR2_2 Pin=XP1-2
+Added Pin To Net: NetName=GND Pin=XP2-1
+Added Pin To Net: NetName=NetR1_2 Pin=XP2-2
+Added Room: Name=Sheet3

cap_plate/Project Logs for cap_plate/PCB2 PCB ECO 01.07.2024 15-13-24.LOG

@@ -0,0 +1,33 @@
+Change Component Designator: OldDesignator=XP1 NewDesignator=XP3
+Change Component Designator: OldDesignator=XP2 NewDesignator=XP4
+Added Component: Designator=XP1(DG3005002P1200AH)
+Add component (AddParameter): Name = "Arrow Part Number"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Arrow Price/Stock"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Datasheet Link"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Height"; Value = "12.6mm"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Manufacturer_Name"; Value = "Degson"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Manufacturer_Part_Number"; Value = "DG300-5.0-02P-12-00A(H)"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Mouser Part Number"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Mouser Price/Stock"; Value = ""; VariantName = "[No Variations]"
+Added Component: Designator=XP2(DG3005002P1200AH)
+Add component (AddParameter): Name = "Arrow Part Number"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Arrow Price/Stock"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Datasheet Link"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Height"; Value = "12.6mm"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Manufacturer_Name"; Value = "Degson"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Manufacturer_Part_Number"; Value = "DG300-5.0-02P-12-00A(H)"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Mouser Part Number"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Mouser Price/Stock"; Value = ""; VariantName = "[No Variations]"
+Added Pin To Net: NetName=GND Pin=XP1-1
+Added Pin To Net: NetName=GND Pin=XP2-1
+Added Pin To Net: NetName=VCC1 Pin=C2-2
+Added Pin To Net: NetName=VCC1 Pin=R1-1
+Added Pin To Net: NetName=VCC1 Pin=XP2-2
+Added Net: Name=VCC1
+Added Pin To Net: NetName=VCC2 Pin=C1-2
+Added Pin To Net: NetName=VCC2 Pin=R2-1
+Added Pin To Net: NetName=VCC2 Pin=XP1-2
+Added Net: Name=VCC2
+Added Member To Class: ClassName=Sheet3 Member=Component XP3 DG300-5.0-02P-12-00A_H_
+Added Member To Class: ClassName=Sheet3 Member=Component XP4 DG300-5.0-02P-12-00A_H_
+Added Room: Name=Sheet3

cap_plate/Project Logs for cap_plate/PCB2 PCB ECO 01.07.2024 15-22-29.LOG

@@ -0,0 +1,3 @@
+Added Member To Class: ClassName=Sheet3 Member=Component XP1 DG300-5.0-02P-12-00A_H_
+Added Member To Class: ClassName=Sheet3 Member=Component XP2 DG300-5.0-02P-12-00A_H_
+Added Room: Name=Sheet3

cap_plate/Project Logs for cap_plate/PCB2 PCB ECO 01.07.2024 15-41-21.LOG

@@ -0,0 +1 @@
+Added Room: Name=Sheet3

cap_plate/Project Logs for cap_plate/PCB2 PCB ECO 01.07.2024 15-41-41.LOG

@@ -0,0 +1,9 @@
+Added Component: Designator=C1(K50-104-63V-2200uF)
+Added Component: Designator=C2(K50-98-63V-1500uF)
+Added Pin To Net: NetName=GND Pin=C1-1
+Added Pin To Net: NetName=VCC2 Pin=C1-2
+Added Pin To Net: NetName=GND Pin=C2-1
+Added Pin To Net: NetName=VCC1 Pin=C2-2
+Added Member To Class: ClassName=Sheet3 Member=Component C1 2200uF
+Added Member To Class: ClassName=Sheet3 Member=Component C2 1500uF
+Added Room: Name=Sheet3

cap_plate/Project Logs for cap_plate/PCB2 PCB ECO 01.07.2024 16-02-00.LOG

@@ -0,0 +1,8 @@
+Removed Pin From Net: NetName=GND Pin=C1-1
+Removed Pin From Net: NetName=GND Pin=XP1-1
+Removed Pin From Net: NetName=GND Pin=XP3-1
+Removed Member From Class: ClassName=Sheet3 Member=C1
+Removed Member From Class: ClassName=Sheet3 Member=R2
+Removed Member From Class: ClassName=Sheet3 Member=XP1
+Removed Member From Class: ClassName=Sheet3 Member=XP3
+Added Room: Name=Sheet3

cap_plate/Project Logs for cap_plate/PCB2 PCB ECO 01.07.2024 16-09-03.LOG

@@ -0,0 +1 @@
+Added Room: Name=Sheet3

cap_plate/Project Logs for cap_plate/PCB2 PCB ECO 01.07.2024 16-09-23.LOG

@@ -0,0 +1 @@
+Added Room: Name=Sheet3

cap_plate/Project Logs for cap_plate/PCB2 PCB ECO 01.07.2024 16-09-33.LOG

@@ -0,0 +1,5 @@
+Added Component: Designator=C2(K50-98-63V-1500uF)
+Added Pin To Net: NetName=GND Pin=C2-1
+Added Pin To Net: NetName=VCC1 Pin=C2-2
+Added Member To Class: ClassName=Sheet3 Member=Component C2 1500uF
+Added Room: Name=Sheet3

cap_plate/Project Logs for cap_plate/PCB2 PCB ECO 01.07.2024 16-22-50.LOG

@@ -0,0 +1 @@
+Added Room: Name=Sheet3

cap_plate/Project Logs for cap_plate/PCB2 PCB ECO 01.07.2024 16-23-03.LOG

@@ -0,0 +1,12 @@
+Added Component: Designator=XP2(DG3005002P1200AH)
+Add component (AddParameter): Name = "Arrow Part Number"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Arrow Price/Stock"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Datasheet Link"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Height"; Value = "12.6mm"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Manufacturer_Name"; Value = "Degson"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Manufacturer_Part_Number"; Value = "DG300-5.0-02P-12-00A(H)"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Mouser Part Number"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Mouser Price/Stock"; Value = ""; VariantName = "[No Variations]"
+Added Pin To Net: NetName=GND Pin=XP2-1
+Added Pin To Net: NetName=VCC1 Pin=XP2-2
+Added Member To Class: ClassName=Sheet3 Member=Component XP2 DG300-5.0-02P-12-00A_H_

cap_plate/Project Logs for cap_plate/PCB2 PCB ECO 01.07.2024 16-24-19.LOG

@@ -0,0 +1,12 @@
+Added Component: Designator=XP2(DG3005002P1200AH)
+Add component (AddParameter): Name = "Arrow Part Number"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Arrow Price/Stock"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Datasheet Link"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Height"; Value = "12.6mm"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Manufacturer_Name"; Value = "Degson"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Manufacturer_Part_Number"; Value = "DG300-5.0-02P-12-00A(H)"; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Mouser Part Number"; Value = ""; VariantName = "[No Variations]"
+Add component (AddParameter): Name = "Mouser Price/Stock"; Value = ""; VariantName = "[No Variations]"
+Added Pin To Net: NetName=VCC1 Pin=XP2-1
+Added Pin To Net: NetName=GND Pin=XP2-2
+Added Member To Class: ClassName=Sheet3 Member=Component XP2 DG300-5.0-02P-12-00A_H_

cap_plate/Project Logs for cap_plate/Sheet3 SCH ECO 01.07.2024 13-11-21.LOG

@@ -0,0 +1,6 @@
+Replace Part C? K50-98-63V-1500uF in C:\Users\Public\Documents\Altium\Projects\cap_plate\Sheet3.SchDoc with K50-98-63V-1500uF from NEW-MODUL.SchLib
+Replace Part C? K50-104-63V-2200uF in C:\Users\Public\Documents\Altium\Projects\cap_plate\Sheet3.SchDoc with K50-104-63V-2200uF from NEW-MODUL.SchLib
+Replace Part R? SQP 5W in C:\Users\Public\Documents\Altium\Projects\cap_plate\Sheet3.SchDoc with SQP 5W from NEW-MODUL.SchLib
+Replace Part R? SQP 5W in C:\Users\Public\Documents\Altium\Projects\cap_plate\Sheet3.SchDoc with SQP 5W from NEW-MODUL.SchLib
+Replace Part XP? DG300-5.0-02P-12-00A_H_ in C:\Users\Public\Documents\Altium\Projects\cap_plate\Sheet3.SchDoc with DG300-5.0-02P-12-00A_H_ from SamacSys.SchLib
+Replace Part XP? DG300-5.0-02P-12-00A_H_ in C:\Users\Public\Documents\Altium\Projects\cap_plate\Sheet3.SchDoc with DG300-5.0-02P-12-00A_H_ from SamacSys.SchLib

cap_plate/Project Logs for cap_plate/Sheet3 SCH ECO 01.07.2024 13-12-11.LOG

@@ -0,0 +1,6 @@
+Change Component Designator: Old Designator=C? New Designator=C1
+Change Component Designator: Old Designator=C? New Designator=C2
+Change Component Designator: Old Designator=R? New Designator=R1
+Change Component Designator: Old Designator=R? New Designator=R2
+Change Component Designator: Old Designator=XP? New Designator=XP1
+Change Component Designator: Old Designator=XP? New Designator=XP2

cap_plate/Project Logs for cap_plate/Sheet3 SCH ECO 01.07.2024 13-19-54.LOG

@@ -0,0 +1,2 @@
+Replace Part XP1 DG300-5.0-02P-12-00A_H_ in C:\Users\Public\Documents\Altium\Projects\cap_plate\Sheet3.SchDoc with DG300-5.0-02P-12-00A_H_ from SamacSys.SchLib
+Replace Part XP2 DG300-5.0-02P-12-00A_H_ in C:\Users\Public\Documents\Altium\Projects\cap_plate\Sheet3.SchDoc with DG300-5.0-02P-12-00A_H_ from SamacSys.SchLib

cap_plate/Project Logs for cap_plate/Sheet3 SCH ECO 01.07.2024 15-12-49.LOG

@@ -0,0 +1,6 @@
+Change Component Designator: Old Designator=C1 New Designator=C?
+Change Component Designator: Old Designator=C2 New Designator=C?
+Change Component Designator: Old Designator=R1 New Designator=R?
+Change Component Designator: Old Designator=R2 New Designator=R?
+Change Component Designator: Old Designator=XP1 New Designator=XP?
+Change Component Designator: Old Designator=XP2 New Designator=XP?

cap_plate/Project Logs for cap_plate/Sheet3 SCH ECO 01.07.2024 15-12-57.LOG

@@ -0,0 +1,8 @@
+Change Component Designator: Old Designator=C? New Designator=C1
+Change Component Designator: Old Designator=C? New Designator=C2
+Change Component Designator: Old Designator=R? New Designator=R1
+Change Component Designator: Old Designator=R? New Designator=R2
+Change Component Designator: Old Designator=XP? New Designator=XP1
+Change Component Designator: Old Designator=XP? New Designator=XP2
+Change Component Designator: Old Designator=XP? New Designator=XP3
+Change Component Designator: Old Designator=XP? New Designator=XP4

cap_plate/Project Logs for cap_plate/Sheet3 SCH ECO 01.07.2024 15-22-21.LOG

@@ -0,0 +1,8 @@
+Replace Part C1 K50-104-63V-2200uF in C:\Users\Public\Documents\Altium\Projects\cap_plate\Sheet3.SchDoc with K50-104-63V-2200uF from NEW-MODUL.SchLib
+Replace Part C2 K50-98-63V-1500uF in C:\Users\Public\Documents\Altium\Projects\cap_plate\Sheet3.SchDoc with K50-98-63V-1500uF from NEW-MODUL.SchLib
+Replace Part R1 SQP 5W in C:\Users\Public\Documents\Altium\Projects\cap_plate\Sheet3.SchDoc with SQP 5W from NEW-MODUL.SchLib
+Replace Part R2 SQP 5W in C:\Users\Public\Documents\Altium\Projects\cap_plate\Sheet3.SchDoc with SQP 5W from NEW-MODUL.SchLib
+Replace Part XP1 DG300-5.0-02P-12-00A_H_ in C:\Users\Public\Documents\Altium\Projects\cap_plate\Sheet3.SchDoc with DG300-5.0-02P-12-00A_H_ from SamacSys.SchLib
+Replace Part XP2 DG300-5.0-02P-12-00A_H_ in C:\Users\Public\Documents\Altium\Projects\cap_plate\Sheet3.SchDoc with DG300-5.0-02P-12-00A_H_ from SamacSys.SchLib
+Replace Part XP3 DG300-5.0-02P-12-00A_H_ in C:\Users\Public\Documents\Altium\Projects\cap_plate\Sheet3.SchDoc with DG300-5.0-02P-12-00A_H_ from SamacSys.SchLib
+Replace Part XP4 DG300-5.0-02P-12-00A_H_ in C:\Users\Public\Documents\Altium\Projects\cap_plate\Sheet3.SchDoc with DG300-5.0-02P-12-00A_H_ from SamacSys.SchLib

cap_plate/Project Logs for cap_plate/Sheet3 SCH ECO 01.07.2024 15-41-05.LOG

@@ -0,0 +1,8 @@
+Replace Part C1 K50-104-63V-2200uF in C:\Users\Public\Documents\Altium\Projects\cap_plate\Sheet3.SchDoc with K50-104-63V-2200uF from NEW-MODUL.SchLib
+Replace Part C2 K50-98-63V-1500uF in C:\Users\Public\Documents\Altium\Projects\cap_plate\Sheet3.SchDoc with K50-98-63V-1500uF from NEW-MODUL.SchLib
+Replace Part R1 SQP 5W in C:\Users\Public\Documents\Altium\Projects\cap_plate\Sheet3.SchDoc with SQP 5W from NEW-MODUL.SchLib
+Replace Part R2 SQP 5W in C:\Users\Public\Documents\Altium\Projects\cap_plate\Sheet3.SchDoc with SQP 5W from NEW-MODUL.SchLib
+Replace Part XP1 DG300-5.0-02P-12-00A_H_ in C:\Users\Public\Documents\Altium\Projects\cap_plate\Sheet3.SchDoc with DG300-5.0-02P-12-00A_H_ from SamacSys.SchLib
+Replace Part XP2 DG300-5.0-02P-12-00A_H_ in C:\Users\Public\Documents\Altium\Projects\cap_plate\Sheet3.SchDoc with DG300-5.0-02P-12-00A_H_ from SamacSys.SchLib
+Replace Part XP3 DG300-5.0-02P-12-00A_H_ in C:\Users\Public\Documents\Altium\Projects\cap_plate\Sheet3.SchDoc with DG300-5.0-02P-12-00A_H_ from SamacSys.SchLib
+Replace Part XP4 DG300-5.0-02P-12-00A_H_ in C:\Users\Public\Documents\Altium\Projects\cap_plate\Sheet3.SchDoc with DG300-5.0-02P-12-00A_H_ from SamacSys.SchLib

cap_plate/Project Logs for cap_plate/Sheet3 SCH ECO 01.07.2024 16-09-16.LOG

@@ -0,0 +1,4 @@
+Replace Part C2 K50-98-63V-1500uF in C:\Users\Public\Documents\Altium\Projects\cap_plate\Sheet3.SchDoc with K50-98-63V-1500uF from NEW-MODUL.SchLib
+Replace Part R1 SQP 5W in C:\Users\Public\Documents\Altium\Projects\cap_plate\Sheet3.SchDoc with SQP 5W from NEW-MODUL.SchLib
+Replace Part XP2 DG300-5.0-02P-12-00A_H_ in C:\Users\Public\Documents\Altium\Projects\cap_plate\Sheet3.SchDoc with DG300-5.0-02P-12-00A_H_ from SamacSys.SchLib
+Replace Part XP4 DG300-5.0-02P-12-00A_H_ in C:\Users\Public\Documents\Altium\Projects\cap_plate\Sheet3.SchDoc with DG300-5.0-02P-12-00A_H_ from SamacSys.SchLib

cap_plate/Project Outputs for cap_plate/Design Rule Check - PCB2.drc

@@ -0,0 +1,69 @@
+Protel Design System Design Rule Check
+PCB File : C:\Users\Public\Documents\Altium\Projects\cap_plate\PCB2.PcbDoc
+Date     : 01.07.2024
+Time     : 15:14:04
+
+Processing Rule : Clearance Constraint (Gap=10mil) (All),(All)
+Rule Violations :0
+
+Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
+Rule Violations :0
+
+Processing Rule : Un-Routed Net Constraint ( (All) )
+   Violation between Un-Routed Net Constraint: Net GND Between Pad C1-1(2824.724mil,1590mil) on Multi-Layer And Pad C2-1(4760mil,1825mil) on Multi-Layer 
+   Violation between Un-Routed Net Constraint: Net GND Between Pad XP3-1(1556.85mil,2420mil) on Multi-Layer And Pad C1-1(2824.724mil,1590mil) on Multi-Layer 
+   Violation between Un-Routed Net Constraint: Net VCC2 Between Pad C1-2(3120mil,1590mil) on Multi-Layer And Pad R2-1(3440mil,3615mil) on Multi-Layer 
+   Violation between Un-Routed Net Constraint: Net VCC2 Between Pad C1-2(3120mil,1590mil) on Multi-Layer And Pad XP1-2(5885mil,1715mil) on Multi-Layer 
+   Violation between Un-Routed Net Constraint: Net GND Between Pad C2-1(4760mil,1825mil) on Multi-Layer And Pad XP1-1(5688.15mil,1715mil) on Multi-Layer 
+   Violation between Un-Routed Net Constraint: Net GND Between Pad XP4-1(3868.15mil,3590mil) on Multi-Layer And Pad C2-1(4760mil,1825mil) on Multi-Layer 
+   Violation between Un-Routed Net Constraint: Net VCC1 Between Pad C2-2(4366.299mil,1825mil) on Multi-Layer And Pad R1-1(5305mil,2815.157mil) on Multi-Layer 
+   Violation between Un-Routed Net Constraint: Net VCC1 Between Pad C2-2(4366.299mil,1825mil) on Multi-Layer And Pad XP2-2(6880mil,1835mil) on Multi-Layer 
+   Violation between Un-Routed Net Constraint: Net NetR1_2 Between Pad XP4-2(4065mil,3590mil) on Multi-Layer And Pad R1-2(5305mil,4075mil) on Multi-Layer 
+   Violation between Un-Routed Net Constraint: Net NetR2_2 Between Pad XP3-2(1360mil,2420mil) on Multi-Layer And Pad R2-2(2180.157mil,3615mil) on Multi-Layer 
+   Violation between Un-Routed Net Constraint: Net GND Between Pad XP1-1(5688.15mil,1715mil) on Multi-Layer And Pad XP2-1(6683.15mil,1835mil) on Multi-Layer 
+Rule Violations :11
+
+Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
+Rule Violations :0
+
+Processing Rule : Width Constraint (Min=10mil) (Max=10mil) (Preferred=10mil) (All)
+Rule Violations :0
+
+Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
+Rule Violations :0
+
+Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (All)
+Rule Violations :0
+
+Processing Rule : Hole To Hole Clearance (Gap=10mil) (All),(All)
+Rule Violations :0
+
+Processing Rule : Minimum Solder Mask Sliver (Gap=10mil) (All),(All)
+Rule Violations :0
+
+Processing Rule : Silk To Solder Mask (Clearance=10mil) (IsPad),(All)
+Rule Violations :0
+
+Processing Rule : Silk to Silk (Clearance=10mil) (All),(All)
+Rule Violations :0
+
+Processing Rule : Net Antennae (Tolerance=0mil) (All)
+Rule Violations :0
+
+Processing Rule : Room Sheet3 (Bounding Region = (7045mil, 1060mil, 8165mil, 1610mil) (InComponentClass('Sheet3'))
+   Violation between Room Definition: Between Room Sheet3 (Bounding Region = (7045mil, 1060mil, 8165mil, 1610mil) (InComponentClass('Sheet3')) And Small Component C1-2200uF (2824.724mil,1590mil) on Top Layer 
+   Violation between Room Definition: Between Room Sheet3 (Bounding Region = (7045mil, 1060mil, 8165mil, 1610mil) (InComponentClass('Sheet3')) And Small Component C2-1500uF (4760mil,1825mil) on Top Layer 
+   Violation between Room Definition: Between Room Sheet3 (Bounding Region = (7045mil, 1060mil, 8165mil, 1610mil) (InComponentClass('Sheet3')) And Small Component R1-2 Îì (5305mil,2815.157mil) on Top Layer 
+   Violation between Room Definition: Between Room Sheet3 (Bounding Region = (7045mil, 1060mil, 8165mil, 1610mil) (InComponentClass('Sheet3')) And Small Component R2-2 Îì (3440mil,3615mil) on Top Layer 
+   Violation between Room Definition: Between Room Sheet3 (Bounding Region = (7045mil, 1060mil, 8165mil, 1610mil) (InComponentClass('Sheet3')) And Small Component XP3-DG300-5.0-02P-12-00A_H_ (1556.85mil,2420mil) on Top Layer 
+   Violation between Room Definition: Between Room Sheet3 (Bounding Region = (7045mil, 1060mil, 8165mil, 1610mil) (InComponentClass('Sheet3')) And Small Component XP4-DG300-5.0-02P-12-00A_H_ (3868.15mil,3590mil) on Top Layer 
+Rule Violations :6
+
+Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
+   Violation between Height Constraint: Small Component C1-2200uF (2824.724mil,1590mil) on Top Layer Actual Height = 1318.898mil
+Rule Violations :1
+
+
+Violations Detected : 18
+Waived Violations : 0
+Time Elapsed        : 00:00:01

cap_plate/cap_plate.PrjPcbStructure

@@ -0,0 +1 @@
+Record=TopLevelDocument|FileName=Sheet3.SchDoc

cap_test_unit/Project Logs for cap_test_unit/PCB1 PCB ECO 01.07.2024 14-31-54.LOG

@@ -0,0 +1,24 @@
+Change Component Comment : Designator=C2 Old Comment=0,1ìêÔ New Comment=0,1 ìêÔ
+Change Component Comment : Designator=C4 Old Comment=0,1ìêÔ New Comment=0,1 ìêÔ
+Change Component Comment : Designator=R5 Old Comment=0.05 Îì New Comment=R2512
+Change Component Comment : Designator=R4 Old Comment=10Îì New Comment=1êÎì
+Change Component Comment : Designator=C3 Old Comment=10íÔ New Comment=0,1 ìêÔ
+Change Component Comment : Designator=C5 Old Comment=10íÔ New Comment=0,1 ìêÔ
+Change Component Comment : Designator=C1 Old Comment=100ïÔ New Comment=0,1 ìêÔ
+Change Component Designator: OldDesignator=C1 NewDesignator=C3
+Change Component Designator: OldDesignator=C2 NewDesignator=C1
+Change Component Designator: OldDesignator=C3 NewDesignator=C2
+Change Component Designator: OldDesignator=R1 NewDesignator=R2
+Change Component Designator: OldDesignator=R2 NewDesignator=R3
+Change Component Designator: OldDesignator=R3 NewDesignator=R4
+Change Component Designator: OldDesignator=R4 NewDesignator=R5
+Change Component Designator: OldDesignator=R5 NewDesignator=R6
+Change Component Description : Designator=R6 Old Description=Resistor 3W R2512 New Description=Resistor 3W
+Added Component: Designator=R1(R0603)
+Add component (AddParameter): Name = "Value"; Value = "1êÎì"; VariantName = "[No Variations]"
+Added Pin To Net: NetName=GND Pin=R1-1
+Added Pin To Net: NetName=ControlIN Pin=R1-2
+Change Net Name : Old Net Name=NetC1_2 New Net Name=NetC3_2
+Change Net Name : Old Net Name=NetR3_2 New Net Name=NetR4_2
+Change Net Name : Old Net Name=NetR4_2 New Net Name=NetR5_2
+Added Member To Class: ClassName=Sheet1 Member=Component R6 R2512

cap_test_unit/Project Logs for cap_test_unit/Sheet1 SCH ECO 01.07.2024 14-26-55.LOG

@@ -0,0 +1 @@
+Change Component Designator: Old Designator=R? New Designator=R6

cap_test_unit/Project Logs for cap_test_unit/Sheet1 SCH ECO 01.07.2024 14-27-34.LOG

@@ -0,0 +1 @@
+Change Value of Parameter Value in Part R6 Old=1êÎì New=10êÎì

cap_test_unit/Project Logs for cap_test_unit/Sheet1 SCH ECO 01.07.2024 14-27-56.LOG

@@ -0,0 +1,19 @@
+Change Component Designator: Old Designator=C1 New Designator=C?
+Change Component Designator: Old Designator=C2 New Designator=C?
+Change Component Designator: Old Designator=C3 New Designator=C?
+Change Component Designator: Old Designator=C4 New Designator=C?
+Change Component Designator: Old Designator=C5 New Designator=C?
+Change Component Designator: Old Designator=DA1 New Designator=DA?
+Change Component Designator: Old Designator=DA1 New Designator=DA?
+Change Component Designator: Old Designator=DA1 New Designator=DA?
+Change Component Designator: Old Designator=R1 New Designator=R?
+Change Component Designator: Old Designator=R2 New Designator=R?
+Change Component Designator: Old Designator=R3 New Designator=R?
+Change Component Designator: Old Designator=R4 New Designator=R?
+Change Component Designator: Old Designator=R5 New Designator=R?
+Change Component Designator: Old Designator=R6 New Designator=R?
+Change Component Designator: Old Designator=VT1 New Designator=VT?
+Change Component Designator: Old Designator=XP1 New Designator=XP?
+Change Component Designator: Old Designator=XP2 New Designator=XP?
+Change Component Designator: Old Designator=XP3 New Designator=XP?
+Change Component Designator: Old Designator=XP4 New Designator=XP?

cap_test_unit/Project Logs for cap_test_unit/Sheet1 SCH ECO 01.07.2024 14-28-04.LOG

@@ -0,0 +1,19 @@
+Change Component Designator: Old Designator=C? New Designator=C1
+Change Component Designator: Old Designator=C? New Designator=C2
+Change Component Designator: Old Designator=C? New Designator=C3
+Change Component Designator: Old Designator=C? New Designator=C4
+Change Component Designator: Old Designator=C? New Designator=C5
+Change Component Designator: Old Designator=DA? New Designator=DA1
+Change Component Designator: Old Designator=DA? New Designator=DA1
+Change Component Designator: Old Designator=DA? New Designator=DA1
+Change Component Designator: Old Designator=R? New Designator=R1
+Change Component Designator: Old Designator=R? New Designator=R2
+Change Component Designator: Old Designator=R? New Designator=R3
+Change Component Designator: Old Designator=R? New Designator=R4
+Change Component Designator: Old Designator=R? New Designator=R5
+Change Component Designator: Old Designator=R? New Designator=R6
+Change Component Designator: Old Designator=VT? New Designator=VT1
+Change Component Designator: Old Designator=XP? New Designator=XP1
+Change Component Designator: Old Designator=XP? New Designator=XP2
+Change Component Designator: Old Designator=XP? New Designator=XP3
+Change Component Designator: Old Designator=XP? New Designator=XP4

cap_test_unit/Project Logs for cap_test_unit/Sheet1 SCH ECO 01.07.2024 14-31-14.LOG

@@ -0,0 +1,19 @@
+Replace Part C1 C0603 in C:\Users\vladi\Nextcloud\ÍÖÔÌ\06. Òåõíè÷åñêàÿ äîêóìåíòàöèÿ\02. Ýëåêòðîíèêà è ýëåêòðèêà\cap_test_unit\cap_test_unit\Sheet1.SchDoc with C0603 from NEW-MODUL.SchLib
+Replace Part C2 C0603 in C:\Users\vladi\Nextcloud\ÍÖÔÌ\06. Òåõíè÷åñêàÿ äîêóìåíòàöèÿ\02. Ýëåêòðîíèêà è ýëåêòðèêà\cap_test_unit\cap_test_unit\Sheet1.SchDoc with C0603 from NEW-MODUL.SchLib
+Replace Part C3 C0603 in C:\Users\vladi\Nextcloud\ÍÖÔÌ\06. Òåõíè÷åñêàÿ äîêóìåíòàöèÿ\02. Ýëåêòðîíèêà è ýëåêòðèêà\cap_test_unit\cap_test_unit\Sheet1.SchDoc with C0603 from NEW-MODUL.SchLib
+Replace Part C4 C0603 in C:\Users\vladi\Nextcloud\ÍÖÔÌ\06. Òåõíè÷åñêàÿ äîêóìåíòàöèÿ\02. Ýëåêòðîíèêà è ýëåêòðèêà\cap_test_unit\cap_test_unit\Sheet1.SchDoc with C0603 from NEW-MODUL.SchLib
+Replace Part C5 C0603 in C:\Users\vladi\Nextcloud\ÍÖÔÌ\06. Òåõíè÷åñêàÿ äîêóìåíòàöèÿ\02. Ýëåêòðîíèêà è ýëåêòðèêà\cap_test_unit\cap_test_unit\Sheet1.SchDoc with C0603 from NEW-MODUL.SchLib
+Replace Part DA1 TL072CDT in C:\Users\vladi\Nextcloud\ÍÖÔÌ\06. Òåõíè÷åñêàÿ äîêóìåíòàöèÿ\02. Ýëåêòðîíèêà è ýëåêòðèêà\cap_test_unit\cap_test_unit\Sheet1.SchDoc with TL072CDT from SamacSys.SchLib
+Replace Part DA1 TL072CDT in C:\Users\vladi\Nextcloud\ÍÖÔÌ\06. Òåõíè÷åñêàÿ äîêóìåíòàöèÿ\02. Ýëåêòðîíèêà è ýëåêòðèêà\cap_test_unit\cap_test_unit\Sheet1.SchDoc with TL072CDT from SamacSys.SchLib
+Replace Part DA1 TL072CDT in C:\Users\vladi\Nextcloud\ÍÖÔÌ\06. Òåõíè÷åñêàÿ äîêóìåíòàöèÿ\02. Ýëåêòðîíèêà è ýëåêòðèêà\cap_test_unit\cap_test_unit\Sheet1.SchDoc with TL072CDT from SamacSys.SchLib
+Replace Part R1 R0603 in C:\Users\vladi\Nextcloud\ÍÖÔÌ\06. Òåõíè÷åñêàÿ äîêóìåíòàöèÿ\02. Ýëåêòðîíèêà è ýëåêòðèêà\cap_test_unit\cap_test_unit\Sheet1.SchDoc with R0603 from NEW-MODUL.SchLib
+Replace Part R2 R0603 in C:\Users\vladi\Nextcloud\ÍÖÔÌ\06. Òåõíè÷åñêàÿ äîêóìåíòàöèÿ\02. Ýëåêòðîíèêà è ýëåêòðèêà\cap_test_unit\cap_test_unit\Sheet1.SchDoc with R0603 from NEW-MODUL.SchLib
+Replace Part R3 R0603 in C:\Users\vladi\Nextcloud\ÍÖÔÌ\06. Òåõíè÷åñêàÿ äîêóìåíòàöèÿ\02. Ýëåêòðîíèêà è ýëåêòðèêà\cap_test_unit\cap_test_unit\Sheet1.SchDoc with R0603 from NEW-MODUL.SchLib
+Replace Part R4 R0603 in C:\Users\vladi\Nextcloud\ÍÖÔÌ\06. Òåõíè÷åñêàÿ äîêóìåíòàöèÿ\02. Ýëåêòðîíèêà è ýëåêòðèêà\cap_test_unit\cap_test_unit\Sheet1.SchDoc with R0603 from NEW-MODUL.SchLib
+Replace Part R5 R0603 in C:\Users\vladi\Nextcloud\ÍÖÔÌ\06. Òåõíè÷åñêàÿ äîêóìåíòàöèÿ\02. Ýëåêòðîíèêà è ýëåêòðèêà\cap_test_unit\cap_test_unit\Sheet1.SchDoc with R0603 from NEW-MODUL.SchLib
+Replace Part R6 R2512 in C:\Users\vladi\Nextcloud\ÍÖÔÌ\06. Òåõíè÷åñêàÿ äîêóìåíòàöèÿ\02. Ýëåêòðîíèêà è ýëåêòðèêà\cap_test_unit\cap_test_unit\Sheet1.SchDoc with R2512 from SamacSys.SchLib
+Replace Part VT1 IRF630 in C:\Users\vladi\Nextcloud\ÍÖÔÌ\06. Òåõíè÷åñêàÿ äîêóìåíòàöèÿ\02. Ýëåêòðîíèêà è ýëåêòðèêà\cap_test_unit\cap_test_unit\Sheet1.SchDoc with IRF630 from SamacSys.SchLib
+Replace Part XP1 PLS-2 in C:\Users\vladi\Nextcloud\ÍÖÔÌ\06. Òåõíè÷åñêàÿ äîêóìåíòàöèÿ\02. Ýëåêòðîíèêà è ýëåêòðèêà\cap_test_unit\cap_test_unit\Sheet1.SchDoc with PLS-2 from Ðàçúåìû.SchLib
+Replace Part XP2 PLS-2 in C:\Users\vladi\Nextcloud\ÍÖÔÌ\06. Òåõíè÷åñêàÿ äîêóìåíòàöèÿ\02. Ýëåêòðîíèêà è ýëåêòðèêà\cap_test_unit\cap_test_unit\Sheet1.SchDoc with PLS-2 from Ðàçúåìû.SchLib
+Replace Part XP3 DG300-5.0-02P-12-00A_H_ in C:\Users\vladi\Nextcloud\ÍÖÔÌ\06. Òåõíè÷åñêàÿ äîêóìåíòàöèÿ\02. Ýëåêòðîíèêà è ýëåêòðèêà\cap_test_unit\cap_test_unit\Sheet1.SchDoc with DG300-5.0-02P-12-00A_H_ from SamacSys.SchLib
+Replace Part XP4 PLS-2 in C:\Users\vladi\Nextcloud\ÍÖÔÌ\06. Òåõíè÷åñêàÿ äîêóìåíòàöèÿ\02. Ýëåêòðîíèêà è ýëåêòðèêà\cap_test_unit\cap_test_unit\Sheet1.SchDoc with PLS-2 from Ðàçúåìû.SchLib

cap_test_unit/Project Outputs for cap_test_unit/Design Rule Check - PCB1.drc

@@ -1,7 +1,7 @@
 Protel Design System Design Rule Check
 PCB File : C:\Users\vladi\Nextcloud\ÍÖÔÌ\06. Òåõíè÷åñêàÿ äîêóìåíòàöèÿ\02. Ýëåêòðîíèêà è ýëåêòðèêà\cap_test_unit\cap_test_unit\PCB1.PcbDoc
 Date     : 01.07.2024
-Time     : 10:57:13
+Time     : 16:50:26
 
 Processing Rule : Clearance Constraint (Gap=0.254mm) (All),(All)
 Rule Violations :0
@@ -31,72 +31,76 @@ Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
 Rule Violations :0
 
 Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
-   Violation between Silk To Solder Mask Clearance Constraint: (0.007mm < 0.254mm) Between Arc (159.766mm,28.448mm) on Top Overlay And Pad XP2-2(160.655mm,27.94mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.007mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C1-1(165.608mm,36.576mm) on Top Layer And Track (166.116mm,35.814mm)(166.624mm,35.814mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C1-1(165.608mm,36.576mm) on Top Layer And Track (166.116mm,37.338mm)(166.624mm,37.338mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C1-2(167.196mm,36.576mm) on Top Layer And Track (166.116mm,35.814mm)(166.624mm,35.814mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C1-2(167.196mm,36.576mm) on Top Layer And Track (166.116mm,37.338mm)(166.624mm,37.338mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C2-1(162.243mm,32.004mm) on Top Layer And Track (162.75mm,31.242mm)(163.258mm,31.242mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C2-1(162.243mm,32.004mm) on Top Layer And Track (162.75mm,31.242mm)(163.258mm,31.242mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C2-1(162.243mm,32.004mm) on Top Layer And Track (162.75mm,32.766mm)(163.258mm,32.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C2-1(162.243mm,32.004mm) on Top Layer And Track (162.814mm,32.766mm)(163.322mm,32.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C2-2(163.83mm,32.004mm) on Top Layer And Track (162.75mm,31.242mm)(163.258mm,31.242mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C2-2(163.83mm,32.004mm) on Top Layer And Track (162.75mm,31.242mm)(163.258mm,31.242mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C2-2(163.83mm,32.004mm) on Top Layer And Track (162.75mm,32.766mm)(163.258mm,32.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C2-2(163.83mm,32.004mm) on Top Layer And Track (162.814mm,32.766mm)(163.322mm,32.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C3-1(162.243mm,30.48mm) on Top Layer And Track (162.75mm,29.718mm)(163.258mm,29.718mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C3-1(162.243mm,30.48mm) on Top Layer And Track (162.75mm,31.242mm)(163.258mm,31.242mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C3-1(162.243mm,30.48mm) on Top Layer And Track (162.75mm,31.242mm)(163.258mm,31.242mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C3-2(163.83mm,30.48mm) on Top Layer And Track (162.75mm,29.718mm)(163.258mm,29.718mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C3-2(163.83mm,30.48mm) on Top Layer And Track (162.75mm,31.242mm)(163.258mm,31.242mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C3-2(163.83mm,30.48mm) on Top Layer And Track (162.75mm,31.242mm)(163.258mm,31.242mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C4-1(175.832mm,32.766mm) on Top Layer And Track (174.815mm,32.004mm)(175.323mm,32.004mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C4-1(175.832mm,32.766mm) on Top Layer And Track (174.815mm,33.528mm)(175.323mm,33.528mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C4-1(175.832mm,32.766mm) on Top Layer And Track (174.815mm,33.528mm)(175.323mm,33.528mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C4-2(174.244mm,32.766mm) on Top Layer And Track (174.815mm,32.004mm)(175.323mm,32.004mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C4-2(174.244mm,32.766mm) on Top Layer And Track (174.815mm,33.528mm)(175.323mm,33.528mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C4-2(174.244mm,32.766mm) on Top Layer And Track (174.815mm,33.528mm)(175.323mm,33.528mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C5-1(175.832mm,34.29mm) on Top Layer And Track (174.815mm,33.528mm)(175.323mm,33.528mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C5-1(175.832mm,34.29mm) on Top Layer And Track (174.815mm,33.528mm)(175.323mm,33.528mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C5-1(175.832mm,34.29mm) on Top Layer And Track (174.815mm,35.052mm)(175.323mm,35.052mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C5-2(174.244mm,34.29mm) on Top Layer And Track (174.815mm,33.528mm)(175.323mm,33.528mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C5-2(174.244mm,34.29mm) on Top Layer And Track (174.815mm,33.528mm)(175.323mm,33.528mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C5-2(174.244mm,34.29mm) on Top Layer And Track (174.815mm,35.052mm)(175.323mm,35.052mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-1(171.622mm,30.607mm) on Top Layer And Track (170.51mm,30.062mm)(170.51mm,34.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-1(171.622mm,30.607mm) on Top Layer And Track (170.86mm,29.932mm)(172.385mm,29.932mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-2(171.622mm,31.877mm) on Top Layer And Track (170.51mm,30.062mm)(170.51mm,34.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-3(171.622mm,33.147mm) on Top Layer And Track (170.51mm,30.062mm)(170.51mm,34.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-4(171.622mm,34.417mm) on Top Layer And Track (170.51mm,30.062mm)(170.51mm,34.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-5(166.198mm,34.417mm) on Top Layer And Track (167.31mm,30.062mm)(167.31mm,34.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-6(166.198mm,33.147mm) on Top Layer And Track (167.31mm,30.062mm)(167.31mm,34.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-7(166.198mm,31.877mm) on Top Layer And Track (167.31mm,30.062mm)(167.31mm,34.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-8(166.198mm,30.607mm) on Top Layer And Track (167.31mm,30.062mm)(167.31mm,34.962mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R1-1(175.768mm,30.226mm) on Top Layer And Track (174.752mm,29.464mm)(175.26mm,29.464mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R1-1(175.768mm,30.226mm) on Top Layer And Track (174.752mm,30.988mm)(175.26mm,30.988mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R1-2(174.18mm,30.226mm) on Top Layer And Track (174.752mm,29.464mm)(175.26mm,29.464mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R1-2(174.18mm,30.226mm) on Top Layer And Track (174.752mm,30.988mm)(175.26mm,30.988mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R2-1(171.196mm,36.576mm) on Top Layer And Track (171.704mm,35.814mm)(172.212mm,35.814mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R2-1(171.196mm,36.576mm) on Top Layer And Track (171.704mm,37.338mm)(172.212mm,37.338mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R2-2(172.784mm,36.576mm) on Top Layer And Track (171.704mm,35.814mm)(172.212mm,35.814mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R2-2(172.784mm,36.576mm) on Top Layer And Track (171.704mm,37.338mm)(172.212mm,37.338mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R3-1(163.83mm,35.052mm) on Top Layer And Track (162.814mm,34.29mm)(163.322mm,34.29mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R3-1(163.83mm,35.052mm) on Top Layer And Track (162.814mm,34.29mm)(163.322mm,34.29mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R3-1(163.83mm,35.052mm) on Top Layer And Track (162.814mm,35.814mm)(163.322mm,35.814mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R3-2(162.243mm,35.052mm) on Top Layer And Track (162.814mm,34.29mm)(163.322mm,34.29mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R3-2(162.243mm,35.052mm) on Top Layer And Track (162.814mm,34.29mm)(163.322mm,34.29mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R3-2(162.243mm,35.052mm) on Top Layer And Track (162.814mm,35.814mm)(163.322mm,35.814mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R4-1(163.83mm,33.528mm) on Top Layer And Track (162.75mm,32.766mm)(163.258mm,32.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R4-1(163.83mm,33.528mm) on Top Layer And Track (162.814mm,32.766mm)(163.322mm,32.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R4-1(163.83mm,33.528mm) on Top Layer And Track (162.814mm,34.29mm)(163.322mm,34.29mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R4-1(163.83mm,33.528mm) on Top Layer And Track (162.814mm,34.29mm)(163.322mm,34.29mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R4-2(162.243mm,33.528mm) on Top Layer And Track (162.75mm,32.766mm)(163.258mm,32.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R4-2(162.243mm,33.528mm) on Top Layer And Track (162.814mm,32.766mm)(163.322mm,32.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R4-2(162.243mm,33.528mm) on Top Layer And Track (162.814mm,34.29mm)(163.322mm,34.29mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
-   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R4-2(162.243mm,33.528mm) on Top Layer And Track (162.814mm,34.29mm)(163.322mm,34.29mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
-Rule Violations :62
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C1-1(162.243mm,34.925mm) on Top Layer And Track (162.75mm,34.163mm)(163.258mm,34.163mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C1-1(162.243mm,34.925mm) on Top Layer And Track (162.75mm,34.163mm)(163.258mm,34.163mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C1-1(162.243mm,34.925mm) on Top Layer And Track (162.75mm,35.687mm)(163.258mm,35.687mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C1-1(162.243mm,34.925mm) on Top Layer And Track (162.814mm,35.687mm)(163.322mm,35.687mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C1-2(163.83mm,34.925mm) on Top Layer And Track (162.75mm,34.163mm)(163.258mm,34.163mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C1-2(163.83mm,34.925mm) on Top Layer And Track (162.75mm,34.163mm)(163.258mm,34.163mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C1-2(163.83mm,34.925mm) on Top Layer And Track (162.75mm,35.687mm)(163.258mm,35.687mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C1-2(163.83mm,34.925mm) on Top Layer And Track (162.814mm,35.687mm)(163.322mm,35.687mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C2-1(162.243mm,33.401mm) on Top Layer And Track (162.75mm,32.639mm)(163.258mm,32.639mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C2-1(162.243mm,33.401mm) on Top Layer And Track (162.75mm,34.163mm)(163.258mm,34.163mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C2-1(162.243mm,33.401mm) on Top Layer And Track (162.75mm,34.163mm)(163.258mm,34.163mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C2-2(163.83mm,33.401mm) on Top Layer And Track (162.75mm,32.639mm)(163.258mm,32.639mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C2-2(163.83mm,33.401mm) on Top Layer And Track (162.75mm,34.163mm)(163.258mm,34.163mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C2-2(163.83mm,33.401mm) on Top Layer And Track (162.75mm,34.163mm)(163.258mm,34.163mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C3-1(165.608mm,39.497mm) on Top Layer And Track (166.116mm,38.735mm)(166.624mm,38.735mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C3-1(165.608mm,39.497mm) on Top Layer And Track (166.116mm,40.259mm)(166.624mm,40.259mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C3-2(167.196mm,39.497mm) on Top Layer And Track (166.116mm,38.735mm)(166.624mm,38.735mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C3-2(167.196mm,39.497mm) on Top Layer And Track (166.116mm,40.259mm)(166.624mm,40.259mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C4-1(175.832mm,35.687mm) on Top Layer And Track (174.815mm,34.925mm)(175.323mm,34.925mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C4-1(175.832mm,35.687mm) on Top Layer And Track (174.815mm,36.449mm)(175.323mm,36.449mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C4-1(175.832mm,35.687mm) on Top Layer And Track (174.815mm,36.449mm)(175.323mm,36.449mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C4-2(174.244mm,35.687mm) on Top Layer And Track (174.815mm,34.925mm)(175.323mm,34.925mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C4-2(174.244mm,35.687mm) on Top Layer And Track (174.815mm,36.449mm)(175.323mm,36.449mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C4-2(174.244mm,35.687mm) on Top Layer And Track (174.815mm,36.449mm)(175.323mm,36.449mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C5-1(175.832mm,37.211mm) on Top Layer And Track (174.815mm,36.449mm)(175.323mm,36.449mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C5-1(175.832mm,37.211mm) on Top Layer And Track (174.815mm,36.449mm)(175.323mm,36.449mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C5-1(175.832mm,37.211mm) on Top Layer And Track (174.815mm,37.973mm)(175.323mm,37.973mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C5-2(174.244mm,37.211mm) on Top Layer And Track (174.815mm,36.449mm)(175.323mm,36.449mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C5-2(174.244mm,37.211mm) on Top Layer And Track (174.815mm,36.449mm)(175.323mm,36.449mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C5-2(174.244mm,37.211mm) on Top Layer And Track (174.815mm,37.973mm)(175.323mm,37.973mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-1(171.622mm,33.528mm) on Top Layer And Track (170.51mm,32.983mm)(170.51mm,37.883mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-1(171.622mm,33.528mm) on Top Layer And Track (170.86mm,32.853mm)(172.385mm,32.853mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-2(171.622mm,34.798mm) on Top Layer And Track (170.51mm,32.983mm)(170.51mm,37.883mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-3(171.622mm,36.068mm) on Top Layer And Track (170.51mm,32.983mm)(170.51mm,37.883mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-4(171.622mm,37.338mm) on Top Layer And Track (170.51mm,32.983mm)(170.51mm,37.883mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-5(166.198mm,37.338mm) on Top Layer And Track (167.31mm,32.983mm)(167.31mm,37.883mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-6(166.198mm,36.068mm) on Top Layer And Track (167.31mm,32.983mm)(167.31mm,37.883mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-7(166.198mm,34.798mm) on Top Layer And Track (167.31mm,32.983mm)(167.31mm,37.883mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-8(166.198mm,33.528mm) on Top Layer And Track (167.31mm,32.983mm)(167.31mm,37.883mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R1-1(178.181mm,35.115mm) on Top Layer And Track (177.419mm,34.099mm)(177.419mm,34.608mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R1-1(178.181mm,35.115mm) on Top Layer And Track (178.943mm,34.099mm)(178.943mm,34.608mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R1-2(178.181mm,33.528mm) on Top Layer And Track (177.419mm,34.099mm)(177.419mm,34.608mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R1-2(178.181mm,33.528mm) on Top Layer And Track (178.943mm,34.099mm)(178.943mm,34.608mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R2-1(175.768mm,33.528mm) on Top Layer And Track (174.752mm,32.766mm)(175.26mm,32.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R2-1(175.768mm,33.528mm) on Top Layer And Track (174.752mm,34.29mm)(175.26mm,34.29mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R2-2(174.18mm,33.528mm) on Top Layer And Track (174.752mm,32.766mm)(175.26mm,32.766mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R2-2(174.18mm,33.528mm) on Top Layer And Track (174.752mm,34.29mm)(175.26mm,34.29mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R3-1(171.196mm,39.497mm) on Top Layer And Track (171.704mm,38.735mm)(172.212mm,38.735mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R3-1(171.196mm,39.497mm) on Top Layer And Track (171.704mm,40.259mm)(172.212mm,40.259mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R3-2(172.784mm,39.497mm) on Top Layer And Track (171.704mm,38.735mm)(172.212mm,38.735mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R3-2(172.784mm,39.497mm) on Top Layer And Track (171.704mm,40.259mm)(172.212mm,40.259mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R4-1(163.83mm,37.973mm) on Top Layer And Track (162.814mm,37.211mm)(163.322mm,37.211mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R4-1(163.83mm,37.973mm) on Top Layer And Track (162.814mm,37.211mm)(163.322mm,37.211mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R4-1(163.83mm,37.973mm) on Top Layer And Track (162.814mm,38.735mm)(163.322mm,38.735mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R4-2(162.243mm,37.973mm) on Top Layer And Track (162.814mm,37.211mm)(163.322mm,37.211mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R4-2(162.243mm,37.973mm) on Top Layer And Track (162.814mm,37.211mm)(163.322mm,37.211mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R4-2(162.243mm,37.973mm) on Top Layer And Track (162.814mm,38.735mm)(163.322mm,38.735mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R5-1(163.83mm,36.449mm) on Top Layer And Track (162.75mm,35.687mm)(163.258mm,35.687mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R5-1(163.83mm,36.449mm) on Top Layer And Track (162.814mm,35.687mm)(163.322mm,35.687mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R5-1(163.83mm,36.449mm) on Top Layer And Track (162.814mm,37.211mm)(163.322mm,37.211mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R5-1(163.83mm,36.449mm) on Top Layer And Track (162.814mm,37.211mm)(163.322mm,37.211mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R5-2(162.243mm,36.449mm) on Top Layer And Track (162.75mm,35.687mm)(163.258mm,35.687mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R5-2(162.243mm,36.449mm) on Top Layer And Track (162.814mm,35.687mm)(163.322mm,35.687mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R5-2(162.243mm,36.449mm) on Top Layer And Track (162.814mm,37.211mm)(163.322mm,37.211mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R5-2(162.243mm,36.449mm) on Top Layer And Track (162.814mm,37.211mm)(163.322mm,37.211mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+Rule Violations :65
 
 Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All)
-Rule Violations :0
+   Violation between Silk To Silk Clearance Constraint: (0.241mm < 0.254mm) Between Text "R2" (177.258mm,33.795mm) on Top Overlay And Track (177.419mm,34.099mm)(177.419mm,34.608mm) on Top Overlay Silk Text to Silk Clearance [0.241mm]
+Rule Violations :1
 
 Processing Rule : Net Antennae (Tolerance=0mm) (All)
 Rule Violations :0
@@ -105,6 +109,6 @@ Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (Al
 Rule Violations :0
 
 
-Violations Detected : 62
+Violations Detected : 66
 Waived Violations : 0
 Time Elapsed        : 00:00:01

cap_test_unit/cap_test_unit.PrjPcb

@@ -23,26 +23,15 @@ DefaultPcbPcad=0
 ReorderDocumentsOnCompile=1
 NameNetsHierarchically=0
 PowerPortNamesTakePriority=0
-AutoSheetNumbering=1
-AutoCrossReferences=1
-NewIndexingOfSheetSymbols=1
 PushECOToAnnotationFile=1
 DItemRevisionGUID=
 ReportSuppressedErrorsInMessages=0
 FSMCodingStyle=eFMSDropDownList_OneProcess
 FSMEncodingStyle=eFMSDropDownList_OneHot
-IsProjectConflictPreventionWarningsEnabled=0
-IsVirtualBomDocumentRemoved=0
 OutputPath=
 LogFolderPath=
 ManagedProjectGUID=
 IncludeDesignInRelease=0
-CrossRefSheetStyle=1
-CrossRefLocationStyle=1
-CrossRefPorts=3
-CrossRefCrossSheets=1
-CrossRefSheetEntries=0
-CrossRefFollowFromMainSettings=1
 
 [Preferences]
 PrefsVaultGUID=
@@ -82,6 +71,112 @@ DItemRevisionGUID=
 GenerateClassCluster=0
 DocumentUniqueId=DAEQFUHC
 
+[Document3]
+DocumentPath=..\..\..\..\..\..\OneDrive\Рабочий стол\altium_lib\NEW-MODUL.PcbLib
+AnnotationEnabled=1
+AnnotateStartValue=1
+AnnotationIndexControlEnabled=0
+AnnotateSuffix=
+AnnotateScope=All
+AnnotateOrder=-1
+DoLibraryUpdate=1
+DoDatabaseUpdate=1
+ClassGenCCAutoEnabled=1
+ClassGenCCAutoRoomEnabled=1
+ClassGenNCAutoScope=None
+DItemRevisionGUID=
+GenerateClassCluster=0
+DocumentUniqueId=
+
+[Document4]
+DocumentPath=..\..\..\..\..\..\OneDrive\Рабочий стол\altium_lib\NEW-MODUL.SchLib
+AnnotationEnabled=1
+AnnotateStartValue=1
+AnnotationIndexControlEnabled=0
+AnnotateSuffix=
+AnnotateScope=All
+AnnotateOrder=-1
+DoLibraryUpdate=1
+DoDatabaseUpdate=1
+ClassGenCCAutoEnabled=1
+ClassGenCCAutoRoomEnabled=1
+ClassGenNCAutoScope=None
+DItemRevisionGUID=
+GenerateClassCluster=0
+DocumentUniqueId=
+
+[Document5]
+DocumentPath=..\..\..\..\..\..\OneDrive\Рабочий стол\altium_lib\SamacSys.PcbLib
+AnnotationEnabled=1
+AnnotateStartValue=1
+AnnotationIndexControlEnabled=0
+AnnotateSuffix=
+AnnotateScope=All
+AnnotateOrder=-1
+DoLibraryUpdate=1
+DoDatabaseUpdate=1
+ClassGenCCAutoEnabled=1
+ClassGenCCAutoRoomEnabled=1
+ClassGenNCAutoScope=None
+DItemRevisionGUID=
+GenerateClassCluster=0
+DocumentUniqueId=
+
+[Document6]
+DocumentPath=..\..\..\..\..\..\OneDrive\Рабочий стол\altium_lib\SamacSys.SchLib
+AnnotationEnabled=1
+AnnotateStartValue=1
+AnnotationIndexControlEnabled=0
+AnnotateSuffix=
+AnnotateScope=All
+AnnotateOrder=-1
+DoLibraryUpdate=1
+DoDatabaseUpdate=1
+ClassGenCCAutoEnabled=1
+ClassGenCCAutoRoomEnabled=1
+ClassGenNCAutoScope=None
+DItemRevisionGUID=
+GenerateClassCluster=0
+DocumentUniqueId=
+
+[Document7]
+DocumentPath=..\..\..\..\..\..\OneDrive\Рабочий стол\altium_lib\Разъемы.PcbLib
+AnnotationEnabled=1
+AnnotateStartValue=1
+AnnotationIndexControlEnabled=0
+AnnotateSuffix=
+AnnotateScope=All
+AnnotateOrder=-1
+DoLibraryUpdate=1
+DoDatabaseUpdate=1
+ClassGenCCAutoEnabled=1
+ClassGenCCAutoRoomEnabled=1
+ClassGenNCAutoScope=None
+DItemRevisionGUID=
+GenerateClassCluster=0
+DocumentUniqueId=
+
+[Document8]
+DocumentPath=..\..\..\..\..\..\OneDrive\Рабочий стол\altium_lib\Разъемы.SchLib
+AnnotationEnabled=1
+AnnotateStartValue=1
+AnnotationIndexControlEnabled=0
+AnnotateSuffix=
+AnnotateScope=All
+AnnotateOrder=-1
+DoLibraryUpdate=1
+DoDatabaseUpdate=1
+ClassGenCCAutoEnabled=1
+ClassGenCCAutoRoomEnabled=1
+ClassGenNCAutoScope=None
+DItemRevisionGUID=
+GenerateClassCluster=0
+DocumentUniqueId=
+
+[GeneratedDocument1]
+DocumentPath=Project Outputs for cap_test_unit\Design Rule Check - PCB1.html
+DItemRevisionGUID=
+
 [Configuration1]
 Name=Sources
 ParameterCount=0
@@ -197,27 +292,17 @@ OutputName20=WireList Netlist
 OutputDocumentPath20=
 OutputVariantName20=
 OutputDefault20=0
-OutputType21=XSpiceNetlist
-OutputName21=Mixed Sim Netlist
-OutputDocumentPath21=
-OutputVariantName21=
-OutputDefault21=0
 
 [OutputGroup2]
 Name=Simulator Outputs
 Description=
-TargetPrinter=Microsoft Print to PDF
+TargetPrinter=HP60AB1A (HP LaserJet Pro M428f-M429f)
 PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
-OutputType1=AdvSimNetlist
-OutputName1=Mixed Sim
-OutputDocumentPath1=
-OutputVariantName1=
-OutputDefault1=0
 
 [OutputGroup3]
 Name=Documentation Outputs
 Description=
-TargetPrinter=Microsoft Print to PDF
+TargetPrinter=Virtual Printer
 PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
 OutputType1=Composite
 OutputName1=Composite Drawing
@@ -225,90 +310,66 @@ OutputDocumentPath1=
 OutputVariantName1=[No Variations]
 OutputDefault1=0
 PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
-OutputType2=Harness Layout Drawing Print
-OutputName2=Harness Layout Drawing Prints
+OutputType2=PCB 3D Print
+OutputName2=PCB 3D Print
 OutputDocumentPath2=
-OutputVariantName2=
+OutputVariantName2=[No Variations]
 OutputDefault2=0
 PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
-OutputType3=Harness Wiring Diagram Print
-OutputName3=Harness Wiring Diagram Prints
+OutputType3=PCB 3D Video
+OutputName3=PCB 3D Video
 OutputDocumentPath3=
-OutputVariantName3=
+OutputVariantName3=[No Variations]
 OutputDefault3=0
 PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
-OutputType4=PCB 3D Print
-OutputName4=PCB 3D Print
+OutputType4=PCB Print
+OutputName4=PCB Prints
 OutputDocumentPath4=
 OutputVariantName4=[No Variations]
 OutputDefault4=0
 PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
-OutputType5=PCB 3D Video
-OutputName5=PCB 3D Video
+OutputType5=PCBDrawing
+OutputName5=Draftsman
 OutputDocumentPath5=
 OutputVariantName5=[No Variations]
 OutputDefault5=0
 PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
-OutputType6=PCB Print
-OutputName6=PCB Prints
+OutputType6=PCBLIB Print
+OutputName6=PCBLIB Prints
 OutputDocumentPath6=
-OutputVariantName6=[No Variations]
+OutputVariantName6=
 OutputDefault6=0
 PageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
-OutputType7=PCBDrawing
-OutputName7=Draftsman
+OutputType7=PDF3D
+OutputName7=PDF3D
 OutputDocumentPath7=
 OutputVariantName7=[No Variations]
 OutputDefault7=0
 PageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
-OutputType8=PCBDrawing
-OutputName8=Draftsman
+OutputType8=PDF3D MBA
+OutputName8=PDF3D MBA
 OutputDocumentPath8=
-OutputVariantName8=[No Variations]
+OutputVariantName8=
 OutputDefault8=0
 PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
-OutputType9=PCBDrawing
-OutputName9=Draftsman
+OutputType9=Report Print
+OutputName9=Report Prints
 OutputDocumentPath9=
-OutputVariantName9=[No Variations]
+OutputVariantName9=
 OutputDefault9=0
 PageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
-OutputType10=PCBLIB Print
-OutputName10=PCBLIB Prints
+OutputType10=Schematic Print
+OutputName10=Schematic Prints
 OutputDocumentPath10=
-OutputVariantName10=[No Variations]
+OutputVariantName10=
 OutputDefault10=0
 PageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
-OutputType11=PDF3D
-OutputName11=PDF3D
+OutputType11=SimView Print
+OutputName11=SimView Prints
 OutputDocumentPath11=
-OutputVariantName11=[No Variations]
+OutputVariantName11=
 OutputDefault11=0
 PageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
-OutputType12=PDF3D MBA
-OutputName12=PDF3D MBA
-OutputDocumentPath12=
-OutputVariantName12=
-OutputDefault12=0
-PageOptions12=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
-OutputType13=Report Print
-OutputName13=Report Prints
-OutputDocumentPath13=
-OutputVariantName13=
-OutputDefault13=0
-PageOptions13=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
-OutputType14=Schematic Print
-OutputName14=Schematic Prints
-OutputDocumentPath14=
-OutputVariantName14=
-OutputDefault14=0
-PageOptions14=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
-OutputType15=SimView Print
-OutputName15=SimView Prints
-OutputDocumentPath15=
-OutputVariantName15=
-OutputDefault15=0
-PageOptions15=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
 
 [OutputGroup4]
 Name=Assembly Outputs
@@ -415,49 +476,31 @@ OutputDocumentPath1=
 OutputVariantName1=[No Variations]
 OutputDefault1=0
 PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
-OutputType2=BOM_ReportCompare
-OutputName2=BOM Compare
+OutputType2=ComponentCrossReference
+OutputName2=Component Cross Reference Report
 OutputDocumentPath2=
 OutputVariantName2=[No Variations]
 OutputDefault2=0
-PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
-OutputType3=ComponentCrossReference
-OutputName3=Component Cross Reference Report
+OutputType3=ReportHierarchy
+OutputName3=Report Project Hierarchy
 OutputDocumentPath3=
 OutputVariantName3=[No Variations]
 OutputDefault3=0
-OutputType4=Export Comments
-OutputName4=Export Comments
+OutputType4=Script
+OutputName4=Script Output
 OutputDocumentPath4=
 OutputVariantName4=[No Variations]
 OutputDefault4=0
-PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
-OutputType5=Project History
-OutputName5=Project History
+OutputType5=SimpleBOM
+OutputName5=Simple BOM
 OutputDocumentPath5=
 OutputVariantName5=[No Variations]
 OutputDefault5=0
-PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
-OutputType6=ReportHierarchy
-OutputName6=Report Project Hierarchy
+OutputType6=SinglePinNetReporter
+OutputName6=Report Single Pin Nets
 OutputDocumentPath6=
 OutputVariantName6=[No Variations]
 OutputDefault6=0
-OutputType7=Script
-OutputName7=Script Output
-OutputDocumentPath7=
-OutputVariantName7=[No Variations]
-OutputDefault7=0
-OutputType8=SimpleBOM
-OutputName8=Simple BOM
-OutputDocumentPath8=
-OutputVariantName8=[No Variations]
-OutputDefault8=0
-OutputType9=SinglePinNetReporter
-OutputName9=Report Single Pin Nets
-OutputDocumentPath9=
-OutputVariantName9=[No Variations]
-OutputDefault9=0
 
 [OutputGroup7]
 Name=Other Outputs
@@ -671,11 +714,6 @@ OutputName11=Specctra Design PCB
 OutputDocumentPath11=
 OutputVariantName11=
 OutputDefault11=0
-OutputType12=Web ReviewOutputName
-OutputName12=Web Review Data
-OutputDocumentPath12=
-OutputVariantName12=
-OutputDefault12=0
 
 [OutputGroup10]
 Name=PostProcess Outputs
@@ -808,23 +846,6 @@ Type116=1
 Type117=1
 Type118=1
 Type119=1
-Type120=1
-Type121=1
-Type122=1
-Type123=1
-Type124=1
-Type125=1
-Type126=1
-Type127=1
-Type128=1
-Type129=1
-Type130=1
-Type131=1
-Type132=1
-Type133=1
-Type134=1
-Type135=1
-Type136=1
 
 [Difference Levels]
 Type1=1
@@ -895,12 +916,6 @@ Type65=1
 Type66=1
 Type67=1
 Type68=1
-Type69=1
-Type70=1
-Type71=1
-Type72=1
-Type73=1
-Type74=1
 
 [Electrical Rules Check]
 Type1=1
@@ -914,8 +929,8 @@ Type8=1
 Type9=1
 Type10=1
 Type11=2
-Type12=2
-Type13=2
+Type12=0
+Type13=0
 Type14=1
 Type15=1
 Type16=1
@@ -1026,34 +1041,6 @@ MultiChannelAlternate=0
 AlternateItemFail=3
 Type122=2
 Type123=1
-Type124=1
-Type125=1
-Type126=1
-Type127=1
-Type128=2
-Type129=2
-Type130=2
-Type131=2
-Type132=2
-Type133=2
-Type134=2
-Type135=2
-Type136=2
-Type137=2
-Type138=1
-Type139=1
-Type140=1
-Type141=1
-Type142=1
-Type143=1
-Type144=1
-Type145=1
-Type146=1
-Type147=2
-Type148=2
-Type149=2
-Type150=2
-Type151=2
 
 [ERC Connection Matrix]
 L1=NNNNNNNNNNNWNNNWW
@@ -1096,10 +1083,52 @@ NetClassManualEnabled=1
 NetClassSeparateForBusSections=0
 
 [LibraryUpdateOptions]
-SelectedOnly=0
+SelectedOnly=1
 UpdateVariants=1
 UpdateToLatestRevision=1
 PartTypes=0
+ComponentLibIdentifierKind0=Library Name And Type
+ComponentLibraryIdentifier0=NEW-MODUL.SchLib
+ComponentDesignItemID0=C0603
+ComponentSymbolReference0=C0603
+ComponentUpdate0=1
+ComponentIsDeviceSheet0=0
+ComponentLibIdentifierKind1=Library Name And Type
+ComponentLibraryIdentifier1=NEW-MODUL.SchLib
+ComponentDesignItemID1=R0603
+ComponentSymbolReference1=R0603
+ComponentUpdate1=1
+ComponentIsDeviceSheet1=0
+ComponentLibIdentifierKind2=Library Name And Type
+ComponentLibraryIdentifier2=SamacSys.SchLib
+ComponentDesignItemID2=DG300-5.0-02P-12-00A_H_
+ComponentSymbolReference2=DG300-5.0-02P-12-00A_H_
+ComponentUpdate2=1
+ComponentIsDeviceSheet2=0
+ComponentLibIdentifierKind3=Library Name And Type
+ComponentLibraryIdentifier3=SamacSys.SchLib
+ComponentDesignItemID3=IRF630
+ComponentSymbolReference3=IRF630
+ComponentUpdate3=1
+ComponentIsDeviceSheet3=0
+ComponentLibIdentifierKind4=Library Name And Type
+ComponentLibraryIdentifier4=SamacSys.SchLib
+ComponentDesignItemID4=R2512
+ComponentSymbolReference4=R2512
+ComponentUpdate4=1
+ComponentIsDeviceSheet4=0
+ComponentLibIdentifierKind5=Library Name And Type
+ComponentLibraryIdentifier5=SamacSys.SchLib
+ComponentDesignItemID5=TL072CDT
+ComponentSymbolReference5=TL072CDT
+ComponentUpdate5=1
+ComponentIsDeviceSheet5=0
+ComponentLibIdentifierKind6=Library Name And Type
+ComponentLibraryIdentifier6=Разъемы.SchLib
+ComponentDesignItemID6=PLS-2
+ComponentSymbolReference6=PLS-2
+ComponentUpdate6=1
+ComponentIsDeviceSheet6=0
 FullReplace=1
 UpdateDesignatorLock=1
 UpdatePartIDLock=1
@@ -1113,6 +1142,55 @@ RemoveParameters=0
 AddModels=1
 RemoveModels=1
 UpdateCurrentModels=1
+ParameterName0=Arrow Part Number
+ParameterUpdate0=1
+ParameterName1=Arrow Price/Stock
+ParameterUpdate1=1
+ParameterName2=Comment
+ParameterUpdate2=1
+ParameterName3=Component Kind
+ParameterUpdate3=1
+ParameterName4=Datasheet Link
+ParameterUpdate4=1
+ParameterName5=Description
+ParameterUpdate5=1
+ParameterName6=Height
+ParameterUpdate6=1
+ParameterName7=Library Reference
+ParameterUpdate7=1
+ParameterName8=Manufacturer_Name
+ParameterUpdate8=1
+ParameterName9=Manufacturer_Part_Number
+ParameterUpdate9=1
+ParameterName10=Mouser Part Number
+ParameterUpdate10=1
+ParameterName11=Mouser Price/Stock
+ParameterUpdate11=1
+ParameterName12=Value
+ParameterUpdate12=1
+ModelTypeGroup0=PCBLIB
+ModelTypeUpdate0=1
+ModelType0=PCBLIB
+ModelName0=C0603
+ModelUpdate0=1
+ModelType1=PCBLIB
+ModelName1=DG3005002P1200AH
+ModelUpdate1=1
+ModelType2=PCBLIB
+ModelName2=PLS-2
+ModelUpdate2=1
+ModelType3=PCBLIB
+ModelName3=R0603
+ModelUpdate3=1
+ModelType4=PCBLIB
+ModelName4=RESC6434X90N
+ModelUpdate4=1
+ModelType5=PCBLIB
+ModelName5=SOIC127P600X175-8N
+ModelUpdate5=1
+ModelType6=PCBLIB
+ModelName6=TO-220_STM
+ModelUpdate6=1
 
 [DatabaseUpdateOptions]
 SelectedOnly=0
@@ -1121,12 +1199,12 @@ UpdateToLatestRevision=1
 PartTypes=0
 
 [Comparison Options]
-ComparisonOptions0=Kind=Net|MinPercent=75|MinMatch=3|ShowMatch=0|UseName=-1|InclAllRules=0
-ComparisonOptions1=Kind=Net Class|MinPercent=75|MinMatch=3|ShowMatch=0|UseName=-1|InclAllRules=0
-ComparisonOptions2=Kind=Component Class|MinPercent=75|MinMatch=3|ShowMatch=0|UseName=-1|InclAllRules=0
-ComparisonOptions3=Kind=Rule|MinPercent=75|MinMatch=3|ShowMatch=0|UseName=-1|InclAllRules=0
-ComparisonOptions4=Kind=Differential Pair|MinPercent=50|MinMatch=1|ShowMatch=0|UseName=0|InclAllRules=0
-ComparisonOptions5=Kind=Structure Class|MinPercent=75|MinMatch=3|ShowMatch=0|UseName=-1|InclAllRules=0
+ComparisonOptions0=Kind=Net|MinPercent=75|MinMatch=3|ShowMatch=0|Confirm=-1|UseName=-1|InclAllRules=0
+ComparisonOptions1=Kind=Net Class|MinPercent=75|MinMatch=3|ShowMatch=0|Confirm=-1|UseName=-1|InclAllRules=0
+ComparisonOptions2=Kind=Component Class|MinPercent=75|MinMatch=3|ShowMatch=0|Confirm=-1|UseName=-1|InclAllRules=0
+ComparisonOptions3=Kind=Rule|MinPercent=75|MinMatch=3|ShowMatch=0|Confirm=-1|UseName=-1|InclAllRules=0
+ComparisonOptions4=Kind=Differential Pair|MinPercent=50|MinMatch=1|ShowMatch=0|Confirm=0|UseName=0|InclAllRules=0
+ComparisonOptions5=Kind=Structure Class|MinPercent=75|MinMatch=3|ShowMatch=0|Confirm=-1|UseName=-1|InclAllRules=0
 
 [SmartPDF]
 PageOptions=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9

cap_test_unit/cap_test_unit.PrjPcbStructure

@@ -1 +1 @@
-Record=TopLevelDocument|FileName=Sheet1.SchDoc
+Record=TopLevelDocument|FileName=Sheet1.SchDoc|SheetNumber=1