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Design Rule Check - PCB2.drc

Design Rule Check - PCB2.drc 4.6 KB
История Исходник

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  1. Protel Design System Design Rule Check
    2. 

  2. PCB File : C:\Users\Public\Documents\Altium\Projects\cap_plate\PCB2.PcbDoc
    3. 

  3. Date     : 01.07.2024
    4. 

  4. Time     : 15:14:04
    5. 

  5. 

  6. Processing Rule : Clearance Constraint (Gap=10mil) (All),(All)
    7. 

  7. Rule Violations :0
    8. 

  8. 

  9. Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
    10. 

  10. Rule Violations :0
    11. 

  11. 

  12. Processing Rule : Un-Routed Net Constraint ( (All) )
    13. 

  13.    Violation between Un-Routed Net Constraint: Net GND Between Pad C1-1(2824.724mil,1590mil) on Multi-Layer And Pad C2-1(4760mil,1825mil) on Multi-Layer 
    14. 

  14.    Violation between Un-Routed Net Constraint: Net GND Between Pad XP3-1(1556.85mil,2420mil) on Multi-Layer And Pad C1-1(2824.724mil,1590mil) on Multi-Layer 
    15. 

  15.    Violation between Un-Routed Net Constraint: Net VCC2 Between Pad C1-2(3120mil,1590mil) on Multi-Layer And Pad R2-1(3440mil,3615mil) on Multi-Layer 
    16. 

  16.    Violation between Un-Routed Net Constraint: Net VCC2 Between Pad C1-2(3120mil,1590mil) on Multi-Layer And Pad XP1-2(5885mil,1715mil) on Multi-Layer 
    17. 

  17.    Violation between Un-Routed Net Constraint: Net GND Between Pad C2-1(4760mil,1825mil) on Multi-Layer And Pad XP1-1(5688.15mil,1715mil) on Multi-Layer 
    18. 

  18.    Violation between Un-Routed Net Constraint: Net GND Between Pad XP4-1(3868.15mil,3590mil) on Multi-Layer And Pad C2-1(4760mil,1825mil) on Multi-Layer 
    19. 

  19.    Violation between Un-Routed Net Constraint: Net VCC1 Between Pad C2-2(4366.299mil,1825mil) on Multi-Layer And Pad R1-1(5305mil,2815.157mil) on Multi-Layer 
    20. 

  20.    Violation between Un-Routed Net Constraint: Net VCC1 Between Pad C2-2(4366.299mil,1825mil) on Multi-Layer And Pad XP2-2(6880mil,1835mil) on Multi-Layer 
    21. 

  21.    Violation between Un-Routed Net Constraint: Net NetR1_2 Between Pad XP4-2(4065mil,3590mil) on Multi-Layer And Pad R1-2(5305mil,4075mil) on Multi-Layer 
    22. 

  22.    Violation between Un-Routed Net Constraint: Net NetR2_2 Between Pad XP3-2(1360mil,2420mil) on Multi-Layer And Pad R2-2(2180.157mil,3615mil) on Multi-Layer 
    23. 

  23.    Violation between Un-Routed Net Constraint: Net GND Between Pad XP1-1(5688.15mil,1715mil) on Multi-Layer And Pad XP2-1(6683.15mil,1835mil) on Multi-Layer 
    24. 

  24. Rule Violations :11
    25. 

  25. 

  26. Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
    27. 

  27. Rule Violations :0
    28. 

  28. 

  29. Processing Rule : Width Constraint (Min=10mil) (Max=10mil) (Preferred=10mil) (All)
    30. 

  30. Rule Violations :0
    31. 

  31. 

  32. Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
    33. 

  33. Rule Violations :0
    34. 

  34. 

  35. Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (All)
    36. 

  36. Rule Violations :0
    37. 

  37. 

  38. Processing Rule : Hole To Hole Clearance (Gap=10mil) (All),(All)
    39. 

  39. Rule Violations :0
    40. 

  40. 

  41. Processing Rule : Minimum Solder Mask Sliver (Gap=10mil) (All),(All)
    42. 

  42. Rule Violations :0
    43. 

  43. 

  44. Processing Rule : Silk To Solder Mask (Clearance=10mil) (IsPad),(All)
    45. 

  45. Rule Violations :0
    46. 

  46. 

  47. Processing Rule : Silk to Silk (Clearance=10mil) (All),(All)
    48. 

  48. Rule Violations :0
    49. 

  49. 

  50. Processing Rule : Net Antennae (Tolerance=0mil) (All)
    51. 

  51. Rule Violations :0
    52. 

  52. 

  53. Processing Rule : Room Sheet3 (Bounding Region = (7045mil, 1060mil, 8165mil, 1610mil) (InComponentClass('Sheet3'))
    54. 

  54.    Violation between Room Definition: Between Room Sheet3 (Bounding Region = (7045mil, 1060mil, 8165mil, 1610mil) (InComponentClass('Sheet3')) And Small Component C1-2200uF (2824.724mil,1590mil) on Top Layer 
    55. 

  55.    Violation between Room Definition: Between Room Sheet3 (Bounding Region = (7045mil, 1060mil, 8165mil, 1610mil) (InComponentClass('Sheet3')) And Small Component C2-1500uF (4760mil,1825mil) on Top Layer 
    56. 

  56.    Violation between Room Definition: Between Room Sheet3 (Bounding Region = (7045mil, 1060mil, 8165mil, 1610mil) (InComponentClass('Sheet3')) And Small Component R1-2 Îì (5305mil,2815.157mil) on Top Layer 
    57. 

  57.    Violation between Room Definition: Between Room Sheet3 (Bounding Region = (7045mil, 1060mil, 8165mil, 1610mil) (InComponentClass('Sheet3')) And Small Component R2-2 Îì (3440mil,3615mil) on Top Layer 
    58. 

  58.    Violation between Room Definition: Between Room Sheet3 (Bounding Region = (7045mil, 1060mil, 8165mil, 1610mil) (InComponentClass('Sheet3')) And Small Component XP3-DG300-5.0-02P-12-00A_H_ (1556.85mil,2420mil) on Top Layer 
    59. 

  59.    Violation between Room Definition: Between Room Sheet3 (Bounding Region = (7045mil, 1060mil, 8165mil, 1610mil) (InComponentClass('Sheet3')) And Small Component XP4-DG300-5.0-02P-12-00A_H_ (3868.15mil,3590mil) on Top Layer 
    60. 

  60. Rule Violations :6
    61. 

  61. 

  62. Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
    63. 

  63.    Violation between Height Constraint: Small Component C1-2200uF (2824.724mil,1590mil) on Top Layer Actual Height = 1318.898mil
    64. 

  64. Rule Violations :1
    65. 

  65. 

  66. 

  67. Violations Detected : 18
    68. 

  68. Waived Violations : 0
    69. 

  69. Time Elapsed        : 00:00:01
    70.