stm32f10x_cec.c 11 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f10x_cec.c
  4. * @author MCD Application Team
  5. * @version V3.5.0
  6. * @date 11-March-2011
  7. * @brief This file provides all the CEC firmware functions.
  8. ******************************************************************************
  9. * @attention
  10. *
  11. * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  12. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  13. * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  14. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  15. * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  16. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  17. *
  18. * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
  19. ******************************************************************************
  20. */
  21. /* Includes ------------------------------------------------------------------*/
  22. #include "stm32f10x_cec.h"
  23. #include "stm32f10x_rcc.h"
  24. /** @addtogroup STM32F10x_StdPeriph_Driver
  25. * @{
  26. */
  27. /** @defgroup CEC
  28. * @brief CEC driver modules
  29. * @{
  30. */
  31. /** @defgroup CEC_Private_TypesDefinitions
  32. * @{
  33. */
  34. /**
  35. * @}
  36. */
  37. /** @defgroup CEC_Private_Defines
  38. * @{
  39. */
  40. /* ------------ CEC registers bit address in the alias region ----------- */
  41. #define CEC_OFFSET (CEC_BASE - PERIPH_BASE)
  42. /* --- CFGR Register ---*/
  43. /* Alias word address of PE bit */
  44. #define CFGR_OFFSET (CEC_OFFSET + 0x00)
  45. #define PE_BitNumber 0x00
  46. #define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))
  47. /* Alias word address of IE bit */
  48. #define IE_BitNumber 0x01
  49. #define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))
  50. /* --- CSR Register ---*/
  51. /* Alias word address of TSOM bit */
  52. #define CSR_OFFSET (CEC_OFFSET + 0x10)
  53. #define TSOM_BitNumber 0x00
  54. #define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))
  55. /* Alias word address of TEOM bit */
  56. #define TEOM_BitNumber 0x01
  57. #define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))
  58. #define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */
  59. #define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */
  60. /**
  61. * @}
  62. */
  63. /** @defgroup CEC_Private_Macros
  64. * @{
  65. */
  66. /**
  67. * @}
  68. */
  69. /** @defgroup CEC_Private_Variables
  70. * @{
  71. */
  72. /**
  73. * @}
  74. */
  75. /** @defgroup CEC_Private_FunctionPrototypes
  76. * @{
  77. */
  78. /**
  79. * @}
  80. */
  81. /** @defgroup CEC_Private_Functions
  82. * @{
  83. */
  84. /**
  85. * @brief Deinitializes the CEC peripheral registers to their default reset
  86. * values.
  87. * @param None
  88. * @retval None
  89. */
  90. void CEC_DeInit(void)
  91. {
  92. /* Enable CEC reset state */
  93. RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);
  94. /* Release CEC from reset state */
  95. RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE);
  96. }
  97. /**
  98. * @brief Initializes the CEC peripheral according to the specified
  99. * parameters in the CEC_InitStruct.
  100. * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that
  101. * contains the configuration information for the specified
  102. * CEC peripheral.
  103. * @retval None
  104. */
  105. void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
  106. {
  107. uint16_t tmpreg = 0;
  108. /* Check the parameters */
  109. assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode));
  110. assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));
  111. /*---------------------------- CEC CFGR Configuration -----------------*/
  112. /* Get the CEC CFGR value */
  113. tmpreg = CEC->CFGR;
  114. /* Clear BTEM and BPEM bits */
  115. tmpreg &= CFGR_CLEAR_Mask;
  116. /* Configure CEC: Bit Timing Error and Bit Period Error */
  117. tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);
  118. /* Write to CEC CFGR register*/
  119. CEC->CFGR = tmpreg;
  120. }
  121. /**
  122. * @brief Enables or disables the specified CEC peripheral.
  123. * @param NewState: new state of the CEC peripheral.
  124. * This parameter can be: ENABLE or DISABLE.
  125. * @retval None
  126. */
  127. void CEC_Cmd(FunctionalState NewState)
  128. {
  129. /* Check the parameters */
  130. assert_param(IS_FUNCTIONAL_STATE(NewState));
  131. *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;
  132. if(NewState == DISABLE)
  133. {
  134. /* Wait until the PE bit is cleared by hardware (Idle Line detected) */
  135. while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)
  136. {
  137. }
  138. }
  139. }
  140. /**
  141. * @brief Enables or disables the CEC interrupt.
  142. * @param NewState: new state of the CEC interrupt.
  143. * This parameter can be: ENABLE or DISABLE.
  144. * @retval None
  145. */
  146. void CEC_ITConfig(FunctionalState NewState)
  147. {
  148. /* Check the parameters */
  149. assert_param(IS_FUNCTIONAL_STATE(NewState));
  150. *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState;
  151. }
  152. /**
  153. * @brief Defines the Own Address of the CEC device.
  154. * @param CEC_OwnAddress: The CEC own address
  155. * @retval None
  156. */
  157. void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
  158. {
  159. /* Check the parameters */
  160. assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
  161. /* Set the CEC own address */
  162. CEC->OAR = CEC_OwnAddress;
  163. }
  164. /**
  165. * @brief Sets the CEC prescaler value.
  166. * @param CEC_Prescaler: CEC prescaler new value
  167. * @retval None
  168. */
  169. void CEC_SetPrescaler(uint16_t CEC_Prescaler)
  170. {
  171. /* Check the parameters */
  172. assert_param(IS_CEC_PRESCALER(CEC_Prescaler));
  173. /* Set the Prescaler value*/
  174. CEC->PRES = CEC_Prescaler;
  175. }
  176. /**
  177. * @brief Transmits single data through the CEC peripheral.
  178. * @param Data: the data to transmit.
  179. * @retval None
  180. */
  181. void CEC_SendDataByte(uint8_t Data)
  182. {
  183. /* Transmit Data */
  184. CEC->TXD = Data ;
  185. }
  186. /**
  187. * @brief Returns the most recent received data by the CEC peripheral.
  188. * @param None
  189. * @retval The received data.
  190. */
  191. uint8_t CEC_ReceiveDataByte(void)
  192. {
  193. /* Receive Data */
  194. return (uint8_t)(CEC->RXD);
  195. }
  196. /**
  197. * @brief Starts a new message.
  198. * @param None
  199. * @retval None
  200. */
  201. void CEC_StartOfMessage(void)
  202. {
  203. /* Starts of new message */
  204. *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1;
  205. }
  206. /**
  207. * @brief Transmits message with or without an EOM bit.
  208. * @param NewState: new state of the CEC Tx End Of Message.
  209. * This parameter can be: ENABLE or DISABLE.
  210. * @retval None
  211. */
  212. void CEC_EndOfMessageCmd(FunctionalState NewState)
  213. {
  214. /* Check the parameters */
  215. assert_param(IS_FUNCTIONAL_STATE(NewState));
  216. /* The data byte will be transmitted with or without an EOM bit*/
  217. *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState;
  218. }
  219. /**
  220. * @brief Gets the CEC flag status
  221. * @param CEC_FLAG: specifies the CEC flag to check.
  222. * This parameter can be one of the following values:
  223. * @arg CEC_FLAG_BTE: Bit Timing Error
  224. * @arg CEC_FLAG_BPE: Bit Period Error
  225. * @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error
  226. * @arg CEC_FLAG_SBE: Start Bit Error
  227. * @arg CEC_FLAG_ACKE: Block Acknowledge Error
  228. * @arg CEC_FLAG_LINE: Line Error
  229. * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error
  230. * @arg CEC_FLAG_TEOM: Tx End Of Message
  231. * @arg CEC_FLAG_TERR: Tx Error
  232. * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
  233. * @arg CEC_FLAG_RSOM: Rx Start Of Message
  234. * @arg CEC_FLAG_REOM: Rx End Of Message
  235. * @arg CEC_FLAG_RERR: Rx Error
  236. * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
  237. * @retval The new state of CEC_FLAG (SET or RESET)
  238. */
  239. FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG)
  240. {
  241. FlagStatus bitstatus = RESET;
  242. uint32_t cecreg = 0, cecbase = 0;
  243. /* Check the parameters */
  244. assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
  245. /* Get the CEC peripheral base address */
  246. cecbase = (uint32_t)(CEC_BASE);
  247. /* Read flag register index */
  248. cecreg = CEC_FLAG >> 28;
  249. /* Get bit[23:0] of the flag */
  250. CEC_FLAG &= FLAG_Mask;
  251. if(cecreg != 0)
  252. {
  253. /* Flag in CEC ESR Register */
  254. CEC_FLAG = (uint32_t)(CEC_FLAG >> 16);
  255. /* Get the CEC ESR register address */
  256. cecbase += 0xC;
  257. }
  258. else
  259. {
  260. /* Get the CEC CSR register address */
  261. cecbase += 0x10;
  262. }
  263. if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET)
  264. {
  265. /* CEC_FLAG is set */
  266. bitstatus = SET;
  267. }
  268. else
  269. {
  270. /* CEC_FLAG is reset */
  271. bitstatus = RESET;
  272. }
  273. /* Return the CEC_FLAG status */
  274. return bitstatus;
  275. }
  276. /**
  277. * @brief Clears the CEC's pending flags.
  278. * @param CEC_FLAG: specifies the flag to clear.
  279. * This parameter can be any combination of the following values:
  280. * @arg CEC_FLAG_TERR: Tx Error
  281. * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
  282. * @arg CEC_FLAG_RSOM: Rx Start Of Message
  283. * @arg CEC_FLAG_REOM: Rx End Of Message
  284. * @arg CEC_FLAG_RERR: Rx Error
  285. * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
  286. * @retval None
  287. */
  288. void CEC_ClearFlag(uint32_t CEC_FLAG)
  289. {
  290. uint32_t tmp = 0x0;
  291. /* Check the parameters */
  292. assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
  293. tmp = CEC->CSR & 0x2;
  294. /* Clear the selected CEC flags */
  295. CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp);
  296. }
  297. /**
  298. * @brief Checks whether the specified CEC interrupt has occurred or not.
  299. * @param CEC_IT: specifies the CEC interrupt source to check.
  300. * This parameter can be one of the following values:
  301. * @arg CEC_IT_TERR: Tx Error
  302. * @arg CEC_IT_TBTF: Tx Block Transfer Finished
  303. * @arg CEC_IT_RERR: Rx Error
  304. * @arg CEC_IT_RBTF: Rx Block Transfer Finished
  305. * @retval The new state of CEC_IT (SET or RESET).
  306. */
  307. ITStatus CEC_GetITStatus(uint8_t CEC_IT)
  308. {
  309. ITStatus bitstatus = RESET;
  310. uint32_t enablestatus = 0;
  311. /* Check the parameters */
  312. assert_param(IS_CEC_GET_IT(CEC_IT));
  313. /* Get the CEC IT enable bit status */
  314. enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ;
  315. /* Check the status of the specified CEC interrupt */
  316. if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus)
  317. {
  318. /* CEC_IT is set */
  319. bitstatus = SET;
  320. }
  321. else
  322. {
  323. /* CEC_IT is reset */
  324. bitstatus = RESET;
  325. }
  326. /* Return the CEC_IT status */
  327. return bitstatus;
  328. }
  329. /**
  330. * @brief Clears the CEC's interrupt pending bits.
  331. * @param CEC_IT: specifies the CEC interrupt pending bit to clear.
  332. * This parameter can be any combination of the following values:
  333. * @arg CEC_IT_TERR: Tx Error
  334. * @arg CEC_IT_TBTF: Tx Block Transfer Finished
  335. * @arg CEC_IT_RERR: Rx Error
  336. * @arg CEC_IT_RBTF: Rx Block Transfer Finished
  337. * @retval None
  338. */
  339. void CEC_ClearITPendingBit(uint16_t CEC_IT)
  340. {
  341. uint32_t tmp = 0x0;
  342. /* Check the parameters */
  343. assert_param(IS_CEC_GET_IT(CEC_IT));
  344. tmp = CEC->CSR & 0x2;
  345. /* Clear the selected CEC interrupt pending bits */
  346. CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp);
  347. }
  348. /**
  349. * @}
  350. */
  351. /**
  352. * @}
  353. */
  354. /**
  355. * @}
  356. */
  357. /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/