STM32_Devel/SOFT/stm32_f0_2/build/main.lst

build/main.elf:     file format elf32-littlearm


Disassembly of section .text:

080000c8 <SystemInit>:
  *         SystemCoreClock variable.
  * @param  None
  * @retval None
  */
void SystemInit (void)
{    
 80000c8:	b580      	push	{r7, lr}
 80000ca:	af00      	add	r7, sp, #0
  /* Set HSION bit */
  RCC->CR |= (uint32_t)0x00000001;
 80000cc:	4b1b      	ldr	r3, [pc, #108]	; (800013c <SystemInit+0x74>)
 80000ce:	4a1b      	ldr	r2, [pc, #108]	; (800013c <SystemInit+0x74>)
 80000d0:	6812      	ldr	r2, [r2, #0]
 80000d2:	2101      	movs	r1, #1
 80000d4:	430a      	orrs	r2, r1
 80000d6:	601a      	str	r2, [r3, #0]
#if defined(STM32F051)   
  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
  RCC->CFGR &= (uint32_t)0xF8FFB80C;
#else
  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
  RCC->CFGR &= (uint32_t)0x08FFB80C;
 80000d8:	4b18      	ldr	r3, [pc, #96]	; (800013c <SystemInit+0x74>)
 80000da:	4a18      	ldr	r2, [pc, #96]	; (800013c <SystemInit+0x74>)
 80000dc:	6852      	ldr	r2, [r2, #4]
 80000de:	4918      	ldr	r1, [pc, #96]	; (8000140 <SystemInit+0x78>)
 80000e0:	400a      	ands	r2, r1
 80000e2:	605a      	str	r2, [r3, #4]
#endif /* STM32F051 */
  
  /* Reset HSEON, CSSON and PLLON bits */
  RCC->CR &= (uint32_t)0xFEF6FFFF;
 80000e4:	4b15      	ldr	r3, [pc, #84]	; (800013c <SystemInit+0x74>)
 80000e6:	4a15      	ldr	r2, [pc, #84]	; (800013c <SystemInit+0x74>)
 80000e8:	6812      	ldr	r2, [r2, #0]
 80000ea:	4916      	ldr	r1, [pc, #88]	; (8000144 <SystemInit+0x7c>)
 80000ec:	400a      	ands	r2, r1
 80000ee:	601a      	str	r2, [r3, #0]

  /* Reset HSEBYP bit */
  RCC->CR &= (uint32_t)0xFFFBFFFF;
 80000f0:	4b12      	ldr	r3, [pc, #72]	; (800013c <SystemInit+0x74>)
 80000f2:	4a12      	ldr	r2, [pc, #72]	; (800013c <SystemInit+0x74>)
 80000f4:	6812      	ldr	r2, [r2, #0]
 80000f6:	4914      	ldr	r1, [pc, #80]	; (8000148 <SystemInit+0x80>)
 80000f8:	400a      	ands	r2, r1
 80000fa:	601a      	str	r2, [r3, #0]

  /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
  RCC->CFGR &= (uint32_t)0xFFC0FFFF;
 80000fc:	4b0f      	ldr	r3, [pc, #60]	; (800013c <SystemInit+0x74>)
 80000fe:	4a0f      	ldr	r2, [pc, #60]	; (800013c <SystemInit+0x74>)
 8000100:	6852      	ldr	r2, [r2, #4]
 8000102:	4912      	ldr	r1, [pc, #72]	; (800014c <SystemInit+0x84>)
 8000104:	400a      	ands	r2, r1
 8000106:	605a      	str	r2, [r3, #4]

  /* Reset PREDIV1[3:0] bits */
  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
 8000108:	4b0c      	ldr	r3, [pc, #48]	; (800013c <SystemInit+0x74>)
 800010a:	4a0c      	ldr	r2, [pc, #48]	; (800013c <SystemInit+0x74>)
 800010c:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
 800010e:	210f      	movs	r1, #15
 8000110:	438a      	bics	r2, r1
 8000112:	62da      	str	r2, [r3, #44]	; 0x2c

  /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
  RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
 8000114:	4b09      	ldr	r3, [pc, #36]	; (800013c <SystemInit+0x74>)
 8000116:	4a09      	ldr	r2, [pc, #36]	; (800013c <SystemInit+0x74>)
 8000118:	6b12      	ldr	r2, [r2, #48]	; 0x30
 800011a:	490d      	ldr	r1, [pc, #52]	; (8000150 <SystemInit+0x88>)
 800011c:	400a      	ands	r2, r1
 800011e:	631a      	str	r2, [r3, #48]	; 0x30

  /* Reset HSI14 bit */
  RCC->CR2 &= (uint32_t)0xFFFFFFFE;
 8000120:	4b06      	ldr	r3, [pc, #24]	; (800013c <SystemInit+0x74>)
 8000122:	4a06      	ldr	r2, [pc, #24]	; (800013c <SystemInit+0x74>)
 8000124:	6b52      	ldr	r2, [r2, #52]	; 0x34
 8000126:	2101      	movs	r1, #1
 8000128:	438a      	bics	r2, r1
 800012a:	635a      	str	r2, [r3, #52]	; 0x34

  /* Disable all interrupts */
  RCC->CIR = 0x00000000;
 800012c:	4b03      	ldr	r3, [pc, #12]	; (800013c <SystemInit+0x74>)
 800012e:	2200      	movs	r2, #0
 8000130:	609a      	str	r2, [r3, #8]

  /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
  SetSysClock();
 8000132:	f000 f879 	bl	8000228 <SetSysClock>
}
 8000136:	46bd      	mov	sp, r7
 8000138:	bd80      	pop	{r7, pc}
 800013a:	46c0      	nop			; (mov r8, r8)
 800013c:	40021000 	.word	0x40021000
 8000140:	08ffb80c 	.word	0x08ffb80c
 8000144:	fef6ffff 	.word	0xfef6ffff
 8000148:	fffbffff 	.word	0xfffbffff
 800014c:	ffc0ffff 	.word	0xffc0ffff
 8000150:	fffffeac 	.word	0xfffffeac

08000154 <SystemCoreClockUpdate>:
  *           value for HSE crystal.
  * @param  None
  * @retval None
  */
void SystemCoreClockUpdate (void)
{
 8000154:	b580      	push	{r7, lr}
 8000156:	b084      	sub	sp, #16
 8000158:	af00      	add	r7, sp, #0
  uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
 800015a:	2300      	movs	r3, #0
 800015c:	60fb      	str	r3, [r7, #12]
 800015e:	2300      	movs	r3, #0
 8000160:	60bb      	str	r3, [r7, #8]
 8000162:	2300      	movs	r3, #0
 8000164:	607b      	str	r3, [r7, #4]
 8000166:	2300      	movs	r3, #0
 8000168:	603b      	str	r3, [r7, #0]

  /* Get SYSCLK source -------------------------------------------------------*/
  tmp = RCC->CFGR & RCC_CFGR_SWS;
 800016a:	4b2a      	ldr	r3, [pc, #168]	; (8000214 <SystemCoreClockUpdate+0xc0>)
 800016c:	685b      	ldr	r3, [r3, #4]
 800016e:	220c      	movs	r2, #12
 8000170:	4013      	ands	r3, r2
 8000172:	60fb      	str	r3, [r7, #12]
  
  switch (tmp)
 8000174:	68fb      	ldr	r3, [r7, #12]
 8000176:	2b04      	cmp	r3, #4
 8000178:	d007      	beq.n	800018a <SystemCoreClockUpdate+0x36>
 800017a:	2b08      	cmp	r3, #8
 800017c:	d009      	beq.n	8000192 <SystemCoreClockUpdate+0x3e>
 800017e:	2b00      	cmp	r3, #0
 8000180:	d131      	bne.n	80001e6 <SystemCoreClockUpdate+0x92>
  {
    case 0x00:  /* HSI used as system clock */
      SystemCoreClock = HSI_VALUE;
 8000182:	4b25      	ldr	r3, [pc, #148]	; (8000218 <SystemCoreClockUpdate+0xc4>)
 8000184:	4a25      	ldr	r2, [pc, #148]	; (800021c <SystemCoreClockUpdate+0xc8>)
 8000186:	601a      	str	r2, [r3, #0]
      break;
 8000188:	e031      	b.n	80001ee <SystemCoreClockUpdate+0x9a>
    case 0x04:  /* HSE used as system clock */
      SystemCoreClock = HSE_VALUE;
 800018a:	4b23      	ldr	r3, [pc, #140]	; (8000218 <SystemCoreClockUpdate+0xc4>)
 800018c:	4a23      	ldr	r2, [pc, #140]	; (800021c <SystemCoreClockUpdate+0xc8>)
 800018e:	601a      	str	r2, [r3, #0]
      break;
 8000190:	e02d      	b.n	80001ee <SystemCoreClockUpdate+0x9a>
    case 0x08:  /* PLL used as system clock */
      /* Get PLL clock source and multiplication factor ----------------------*/
      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
 8000192:	4b20      	ldr	r3, [pc, #128]	; (8000214 <SystemCoreClockUpdate+0xc0>)
 8000194:	685a      	ldr	r2, [r3, #4]
 8000196:	23f0      	movs	r3, #240	; 0xf0
 8000198:	039b      	lsls	r3, r3, #14
 800019a:	4013      	ands	r3, r2
 800019c:	60bb      	str	r3, [r7, #8]
      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
 800019e:	4b1d      	ldr	r3, [pc, #116]	; (8000214 <SystemCoreClockUpdate+0xc0>)
 80001a0:	685a      	ldr	r2, [r3, #4]
 80001a2:	23c0      	movs	r3, #192	; 0xc0
 80001a4:	025b      	lsls	r3, r3, #9
 80001a6:	4013      	ands	r3, r2
 80001a8:	607b      	str	r3, [r7, #4]
      pllmull = ( pllmull >> 18) + 2;
 80001aa:	68bb      	ldr	r3, [r7, #8]
 80001ac:	0c9b      	lsrs	r3, r3, #18
 80001ae:	3302      	adds	r3, #2
 80001b0:	60bb      	str	r3, [r7, #8]
      
      if (pllsource == 0x00)
 80001b2:	687b      	ldr	r3, [r7, #4]
 80001b4:	2b00      	cmp	r3, #0
 80001b6:	d105      	bne.n	80001c4 <SystemCoreClockUpdate+0x70>
      {
        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
 80001b8:	68bb      	ldr	r3, [r7, #8]
 80001ba:	4a19      	ldr	r2, [pc, #100]	; (8000220 <SystemCoreClockUpdate+0xcc>)
 80001bc:	435a      	muls	r2, r3
 80001be:	4b16      	ldr	r3, [pc, #88]	; (8000218 <SystemCoreClockUpdate+0xc4>)
 80001c0:	601a      	str	r2, [r3, #0]
      {
        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
        /* HSE oscillator clock selected as PREDIV1 clock entry */
        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
      }      
      break;
 80001c2:	e014      	b.n	80001ee <SystemCoreClockUpdate+0x9a>
        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
      }
      else
      {
        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
 80001c4:	4b13      	ldr	r3, [pc, #76]	; (8000214 <SystemCoreClockUpdate+0xc0>)
 80001c6:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 80001c8:	220f      	movs	r2, #15
 80001ca:	4013      	ands	r3, r2
 80001cc:	3301      	adds	r3, #1
 80001ce:	603b      	str	r3, [r7, #0]
        /* HSE oscillator clock selected as PREDIV1 clock entry */
        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
 80001d0:	4812      	ldr	r0, [pc, #72]	; (800021c <SystemCoreClockUpdate+0xc8>)
 80001d2:	6839      	ldr	r1, [r7, #0]
 80001d4:	f002 faa8 	bl	8002728 <____aeabi_uidiv_from_thumb>
 80001d8:	1c03      	adds	r3, r0, #0
 80001da:	1c1a      	adds	r2, r3, #0
 80001dc:	68bb      	ldr	r3, [r7, #8]
 80001de:	435a      	muls	r2, r3
 80001e0:	4b0d      	ldr	r3, [pc, #52]	; (8000218 <SystemCoreClockUpdate+0xc4>)
 80001e2:	601a      	str	r2, [r3, #0]
      }      
      break;
 80001e4:	e003      	b.n	80001ee <SystemCoreClockUpdate+0x9a>
    default: /* HSI used as system clock */
      SystemCoreClock = HSI_VALUE;
 80001e6:	4b0c      	ldr	r3, [pc, #48]	; (8000218 <SystemCoreClockUpdate+0xc4>)
 80001e8:	4a0c      	ldr	r2, [pc, #48]	; (800021c <SystemCoreClockUpdate+0xc8>)
 80001ea:	601a      	str	r2, [r3, #0]
      break;
 80001ec:	46c0      	nop			; (mov r8, r8)
  }
  /* Compute HCLK clock frequency ----------------*/
  /* Get HCLK prescaler */
  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
 80001ee:	4b09      	ldr	r3, [pc, #36]	; (8000214 <SystemCoreClockUpdate+0xc0>)
 80001f0:	685b      	ldr	r3, [r3, #4]
 80001f2:	22f0      	movs	r2, #240	; 0xf0
 80001f4:	4013      	ands	r3, r2
 80001f6:	091b      	lsrs	r3, r3, #4
 80001f8:	4a0a      	ldr	r2, [pc, #40]	; (8000224 <SystemCoreClockUpdate+0xd0>)
 80001fa:	5cd3      	ldrb	r3, [r2, r3]
 80001fc:	b2db      	uxtb	r3, r3
 80001fe:	60fb      	str	r3, [r7, #12]
  /* HCLK clock frequency */
  SystemCoreClock >>= tmp;  
 8000200:	4b05      	ldr	r3, [pc, #20]	; (8000218 <SystemCoreClockUpdate+0xc4>)
 8000202:	681a      	ldr	r2, [r3, #0]
 8000204:	68fb      	ldr	r3, [r7, #12]
 8000206:	40da      	lsrs	r2, r3
 8000208:	4b03      	ldr	r3, [pc, #12]	; (8000218 <SystemCoreClockUpdate+0xc4>)
 800020a:	601a      	str	r2, [r3, #0]
}
 800020c:	46bd      	mov	sp, r7
 800020e:	b004      	add	sp, #16
 8000210:	bd80      	pop	{r7, pc}
 8000212:	46c0      	nop			; (mov r8, r8)
 8000214:	40021000 	.word	0x40021000
 8000218:	20000000 	.word	0x20000000
 800021c:	007a1200 	.word	0x007a1200
 8000220:	003d0900 	.word	0x003d0900
 8000224:	20000004 	.word	0x20000004

08000228 <SetSysClock>:
  *         is reset to the default reset state (done in SystemInit() function).
  * @param  None
  * @retval None
  */
static void SetSysClock(void)
{
 8000228:	b580      	push	{r7, lr}
 800022a:	b082      	sub	sp, #8
 800022c:	af00      	add	r7, sp, #0
  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
 800022e:	2300      	movs	r3, #0
 8000230:	607b      	str	r3, [r7, #4]
 8000232:	2300      	movs	r3, #0
 8000234:	603b      	str	r3, [r7, #0]
/*            PLL (clocked by HSE) used as System clock source                */
/******************************************************************************/
  
  /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
  /* Enable HSE */    
  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
 8000236:	4b31      	ldr	r3, [pc, #196]	; (80002fc <SetSysClock+0xd4>)
 8000238:	4a30      	ldr	r2, [pc, #192]	; (80002fc <SetSysClock+0xd4>)
 800023a:	6812      	ldr	r2, [r2, #0]
 800023c:	2180      	movs	r1, #128	; 0x80
 800023e:	0249      	lsls	r1, r1, #9
 8000240:	430a      	orrs	r2, r1
 8000242:	601a      	str	r2, [r3, #0]
 
  /* Wait till HSE is ready and if Time out is reached exit */
  do
  {
    HSEStatus = RCC->CR & RCC_CR_HSERDY;
 8000244:	4b2d      	ldr	r3, [pc, #180]	; (80002fc <SetSysClock+0xd4>)
 8000246:	681a      	ldr	r2, [r3, #0]
 8000248:	2380      	movs	r3, #128	; 0x80
 800024a:	029b      	lsls	r3, r3, #10
 800024c:	4013      	ands	r3, r2
 800024e:	603b      	str	r3, [r7, #0]
    StartUpCounter++;  
 8000250:	687b      	ldr	r3, [r7, #4]
 8000252:	3301      	adds	r3, #1
 8000254:	607b      	str	r3, [r7, #4]
  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
 8000256:	683b      	ldr	r3, [r7, #0]
 8000258:	2b00      	cmp	r3, #0
 800025a:	d104      	bne.n	8000266 <SetSysClock+0x3e>
 800025c:	687a      	ldr	r2, [r7, #4]
 800025e:	23a0      	movs	r3, #160	; 0xa0
 8000260:	01db      	lsls	r3, r3, #7
 8000262:	429a      	cmp	r2, r3
 8000264:	d1ee      	bne.n	8000244 <SetSysClock+0x1c>

  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
 8000266:	4b25      	ldr	r3, [pc, #148]	; (80002fc <SetSysClock+0xd4>)
 8000268:	681a      	ldr	r2, [r3, #0]
 800026a:	2380      	movs	r3, #128	; 0x80
 800026c:	029b      	lsls	r3, r3, #10
 800026e:	4013      	ands	r3, r2
 8000270:	d002      	beq.n	8000278 <SetSysClock+0x50>
  {
    HSEStatus = (uint32_t)0x01;
 8000272:	2301      	movs	r3, #1
 8000274:	603b      	str	r3, [r7, #0]
 8000276:	e001      	b.n	800027c <SetSysClock+0x54>
  }
  else
  {
    HSEStatus = (uint32_t)0x00;
 8000278:	2300      	movs	r3, #0
 800027a:	603b      	str	r3, [r7, #0]
  }  

  if (HSEStatus == (uint32_t)0x01)
 800027c:	683b      	ldr	r3, [r7, #0]
 800027e:	2b01      	cmp	r3, #1
 8000280:	d138      	bne.n	80002f4 <SetSysClock+0xcc>
  {
    /* Enable Prefetch Buffer and set Flash Latency */
    FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
 8000282:	4b1f      	ldr	r3, [pc, #124]	; (8000300 <SetSysClock+0xd8>)
 8000284:	2211      	movs	r2, #17
 8000286:	601a      	str	r2, [r3, #0]
 
    /* HCLK = SYSCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
 8000288:	4b1c      	ldr	r3, [pc, #112]	; (80002fc <SetSysClock+0xd4>)
 800028a:	4a1c      	ldr	r2, [pc, #112]	; (80002fc <SetSysClock+0xd4>)
 800028c:	6852      	ldr	r2, [r2, #4]
 800028e:	605a      	str	r2, [r3, #4]
      
    /* PCLK = HCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
 8000290:	4b1a      	ldr	r3, [pc, #104]	; (80002fc <SetSysClock+0xd4>)
 8000292:	4a1a      	ldr	r2, [pc, #104]	; (80002fc <SetSysClock+0xd4>)
 8000294:	6852      	ldr	r2, [r2, #4]
 8000296:	605a      	str	r2, [r3, #4]

    /* PLL configuration */
    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
 8000298:	4b18      	ldr	r3, [pc, #96]	; (80002fc <SetSysClock+0xd4>)
 800029a:	4a18      	ldr	r2, [pc, #96]	; (80002fc <SetSysClock+0xd4>)
 800029c:	6852      	ldr	r2, [r2, #4]
 800029e:	4919      	ldr	r1, [pc, #100]	; (8000304 <SetSysClock+0xdc>)
 80002a0:	400a      	ands	r2, r1
 80002a2:	605a      	str	r2, [r3, #4]
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6);
 80002a4:	4b15      	ldr	r3, [pc, #84]	; (80002fc <SetSysClock+0xd4>)
 80002a6:	4a15      	ldr	r2, [pc, #84]	; (80002fc <SetSysClock+0xd4>)
 80002a8:	6852      	ldr	r2, [r2, #4]
 80002aa:	2188      	movs	r1, #136	; 0x88
 80002ac:	0349      	lsls	r1, r1, #13
 80002ae:	430a      	orrs	r2, r1
 80002b0:	605a      	str	r2, [r3, #4]
            
    /* Enable PLL */
    RCC->CR |= RCC_CR_PLLON;
 80002b2:	4b12      	ldr	r3, [pc, #72]	; (80002fc <SetSysClock+0xd4>)
 80002b4:	4a11      	ldr	r2, [pc, #68]	; (80002fc <SetSysClock+0xd4>)
 80002b6:	6812      	ldr	r2, [r2, #0]
 80002b8:	2180      	movs	r1, #128	; 0x80
 80002ba:	0449      	lsls	r1, r1, #17
 80002bc:	430a      	orrs	r2, r1
 80002be:	601a      	str	r2, [r3, #0]

    /* Wait till PLL is ready */
    while((RCC->CR & RCC_CR_PLLRDY) == 0)
 80002c0:	46c0      	nop			; (mov r8, r8)
 80002c2:	4b0e      	ldr	r3, [pc, #56]	; (80002fc <SetSysClock+0xd4>)
 80002c4:	681a      	ldr	r2, [r3, #0]
 80002c6:	2380      	movs	r3, #128	; 0x80
 80002c8:	049b      	lsls	r3, r3, #18
 80002ca:	4013      	ands	r3, r2
 80002cc:	d0f9      	beq.n	80002c2 <SetSysClock+0x9a>
    {
    }

    /* Select PLL as system clock source */
    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
 80002ce:	4b0b      	ldr	r3, [pc, #44]	; (80002fc <SetSysClock+0xd4>)
 80002d0:	4a0a      	ldr	r2, [pc, #40]	; (80002fc <SetSysClock+0xd4>)
 80002d2:	6852      	ldr	r2, [r2, #4]
 80002d4:	2103      	movs	r1, #3
 80002d6:	438a      	bics	r2, r1
 80002d8:	605a      	str	r2, [r3, #4]
    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
 80002da:	4b08      	ldr	r3, [pc, #32]	; (80002fc <SetSysClock+0xd4>)
 80002dc:	4a07      	ldr	r2, [pc, #28]	; (80002fc <SetSysClock+0xd4>)
 80002de:	6852      	ldr	r2, [r2, #4]
 80002e0:	2102      	movs	r1, #2
 80002e2:	430a      	orrs	r2, r1
 80002e4:	605a      	str	r2, [r3, #4]

    /* Wait till PLL is used as system clock source */
    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
 80002e6:	46c0      	nop			; (mov r8, r8)
 80002e8:	4b04      	ldr	r3, [pc, #16]	; (80002fc <SetSysClock+0xd4>)
 80002ea:	685b      	ldr	r3, [r3, #4]
 80002ec:	220c      	movs	r2, #12
 80002ee:	4013      	ands	r3, r2
 80002f0:	2b08      	cmp	r3, #8
 80002f2:	d1f9      	bne.n	80002e8 <SetSysClock+0xc0>
  }
  else
  { /* If HSE fails to start-up, the application will have wrong clock 
         configuration. User can add here some code to deal with this error */
  }  
}
 80002f4:	46bd      	mov	sp, r7
 80002f6:	b002      	add	sp, #8
 80002f8:	bd80      	pop	{r7, pc}
 80002fa:	46c0      	nop			; (mov r8, r8)
 80002fc:	40021000 	.word	0x40021000
 8000300:	40022000 	.word	0x40022000
 8000304:	ffc07fff 	.word	0xffc07fff

08000308 <RCC_DeInit>:
  * @note      LSI, LSE and RTC clocks
  * @param  None
  * @retval None
  */
void RCC_DeInit(void)
{
 8000308:	b580      	push	{r7, lr}
 800030a:	af00      	add	r7, sp, #0
  /* Set HSION bit */
  RCC->CR |= (uint32_t)0x00000001;
 800030c:	4b1a      	ldr	r3, [pc, #104]	; (8000378 <RCC_DeInit+0x70>)
 800030e:	4a1a      	ldr	r2, [pc, #104]	; (8000378 <RCC_DeInit+0x70>)
 8000310:	6812      	ldr	r2, [r2, #0]
 8000312:	2101      	movs	r1, #1
 8000314:	430a      	orrs	r2, r1
 8000316:	601a      	str	r2, [r3, #0]
#if defined (STM32F051)
  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */
  RCC->CFGR &= (uint32_t)0xF8FFB80C;
#else
  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
  RCC->CFGR &= (uint32_t)0x08FFB80C;
 8000318:	4b17      	ldr	r3, [pc, #92]	; (8000378 <RCC_DeInit+0x70>)
 800031a:	4a17      	ldr	r2, [pc, #92]	; (8000378 <RCC_DeInit+0x70>)
 800031c:	6852      	ldr	r2, [r2, #4]
 800031e:	4917      	ldr	r1, [pc, #92]	; (800037c <RCC_DeInit+0x74>)
 8000320:	400a      	ands	r2, r1
 8000322:	605a      	str	r2, [r3, #4]
#endif /* STM32F051 */
  
  /* Reset HSEON, CSSON and PLLON bits */
  RCC->CR &= (uint32_t)0xFEF6FFFF;
 8000324:	4b14      	ldr	r3, [pc, #80]	; (8000378 <RCC_DeInit+0x70>)
 8000326:	4a14      	ldr	r2, [pc, #80]	; (8000378 <RCC_DeInit+0x70>)
 8000328:	6812      	ldr	r2, [r2, #0]
 800032a:	4915      	ldr	r1, [pc, #84]	; (8000380 <RCC_DeInit+0x78>)
 800032c:	400a      	ands	r2, r1
 800032e:	601a      	str	r2, [r3, #0]

  /* Reset HSEBYP bit */
  RCC->CR &= (uint32_t)0xFFFBFFFF;
 8000330:	4b11      	ldr	r3, [pc, #68]	; (8000378 <RCC_DeInit+0x70>)
 8000332:	4a11      	ldr	r2, [pc, #68]	; (8000378 <RCC_DeInit+0x70>)
 8000334:	6812      	ldr	r2, [r2, #0]
 8000336:	4913      	ldr	r1, [pc, #76]	; (8000384 <RCC_DeInit+0x7c>)
 8000338:	400a      	ands	r2, r1
 800033a:	601a      	str	r2, [r3, #0]

  /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
  RCC->CFGR &= (uint32_t)0xFFC0FFFF;
 800033c:	4b0e      	ldr	r3, [pc, #56]	; (8000378 <RCC_DeInit+0x70>)
 800033e:	4a0e      	ldr	r2, [pc, #56]	; (8000378 <RCC_DeInit+0x70>)
 8000340:	6852      	ldr	r2, [r2, #4]
 8000342:	4911      	ldr	r1, [pc, #68]	; (8000388 <RCC_DeInit+0x80>)
 8000344:	400a      	ands	r2, r1
 8000346:	605a      	str	r2, [r3, #4]

  /* Reset PREDIV1[3:0] bits */
  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
 8000348:	4b0b      	ldr	r3, [pc, #44]	; (8000378 <RCC_DeInit+0x70>)
 800034a:	4a0b      	ldr	r2, [pc, #44]	; (8000378 <RCC_DeInit+0x70>)
 800034c:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
 800034e:	210f      	movs	r1, #15
 8000350:	438a      	bics	r2, r1
 8000352:	62da      	str	r2, [r3, #44]	; 0x2c

  /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
  RCC->CFGR3 &= (uint32_t)0xFFF0FEAC;
 8000354:	4b08      	ldr	r3, [pc, #32]	; (8000378 <RCC_DeInit+0x70>)
 8000356:	4a08      	ldr	r2, [pc, #32]	; (8000378 <RCC_DeInit+0x70>)
 8000358:	6b12      	ldr	r2, [r2, #48]	; 0x30
 800035a:	490c      	ldr	r1, [pc, #48]	; (800038c <RCC_DeInit+0x84>)
 800035c:	400a      	ands	r2, r1
 800035e:	631a      	str	r2, [r3, #48]	; 0x30
  
  /* Reset HSI14 bit */
  RCC->CR2 &= (uint32_t)0xFFFFFFFE;
 8000360:	4b05      	ldr	r3, [pc, #20]	; (8000378 <RCC_DeInit+0x70>)
 8000362:	4a05      	ldr	r2, [pc, #20]	; (8000378 <RCC_DeInit+0x70>)
 8000364:	6b52      	ldr	r2, [r2, #52]	; 0x34
 8000366:	2101      	movs	r1, #1
 8000368:	438a      	bics	r2, r1
 800036a:	635a      	str	r2, [r3, #52]	; 0x34

  /* Disable all interrupts */
  RCC->CIR = 0x00000000;
 800036c:	4b02      	ldr	r3, [pc, #8]	; (8000378 <RCC_DeInit+0x70>)
 800036e:	2200      	movs	r2, #0
 8000370:	609a      	str	r2, [r3, #8]
}
 8000372:	46bd      	mov	sp, r7
 8000374:	bd80      	pop	{r7, pc}
 8000376:	46c0      	nop			; (mov r8, r8)
 8000378:	40021000 	.word	0x40021000
 800037c:	08ffb80c 	.word	0x08ffb80c
 8000380:	fef6ffff 	.word	0xfef6ffff
 8000384:	fffbffff 	.word	0xfffbffff
 8000388:	ffc0ffff 	.word	0xffc0ffff
 800038c:	fff0feac 	.word	0xfff0feac

08000390 <RCC_HSEConfig>:
  *            @arg RCC_HSE_ON: turn ON the HSE oscillator
  *            @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
  * @retval None
  */
void RCC_HSEConfig(uint8_t RCC_HSE)
{
 8000390:	b580      	push	{r7, lr}
 8000392:	b082      	sub	sp, #8
 8000394:	af00      	add	r7, sp, #0
 8000396:	1c02      	adds	r2, r0, #0
 8000398:	1dfb      	adds	r3, r7, #7
 800039a:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_RCC_HSE(RCC_HSE));

  /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
  *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE_OFF;
 800039c:	4b04      	ldr	r3, [pc, #16]	; (80003b0 <RCC_HSEConfig+0x20>)
 800039e:	2200      	movs	r2, #0
 80003a0:	701a      	strb	r2, [r3, #0]

  /* Set the new HSE configuration -------------------------------------------*/
  *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE;
 80003a2:	4a03      	ldr	r2, [pc, #12]	; (80003b0 <RCC_HSEConfig+0x20>)
 80003a4:	1dfb      	adds	r3, r7, #7
 80003a6:	781b      	ldrb	r3, [r3, #0]
 80003a8:	7013      	strb	r3, [r2, #0]

}
 80003aa:	46bd      	mov	sp, r7
 80003ac:	b002      	add	sp, #8
 80003ae:	bd80      	pop	{r7, pc}
 80003b0:	40021002 	.word	0x40021002

080003b4 <RCC_WaitForHSEStartUp>:
  * @retval An ErrorStatus enumeration value:
  *          - SUCCESS: HSE oscillator is stable and ready to use
  *          - ERROR: HSE oscillator not yet ready
  */
ErrorStatus RCC_WaitForHSEStartUp(void)
{
 80003b4:	b590      	push	{r4, r7, lr}
 80003b6:	b083      	sub	sp, #12
 80003b8:	af00      	add	r7, sp, #0
  __IO uint32_t StartUpCounter = 0;
 80003ba:	2300      	movs	r3, #0
 80003bc:	603b      	str	r3, [r7, #0]
  ErrorStatus status = ERROR;
 80003be:	1dfb      	adds	r3, r7, #7
 80003c0:	2200      	movs	r2, #0
 80003c2:	701a      	strb	r2, [r3, #0]
  FlagStatus HSEStatus = RESET;
 80003c4:	1dbb      	adds	r3, r7, #6
 80003c6:	2200      	movs	r2, #0
 80003c8:	701a      	strb	r2, [r3, #0]
  
  /* Wait till HSE is ready and if timeout is reached exit */
  do
  {
    HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
 80003ca:	1dbc      	adds	r4, r7, #6
 80003cc:	2011      	movs	r0, #17
 80003ce:	f000 fd3f 	bl	8000e50 <RCC_GetFlagStatus>
 80003d2:	1c03      	adds	r3, r0, #0
 80003d4:	7023      	strb	r3, [r4, #0]
    StartUpCounter++;  
 80003d6:	683b      	ldr	r3, [r7, #0]
 80003d8:	3301      	adds	r3, #1
 80003da:	603b      	str	r3, [r7, #0]
  } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
 80003dc:	683a      	ldr	r2, [r7, #0]
 80003de:	23a0      	movs	r3, #160	; 0xa0
 80003e0:	01db      	lsls	r3, r3, #7
 80003e2:	429a      	cmp	r2, r3
 80003e4:	d003      	beq.n	80003ee <RCC_WaitForHSEStartUp+0x3a>
 80003e6:	1dbb      	adds	r3, r7, #6
 80003e8:	781b      	ldrb	r3, [r3, #0]
 80003ea:	2b00      	cmp	r3, #0
 80003ec:	d0ed      	beq.n	80003ca <RCC_WaitForHSEStartUp+0x16>
  
  if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
 80003ee:	2011      	movs	r0, #17
 80003f0:	f000 fd2e 	bl	8000e50 <RCC_GetFlagStatus>
 80003f4:	1e03      	subs	r3, r0, #0
 80003f6:	d003      	beq.n	8000400 <RCC_WaitForHSEStartUp+0x4c>
  {
    status = SUCCESS;
 80003f8:	1dfb      	adds	r3, r7, #7
 80003fa:	2201      	movs	r2, #1
 80003fc:	701a      	strb	r2, [r3, #0]
 80003fe:	e002      	b.n	8000406 <RCC_WaitForHSEStartUp+0x52>
  }
  else
  {
    status = ERROR;
 8000400:	1dfb      	adds	r3, r7, #7
 8000402:	2200      	movs	r2, #0
 8000404:	701a      	strb	r2, [r3, #0]
  }  
  return (status);
 8000406:	1dfb      	adds	r3, r7, #7
 8000408:	781b      	ldrb	r3, [r3, #0]
}
 800040a:	1c18      	adds	r0, r3, #0
 800040c:	46bd      	mov	sp, r7
 800040e:	b003      	add	sp, #12
 8000410:	bd90      	pop	{r4, r7, pc}
 8000412:	46c0      	nop			; (mov r8, r8)

08000414 <RCC_AdjustHSICalibrationValue>:
  * @param  HSICalibrationValue: specifies the HSI calibration trimming value.
  *          This parameter must be a number between 0 and 0x1F.
  * @retval None
  */
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
{
 8000414:	b580      	push	{r7, lr}
 8000416:	b084      	sub	sp, #16
 8000418:	af00      	add	r7, sp, #0
 800041a:	1c02      	adds	r2, r0, #0
 800041c:	1dfb      	adds	r3, r7, #7
 800041e:	701a      	strb	r2, [r3, #0]
  uint32_t tmpreg = 0;
 8000420:	2300      	movs	r3, #0
 8000422:	60fb      	str	r3, [r7, #12]
  
  /* Check the parameters */
  assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));
  
  tmpreg = RCC->CR;
 8000424:	4b09      	ldr	r3, [pc, #36]	; (800044c <RCC_AdjustHSICalibrationValue+0x38>)
 8000426:	681b      	ldr	r3, [r3, #0]
 8000428:	60fb      	str	r3, [r7, #12]
  
  /* Clear HSITRIM[4:0] bits */
  tmpreg &= ~RCC_CR_HSITRIM;
 800042a:	68fb      	ldr	r3, [r7, #12]
 800042c:	22f8      	movs	r2, #248	; 0xf8
 800042e:	4393      	bics	r3, r2
 8000430:	60fb      	str	r3, [r7, #12]
  
  /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
  tmpreg |= (uint32_t)HSICalibrationValue << 3;
 8000432:	1dfb      	adds	r3, r7, #7
 8000434:	781b      	ldrb	r3, [r3, #0]
 8000436:	00db      	lsls	r3, r3, #3
 8000438:	68fa      	ldr	r2, [r7, #12]
 800043a:	4313      	orrs	r3, r2
 800043c:	60fb      	str	r3, [r7, #12]

  /* Store the new value */
  RCC->CR = tmpreg;
 800043e:	4b03      	ldr	r3, [pc, #12]	; (800044c <RCC_AdjustHSICalibrationValue+0x38>)
 8000440:	68fa      	ldr	r2, [r7, #12]
 8000442:	601a      	str	r2, [r3, #0]
}
 8000444:	46bd      	mov	sp, r7
 8000446:	b004      	add	sp, #16
 8000448:	bd80      	pop	{r7, pc}
 800044a:	46c0      	nop			; (mov r8, r8)
 800044c:	40021000 	.word	0x40021000

08000450 <RCC_HSICmd>:
  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
  *         clock cycles.
  * @retval None
  */
void RCC_HSICmd(FunctionalState NewState)
{
 8000450:	b580      	push	{r7, lr}
 8000452:	b082      	sub	sp, #8
 8000454:	af00      	add	r7, sp, #0
 8000456:	1c02      	adds	r2, r0, #0
 8000458:	1dfb      	adds	r3, r7, #7
 800045a:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  
  if (NewState != DISABLE)
 800045c:	1dfb      	adds	r3, r7, #7
 800045e:	781b      	ldrb	r3, [r3, #0]
 8000460:	2b00      	cmp	r3, #0
 8000462:	d006      	beq.n	8000472 <RCC_HSICmd+0x22>
  {
    RCC->CR |= RCC_CR_HSION;
 8000464:	4b07      	ldr	r3, [pc, #28]	; (8000484 <RCC_HSICmd+0x34>)
 8000466:	4a07      	ldr	r2, [pc, #28]	; (8000484 <RCC_HSICmd+0x34>)
 8000468:	6812      	ldr	r2, [r2, #0]
 800046a:	2101      	movs	r1, #1
 800046c:	430a      	orrs	r2, r1
 800046e:	601a      	str	r2, [r3, #0]
 8000470:	e005      	b.n	800047e <RCC_HSICmd+0x2e>
  }
  else
  {
    RCC->CR &= ~RCC_CR_HSION;
 8000472:	4b04      	ldr	r3, [pc, #16]	; (8000484 <RCC_HSICmd+0x34>)
 8000474:	4a03      	ldr	r2, [pc, #12]	; (8000484 <RCC_HSICmd+0x34>)
 8000476:	6812      	ldr	r2, [r2, #0]
 8000478:	2101      	movs	r1, #1
 800047a:	438a      	bics	r2, r1
 800047c:	601a      	str	r2, [r3, #0]
  }
}
 800047e:	46bd      	mov	sp, r7
 8000480:	b002      	add	sp, #8
 8000482:	bd80      	pop	{r7, pc}
 8000484:	40021000 	.word	0x40021000

08000488 <RCC_AdjustHSI14CalibrationValue>:
  * @param  HSI14CalibrationValue: specifies the HSI14 calibration trimming value.
  *          This parameter must be a number between 0 and 0x1F.
  * @retval None
  */
void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue)
{
 8000488:	b580      	push	{r7, lr}
 800048a:	b084      	sub	sp, #16
 800048c:	af00      	add	r7, sp, #0
 800048e:	1c02      	adds	r2, r0, #0
 8000490:	1dfb      	adds	r3, r7, #7
 8000492:	701a      	strb	r2, [r3, #0]
  uint32_t tmpreg = 0;
 8000494:	2300      	movs	r3, #0
 8000496:	60fb      	str	r3, [r7, #12]
  
  /* Check the parameters */
  assert_param(IS_RCC_HSI14_CALIBRATION_VALUE(HSI14CalibrationValue));
  
  tmpreg = RCC->CR2;
 8000498:	4b09      	ldr	r3, [pc, #36]	; (80004c0 <RCC_AdjustHSI14CalibrationValue+0x38>)
 800049a:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 800049c:	60fb      	str	r3, [r7, #12]
  
  /* Clear HSI14TRIM[4:0] bits */
  tmpreg &= ~RCC_CR2_HSI14TRIM;
 800049e:	68fb      	ldr	r3, [r7, #12]
 80004a0:	22f8      	movs	r2, #248	; 0xf8
 80004a2:	4393      	bics	r3, r2
 80004a4:	60fb      	str	r3, [r7, #12]
  
  /* Set the HSITRIM14[4:0] bits according to HSI14CalibrationValue value */
  tmpreg |= (uint32_t)HSI14CalibrationValue << 3;
 80004a6:	1dfb      	adds	r3, r7, #7
 80004a8:	781b      	ldrb	r3, [r3, #0]
 80004aa:	00db      	lsls	r3, r3, #3
 80004ac:	68fa      	ldr	r2, [r7, #12]
 80004ae:	4313      	orrs	r3, r2
 80004b0:	60fb      	str	r3, [r7, #12]

  /* Store the new value */
  RCC->CR2 = tmpreg;
 80004b2:	4b03      	ldr	r3, [pc, #12]	; (80004c0 <RCC_AdjustHSI14CalibrationValue+0x38>)
 80004b4:	68fa      	ldr	r2, [r7, #12]
 80004b6:	635a      	str	r2, [r3, #52]	; 0x34
}
 80004b8:	46bd      	mov	sp, r7
 80004ba:	b004      	add	sp, #16
 80004bc:	bd80      	pop	{r7, pc}
 80004be:	46c0      	nop			; (mov r8, r8)
 80004c0:	40021000 	.word	0x40021000

080004c4 <RCC_HSI14Cmd>:
  * @note   When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator
  *         clock cycles.
  * @retval None
  */
void RCC_HSI14Cmd(FunctionalState NewState)
{
 80004c4:	b580      	push	{r7, lr}
 80004c6:	b082      	sub	sp, #8
 80004c8:	af00      	add	r7, sp, #0
 80004ca:	1c02      	adds	r2, r0, #0
 80004cc:	1dfb      	adds	r3, r7, #7
 80004ce:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  
  if (NewState != DISABLE)
 80004d0:	1dfb      	adds	r3, r7, #7
 80004d2:	781b      	ldrb	r3, [r3, #0]
 80004d4:	2b00      	cmp	r3, #0
 80004d6:	d006      	beq.n	80004e6 <RCC_HSI14Cmd+0x22>
  {
    RCC->CR2 |= RCC_CR2_HSI14ON;
 80004d8:	4b07      	ldr	r3, [pc, #28]	; (80004f8 <RCC_HSI14Cmd+0x34>)
 80004da:	4a07      	ldr	r2, [pc, #28]	; (80004f8 <RCC_HSI14Cmd+0x34>)
 80004dc:	6b52      	ldr	r2, [r2, #52]	; 0x34
 80004de:	2101      	movs	r1, #1
 80004e0:	430a      	orrs	r2, r1
 80004e2:	635a      	str	r2, [r3, #52]	; 0x34
 80004e4:	e005      	b.n	80004f2 <RCC_HSI14Cmd+0x2e>
  }
  else
  {
    RCC->CR2 &= ~RCC_CR2_HSI14ON;
 80004e6:	4b04      	ldr	r3, [pc, #16]	; (80004f8 <RCC_HSI14Cmd+0x34>)
 80004e8:	4a03      	ldr	r2, [pc, #12]	; (80004f8 <RCC_HSI14Cmd+0x34>)
 80004ea:	6b52      	ldr	r2, [r2, #52]	; 0x34
 80004ec:	2101      	movs	r1, #1
 80004ee:	438a      	bics	r2, r1
 80004f0:	635a      	str	r2, [r3, #52]	; 0x34
  }
}
 80004f2:	46bd      	mov	sp, r7
 80004f4:	b002      	add	sp, #8
 80004f6:	bd80      	pop	{r7, pc}
 80004f8:	40021000 	.word	0x40021000

080004fc <RCC_HSI14ADCRequestCmd>:
  * @param  NewState: new state of the HSI14 ADC request.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_HSI14ADCRequestCmd(FunctionalState NewState)
{
 80004fc:	b580      	push	{r7, lr}
 80004fe:	b082      	sub	sp, #8
 8000500:	af00      	add	r7, sp, #0
 8000502:	1c02      	adds	r2, r0, #0
 8000504:	1dfb      	adds	r3, r7, #7
 8000506:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  
  if (NewState != DISABLE)
 8000508:	1dfb      	adds	r3, r7, #7
 800050a:	781b      	ldrb	r3, [r3, #0]
 800050c:	2b00      	cmp	r3, #0
 800050e:	d006      	beq.n	800051e <RCC_HSI14ADCRequestCmd+0x22>
  {
    RCC->CR2 &= ~RCC_CR2_HSI14DIS;
 8000510:	4b07      	ldr	r3, [pc, #28]	; (8000530 <RCC_HSI14ADCRequestCmd+0x34>)
 8000512:	4a07      	ldr	r2, [pc, #28]	; (8000530 <RCC_HSI14ADCRequestCmd+0x34>)
 8000514:	6b52      	ldr	r2, [r2, #52]	; 0x34
 8000516:	2104      	movs	r1, #4
 8000518:	438a      	bics	r2, r1
 800051a:	635a      	str	r2, [r3, #52]	; 0x34
 800051c:	e005      	b.n	800052a <RCC_HSI14ADCRequestCmd+0x2e>
  }
  else
  {
    RCC->CR2 |= RCC_CR2_HSI14DIS;
 800051e:	4b04      	ldr	r3, [pc, #16]	; (8000530 <RCC_HSI14ADCRequestCmd+0x34>)
 8000520:	4a03      	ldr	r2, [pc, #12]	; (8000530 <RCC_HSI14ADCRequestCmd+0x34>)
 8000522:	6b52      	ldr	r2, [r2, #52]	; 0x34
 8000524:	2104      	movs	r1, #4
 8000526:	430a      	orrs	r2, r1
 8000528:	635a      	str	r2, [r3, #52]	; 0x34
  }
}
 800052a:	46bd      	mov	sp, r7
 800052c:	b002      	add	sp, #8
 800052e:	bd80      	pop	{r7, pc}
 8000530:	40021000 	.word	0x40021000

08000534 <RCC_LSEConfig>:
  *            @arg RCC_LSE_ON: turn ON the LSE oscillator
  *            @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
  * @retval None
  */
void RCC_LSEConfig(uint32_t RCC_LSE)
{
 8000534:	b580      	push	{r7, lr}
 8000536:	b082      	sub	sp, #8
 8000538:	af00      	add	r7, sp, #0
 800053a:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_RCC_LSE(RCC_LSE));

  /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
  /* Reset LSEON bit */
  RCC->BDCR &= ~(RCC_BDCR_LSEON);
 800053c:	4b0a      	ldr	r3, [pc, #40]	; (8000568 <RCC_LSEConfig+0x34>)
 800053e:	4a0a      	ldr	r2, [pc, #40]	; (8000568 <RCC_LSEConfig+0x34>)
 8000540:	6a12      	ldr	r2, [r2, #32]
 8000542:	2101      	movs	r1, #1
 8000544:	438a      	bics	r2, r1
 8000546:	621a      	str	r2, [r3, #32]

  /* Reset LSEBYP bit */
  RCC->BDCR &= ~(RCC_BDCR_LSEBYP);
 8000548:	4b07      	ldr	r3, [pc, #28]	; (8000568 <RCC_LSEConfig+0x34>)
 800054a:	4a07      	ldr	r2, [pc, #28]	; (8000568 <RCC_LSEConfig+0x34>)
 800054c:	6a12      	ldr	r2, [r2, #32]
 800054e:	2104      	movs	r1, #4
 8000550:	438a      	bics	r2, r1
 8000552:	621a      	str	r2, [r3, #32]

  /* Configure LSE */
  RCC->BDCR |= RCC_LSE;
 8000554:	4b04      	ldr	r3, [pc, #16]	; (8000568 <RCC_LSEConfig+0x34>)
 8000556:	4a04      	ldr	r2, [pc, #16]	; (8000568 <RCC_LSEConfig+0x34>)
 8000558:	6a11      	ldr	r1, [r2, #32]
 800055a:	687a      	ldr	r2, [r7, #4]
 800055c:	430a      	orrs	r2, r1
 800055e:	621a      	str	r2, [r3, #32]
}
 8000560:	46bd      	mov	sp, r7
 8000562:	b002      	add	sp, #8
 8000564:	bd80      	pop	{r7, pc}
 8000566:	46c0      	nop			; (mov r8, r8)
 8000568:	40021000 	.word	0x40021000

0800056c <RCC_LSEDriveConfig>:
  *            @arg RCC_LSEDrive_MediumHigh: LSE oscillator medium high drive capability.
  *            @arg RCC_LSEDrive_High: LSE oscillator high drive capability.
  * @retval None
  */
void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive)
{
 800056c:	b580      	push	{r7, lr}
 800056e:	b082      	sub	sp, #8
 8000570:	af00      	add	r7, sp, #0
 8000572:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_RCC_LSE_DRIVE(RCC_LSEDrive));
  
  /* Clear LSEDRV[1:0] bits */
  RCC->BDCR &= ~(RCC_BDCR_LSEDRV);
 8000574:	4b07      	ldr	r3, [pc, #28]	; (8000594 <RCC_LSEDriveConfig+0x28>)
 8000576:	4a07      	ldr	r2, [pc, #28]	; (8000594 <RCC_LSEDriveConfig+0x28>)
 8000578:	6a12      	ldr	r2, [r2, #32]
 800057a:	2118      	movs	r1, #24
 800057c:	438a      	bics	r2, r1
 800057e:	621a      	str	r2, [r3, #32]

  /* Set the LSE Drive */
  RCC->BDCR |= RCC_LSEDrive;
 8000580:	4b04      	ldr	r3, [pc, #16]	; (8000594 <RCC_LSEDriveConfig+0x28>)
 8000582:	4a04      	ldr	r2, [pc, #16]	; (8000594 <RCC_LSEDriveConfig+0x28>)
 8000584:	6a11      	ldr	r1, [r2, #32]
 8000586:	687a      	ldr	r2, [r7, #4]
 8000588:	430a      	orrs	r2, r1
 800058a:	621a      	str	r2, [r3, #32]
}
 800058c:	46bd      	mov	sp, r7
 800058e:	b002      	add	sp, #8
 8000590:	bd80      	pop	{r7, pc}
 8000592:	46c0      	nop			; (mov r8, r8)
 8000594:	40021000 	.word	0x40021000

08000598 <RCC_LSICmd>:
  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
  *         clock cycles.
  * @retval None
  */
void RCC_LSICmd(FunctionalState NewState)
{
 8000598:	b580      	push	{r7, lr}
 800059a:	b082      	sub	sp, #8
 800059c:	af00      	add	r7, sp, #0
 800059e:	1c02      	adds	r2, r0, #0
 80005a0:	1dfb      	adds	r3, r7, #7
 80005a2:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  
  if (NewState != DISABLE)
 80005a4:	1dfb      	adds	r3, r7, #7
 80005a6:	781b      	ldrb	r3, [r3, #0]
 80005a8:	2b00      	cmp	r3, #0
 80005aa:	d006      	beq.n	80005ba <RCC_LSICmd+0x22>
  {
    RCC->CSR |= RCC_CSR_LSION;
 80005ac:	4b07      	ldr	r3, [pc, #28]	; (80005cc <RCC_LSICmd+0x34>)
 80005ae:	4a07      	ldr	r2, [pc, #28]	; (80005cc <RCC_LSICmd+0x34>)
 80005b0:	6a52      	ldr	r2, [r2, #36]	; 0x24
 80005b2:	2101      	movs	r1, #1
 80005b4:	430a      	orrs	r2, r1
 80005b6:	625a      	str	r2, [r3, #36]	; 0x24
 80005b8:	e005      	b.n	80005c6 <RCC_LSICmd+0x2e>
  }
  else
  {
    RCC->CSR &= ~RCC_CSR_LSION;
 80005ba:	4b04      	ldr	r3, [pc, #16]	; (80005cc <RCC_LSICmd+0x34>)
 80005bc:	4a03      	ldr	r2, [pc, #12]	; (80005cc <RCC_LSICmd+0x34>)
 80005be:	6a52      	ldr	r2, [r2, #36]	; 0x24
 80005c0:	2101      	movs	r1, #1
 80005c2:	438a      	bics	r2, r1
 80005c4:	625a      	str	r2, [r3, #36]	; 0x24
  }
}
 80005c6:	46bd      	mov	sp, r7
 80005c8:	b002      	add	sp, #8
 80005ca:	bd80      	pop	{r7, pc}
 80005cc:	40021000 	.word	0x40021000

080005d0 <RCC_PLLConfig>:
  *          This parameter can be RCC_PLLMul_x where x:[2,16] 
  *
  * @retval None
  */
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
{
 80005d0:	b580      	push	{r7, lr}
 80005d2:	b082      	sub	sp, #8
 80005d4:	af00      	add	r7, sp, #0
 80005d6:	6078      	str	r0, [r7, #4]
 80005d8:	6039      	str	r1, [r7, #0]
  /* Check the parameters */
  assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
  assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));

  /* Clear PLL Source [16] and Multiplier [21:18] bits */
  RCC->CFGR &= ~(RCC_CFGR_PLLMULL | RCC_CFGR_PLLSRC);
 80005da:	4b08      	ldr	r3, [pc, #32]	; (80005fc <RCC_PLLConfig+0x2c>)
 80005dc:	4a07      	ldr	r2, [pc, #28]	; (80005fc <RCC_PLLConfig+0x2c>)
 80005de:	6852      	ldr	r2, [r2, #4]
 80005e0:	4907      	ldr	r1, [pc, #28]	; (8000600 <RCC_PLLConfig+0x30>)
 80005e2:	400a      	ands	r2, r1
 80005e4:	605a      	str	r2, [r3, #4]

  /* Set the PLL Source and Multiplier */
  RCC->CFGR |= (uint32_t)(RCC_PLLSource | RCC_PLLMul);
 80005e6:	4b05      	ldr	r3, [pc, #20]	; (80005fc <RCC_PLLConfig+0x2c>)
 80005e8:	4a04      	ldr	r2, [pc, #16]	; (80005fc <RCC_PLLConfig+0x2c>)
 80005ea:	6851      	ldr	r1, [r2, #4]
 80005ec:	6878      	ldr	r0, [r7, #4]
 80005ee:	683a      	ldr	r2, [r7, #0]
 80005f0:	4302      	orrs	r2, r0
 80005f2:	430a      	orrs	r2, r1
 80005f4:	605a      	str	r2, [r3, #4]
}
 80005f6:	46bd      	mov	sp, r7
 80005f8:	b002      	add	sp, #8
 80005fa:	bd80      	pop	{r7, pc}
 80005fc:	40021000 	.word	0x40021000
 8000600:	ffc27fff 	.word	0xffc27fff

08000604 <RCC_PLLCmd>:
  * @param  NewState: new state of the PLL.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_PLLCmd(FunctionalState NewState)
{
 8000604:	b580      	push	{r7, lr}
 8000606:	b082      	sub	sp, #8
 8000608:	af00      	add	r7, sp, #0
 800060a:	1c02      	adds	r2, r0, #0
 800060c:	1dfb      	adds	r3, r7, #7
 800060e:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  
  if (NewState != DISABLE)
 8000610:	1dfb      	adds	r3, r7, #7
 8000612:	781b      	ldrb	r3, [r3, #0]
 8000614:	2b00      	cmp	r3, #0
 8000616:	d007      	beq.n	8000628 <RCC_PLLCmd+0x24>
  {
    RCC->CR |= RCC_CR_PLLON;
 8000618:	4b08      	ldr	r3, [pc, #32]	; (800063c <RCC_PLLCmd+0x38>)
 800061a:	4a08      	ldr	r2, [pc, #32]	; (800063c <RCC_PLLCmd+0x38>)
 800061c:	6812      	ldr	r2, [r2, #0]
 800061e:	2180      	movs	r1, #128	; 0x80
 8000620:	0449      	lsls	r1, r1, #17
 8000622:	430a      	orrs	r2, r1
 8000624:	601a      	str	r2, [r3, #0]
 8000626:	e005      	b.n	8000634 <RCC_PLLCmd+0x30>
  }
  else
  {
    RCC->CR &= ~RCC_CR_PLLON;
 8000628:	4b04      	ldr	r3, [pc, #16]	; (800063c <RCC_PLLCmd+0x38>)
 800062a:	4a04      	ldr	r2, [pc, #16]	; (800063c <RCC_PLLCmd+0x38>)
 800062c:	6812      	ldr	r2, [r2, #0]
 800062e:	4904      	ldr	r1, [pc, #16]	; (8000640 <RCC_PLLCmd+0x3c>)
 8000630:	400a      	ands	r2, r1
 8000632:	601a      	str	r2, [r3, #0]
  }
}
 8000634:	46bd      	mov	sp, r7
 8000636:	b002      	add	sp, #8
 8000638:	bd80      	pop	{r7, pc}
 800063a:	46c0      	nop			; (mov r8, r8)
 800063c:	40021000 	.word	0x40021000
 8000640:	feffffff 	.word	0xfeffffff

08000644 <RCC_HSI48Cmd>:
  * @param  NewState: new state of the HSI48.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_HSI48Cmd(FunctionalState NewState)
{
 8000644:	b580      	push	{r7, lr}
 8000646:	b082      	sub	sp, #8
 8000648:	af00      	add	r7, sp, #0
 800064a:	1c02      	adds	r2, r0, #0
 800064c:	1dfb      	adds	r3, r7, #7
 800064e:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  
  if (NewState != DISABLE)
 8000650:	1dfb      	adds	r3, r7, #7
 8000652:	781b      	ldrb	r3, [r3, #0]
 8000654:	2b00      	cmp	r3, #0
 8000656:	d007      	beq.n	8000668 <RCC_HSI48Cmd+0x24>
  {
    RCC->CR2 |= RCC_CR2_HSI48ON;
 8000658:	4b08      	ldr	r3, [pc, #32]	; (800067c <RCC_HSI48Cmd+0x38>)
 800065a:	4a08      	ldr	r2, [pc, #32]	; (800067c <RCC_HSI48Cmd+0x38>)
 800065c:	6b52      	ldr	r2, [r2, #52]	; 0x34
 800065e:	2180      	movs	r1, #128	; 0x80
 8000660:	0249      	lsls	r1, r1, #9
 8000662:	430a      	orrs	r2, r1
 8000664:	635a      	str	r2, [r3, #52]	; 0x34
 8000666:	e005      	b.n	8000674 <RCC_HSI48Cmd+0x30>
  }
  else
  {
    RCC->CR2 &= ~RCC_CR2_HSI48ON;
 8000668:	4b04      	ldr	r3, [pc, #16]	; (800067c <RCC_HSI48Cmd+0x38>)
 800066a:	4a04      	ldr	r2, [pc, #16]	; (800067c <RCC_HSI48Cmd+0x38>)
 800066c:	6b52      	ldr	r2, [r2, #52]	; 0x34
 800066e:	4904      	ldr	r1, [pc, #16]	; (8000680 <RCC_HSI48Cmd+0x3c>)
 8000670:	400a      	ands	r2, r1
 8000672:	635a      	str	r2, [r3, #52]	; 0x34
  }
}
 8000674:	46bd      	mov	sp, r7
 8000676:	b002      	add	sp, #8
 8000678:	bd80      	pop	{r7, pc}
 800067a:	46c0      	nop			; (mov r8, r8)
 800067c:	40021000 	.word	0x40021000
 8000680:	fffeffff 	.word	0xfffeffff

08000684 <RCC_PREDIV1Config>:
  * @param  RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
  *          This parameter can be RCC_PREDIV1_Divx where x:[1,16]
  * @retval None
  */
void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div)
{
 8000684:	b580      	push	{r7, lr}
 8000686:	b084      	sub	sp, #16
 8000688:	af00      	add	r7, sp, #0
 800068a:	6078      	str	r0, [r7, #4]
  uint32_t tmpreg = 0;
 800068c:	2300      	movs	r3, #0
 800068e:	60fb      	str	r3, [r7, #12]
  
  /* Check the parameters */
  assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));

  tmpreg = RCC->CFGR2;
 8000690:	4b08      	ldr	r3, [pc, #32]	; (80006b4 <RCC_PREDIV1Config+0x30>)
 8000692:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8000694:	60fb      	str	r3, [r7, #12]
  /* Clear PREDIV1[3:0] bits */
  tmpreg &= ~(RCC_CFGR2_PREDIV1);
 8000696:	68fb      	ldr	r3, [r7, #12]
 8000698:	220f      	movs	r2, #15
 800069a:	4393      	bics	r3, r2
 800069c:	60fb      	str	r3, [r7, #12]
  /* Set the PREDIV1 division factor */
  tmpreg |= RCC_PREDIV1_Div;
 800069e:	68fa      	ldr	r2, [r7, #12]
 80006a0:	687b      	ldr	r3, [r7, #4]
 80006a2:	4313      	orrs	r3, r2
 80006a4:	60fb      	str	r3, [r7, #12]
  /* Store the new value */
  RCC->CFGR2 = tmpreg;
 80006a6:	4b03      	ldr	r3, [pc, #12]	; (80006b4 <RCC_PREDIV1Config+0x30>)
 80006a8:	68fa      	ldr	r2, [r7, #12]
 80006aa:	62da      	str	r2, [r3, #44]	; 0x2c
}
 80006ac:	46bd      	mov	sp, r7
 80006ae:	b004      	add	sp, #16
 80006b0:	bd80      	pop	{r7, pc}
 80006b2:	46c0      	nop			; (mov r8, r8)
 80006b4:	40021000 	.word	0x40021000

080006b8 <RCC_ClockSecuritySystemCmd>:
  * @param  NewState: new state of the Clock Security System.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
{
 80006b8:	b580      	push	{r7, lr}
 80006ba:	b082      	sub	sp, #8
 80006bc:	af00      	add	r7, sp, #0
 80006be:	1c02      	adds	r2, r0, #0
 80006c0:	1dfb      	adds	r3, r7, #7
 80006c2:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  
  if (NewState != DISABLE)
 80006c4:	1dfb      	adds	r3, r7, #7
 80006c6:	781b      	ldrb	r3, [r3, #0]
 80006c8:	2b00      	cmp	r3, #0
 80006ca:	d007      	beq.n	80006dc <RCC_ClockSecuritySystemCmd+0x24>
  {
    RCC->CR |= RCC_CR_CSSON;
 80006cc:	4b08      	ldr	r3, [pc, #32]	; (80006f0 <RCC_ClockSecuritySystemCmd+0x38>)
 80006ce:	4a08      	ldr	r2, [pc, #32]	; (80006f0 <RCC_ClockSecuritySystemCmd+0x38>)
 80006d0:	6812      	ldr	r2, [r2, #0]
 80006d2:	2180      	movs	r1, #128	; 0x80
 80006d4:	0309      	lsls	r1, r1, #12
 80006d6:	430a      	orrs	r2, r1
 80006d8:	601a      	str	r2, [r3, #0]
 80006da:	e005      	b.n	80006e8 <RCC_ClockSecuritySystemCmd+0x30>
  }
  else
  {
    RCC->CR &= ~RCC_CR_CSSON;
 80006dc:	4b04      	ldr	r3, [pc, #16]	; (80006f0 <RCC_ClockSecuritySystemCmd+0x38>)
 80006de:	4a04      	ldr	r2, [pc, #16]	; (80006f0 <RCC_ClockSecuritySystemCmd+0x38>)
 80006e0:	6812      	ldr	r2, [r2, #0]
 80006e2:	4904      	ldr	r1, [pc, #16]	; (80006f4 <RCC_ClockSecuritySystemCmd+0x3c>)
 80006e4:	400a      	ands	r2, r1
 80006e6:	601a      	str	r2, [r3, #0]
  }
}
 80006e8:	46bd      	mov	sp, r7
 80006ea:	b002      	add	sp, #8
 80006ec:	bd80      	pop	{r7, pc}
 80006ee:	46c0      	nop			; (mov r8, r8)
 80006f0:	40021000 	.word	0x40021000
 80006f4:	fff7ffff 	.word	0xfff7ffff

080006f8 <RCC_MCOConfig>:
  *            @arg RCC_MCOPrescaler_64: MCO clock is divided by 64.
  *            @arg RCC_MCOPrescaler_128: MCO clock is divided by 128.    
  * @retval None
  */
void RCC_MCOConfig(uint8_t RCC_MCOSource, uint32_t RCC_MCOPrescaler)
{
 80006f8:	b580      	push	{r7, lr}
 80006fa:	b084      	sub	sp, #16
 80006fc:	af00      	add	r7, sp, #0
 80006fe:	1c02      	adds	r2, r0, #0
 8000700:	6039      	str	r1, [r7, #0]
 8000702:	1dfb      	adds	r3, r7, #7
 8000704:	701a      	strb	r2, [r3, #0]
  uint32_t tmpreg = 0;
 8000706:	2300      	movs	r3, #0
 8000708:	60fb      	str	r3, [r7, #12]
  /* Check the parameters */
  assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
  assert_param(IS_RCC_MCO_PRESCALER(RCC_MCOPrescaler));
    
  /* Get CFGR value */  
  tmpreg = RCC->CFGR;
 800070a:	4b0a      	ldr	r3, [pc, #40]	; (8000734 <RCC_MCOConfig+0x3c>)
 800070c:	685b      	ldr	r3, [r3, #4]
 800070e:	60fb      	str	r3, [r7, #12]
  /* Clear MCOPRE[2:0] bits */
  tmpreg &= ~(RCC_CFGR_MCO_PRE | RCC_CFGR_MCO | RCC_CFGR_PLLNODIV);
 8000710:	68fb      	ldr	r3, [r7, #12]
 8000712:	021b      	lsls	r3, r3, #8
 8000714:	0a1b      	lsrs	r3, r3, #8
 8000716:	60fb      	str	r3, [r7, #12]
  /* Set the RCC_MCOSource and RCC_MCOPrescaler */
  tmpreg |= (RCC_MCOPrescaler | ((uint32_t)RCC_MCOSource<<24));
 8000718:	1dfb      	adds	r3, r7, #7
 800071a:	781b      	ldrb	r3, [r3, #0]
 800071c:	061a      	lsls	r2, r3, #24
 800071e:	683b      	ldr	r3, [r7, #0]
 8000720:	4313      	orrs	r3, r2
 8000722:	68fa      	ldr	r2, [r7, #12]
 8000724:	4313      	orrs	r3, r2
 8000726:	60fb      	str	r3, [r7, #12]
  /* Store the new value */
  RCC->CFGR = tmpreg;
 8000728:	4b02      	ldr	r3, [pc, #8]	; (8000734 <RCC_MCOConfig+0x3c>)
 800072a:	68fa      	ldr	r2, [r7, #12]
 800072c:	605a      	str	r2, [r3, #4]
}
 800072e:	46bd      	mov	sp, r7
 8000730:	b004      	add	sp, #16
 8000732:	bd80      	pop	{r7, pc}
 8000734:	40021000 	.word	0x40021000

08000738 <RCC_SYSCLKConfig>:
  *            @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
  *            @arg RCC_SYSCLKSource_HSI48:  HSI48 selected as system clock source, applicable only for STM32F072 devices  
  * @retval None
  */
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
{
 8000738:	b580      	push	{r7, lr}
 800073a:	b084      	sub	sp, #16
 800073c:	af00      	add	r7, sp, #0
 800073e:	6078      	str	r0, [r7, #4]
  uint32_t tmpreg = 0;
 8000740:	2300      	movs	r3, #0
 8000742:	60fb      	str	r3, [r7, #12]
  
  /* Check the parameters */
  assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
  
  tmpreg = RCC->CFGR;
 8000744:	4b08      	ldr	r3, [pc, #32]	; (8000768 <RCC_SYSCLKConfig+0x30>)
 8000746:	685b      	ldr	r3, [r3, #4]
 8000748:	60fb      	str	r3, [r7, #12]
  
  /* Clear SW[1:0] bits */
  tmpreg &= ~RCC_CFGR_SW;
 800074a:	68fb      	ldr	r3, [r7, #12]
 800074c:	2203      	movs	r2, #3
 800074e:	4393      	bics	r3, r2
 8000750:	60fb      	str	r3, [r7, #12]
  
  /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
  tmpreg |= RCC_SYSCLKSource;
 8000752:	68fa      	ldr	r2, [r7, #12]
 8000754:	687b      	ldr	r3, [r7, #4]
 8000756:	4313      	orrs	r3, r2
 8000758:	60fb      	str	r3, [r7, #12]
  
  /* Store the new value */
  RCC->CFGR = tmpreg;
 800075a:	4b03      	ldr	r3, [pc, #12]	; (8000768 <RCC_SYSCLKConfig+0x30>)
 800075c:	68fa      	ldr	r2, [r7, #12]
 800075e:	605a      	str	r2, [r3, #4]
}
 8000760:	46bd      	mov	sp, r7
 8000762:	b004      	add	sp, #16
 8000764:	bd80      	pop	{r7, pc}
 8000766:	46c0      	nop			; (mov r8, r8)
 8000768:	40021000 	.word	0x40021000

0800076c <RCC_GetSYSCLKSource>:
  *           - 0x04: HSE used as system clock  
  *           - 0x08: PLL used as system clock
  *           - 0x0C: HSI48 used as system clock, applicable only for STM32F072 devices  
  */
uint8_t RCC_GetSYSCLKSource(void)
{
 800076c:	b580      	push	{r7, lr}
 800076e:	af00      	add	r7, sp, #0
  return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
 8000770:	4b04      	ldr	r3, [pc, #16]	; (8000784 <RCC_GetSYSCLKSource+0x18>)
 8000772:	685b      	ldr	r3, [r3, #4]
 8000774:	b2db      	uxtb	r3, r3
 8000776:	220c      	movs	r2, #12
 8000778:	4013      	ands	r3, r2
 800077a:	b2db      	uxtb	r3, r3
}
 800077c:	1c18      	adds	r0, r3, #0
 800077e:	46bd      	mov	sp, r7
 8000780:	bd80      	pop	{r7, pc}
 8000782:	46c0      	nop			; (mov r8, r8)
 8000784:	40021000 	.word	0x40021000

08000788 <RCC_HCLKConfig>:
  *            @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
  *            @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
  * @retval None
  */
void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
{
 8000788:	b580      	push	{r7, lr}
 800078a:	b084      	sub	sp, #16
 800078c:	af00      	add	r7, sp, #0
 800078e:	6078      	str	r0, [r7, #4]
  uint32_t tmpreg = 0;
 8000790:	2300      	movs	r3, #0
 8000792:	60fb      	str	r3, [r7, #12]
  
  /* Check the parameters */
  assert_param(IS_RCC_HCLK(RCC_SYSCLK));
  
  tmpreg = RCC->CFGR;
 8000794:	4b08      	ldr	r3, [pc, #32]	; (80007b8 <RCC_HCLKConfig+0x30>)
 8000796:	685b      	ldr	r3, [r3, #4]
 8000798:	60fb      	str	r3, [r7, #12]
  
  /* Clear HPRE[3:0] bits */
  tmpreg &= ~RCC_CFGR_HPRE;
 800079a:	68fb      	ldr	r3, [r7, #12]
 800079c:	22f0      	movs	r2, #240	; 0xf0
 800079e:	4393      	bics	r3, r2
 80007a0:	60fb      	str	r3, [r7, #12]
  
  /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
  tmpreg |= RCC_SYSCLK;
 80007a2:	68fa      	ldr	r2, [r7, #12]
 80007a4:	687b      	ldr	r3, [r7, #4]
 80007a6:	4313      	orrs	r3, r2
 80007a8:	60fb      	str	r3, [r7, #12]
  
  /* Store the new value */
  RCC->CFGR = tmpreg;
 80007aa:	4b03      	ldr	r3, [pc, #12]	; (80007b8 <RCC_HCLKConfig+0x30>)
 80007ac:	68fa      	ldr	r2, [r7, #12]
 80007ae:	605a      	str	r2, [r3, #4]
}
 80007b0:	46bd      	mov	sp, r7
 80007b2:	b004      	add	sp, #16
 80007b4:	bd80      	pop	{r7, pc}
 80007b6:	46c0      	nop			; (mov r8, r8)
 80007b8:	40021000 	.word	0x40021000

080007bc <RCC_PCLKConfig>:
  *            @arg RCC_HCLK_Div8: APB clock = HCLK/8
  *            @arg RCC_HCLK_Div16: APB clock = HCLK/16
  * @retval None
  */
void RCC_PCLKConfig(uint32_t RCC_HCLK)
{
 80007bc:	b580      	push	{r7, lr}
 80007be:	b084      	sub	sp, #16
 80007c0:	af00      	add	r7, sp, #0
 80007c2:	6078      	str	r0, [r7, #4]
  uint32_t tmpreg = 0;
 80007c4:	2300      	movs	r3, #0
 80007c6:	60fb      	str	r3, [r7, #12]
  
  /* Check the parameters */
  assert_param(IS_RCC_PCLK(RCC_HCLK));
  
  tmpreg = RCC->CFGR;
 80007c8:	4b08      	ldr	r3, [pc, #32]	; (80007ec <RCC_PCLKConfig+0x30>)
 80007ca:	685b      	ldr	r3, [r3, #4]
 80007cc:	60fb      	str	r3, [r7, #12]
  
  /* Clear PPRE[2:0] bits */
  tmpreg &= ~RCC_CFGR_PPRE;
 80007ce:	68fb      	ldr	r3, [r7, #12]
 80007d0:	4a07      	ldr	r2, [pc, #28]	; (80007f0 <RCC_PCLKConfig+0x34>)
 80007d2:	4013      	ands	r3, r2
 80007d4:	60fb      	str	r3, [r7, #12]
  
  /* Set PPRE[2:0] bits according to RCC_HCLK value */
  tmpreg |= RCC_HCLK;
 80007d6:	68fa      	ldr	r2, [r7, #12]
 80007d8:	687b      	ldr	r3, [r7, #4]
 80007da:	4313      	orrs	r3, r2
 80007dc:	60fb      	str	r3, [r7, #12]
  
  /* Store the new value */
  RCC->CFGR = tmpreg;
 80007de:	4b03      	ldr	r3, [pc, #12]	; (80007ec <RCC_PCLKConfig+0x30>)
 80007e0:	68fa      	ldr	r2, [r7, #12]
 80007e2:	605a      	str	r2, [r3, #4]
}
 80007e4:	46bd      	mov	sp, r7
 80007e6:	b004      	add	sp, #16
 80007e8:	bd80      	pop	{r7, pc}
 80007ea:	46c0      	nop			; (mov r8, r8)
 80007ec:	40021000 	.word	0x40021000
 80007f0:	fffff8ff 	.word	0xfffff8ff

080007f4 <RCC_ADCCLKConfig>:
  *             @arg RCC_ADCCLK_PCLK_Div2: ADC clock = PCLK/2
  *             @arg RCC_ADCCLK_PCLK_Div4: ADC clock = PCLK/4  
  * @retval None
  */
void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK)
{ 
 80007f4:	b580      	push	{r7, lr}
 80007f6:	b082      	sub	sp, #8
 80007f8:	af00      	add	r7, sp, #0
 80007fa:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_RCC_ADCCLK(RCC_ADCCLK));

  /* Clear ADCPRE bit */
  RCC->CFGR &= ~RCC_CFGR_ADCPRE;
 80007fc:	4b0e      	ldr	r3, [pc, #56]	; (8000838 <RCC_ADCCLKConfig+0x44>)
 80007fe:	4a0e      	ldr	r2, [pc, #56]	; (8000838 <RCC_ADCCLKConfig+0x44>)
 8000800:	6852      	ldr	r2, [r2, #4]
 8000802:	490e      	ldr	r1, [pc, #56]	; (800083c <RCC_ADCCLKConfig+0x48>)
 8000804:	400a      	ands	r2, r1
 8000806:	605a      	str	r2, [r3, #4]
  /* Set ADCPRE bits according to RCC_PCLK value */
  RCC->CFGR |= RCC_ADCCLK & 0xFFFF;
 8000808:	4b0b      	ldr	r3, [pc, #44]	; (8000838 <RCC_ADCCLKConfig+0x44>)
 800080a:	4a0b      	ldr	r2, [pc, #44]	; (8000838 <RCC_ADCCLKConfig+0x44>)
 800080c:	6851      	ldr	r1, [r2, #4]
 800080e:	687a      	ldr	r2, [r7, #4]
 8000810:	0412      	lsls	r2, r2, #16
 8000812:	0c12      	lsrs	r2, r2, #16
 8000814:	430a      	orrs	r2, r1
 8000816:	605a      	str	r2, [r3, #4]

  /* Clear ADCSW bit */
  RCC->CFGR3 &= ~RCC_CFGR3_ADCSW; 
 8000818:	4b07      	ldr	r3, [pc, #28]	; (8000838 <RCC_ADCCLKConfig+0x44>)
 800081a:	4a07      	ldr	r2, [pc, #28]	; (8000838 <RCC_ADCCLKConfig+0x44>)
 800081c:	6b12      	ldr	r2, [r2, #48]	; 0x30
 800081e:	4908      	ldr	r1, [pc, #32]	; (8000840 <RCC_ADCCLKConfig+0x4c>)
 8000820:	400a      	ands	r2, r1
 8000822:	631a      	str	r2, [r3, #48]	; 0x30
  /* Set ADCSW bits according to RCC_ADCCLK value */
  RCC->CFGR3 |= RCC_ADCCLK >> 16;  
 8000824:	4b04      	ldr	r3, [pc, #16]	; (8000838 <RCC_ADCCLKConfig+0x44>)
 8000826:	4a04      	ldr	r2, [pc, #16]	; (8000838 <RCC_ADCCLKConfig+0x44>)
 8000828:	6b11      	ldr	r1, [r2, #48]	; 0x30
 800082a:	687a      	ldr	r2, [r7, #4]
 800082c:	0c12      	lsrs	r2, r2, #16
 800082e:	430a      	orrs	r2, r1
 8000830:	631a      	str	r2, [r3, #48]	; 0x30
}
 8000832:	46bd      	mov	sp, r7
 8000834:	b002      	add	sp, #8
 8000836:	bd80      	pop	{r7, pc}
 8000838:	40021000 	.word	0x40021000
 800083c:	ffffbfff 	.word	0xffffbfff
 8000840:	fffffeff 	.word	0xfffffeff

08000844 <RCC_CECCLKConfig>:
  *             @arg RCC_CECCLK_HSI_Div244: CEC clock = HSI/244 (32768Hz)
  *             @arg RCC_CECCLK_LSE: CEC clock = LSE
  * @retval None
  */
void RCC_CECCLKConfig(uint32_t RCC_CECCLK)
{ 
 8000844:	b580      	push	{r7, lr}
 8000846:	b082      	sub	sp, #8
 8000848:	af00      	add	r7, sp, #0
 800084a:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_RCC_CECCLK(RCC_CECCLK));

  /* Clear CECSW bit */
  RCC->CFGR3 &= ~RCC_CFGR3_CECSW;
 800084c:	4b07      	ldr	r3, [pc, #28]	; (800086c <RCC_CECCLKConfig+0x28>)
 800084e:	4a07      	ldr	r2, [pc, #28]	; (800086c <RCC_CECCLKConfig+0x28>)
 8000850:	6b12      	ldr	r2, [r2, #48]	; 0x30
 8000852:	2140      	movs	r1, #64	; 0x40
 8000854:	438a      	bics	r2, r1
 8000856:	631a      	str	r2, [r3, #48]	; 0x30
  /* Set CECSW bits according to RCC_CECCLK value */
  RCC->CFGR3 |= RCC_CECCLK;
 8000858:	4b04      	ldr	r3, [pc, #16]	; (800086c <RCC_CECCLKConfig+0x28>)
 800085a:	4a04      	ldr	r2, [pc, #16]	; (800086c <RCC_CECCLKConfig+0x28>)
 800085c:	6b11      	ldr	r1, [r2, #48]	; 0x30
 800085e:	687a      	ldr	r2, [r7, #4]
 8000860:	430a      	orrs	r2, r1
 8000862:	631a      	str	r2, [r3, #48]	; 0x30
}
 8000864:	46bd      	mov	sp, r7
 8000866:	b002      	add	sp, #8
 8000868:	bd80      	pop	{r7, pc}
 800086a:	46c0      	nop			; (mov r8, r8)
 800086c:	40021000 	.word	0x40021000

08000870 <RCC_I2CCLKConfig>:
  *             @arg RCC_I2C1CLK_HSI: I2C1 clock = HSI
  *             @arg RCC_I2C1CLK_SYSCLK: I2C1 clock = System Clock
  * @retval None
  */
void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK)
{ 
 8000870:	b580      	push	{r7, lr}
 8000872:	b082      	sub	sp, #8
 8000874:	af00      	add	r7, sp, #0
 8000876:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_RCC_I2CCLK(RCC_I2CCLK));

  /* Clear I2CSW bit */
  RCC->CFGR3 &= ~RCC_CFGR3_I2C1SW;
 8000878:	4b07      	ldr	r3, [pc, #28]	; (8000898 <RCC_I2CCLKConfig+0x28>)
 800087a:	4a07      	ldr	r2, [pc, #28]	; (8000898 <RCC_I2CCLKConfig+0x28>)
 800087c:	6b12      	ldr	r2, [r2, #48]	; 0x30
 800087e:	2110      	movs	r1, #16
 8000880:	438a      	bics	r2, r1
 8000882:	631a      	str	r2, [r3, #48]	; 0x30
  /* Set I2CSW bits according to RCC_I2CCLK value */
  RCC->CFGR3 |= RCC_I2CCLK;
 8000884:	4b04      	ldr	r3, [pc, #16]	; (8000898 <RCC_I2CCLKConfig+0x28>)
 8000886:	4a04      	ldr	r2, [pc, #16]	; (8000898 <RCC_I2CCLKConfig+0x28>)
 8000888:	6b11      	ldr	r1, [r2, #48]	; 0x30
 800088a:	687a      	ldr	r2, [r7, #4]
 800088c:	430a      	orrs	r2, r1
 800088e:	631a      	str	r2, [r3, #48]	; 0x30
}
 8000890:	46bd      	mov	sp, r7
 8000892:	b002      	add	sp, #8
 8000894:	bd80      	pop	{r7, pc}
 8000896:	46c0      	nop			; (mov r8, r8)
 8000898:	40021000 	.word	0x40021000

0800089c <RCC_USARTCLKConfig>:
  *             @arg RCC_USART3CLK_LSE: USART3 clock = LSE Clock, applicable only for STM32F091 devices
  *             @arg RCC_USART3CLK_HSI: USART3 clock = HSI Clock, applicable only for STM32F091 devices   
  * @retval None
  */
void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK)
{ 
 800089c:	b580      	push	{r7, lr}
 800089e:	b084      	sub	sp, #16
 80008a0:	af00      	add	r7, sp, #0
 80008a2:	6078      	str	r0, [r7, #4]
  uint32_t tmp = 0;
 80008a4:	2300      	movs	r3, #0
 80008a6:	60fb      	str	r3, [r7, #12]
  
  /* Check the parameters */
  assert_param(IS_RCC_USARTCLK(RCC_USARTCLK));

  /* Get USART index */
  tmp = (RCC_USARTCLK >> 28);
 80008a8:	687b      	ldr	r3, [r7, #4]
 80008aa:	0f1b      	lsrs	r3, r3, #28
 80008ac:	60fb      	str	r3, [r7, #12]

  /* Clear USARTSW[1:0] bit */
  if (tmp == (uint32_t)0x00000001)
 80008ae:	68fb      	ldr	r3, [r7, #12]
 80008b0:	2b01      	cmp	r3, #1
 80008b2:	d106      	bne.n	80008c2 <RCC_USARTCLKConfig+0x26>
  {
    /* Clear USART1SW[1:0] bit */  
    RCC->CFGR3 &= ~RCC_CFGR3_USART1SW;
 80008b4:	4b0f      	ldr	r3, [pc, #60]	; (80008f4 <RCC_USARTCLKConfig+0x58>)
 80008b6:	4a0f      	ldr	r2, [pc, #60]	; (80008f4 <RCC_USARTCLKConfig+0x58>)
 80008b8:	6b12      	ldr	r2, [r2, #48]	; 0x30
 80008ba:	2103      	movs	r1, #3
 80008bc:	438a      	bics	r2, r1
 80008be:	631a      	str	r2, [r3, #48]	; 0x30
 80008c0:	e00f      	b.n	80008e2 <RCC_USARTCLKConfig+0x46>
  }
  else if (tmp == (uint32_t)0x00000002)
 80008c2:	68fb      	ldr	r3, [r7, #12]
 80008c4:	2b02      	cmp	r3, #2
 80008c6:	d106      	bne.n	80008d6 <RCC_USARTCLKConfig+0x3a>
  {
    /* Clear USART2SW[1:0] bit */
    RCC->CFGR3 &= ~RCC_CFGR3_USART2SW;
 80008c8:	4b0a      	ldr	r3, [pc, #40]	; (80008f4 <RCC_USARTCLKConfig+0x58>)
 80008ca:	4a0a      	ldr	r2, [pc, #40]	; (80008f4 <RCC_USARTCLKConfig+0x58>)
 80008cc:	6b12      	ldr	r2, [r2, #48]	; 0x30
 80008ce:	490a      	ldr	r1, [pc, #40]	; (80008f8 <RCC_USARTCLKConfig+0x5c>)
 80008d0:	400a      	ands	r2, r1
 80008d2:	631a      	str	r2, [r3, #48]	; 0x30
 80008d4:	e005      	b.n	80008e2 <RCC_USARTCLKConfig+0x46>
  }
  else 
  {
    /* Clear USART3SW[1:0] bit */
    RCC->CFGR3 &= ~RCC_CFGR3_USART3SW;
 80008d6:	4b07      	ldr	r3, [pc, #28]	; (80008f4 <RCC_USARTCLKConfig+0x58>)
 80008d8:	4a06      	ldr	r2, [pc, #24]	; (80008f4 <RCC_USARTCLKConfig+0x58>)
 80008da:	6b12      	ldr	r2, [r2, #48]	; 0x30
 80008dc:	4907      	ldr	r1, [pc, #28]	; (80008fc <RCC_USARTCLKConfig+0x60>)
 80008de:	400a      	ands	r2, r1
 80008e0:	631a      	str	r2, [r3, #48]	; 0x30
  }

  /* Set USARTxSW bits according to RCC_USARTCLK value */
  RCC->CFGR3 |= RCC_USARTCLK;
 80008e2:	4b04      	ldr	r3, [pc, #16]	; (80008f4 <RCC_USARTCLKConfig+0x58>)
 80008e4:	4a03      	ldr	r2, [pc, #12]	; (80008f4 <RCC_USARTCLKConfig+0x58>)
 80008e6:	6b11      	ldr	r1, [r2, #48]	; 0x30
 80008e8:	687a      	ldr	r2, [r7, #4]
 80008ea:	430a      	orrs	r2, r1
 80008ec:	631a      	str	r2, [r3, #48]	; 0x30
}
 80008ee:	46bd      	mov	sp, r7
 80008f0:	b004      	add	sp, #16
 80008f2:	bd80      	pop	{r7, pc}
 80008f4:	40021000 	.word	0x40021000
 80008f8:	fffcffff 	.word	0xfffcffff
 80008fc:	fff3ffff 	.word	0xfff3ffff

08000900 <RCC_USBCLKConfig>:
  *             @arg RCC_USBCLK_HSI48: USB clock = HSI48
  *             @arg RCC_USBCLK_PLLCLK: USB clock = PLL clock
  * @retval None
  */
void RCC_USBCLKConfig(uint32_t RCC_USBCLK)
{ 
 8000900:	b580      	push	{r7, lr}
 8000902:	b082      	sub	sp, #8
 8000904:	af00      	add	r7, sp, #0
 8000906:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_RCC_USBCLK(RCC_USBCLK));

  /* Clear USBSW bit */
  RCC->CFGR3 &= ~RCC_CFGR3_USBSW;
 8000908:	4b07      	ldr	r3, [pc, #28]	; (8000928 <RCC_USBCLKConfig+0x28>)
 800090a:	4a07      	ldr	r2, [pc, #28]	; (8000928 <RCC_USBCLKConfig+0x28>)
 800090c:	6b12      	ldr	r2, [r2, #48]	; 0x30
 800090e:	2180      	movs	r1, #128	; 0x80
 8000910:	438a      	bics	r2, r1
 8000912:	631a      	str	r2, [r3, #48]	; 0x30
  /* Set USBSW bits according to RCC_USBCLK value */
  RCC->CFGR3 |= RCC_USBCLK;
 8000914:	4b04      	ldr	r3, [pc, #16]	; (8000928 <RCC_USBCLKConfig+0x28>)
 8000916:	4a04      	ldr	r2, [pc, #16]	; (8000928 <RCC_USBCLKConfig+0x28>)
 8000918:	6b11      	ldr	r1, [r2, #48]	; 0x30
 800091a:	687a      	ldr	r2, [r7, #4]
 800091c:	430a      	orrs	r2, r1
 800091e:	631a      	str	r2, [r3, #48]	; 0x30
}
 8000920:	46bd      	mov	sp, r7
 8000922:	b002      	add	sp, #8
 8000924:	bd80      	pop	{r7, pc}
 8000926:	46c0      	nop			; (mov r8, r8)
 8000928:	40021000 	.word	0x40021000

0800092c <RCC_GetClocksFreq>:
  *         configuration based on this function will be incorrect.
  *    
  * @retval None
  */
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
{
 800092c:	b580      	push	{r7, lr}
 800092e:	b088      	sub	sp, #32
 8000930:	af00      	add	r7, sp, #0
 8000932:	6078      	str	r0, [r7, #4]
  uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0, presc = 0, pllclk = 0;
 8000934:	2300      	movs	r3, #0
 8000936:	61bb      	str	r3, [r7, #24]
 8000938:	2300      	movs	r3, #0
 800093a:	617b      	str	r3, [r7, #20]
 800093c:	2300      	movs	r3, #0
 800093e:	613b      	str	r3, [r7, #16]
 8000940:	2300      	movs	r3, #0
 8000942:	60fb      	str	r3, [r7, #12]
 8000944:	2300      	movs	r3, #0
 8000946:	60bb      	str	r3, [r7, #8]
 8000948:	2300      	movs	r3, #0
 800094a:	61fb      	str	r3, [r7, #28]

  /* Get SYSCLK source -------------------------------------------------------*/
  tmp = RCC->CFGR & RCC_CFGR_SWS;
 800094c:	4ba3      	ldr	r3, [pc, #652]	; (8000bdc <RCC_GetClocksFreq+0x2b0>)
 800094e:	685b      	ldr	r3, [r3, #4]
 8000950:	220c      	movs	r2, #12
 8000952:	4013      	ands	r3, r2
 8000954:	61bb      	str	r3, [r7, #24]
  
  switch (tmp)
 8000956:	69bb      	ldr	r3, [r7, #24]
 8000958:	2b04      	cmp	r3, #4
 800095a:	d00c      	beq.n	8000976 <RCC_GetClocksFreq+0x4a>
 800095c:	d802      	bhi.n	8000964 <RCC_GetClocksFreq+0x38>
 800095e:	2b00      	cmp	r3, #0
 8000960:	d005      	beq.n	800096e <RCC_GetClocksFreq+0x42>
 8000962:	e03b      	b.n	80009dc <RCC_GetClocksFreq+0xb0>
 8000964:	2b08      	cmp	r3, #8
 8000966:	d00a      	beq.n	800097e <RCC_GetClocksFreq+0x52>
 8000968:	2b0c      	cmp	r3, #12
 800096a:	d033      	beq.n	80009d4 <RCC_GetClocksFreq+0xa8>
 800096c:	e036      	b.n	80009dc <RCC_GetClocksFreq+0xb0>
  {
    case 0x00:  /* HSI used as system clock */
      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
 800096e:	687b      	ldr	r3, [r7, #4]
 8000970:	4a9b      	ldr	r2, [pc, #620]	; (8000be0 <RCC_GetClocksFreq+0x2b4>)
 8000972:	601a      	str	r2, [r3, #0]
      break;
 8000974:	e036      	b.n	80009e4 <RCC_GetClocksFreq+0xb8>
    case 0x04:  /* HSE used as system clock */
      RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
 8000976:	687b      	ldr	r3, [r7, #4]
 8000978:	4a99      	ldr	r2, [pc, #612]	; (8000be0 <RCC_GetClocksFreq+0x2b4>)
 800097a:	601a      	str	r2, [r3, #0]
      break;
 800097c:	e032      	b.n	80009e4 <RCC_GetClocksFreq+0xb8>
    case 0x08:  /* PLL used as system clock */
      /* Get PLL clock source and multiplication factor ----------------------*/
      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
 800097e:	4b97      	ldr	r3, [pc, #604]	; (8000bdc <RCC_GetClocksFreq+0x2b0>)
 8000980:	685a      	ldr	r2, [r3, #4]
 8000982:	23f0      	movs	r3, #240	; 0xf0
 8000984:	039b      	lsls	r3, r3, #14
 8000986:	4013      	ands	r3, r2
 8000988:	617b      	str	r3, [r7, #20]
      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
 800098a:	4b94      	ldr	r3, [pc, #592]	; (8000bdc <RCC_GetClocksFreq+0x2b0>)
 800098c:	685a      	ldr	r2, [r3, #4]
 800098e:	23c0      	movs	r3, #192	; 0xc0
 8000990:	025b      	lsls	r3, r3, #9
 8000992:	4013      	ands	r3, r2
 8000994:	613b      	str	r3, [r7, #16]
      pllmull = ( pllmull >> 18) + 2;
 8000996:	697b      	ldr	r3, [r7, #20]
 8000998:	0c9b      	lsrs	r3, r3, #18
 800099a:	3302      	adds	r3, #2
 800099c:	617b      	str	r3, [r7, #20]
      
      if (pllsource == 0x00)
 800099e:	693b      	ldr	r3, [r7, #16]
 80009a0:	2b00      	cmp	r3, #0
 80009a2:	d104      	bne.n	80009ae <RCC_GetClocksFreq+0x82>
      {
        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
        pllclk = (HSI_VALUE >> 1) * pllmull;
 80009a4:	697b      	ldr	r3, [r7, #20]
 80009a6:	4a8f      	ldr	r2, [pc, #572]	; (8000be4 <RCC_GetClocksFreq+0x2b8>)
 80009a8:	4353      	muls	r3, r2
 80009aa:	61fb      	str	r3, [r7, #28]
 80009ac:	e00e      	b.n	80009cc <RCC_GetClocksFreq+0xa0>
      }
      else
      {
        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
 80009ae:	4b8b      	ldr	r3, [pc, #556]	; (8000bdc <RCC_GetClocksFreq+0x2b0>)
 80009b0:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 80009b2:	220f      	movs	r2, #15
 80009b4:	4013      	ands	r3, r2
 80009b6:	3301      	adds	r3, #1
 80009b8:	60fb      	str	r3, [r7, #12]
        /* HSE oscillator clock selected as PREDIV1 clock entry */
        pllclk = (HSE_VALUE / prediv1factor) * pllmull; 
 80009ba:	4889      	ldr	r0, [pc, #548]	; (8000be0 <RCC_GetClocksFreq+0x2b4>)
 80009bc:	68f9      	ldr	r1, [r7, #12]
 80009be:	f001 feb3 	bl	8002728 <____aeabi_uidiv_from_thumb>
 80009c2:	1c03      	adds	r3, r0, #0
 80009c4:	1c1a      	adds	r2, r3, #0
 80009c6:	697b      	ldr	r3, [r7, #20]
 80009c8:	4353      	muls	r3, r2
 80009ca:	61fb      	str	r3, [r7, #28]
      }
      RCC_Clocks->SYSCLK_Frequency = pllclk;      
 80009cc:	687b      	ldr	r3, [r7, #4]
 80009ce:	69fa      	ldr	r2, [r7, #28]
 80009d0:	601a      	str	r2, [r3, #0]
      break;
 80009d2:	e007      	b.n	80009e4 <RCC_GetClocksFreq+0xb8>
    case 0x0C:  /* HSI48 used as system clock */
      RCC_Clocks->SYSCLK_Frequency = HSI48_VALUE;
 80009d4:	687b      	ldr	r3, [r7, #4]
 80009d6:	4a84      	ldr	r2, [pc, #528]	; (8000be8 <RCC_GetClocksFreq+0x2bc>)
 80009d8:	601a      	str	r2, [r3, #0]
      break;
 80009da:	e003      	b.n	80009e4 <RCC_GetClocksFreq+0xb8>
    default: /* HSI used as system clock */
      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
 80009dc:	687b      	ldr	r3, [r7, #4]
 80009de:	4a80      	ldr	r2, [pc, #512]	; (8000be0 <RCC_GetClocksFreq+0x2b4>)
 80009e0:	601a      	str	r2, [r3, #0]
      break;
 80009e2:	46c0      	nop			; (mov r8, r8)
  }
  /* Compute HCLK, PCLK clocks frequencies -----------------------------------*/
  /* Get HCLK prescaler */
  tmp = RCC->CFGR & RCC_CFGR_HPRE;
 80009e4:	4b7d      	ldr	r3, [pc, #500]	; (8000bdc <RCC_GetClocksFreq+0x2b0>)
 80009e6:	685b      	ldr	r3, [r3, #4]
 80009e8:	22f0      	movs	r2, #240	; 0xf0
 80009ea:	4013      	ands	r3, r2
 80009ec:	61bb      	str	r3, [r7, #24]
  tmp = tmp >> 4;
 80009ee:	69bb      	ldr	r3, [r7, #24]
 80009f0:	091b      	lsrs	r3, r3, #4
 80009f2:	61bb      	str	r3, [r7, #24]
  presc = APBAHBPrescTable[tmp]; 
 80009f4:	4a7d      	ldr	r2, [pc, #500]	; (8000bec <RCC_GetClocksFreq+0x2c0>)
 80009f6:	69bb      	ldr	r3, [r7, #24]
 80009f8:	18d3      	adds	r3, r2, r3
 80009fa:	781b      	ldrb	r3, [r3, #0]
 80009fc:	b2db      	uxtb	r3, r3
 80009fe:	60bb      	str	r3, [r7, #8]
  /* HCLK clock frequency */
  RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
 8000a00:	687b      	ldr	r3, [r7, #4]
 8000a02:	681a      	ldr	r2, [r3, #0]
 8000a04:	68bb      	ldr	r3, [r7, #8]
 8000a06:	40da      	lsrs	r2, r3
 8000a08:	687b      	ldr	r3, [r7, #4]
 8000a0a:	605a      	str	r2, [r3, #4]

  /* Get PCLK prescaler */
  tmp = RCC->CFGR & RCC_CFGR_PPRE;
 8000a0c:	4b73      	ldr	r3, [pc, #460]	; (8000bdc <RCC_GetClocksFreq+0x2b0>)
 8000a0e:	685a      	ldr	r2, [r3, #4]
 8000a10:	23e0      	movs	r3, #224	; 0xe0
 8000a12:	00db      	lsls	r3, r3, #3
 8000a14:	4013      	ands	r3, r2
 8000a16:	61bb      	str	r3, [r7, #24]
  tmp = tmp >> 8;
 8000a18:	69bb      	ldr	r3, [r7, #24]
 8000a1a:	0a1b      	lsrs	r3, r3, #8
 8000a1c:	61bb      	str	r3, [r7, #24]
  presc = APBAHBPrescTable[tmp];
 8000a1e:	4a73      	ldr	r2, [pc, #460]	; (8000bec <RCC_GetClocksFreq+0x2c0>)
 8000a20:	69bb      	ldr	r3, [r7, #24]
 8000a22:	18d3      	adds	r3, r2, r3
 8000a24:	781b      	ldrb	r3, [r3, #0]
 8000a26:	b2db      	uxtb	r3, r3
 8000a28:	60bb      	str	r3, [r7, #8]
  /* PCLK clock frequency */
  RCC_Clocks->PCLK_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
 8000a2a:	687b      	ldr	r3, [r7, #4]
 8000a2c:	685a      	ldr	r2, [r3, #4]
 8000a2e:	68bb      	ldr	r3, [r7, #8]
 8000a30:	40da      	lsrs	r2, r3
 8000a32:	687b      	ldr	r3, [r7, #4]
 8000a34:	609a      	str	r2, [r3, #8]

  /* ADCCLK clock frequency */
  if((RCC->CFGR3 & RCC_CFGR3_ADCSW) != RCC_CFGR3_ADCSW)
 8000a36:	4b69      	ldr	r3, [pc, #420]	; (8000bdc <RCC_GetClocksFreq+0x2b0>)
 8000a38:	6b1a      	ldr	r2, [r3, #48]	; 0x30
 8000a3a:	2380      	movs	r3, #128	; 0x80
 8000a3c:	005b      	lsls	r3, r3, #1
 8000a3e:	4013      	ands	r3, r2
 8000a40:	d103      	bne.n	8000a4a <RCC_GetClocksFreq+0x11e>
  {
    /* ADC Clock is HSI14 Osc. */
    RCC_Clocks->ADCCLK_Frequency = HSI14_VALUE;
 8000a42:	687b      	ldr	r3, [r7, #4]
 8000a44:	4a6a      	ldr	r2, [pc, #424]	; (8000bf0 <RCC_GetClocksFreq+0x2c4>)
 8000a46:	60da      	str	r2, [r3, #12]
 8000a48:	e010      	b.n	8000a6c <RCC_GetClocksFreq+0x140>
  }
  else
  {
    if((RCC->CFGR & RCC_CFGR_ADCPRE) != RCC_CFGR_ADCPRE)
 8000a4a:	4b64      	ldr	r3, [pc, #400]	; (8000bdc <RCC_GetClocksFreq+0x2b0>)
 8000a4c:	685a      	ldr	r2, [r3, #4]
 8000a4e:	2380      	movs	r3, #128	; 0x80
 8000a50:	01db      	lsls	r3, r3, #7
 8000a52:	4013      	ands	r3, r2
 8000a54:	d105      	bne.n	8000a62 <RCC_GetClocksFreq+0x136>
    {
      /* ADC Clock is derived from PCLK/2 */
      RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK_Frequency >> 1;
 8000a56:	687b      	ldr	r3, [r7, #4]
 8000a58:	689b      	ldr	r3, [r3, #8]
 8000a5a:	085a      	lsrs	r2, r3, #1
 8000a5c:	687b      	ldr	r3, [r7, #4]
 8000a5e:	60da      	str	r2, [r3, #12]
 8000a60:	e004      	b.n	8000a6c <RCC_GetClocksFreq+0x140>
    }
    else
    {
      /* ADC Clock is derived from PCLK/4 */
      RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK_Frequency >> 2;
 8000a62:	687b      	ldr	r3, [r7, #4]
 8000a64:	689b      	ldr	r3, [r3, #8]
 8000a66:	089a      	lsrs	r2, r3, #2
 8000a68:	687b      	ldr	r3, [r7, #4]
 8000a6a:	60da      	str	r2, [r3, #12]
    }
    
  }

  /* CECCLK clock frequency */
  if((RCC->CFGR3 & RCC_CFGR3_CECSW) != RCC_CFGR3_CECSW)
 8000a6c:	4b5b      	ldr	r3, [pc, #364]	; (8000bdc <RCC_GetClocksFreq+0x2b0>)
 8000a6e:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8000a70:	2240      	movs	r2, #64	; 0x40
 8000a72:	4013      	ands	r3, r2
 8000a74:	d103      	bne.n	8000a7e <RCC_GetClocksFreq+0x152>
  {
    /* CEC Clock is HSI/244 */
    RCC_Clocks->CECCLK_Frequency = HSI_VALUE / 244;
 8000a76:	687b      	ldr	r3, [r7, #4]
 8000a78:	4a5e      	ldr	r2, [pc, #376]	; (8000bf4 <RCC_GetClocksFreq+0x2c8>)
 8000a7a:	611a      	str	r2, [r3, #16]
 8000a7c:	e003      	b.n	8000a86 <RCC_GetClocksFreq+0x15a>
  }
  else
  {
    /* CECC Clock is LSE Osc. */
    RCC_Clocks->CECCLK_Frequency = LSE_VALUE;
 8000a7e:	687b      	ldr	r3, [r7, #4]
 8000a80:	2280      	movs	r2, #128	; 0x80
 8000a82:	0212      	lsls	r2, r2, #8
 8000a84:	611a      	str	r2, [r3, #16]
  }

  /* I2C1CLK clock frequency */
  if((RCC->CFGR3 & RCC_CFGR3_I2C1SW) != RCC_CFGR3_I2C1SW)
 8000a86:	4b55      	ldr	r3, [pc, #340]	; (8000bdc <RCC_GetClocksFreq+0x2b0>)
 8000a88:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8000a8a:	2210      	movs	r2, #16
 8000a8c:	4013      	ands	r3, r2
 8000a8e:	d103      	bne.n	8000a98 <RCC_GetClocksFreq+0x16c>
  {
    /* I2C1 Clock is HSI Osc. */
    RCC_Clocks->I2C1CLK_Frequency = HSI_VALUE;
 8000a90:	687b      	ldr	r3, [r7, #4]
 8000a92:	4a53      	ldr	r2, [pc, #332]	; (8000be0 <RCC_GetClocksFreq+0x2b4>)
 8000a94:	615a      	str	r2, [r3, #20]
 8000a96:	e003      	b.n	8000aa0 <RCC_GetClocksFreq+0x174>
  }
  else
  {
    /* I2C1 Clock is System Clock */
    RCC_Clocks->I2C1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
 8000a98:	687b      	ldr	r3, [r7, #4]
 8000a9a:	681a      	ldr	r2, [r3, #0]
 8000a9c:	687b      	ldr	r3, [r7, #4]
 8000a9e:	615a      	str	r2, [r3, #20]
  }

  /* USART1CLK clock frequency */
  if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == 0x0)
 8000aa0:	4b4e      	ldr	r3, [pc, #312]	; (8000bdc <RCC_GetClocksFreq+0x2b0>)
 8000aa2:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8000aa4:	2203      	movs	r2, #3
 8000aa6:	4013      	ands	r3, r2
 8000aa8:	d104      	bne.n	8000ab4 <RCC_GetClocksFreq+0x188>
  {
    /* USART1 Clock is PCLK */
    RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK_Frequency;
 8000aaa:	687b      	ldr	r3, [r7, #4]
 8000aac:	689a      	ldr	r2, [r3, #8]
 8000aae:	687b      	ldr	r3, [r7, #4]
 8000ab0:	619a      	str	r2, [r3, #24]
 8000ab2:	e01e      	b.n	8000af2 <RCC_GetClocksFreq+0x1c6>
  }
  else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_0)
 8000ab4:	4b49      	ldr	r3, [pc, #292]	; (8000bdc <RCC_GetClocksFreq+0x2b0>)
 8000ab6:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8000ab8:	2203      	movs	r2, #3
 8000aba:	4013      	ands	r3, r2
 8000abc:	2b01      	cmp	r3, #1
 8000abe:	d104      	bne.n	8000aca <RCC_GetClocksFreq+0x19e>
  {
    /* USART1 Clock is System Clock */
    RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
 8000ac0:	687b      	ldr	r3, [r7, #4]
 8000ac2:	681a      	ldr	r2, [r3, #0]
 8000ac4:	687b      	ldr	r3, [r7, #4]
 8000ac6:	619a      	str	r2, [r3, #24]
 8000ac8:	e013      	b.n	8000af2 <RCC_GetClocksFreq+0x1c6>
  }
  else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_1)
 8000aca:	4b44      	ldr	r3, [pc, #272]	; (8000bdc <RCC_GetClocksFreq+0x2b0>)
 8000acc:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8000ace:	2203      	movs	r2, #3
 8000ad0:	4013      	ands	r3, r2
 8000ad2:	2b02      	cmp	r3, #2
 8000ad4:	d104      	bne.n	8000ae0 <RCC_GetClocksFreq+0x1b4>
  {
    /* USART1 Clock is LSE Osc. */
    RCC_Clocks->USART1CLK_Frequency = LSE_VALUE;
 8000ad6:	687b      	ldr	r3, [r7, #4]
 8000ad8:	2280      	movs	r2, #128	; 0x80
 8000ada:	0212      	lsls	r2, r2, #8
 8000adc:	619a      	str	r2, [r3, #24]
 8000ade:	e008      	b.n	8000af2 <RCC_GetClocksFreq+0x1c6>
  }
  else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW)
 8000ae0:	4b3e      	ldr	r3, [pc, #248]	; (8000bdc <RCC_GetClocksFreq+0x2b0>)
 8000ae2:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8000ae4:	2203      	movs	r2, #3
 8000ae6:	4013      	ands	r3, r2
 8000ae8:	2b03      	cmp	r3, #3
 8000aea:	d102      	bne.n	8000af2 <RCC_GetClocksFreq+0x1c6>
  {
    /* USART1 Clock is HSI Osc. */
    RCC_Clocks->USART1CLK_Frequency = HSI_VALUE;
 8000aec:	687b      	ldr	r3, [r7, #4]
 8000aee:	4a3c      	ldr	r2, [pc, #240]	; (8000be0 <RCC_GetClocksFreq+0x2b4>)
 8000af0:	619a      	str	r2, [r3, #24]
  }
  
  /* USART2CLK clock frequency */
  if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == 0x0)
 8000af2:	4b3a      	ldr	r3, [pc, #232]	; (8000bdc <RCC_GetClocksFreq+0x2b0>)
 8000af4:	6b1a      	ldr	r2, [r3, #48]	; 0x30
 8000af6:	23c0      	movs	r3, #192	; 0xc0
 8000af8:	029b      	lsls	r3, r3, #10
 8000afa:	4013      	ands	r3, r2
 8000afc:	d104      	bne.n	8000b08 <RCC_GetClocksFreq+0x1dc>
  {
    /* USART Clock is PCLK */
    RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->PCLK_Frequency;
 8000afe:	687b      	ldr	r3, [r7, #4]
 8000b00:	689a      	ldr	r2, [r3, #8]
 8000b02:	687b      	ldr	r3, [r7, #4]
 8000b04:	61da      	str	r2, [r3, #28]
 8000b06:	e027      	b.n	8000b58 <RCC_GetClocksFreq+0x22c>
  }
  else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_0)
 8000b08:	4b34      	ldr	r3, [pc, #208]	; (8000bdc <RCC_GetClocksFreq+0x2b0>)
 8000b0a:	6b1a      	ldr	r2, [r3, #48]	; 0x30
 8000b0c:	23c0      	movs	r3, #192	; 0xc0
 8000b0e:	029b      	lsls	r3, r3, #10
 8000b10:	401a      	ands	r2, r3
 8000b12:	2380      	movs	r3, #128	; 0x80
 8000b14:	025b      	lsls	r3, r3, #9
 8000b16:	429a      	cmp	r2, r3
 8000b18:	d104      	bne.n	8000b24 <RCC_GetClocksFreq+0x1f8>
  {
    /* USART Clock is System Clock */
    RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
 8000b1a:	687b      	ldr	r3, [r7, #4]
 8000b1c:	681a      	ldr	r2, [r3, #0]
 8000b1e:	687b      	ldr	r3, [r7, #4]
 8000b20:	61da      	str	r2, [r3, #28]
 8000b22:	e019      	b.n	8000b58 <RCC_GetClocksFreq+0x22c>
  }
  else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_1)
 8000b24:	4b2d      	ldr	r3, [pc, #180]	; (8000bdc <RCC_GetClocksFreq+0x2b0>)
 8000b26:	6b1a      	ldr	r2, [r3, #48]	; 0x30
 8000b28:	23c0      	movs	r3, #192	; 0xc0
 8000b2a:	029b      	lsls	r3, r3, #10
 8000b2c:	401a      	ands	r2, r3
 8000b2e:	2380      	movs	r3, #128	; 0x80
 8000b30:	029b      	lsls	r3, r3, #10
 8000b32:	429a      	cmp	r2, r3
 8000b34:	d104      	bne.n	8000b40 <RCC_GetClocksFreq+0x214>
  {
    /* USART Clock is LSE Osc. */
    RCC_Clocks->USART2CLK_Frequency = LSE_VALUE;
 8000b36:	687b      	ldr	r3, [r7, #4]
 8000b38:	2280      	movs	r2, #128	; 0x80
 8000b3a:	0212      	lsls	r2, r2, #8
 8000b3c:	61da      	str	r2, [r3, #28]
 8000b3e:	e00b      	b.n	8000b58 <RCC_GetClocksFreq+0x22c>
  }
  else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW)
 8000b40:	4b26      	ldr	r3, [pc, #152]	; (8000bdc <RCC_GetClocksFreq+0x2b0>)
 8000b42:	6b1a      	ldr	r2, [r3, #48]	; 0x30
 8000b44:	23c0      	movs	r3, #192	; 0xc0
 8000b46:	029b      	lsls	r3, r3, #10
 8000b48:	401a      	ands	r2, r3
 8000b4a:	23c0      	movs	r3, #192	; 0xc0
 8000b4c:	029b      	lsls	r3, r3, #10
 8000b4e:	429a      	cmp	r2, r3
 8000b50:	d102      	bne.n	8000b58 <RCC_GetClocksFreq+0x22c>
  {
    /* USART Clock is HSI Osc. */
    RCC_Clocks->USART2CLK_Frequency = HSI_VALUE;
 8000b52:	687b      	ldr	r3, [r7, #4]
 8000b54:	4a22      	ldr	r2, [pc, #136]	; (8000be0 <RCC_GetClocksFreq+0x2b4>)
 8000b56:	61da      	str	r2, [r3, #28]
  }
  
  /* USART3CLK clock frequency */
  if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == 0x0)
 8000b58:	4b20      	ldr	r3, [pc, #128]	; (8000bdc <RCC_GetClocksFreq+0x2b0>)
 8000b5a:	6b1a      	ldr	r2, [r3, #48]	; 0x30
 8000b5c:	23c0      	movs	r3, #192	; 0xc0
 8000b5e:	031b      	lsls	r3, r3, #12
 8000b60:	4013      	ands	r3, r2
 8000b62:	d104      	bne.n	8000b6e <RCC_GetClocksFreq+0x242>
  {
    /* USART Clock is PCLK */
    RCC_Clocks->USART3CLK_Frequency = RCC_Clocks->PCLK_Frequency;
 8000b64:	687b      	ldr	r3, [r7, #4]
 8000b66:	689a      	ldr	r2, [r3, #8]
 8000b68:	687b      	ldr	r3, [r7, #4]
 8000b6a:	621a      	str	r2, [r3, #32]
 8000b6c:	e027      	b.n	8000bbe <RCC_GetClocksFreq+0x292>
  }
  else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW_0)
 8000b6e:	4b1b      	ldr	r3, [pc, #108]	; (8000bdc <RCC_GetClocksFreq+0x2b0>)
 8000b70:	6b1a      	ldr	r2, [r3, #48]	; 0x30
 8000b72:	23c0      	movs	r3, #192	; 0xc0
 8000b74:	031b      	lsls	r3, r3, #12
 8000b76:	401a      	ands	r2, r3
 8000b78:	2380      	movs	r3, #128	; 0x80
 8000b7a:	02db      	lsls	r3, r3, #11
 8000b7c:	429a      	cmp	r2, r3
 8000b7e:	d104      	bne.n	8000b8a <RCC_GetClocksFreq+0x25e>
  {
    /* USART Clock is System Clock */
    RCC_Clocks->USART3CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
 8000b80:	687b      	ldr	r3, [r7, #4]
 8000b82:	681a      	ldr	r2, [r3, #0]
 8000b84:	687b      	ldr	r3, [r7, #4]
 8000b86:	621a      	str	r2, [r3, #32]
 8000b88:	e019      	b.n	8000bbe <RCC_GetClocksFreq+0x292>
  }
  else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW_1)
 8000b8a:	4b14      	ldr	r3, [pc, #80]	; (8000bdc <RCC_GetClocksFreq+0x2b0>)
 8000b8c:	6b1a      	ldr	r2, [r3, #48]	; 0x30
 8000b8e:	23c0      	movs	r3, #192	; 0xc0
 8000b90:	031b      	lsls	r3, r3, #12
 8000b92:	401a      	ands	r2, r3
 8000b94:	2380      	movs	r3, #128	; 0x80
 8000b96:	031b      	lsls	r3, r3, #12
 8000b98:	429a      	cmp	r2, r3
 8000b9a:	d104      	bne.n	8000ba6 <RCC_GetClocksFreq+0x27a>
  {
    /* USART Clock is LSE Osc. */
    RCC_Clocks->USART3CLK_Frequency = LSE_VALUE;
 8000b9c:	687b      	ldr	r3, [r7, #4]
 8000b9e:	2280      	movs	r2, #128	; 0x80
 8000ba0:	0212      	lsls	r2, r2, #8
 8000ba2:	621a      	str	r2, [r3, #32]
 8000ba4:	e00b      	b.n	8000bbe <RCC_GetClocksFreq+0x292>
  }
  else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW)
 8000ba6:	4b0d      	ldr	r3, [pc, #52]	; (8000bdc <RCC_GetClocksFreq+0x2b0>)
 8000ba8:	6b1a      	ldr	r2, [r3, #48]	; 0x30
 8000baa:	23c0      	movs	r3, #192	; 0xc0
 8000bac:	031b      	lsls	r3, r3, #12
 8000bae:	401a      	ands	r2, r3
 8000bb0:	23c0      	movs	r3, #192	; 0xc0
 8000bb2:	031b      	lsls	r3, r3, #12
 8000bb4:	429a      	cmp	r2, r3
 8000bb6:	d102      	bne.n	8000bbe <RCC_GetClocksFreq+0x292>
  {
    /* USART Clock is HSI Osc. */
    RCC_Clocks->USART3CLK_Frequency = HSI_VALUE;
 8000bb8:	687b      	ldr	r3, [r7, #4]
 8000bba:	4a09      	ldr	r2, [pc, #36]	; (8000be0 <RCC_GetClocksFreq+0x2b4>)
 8000bbc:	621a      	str	r2, [r3, #32]
  }
  
  /* USBCLK clock frequency */
  if((RCC->CFGR3 & RCC_CFGR3_USBSW) != RCC_CFGR3_USBSW)
 8000bbe:	4b07      	ldr	r3, [pc, #28]	; (8000bdc <RCC_GetClocksFreq+0x2b0>)
 8000bc0:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8000bc2:	2280      	movs	r2, #128	; 0x80
 8000bc4:	4013      	ands	r3, r2
 8000bc6:	d103      	bne.n	8000bd0 <RCC_GetClocksFreq+0x2a4>
  {
    /* USB Clock is HSI48 */
    RCC_Clocks->USBCLK_Frequency = HSI48_VALUE;
 8000bc8:	687b      	ldr	r3, [r7, #4]
 8000bca:	4a07      	ldr	r2, [pc, #28]	; (8000be8 <RCC_GetClocksFreq+0x2bc>)
 8000bcc:	625a      	str	r2, [r3, #36]	; 0x24
 8000bce:	e002      	b.n	8000bd6 <RCC_GetClocksFreq+0x2aa>
  }
  else
  {
    /* USB Clock is PLL clock */
    RCC_Clocks->USBCLK_Frequency = pllclk;
 8000bd0:	687b      	ldr	r3, [r7, #4]
 8000bd2:	69fa      	ldr	r2, [r7, #28]
 8000bd4:	625a      	str	r2, [r3, #36]	; 0x24
  }   
}
 8000bd6:	46bd      	mov	sp, r7
 8000bd8:	b008      	add	sp, #32
 8000bda:	bd80      	pop	{r7, pc}
 8000bdc:	40021000 	.word	0x40021000
 8000be0:	007a1200 	.word	0x007a1200
 8000be4:	003d0900 	.word	0x003d0900
 8000be8:	02dc6c00 	.word	0x02dc6c00
 8000bec:	20000014 	.word	0x20000014
 8000bf0:	00d59f80 	.word	0x00d59f80
 8000bf4:	00008012 	.word	0x00008012

08000bf8 <RCC_RTCCLKConfig>:
  *         RTC clock source).
  *                          
  * @retval None
  */
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
{
 8000bf8:	b580      	push	{r7, lr}
 8000bfa:	b082      	sub	sp, #8
 8000bfc:	af00      	add	r7, sp, #0
 8000bfe:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
  
  /* Select the RTC clock source */
  RCC->BDCR |= RCC_RTCCLKSource;
 8000c00:	4b04      	ldr	r3, [pc, #16]	; (8000c14 <RCC_RTCCLKConfig+0x1c>)
 8000c02:	4a04      	ldr	r2, [pc, #16]	; (8000c14 <RCC_RTCCLKConfig+0x1c>)
 8000c04:	6a11      	ldr	r1, [r2, #32]
 8000c06:	687a      	ldr	r2, [r7, #4]
 8000c08:	430a      	orrs	r2, r1
 8000c0a:	621a      	str	r2, [r3, #32]
}
 8000c0c:	46bd      	mov	sp, r7
 8000c0e:	b002      	add	sp, #8
 8000c10:	bd80      	pop	{r7, pc}
 8000c12:	46c0      	nop			; (mov r8, r8)
 8000c14:	40021000 	.word	0x40021000

08000c18 <RCC_RTCCLKCmd>:
  * @param  NewState: new state of the RTC clock.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_RTCCLKCmd(FunctionalState NewState)
{
 8000c18:	b580      	push	{r7, lr}
 8000c1a:	b082      	sub	sp, #8
 8000c1c:	af00      	add	r7, sp, #0
 8000c1e:	1c02      	adds	r2, r0, #0
 8000c20:	1dfb      	adds	r3, r7, #7
 8000c22:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  
  if (NewState != DISABLE)
 8000c24:	1dfb      	adds	r3, r7, #7
 8000c26:	781b      	ldrb	r3, [r3, #0]
 8000c28:	2b00      	cmp	r3, #0
 8000c2a:	d007      	beq.n	8000c3c <RCC_RTCCLKCmd+0x24>
  {
    RCC->BDCR |= RCC_BDCR_RTCEN;
 8000c2c:	4b08      	ldr	r3, [pc, #32]	; (8000c50 <RCC_RTCCLKCmd+0x38>)
 8000c2e:	4a08      	ldr	r2, [pc, #32]	; (8000c50 <RCC_RTCCLKCmd+0x38>)
 8000c30:	6a12      	ldr	r2, [r2, #32]
 8000c32:	2180      	movs	r1, #128	; 0x80
 8000c34:	0209      	lsls	r1, r1, #8
 8000c36:	430a      	orrs	r2, r1
 8000c38:	621a      	str	r2, [r3, #32]
 8000c3a:	e005      	b.n	8000c48 <RCC_RTCCLKCmd+0x30>
  }
  else
  {
    RCC->BDCR &= ~RCC_BDCR_RTCEN;
 8000c3c:	4b04      	ldr	r3, [pc, #16]	; (8000c50 <RCC_RTCCLKCmd+0x38>)
 8000c3e:	4a04      	ldr	r2, [pc, #16]	; (8000c50 <RCC_RTCCLKCmd+0x38>)
 8000c40:	6a12      	ldr	r2, [r2, #32]
 8000c42:	4904      	ldr	r1, [pc, #16]	; (8000c54 <RCC_RTCCLKCmd+0x3c>)
 8000c44:	400a      	ands	r2, r1
 8000c46:	621a      	str	r2, [r3, #32]
  }
}
 8000c48:	46bd      	mov	sp, r7
 8000c4a:	b002      	add	sp, #8
 8000c4c:	bd80      	pop	{r7, pc}
 8000c4e:	46c0      	nop			; (mov r8, r8)
 8000c50:	40021000 	.word	0x40021000
 8000c54:	ffff7fff 	.word	0xffff7fff

08000c58 <RCC_BackupResetCmd>:
  * @param  NewState: new state of the Backup domain reset.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_BackupResetCmd(FunctionalState NewState)
{
 8000c58:	b580      	push	{r7, lr}
 8000c5a:	b082      	sub	sp, #8
 8000c5c:	af00      	add	r7, sp, #0
 8000c5e:	1c02      	adds	r2, r0, #0
 8000c60:	1dfb      	adds	r3, r7, #7
 8000c62:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  
  if (NewState != DISABLE)
 8000c64:	1dfb      	adds	r3, r7, #7
 8000c66:	781b      	ldrb	r3, [r3, #0]
 8000c68:	2b00      	cmp	r3, #0
 8000c6a:	d007      	beq.n	8000c7c <RCC_BackupResetCmd+0x24>
  {
    RCC->BDCR |= RCC_BDCR_BDRST;
 8000c6c:	4b08      	ldr	r3, [pc, #32]	; (8000c90 <RCC_BackupResetCmd+0x38>)
 8000c6e:	4a08      	ldr	r2, [pc, #32]	; (8000c90 <RCC_BackupResetCmd+0x38>)
 8000c70:	6a12      	ldr	r2, [r2, #32]
 8000c72:	2180      	movs	r1, #128	; 0x80
 8000c74:	0249      	lsls	r1, r1, #9
 8000c76:	430a      	orrs	r2, r1
 8000c78:	621a      	str	r2, [r3, #32]
 8000c7a:	e005      	b.n	8000c88 <RCC_BackupResetCmd+0x30>
  }
  else
  {
    RCC->BDCR &= ~RCC_BDCR_BDRST;
 8000c7c:	4b04      	ldr	r3, [pc, #16]	; (8000c90 <RCC_BackupResetCmd+0x38>)
 8000c7e:	4a04      	ldr	r2, [pc, #16]	; (8000c90 <RCC_BackupResetCmd+0x38>)
 8000c80:	6a12      	ldr	r2, [r2, #32]
 8000c82:	4904      	ldr	r1, [pc, #16]	; (8000c94 <RCC_BackupResetCmd+0x3c>)
 8000c84:	400a      	ands	r2, r1
 8000c86:	621a      	str	r2, [r3, #32]
  }
}
 8000c88:	46bd      	mov	sp, r7
 8000c8a:	b002      	add	sp, #8
 8000c8c:	bd80      	pop	{r7, pc}
 8000c8e:	46c0      	nop			; (mov r8, r8)
 8000c90:	40021000 	.word	0x40021000
 8000c94:	fffeffff 	.word	0xfffeffff

08000c98 <RCC_AHBPeriphClockCmd>:
  * @param  NewState: new state of the specified peripheral clock.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
{
 8000c98:	b580      	push	{r7, lr}
 8000c9a:	b082      	sub	sp, #8
 8000c9c:	af00      	add	r7, sp, #0
 8000c9e:	6078      	str	r0, [r7, #4]
 8000ca0:	1c0a      	adds	r2, r1, #0
 8000ca2:	1cfb      	adds	r3, r7, #3
 8000ca4:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  
  if (NewState != DISABLE)
 8000ca6:	1cfb      	adds	r3, r7, #3
 8000ca8:	781b      	ldrb	r3, [r3, #0]
 8000caa:	2b00      	cmp	r3, #0
 8000cac:	d006      	beq.n	8000cbc <RCC_AHBPeriphClockCmd+0x24>
  {
    RCC->AHBENR |= RCC_AHBPeriph;
 8000cae:	4b08      	ldr	r3, [pc, #32]	; (8000cd0 <RCC_AHBPeriphClockCmd+0x38>)
 8000cb0:	4a07      	ldr	r2, [pc, #28]	; (8000cd0 <RCC_AHBPeriphClockCmd+0x38>)
 8000cb2:	6951      	ldr	r1, [r2, #20]
 8000cb4:	687a      	ldr	r2, [r7, #4]
 8000cb6:	430a      	orrs	r2, r1
 8000cb8:	615a      	str	r2, [r3, #20]
 8000cba:	e006      	b.n	8000cca <RCC_AHBPeriphClockCmd+0x32>
  }
  else
  {
    RCC->AHBENR &= ~RCC_AHBPeriph;
 8000cbc:	4b04      	ldr	r3, [pc, #16]	; (8000cd0 <RCC_AHBPeriphClockCmd+0x38>)
 8000cbe:	4a04      	ldr	r2, [pc, #16]	; (8000cd0 <RCC_AHBPeriphClockCmd+0x38>)
 8000cc0:	6952      	ldr	r2, [r2, #20]
 8000cc2:	6879      	ldr	r1, [r7, #4]
 8000cc4:	43c9      	mvns	r1, r1
 8000cc6:	400a      	ands	r2, r1
 8000cc8:	615a      	str	r2, [r3, #20]
  }
}
 8000cca:	46bd      	mov	sp, r7
 8000ccc:	b002      	add	sp, #8
 8000cce:	bd80      	pop	{r7, pc}
 8000cd0:	40021000 	.word	0x40021000

08000cd4 <RCC_APB2PeriphClockCmd>:
  * @param  NewState: new state of the specified peripheral clock.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
{
 8000cd4:	b580      	push	{r7, lr}
 8000cd6:	b082      	sub	sp, #8
 8000cd8:	af00      	add	r7, sp, #0
 8000cda:	6078      	str	r0, [r7, #4]
 8000cdc:	1c0a      	adds	r2, r1, #0
 8000cde:	1cfb      	adds	r3, r7, #3
 8000ce0:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
 8000ce2:	1cfb      	adds	r3, r7, #3
 8000ce4:	781b      	ldrb	r3, [r3, #0]
 8000ce6:	2b00      	cmp	r3, #0
 8000ce8:	d006      	beq.n	8000cf8 <RCC_APB2PeriphClockCmd+0x24>
  {
    RCC->APB2ENR |= RCC_APB2Periph;
 8000cea:	4b08      	ldr	r3, [pc, #32]	; (8000d0c <RCC_APB2PeriphClockCmd+0x38>)
 8000cec:	4a07      	ldr	r2, [pc, #28]	; (8000d0c <RCC_APB2PeriphClockCmd+0x38>)
 8000cee:	6991      	ldr	r1, [r2, #24]
 8000cf0:	687a      	ldr	r2, [r7, #4]
 8000cf2:	430a      	orrs	r2, r1
 8000cf4:	619a      	str	r2, [r3, #24]
 8000cf6:	e006      	b.n	8000d06 <RCC_APB2PeriphClockCmd+0x32>
  }
  else
  {
    RCC->APB2ENR &= ~RCC_APB2Periph;
 8000cf8:	4b04      	ldr	r3, [pc, #16]	; (8000d0c <RCC_APB2PeriphClockCmd+0x38>)
 8000cfa:	4a04      	ldr	r2, [pc, #16]	; (8000d0c <RCC_APB2PeriphClockCmd+0x38>)
 8000cfc:	6992      	ldr	r2, [r2, #24]
 8000cfe:	6879      	ldr	r1, [r7, #4]
 8000d00:	43c9      	mvns	r1, r1
 8000d02:	400a      	ands	r2, r1
 8000d04:	619a      	str	r2, [r3, #24]
  }
}
 8000d06:	46bd      	mov	sp, r7
 8000d08:	b002      	add	sp, #8
 8000d0a:	bd80      	pop	{r7, pc}
 8000d0c:	40021000 	.word	0x40021000

08000d10 <RCC_APB1PeriphClockCmd>:
  * @param  NewState: new state of the specified peripheral clock.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
{
 8000d10:	b580      	push	{r7, lr}
 8000d12:	b082      	sub	sp, #8
 8000d14:	af00      	add	r7, sp, #0
 8000d16:	6078      	str	r0, [r7, #4]
 8000d18:	1c0a      	adds	r2, r1, #0
 8000d1a:	1cfb      	adds	r3, r7, #3
 8000d1c:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
 8000d1e:	1cfb      	adds	r3, r7, #3
 8000d20:	781b      	ldrb	r3, [r3, #0]
 8000d22:	2b00      	cmp	r3, #0
 8000d24:	d006      	beq.n	8000d34 <RCC_APB1PeriphClockCmd+0x24>
  {
    RCC->APB1ENR |= RCC_APB1Periph;
 8000d26:	4b08      	ldr	r3, [pc, #32]	; (8000d48 <RCC_APB1PeriphClockCmd+0x38>)
 8000d28:	4a07      	ldr	r2, [pc, #28]	; (8000d48 <RCC_APB1PeriphClockCmd+0x38>)
 8000d2a:	69d1      	ldr	r1, [r2, #28]
 8000d2c:	687a      	ldr	r2, [r7, #4]
 8000d2e:	430a      	orrs	r2, r1
 8000d30:	61da      	str	r2, [r3, #28]
 8000d32:	e006      	b.n	8000d42 <RCC_APB1PeriphClockCmd+0x32>
  }
  else
  {
    RCC->APB1ENR &= ~RCC_APB1Periph;
 8000d34:	4b04      	ldr	r3, [pc, #16]	; (8000d48 <RCC_APB1PeriphClockCmd+0x38>)
 8000d36:	4a04      	ldr	r2, [pc, #16]	; (8000d48 <RCC_APB1PeriphClockCmd+0x38>)
 8000d38:	69d2      	ldr	r2, [r2, #28]
 8000d3a:	6879      	ldr	r1, [r7, #4]
 8000d3c:	43c9      	mvns	r1, r1
 8000d3e:	400a      	ands	r2, r1
 8000d40:	61da      	str	r2, [r3, #28]
  }
}
 8000d42:	46bd      	mov	sp, r7
 8000d44:	b002      	add	sp, #8
 8000d46:	bd80      	pop	{r7, pc}
 8000d48:	40021000 	.word	0x40021000

08000d4c <RCC_AHBPeriphResetCmd>:
  * @param  NewState: new state of the specified peripheral reset.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
{
 8000d4c:	b580      	push	{r7, lr}
 8000d4e:	b082      	sub	sp, #8
 8000d50:	af00      	add	r7, sp, #0
 8000d52:	6078      	str	r0, [r7, #4]
 8000d54:	1c0a      	adds	r2, r1, #0
 8000d56:	1cfb      	adds	r3, r7, #3
 8000d58:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_RCC_AHB_RST_PERIPH(RCC_AHBPeriph));
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
 8000d5a:	1cfb      	adds	r3, r7, #3
 8000d5c:	781b      	ldrb	r3, [r3, #0]
 8000d5e:	2b00      	cmp	r3, #0
 8000d60:	d006      	beq.n	8000d70 <RCC_AHBPeriphResetCmd+0x24>
  {
    RCC->AHBRSTR |= RCC_AHBPeriph;
 8000d62:	4b08      	ldr	r3, [pc, #32]	; (8000d84 <RCC_AHBPeriphResetCmd+0x38>)
 8000d64:	4a07      	ldr	r2, [pc, #28]	; (8000d84 <RCC_AHBPeriphResetCmd+0x38>)
 8000d66:	6a91      	ldr	r1, [r2, #40]	; 0x28
 8000d68:	687a      	ldr	r2, [r7, #4]
 8000d6a:	430a      	orrs	r2, r1
 8000d6c:	629a      	str	r2, [r3, #40]	; 0x28
 8000d6e:	e006      	b.n	8000d7e <RCC_AHBPeriphResetCmd+0x32>
  }
  else
  {
    RCC->AHBRSTR &= ~RCC_AHBPeriph;
 8000d70:	4b04      	ldr	r3, [pc, #16]	; (8000d84 <RCC_AHBPeriphResetCmd+0x38>)
 8000d72:	4a04      	ldr	r2, [pc, #16]	; (8000d84 <RCC_AHBPeriphResetCmd+0x38>)
 8000d74:	6a92      	ldr	r2, [r2, #40]	; 0x28
 8000d76:	6879      	ldr	r1, [r7, #4]
 8000d78:	43c9      	mvns	r1, r1
 8000d7a:	400a      	ands	r2, r1
 8000d7c:	629a      	str	r2, [r3, #40]	; 0x28
  }
}
 8000d7e:	46bd      	mov	sp, r7
 8000d80:	b002      	add	sp, #8
 8000d82:	bd80      	pop	{r7, pc}
 8000d84:	40021000 	.word	0x40021000

08000d88 <RCC_APB2PeriphResetCmd>:
  * @param  NewState: new state of the specified peripheral reset.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
{
 8000d88:	b580      	push	{r7, lr}
 8000d8a:	b082      	sub	sp, #8
 8000d8c:	af00      	add	r7, sp, #0
 8000d8e:	6078      	str	r0, [r7, #4]
 8000d90:	1c0a      	adds	r2, r1, #0
 8000d92:	1cfb      	adds	r3, r7, #3
 8000d94:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
 8000d96:	1cfb      	adds	r3, r7, #3
 8000d98:	781b      	ldrb	r3, [r3, #0]
 8000d9a:	2b00      	cmp	r3, #0
 8000d9c:	d006      	beq.n	8000dac <RCC_APB2PeriphResetCmd+0x24>
  {
    RCC->APB2RSTR |= RCC_APB2Periph;
 8000d9e:	4b08      	ldr	r3, [pc, #32]	; (8000dc0 <RCC_APB2PeriphResetCmd+0x38>)
 8000da0:	4a07      	ldr	r2, [pc, #28]	; (8000dc0 <RCC_APB2PeriphResetCmd+0x38>)
 8000da2:	68d1      	ldr	r1, [r2, #12]
 8000da4:	687a      	ldr	r2, [r7, #4]
 8000da6:	430a      	orrs	r2, r1
 8000da8:	60da      	str	r2, [r3, #12]
 8000daa:	e006      	b.n	8000dba <RCC_APB2PeriphResetCmd+0x32>
  }
  else
  {
    RCC->APB2RSTR &= ~RCC_APB2Periph;
 8000dac:	4b04      	ldr	r3, [pc, #16]	; (8000dc0 <RCC_APB2PeriphResetCmd+0x38>)
 8000dae:	4a04      	ldr	r2, [pc, #16]	; (8000dc0 <RCC_APB2PeriphResetCmd+0x38>)
 8000db0:	68d2      	ldr	r2, [r2, #12]
 8000db2:	6879      	ldr	r1, [r7, #4]
 8000db4:	43c9      	mvns	r1, r1
 8000db6:	400a      	ands	r2, r1
 8000db8:	60da      	str	r2, [r3, #12]
  }
}
 8000dba:	46bd      	mov	sp, r7
 8000dbc:	b002      	add	sp, #8
 8000dbe:	bd80      	pop	{r7, pc}
 8000dc0:	40021000 	.word	0x40021000

08000dc4 <RCC_APB1PeriphResetCmd>:
  * @param  NewState: new state of the specified peripheral clock.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
{
 8000dc4:	b580      	push	{r7, lr}
 8000dc6:	b082      	sub	sp, #8
 8000dc8:	af00      	add	r7, sp, #0
 8000dca:	6078      	str	r0, [r7, #4]
 8000dcc:	1c0a      	adds	r2, r1, #0
 8000dce:	1cfb      	adds	r3, r7, #3
 8000dd0:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
 8000dd2:	1cfb      	adds	r3, r7, #3
 8000dd4:	781b      	ldrb	r3, [r3, #0]
 8000dd6:	2b00      	cmp	r3, #0
 8000dd8:	d006      	beq.n	8000de8 <RCC_APB1PeriphResetCmd+0x24>
  {
    RCC->APB1RSTR |= RCC_APB1Periph;
 8000dda:	4b08      	ldr	r3, [pc, #32]	; (8000dfc <RCC_APB1PeriphResetCmd+0x38>)
 8000ddc:	4a07      	ldr	r2, [pc, #28]	; (8000dfc <RCC_APB1PeriphResetCmd+0x38>)
 8000dde:	6911      	ldr	r1, [r2, #16]
 8000de0:	687a      	ldr	r2, [r7, #4]
 8000de2:	430a      	orrs	r2, r1
 8000de4:	611a      	str	r2, [r3, #16]
 8000de6:	e006      	b.n	8000df6 <RCC_APB1PeriphResetCmd+0x32>
  }
  else
  {
    RCC->APB1RSTR &= ~RCC_APB1Periph;
 8000de8:	4b04      	ldr	r3, [pc, #16]	; (8000dfc <RCC_APB1PeriphResetCmd+0x38>)
 8000dea:	4a04      	ldr	r2, [pc, #16]	; (8000dfc <RCC_APB1PeriphResetCmd+0x38>)
 8000dec:	6912      	ldr	r2, [r2, #16]
 8000dee:	6879      	ldr	r1, [r7, #4]
 8000df0:	43c9      	mvns	r1, r1
 8000df2:	400a      	ands	r2, r1
 8000df4:	611a      	str	r2, [r3, #16]
  }
}
 8000df6:	46bd      	mov	sp, r7
 8000df8:	b002      	add	sp, #8
 8000dfa:	bd80      	pop	{r7, pc}
 8000dfc:	40021000 	.word	0x40021000

08000e00 <RCC_ITConfig>:
  * @param  NewState: new state of the specified RCC interrupts.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
{
 8000e00:	b580      	push	{r7, lr}
 8000e02:	b082      	sub	sp, #8
 8000e04:	af00      	add	r7, sp, #0
 8000e06:	1c02      	adds	r2, r0, #0
 8000e08:	1dfb      	adds	r3, r7, #7
 8000e0a:	701a      	strb	r2, [r3, #0]
 8000e0c:	1dbb      	adds	r3, r7, #6
 8000e0e:	1c0a      	adds	r2, r1, #0
 8000e10:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_RCC_IT(RCC_IT));
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  
  if (NewState != DISABLE)
 8000e12:	1dbb      	adds	r3, r7, #6
 8000e14:	781b      	ldrb	r3, [r3, #0]
 8000e16:	2b00      	cmp	r3, #0
 8000e18:	d009      	beq.n	8000e2e <RCC_ITConfig+0x2e>
  {
    /* Perform Byte access to RCC_CIR[13:8] bits to enable the selected interrupts */
    *(__IO uint8_t *) CIR_BYTE1_ADDRESS |= RCC_IT;
 8000e1a:	490c      	ldr	r1, [pc, #48]	; (8000e4c <RCC_ITConfig+0x4c>)
 8000e1c:	4b0b      	ldr	r3, [pc, #44]	; (8000e4c <RCC_ITConfig+0x4c>)
 8000e1e:	781b      	ldrb	r3, [r3, #0]
 8000e20:	b2da      	uxtb	r2, r3
 8000e22:	1dfb      	adds	r3, r7, #7
 8000e24:	781b      	ldrb	r3, [r3, #0]
 8000e26:	4313      	orrs	r3, r2
 8000e28:	b2db      	uxtb	r3, r3
 8000e2a:	700b      	strb	r3, [r1, #0]
 8000e2c:	e00a      	b.n	8000e44 <RCC_ITConfig+0x44>
  }
  else
  {
    /* Perform Byte access to RCC_CIR[13:8] bits to disable the selected interrupts */
    *(__IO uint8_t *) CIR_BYTE1_ADDRESS &= (uint8_t)~RCC_IT;
 8000e2e:	4907      	ldr	r1, [pc, #28]	; (8000e4c <RCC_ITConfig+0x4c>)
 8000e30:	4b06      	ldr	r3, [pc, #24]	; (8000e4c <RCC_ITConfig+0x4c>)
 8000e32:	781b      	ldrb	r3, [r3, #0]
 8000e34:	b2db      	uxtb	r3, r3
 8000e36:	1dfa      	adds	r2, r7, #7
 8000e38:	7812      	ldrb	r2, [r2, #0]
 8000e3a:	43d2      	mvns	r2, r2
 8000e3c:	b2d2      	uxtb	r2, r2
 8000e3e:	4013      	ands	r3, r2
 8000e40:	b2db      	uxtb	r3, r3
 8000e42:	700b      	strb	r3, [r1, #0]
  }
}
 8000e44:	46bd      	mov	sp, r7
 8000e46:	b002      	add	sp, #8
 8000e48:	bd80      	pop	{r7, pc}
 8000e4a:	46c0      	nop			; (mov r8, r8)
 8000e4c:	40021009 	.word	0x40021009

08000e50 <RCC_GetFlagStatus>:
  *             @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready
  *             @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready, applicable only for STM32F072 devices    
  * @retval The new state of RCC_FLAG (SET or RESET).
  */
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
{
 8000e50:	b580      	push	{r7, lr}
 8000e52:	b086      	sub	sp, #24
 8000e54:	af00      	add	r7, sp, #0
 8000e56:	1c02      	adds	r2, r0, #0
 8000e58:	1dfb      	adds	r3, r7, #7
 8000e5a:	701a      	strb	r2, [r3, #0]
  uint32_t tmp = 0;
 8000e5c:	2300      	movs	r3, #0
 8000e5e:	60fb      	str	r3, [r7, #12]
  uint32_t statusreg = 0;
 8000e60:	2300      	movs	r3, #0
 8000e62:	617b      	str	r3, [r7, #20]
  FlagStatus bitstatus = RESET;
 8000e64:	2313      	movs	r3, #19
 8000e66:	18fb      	adds	r3, r7, r3
 8000e68:	2200      	movs	r2, #0
 8000e6a:	701a      	strb	r2, [r3, #0]

  /* Check the parameters */
  assert_param(IS_RCC_FLAG(RCC_FLAG));

  /* Get the RCC register index */
  tmp = RCC_FLAG >> 5;
 8000e6c:	1dfb      	adds	r3, r7, #7
 8000e6e:	781b      	ldrb	r3, [r3, #0]
 8000e70:	095b      	lsrs	r3, r3, #5
 8000e72:	b2db      	uxtb	r3, r3
 8000e74:	60fb      	str	r3, [r7, #12]

  if (tmp == 0)               /* The flag to check is in CR register */
 8000e76:	68fb      	ldr	r3, [r7, #12]
 8000e78:	2b00      	cmp	r3, #0
 8000e7a:	d103      	bne.n	8000e84 <RCC_GetFlagStatus+0x34>
  {
    statusreg = RCC->CR;
 8000e7c:	4b18      	ldr	r3, [pc, #96]	; (8000ee0 <RCC_GetFlagStatus+0x90>)
 8000e7e:	681b      	ldr	r3, [r3, #0]
 8000e80:	617b      	str	r3, [r7, #20]
 8000e82:	e010      	b.n	8000ea6 <RCC_GetFlagStatus+0x56>
  }
  else if (tmp == 1)          /* The flag to check is in BDCR register */
 8000e84:	68fb      	ldr	r3, [r7, #12]
 8000e86:	2b01      	cmp	r3, #1
 8000e88:	d103      	bne.n	8000e92 <RCC_GetFlagStatus+0x42>
  {
    statusreg = RCC->BDCR;
 8000e8a:	4b15      	ldr	r3, [pc, #84]	; (8000ee0 <RCC_GetFlagStatus+0x90>)
 8000e8c:	6a1b      	ldr	r3, [r3, #32]
 8000e8e:	617b      	str	r3, [r7, #20]
 8000e90:	e009      	b.n	8000ea6 <RCC_GetFlagStatus+0x56>
  }
  else if (tmp == 2)          /* The flag to check is in CSR register */
 8000e92:	68fb      	ldr	r3, [r7, #12]
 8000e94:	2b02      	cmp	r3, #2
 8000e96:	d103      	bne.n	8000ea0 <RCC_GetFlagStatus+0x50>
  {
    statusreg = RCC->CSR;
 8000e98:	4b11      	ldr	r3, [pc, #68]	; (8000ee0 <RCC_GetFlagStatus+0x90>)
 8000e9a:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8000e9c:	617b      	str	r3, [r7, #20]
 8000e9e:	e002      	b.n	8000ea6 <RCC_GetFlagStatus+0x56>
  }
  else                        /* The flag to check is in CR2 register */
  {
    statusreg = RCC->CR2;
 8000ea0:	4b0f      	ldr	r3, [pc, #60]	; (8000ee0 <RCC_GetFlagStatus+0x90>)
 8000ea2:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8000ea4:	617b      	str	r3, [r7, #20]
  }    

  /* Get the flag position */
  tmp = RCC_FLAG & FLAG_MASK;
 8000ea6:	1dfb      	adds	r3, r7, #7
 8000ea8:	781b      	ldrb	r3, [r3, #0]
 8000eaa:	221f      	movs	r2, #31
 8000eac:	4013      	ands	r3, r2
 8000eae:	60fb      	str	r3, [r7, #12]

  if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
 8000eb0:	68fb      	ldr	r3, [r7, #12]
 8000eb2:	697a      	ldr	r2, [r7, #20]
 8000eb4:	40da      	lsrs	r2, r3
 8000eb6:	1c13      	adds	r3, r2, #0
 8000eb8:	2201      	movs	r2, #1
 8000eba:	4013      	ands	r3, r2
 8000ebc:	d004      	beq.n	8000ec8 <RCC_GetFlagStatus+0x78>
  {
    bitstatus = SET;
 8000ebe:	2313      	movs	r3, #19
 8000ec0:	18fb      	adds	r3, r7, r3
 8000ec2:	2201      	movs	r2, #1
 8000ec4:	701a      	strb	r2, [r3, #0]
 8000ec6:	e003      	b.n	8000ed0 <RCC_GetFlagStatus+0x80>
  }
  else
  {
    bitstatus = RESET;
 8000ec8:	2313      	movs	r3, #19
 8000eca:	18fb      	adds	r3, r7, r3
 8000ecc:	2200      	movs	r2, #0
 8000ece:	701a      	strb	r2, [r3, #0]
  }
  /* Return the flag status */
  return bitstatus;
 8000ed0:	2313      	movs	r3, #19
 8000ed2:	18fb      	adds	r3, r7, r3
 8000ed4:	781b      	ldrb	r3, [r3, #0]
}
 8000ed6:	1c18      	adds	r0, r3, #0
 8000ed8:	46bd      	mov	sp, r7
 8000eda:	b006      	add	sp, #24
 8000edc:	bd80      	pop	{r7, pc}
 8000ede:	46c0      	nop			; (mov r8, r8)
 8000ee0:	40021000 	.word	0x40021000

08000ee4 <RCC_ClearFlag>:
  *         RCC_FLAG_LPWRRST.
  * @param  None
  * @retval None
  */
void RCC_ClearFlag(void)
{
 8000ee4:	b580      	push	{r7, lr}
 8000ee6:	af00      	add	r7, sp, #0
  /* Set RMVF bit to clear the reset flags */
  RCC->CSR |= RCC_CSR_RMVF;
 8000ee8:	4b04      	ldr	r3, [pc, #16]	; (8000efc <RCC_ClearFlag+0x18>)
 8000eea:	4a04      	ldr	r2, [pc, #16]	; (8000efc <RCC_ClearFlag+0x18>)
 8000eec:	6a52      	ldr	r2, [r2, #36]	; 0x24
 8000eee:	2180      	movs	r1, #128	; 0x80
 8000ef0:	0449      	lsls	r1, r1, #17
 8000ef2:	430a      	orrs	r2, r1
 8000ef4:	625a      	str	r2, [r3, #36]	; 0x24
}
 8000ef6:	46bd      	mov	sp, r7
 8000ef8:	bd80      	pop	{r7, pc}
 8000efa:	46c0      	nop			; (mov r8, r8)
 8000efc:	40021000 	.word	0x40021000

08000f00 <RCC_GetITStatus>:
  *             @arg RCC_IT_HSI48RDY: HSI48 ready interrupt, applicable only for STM32F072 devices    
  *             @arg RCC_IT_CSS: Clock Security System interrupt
  * @retval The new state of RCC_IT (SET or RESET).
  */
ITStatus RCC_GetITStatus(uint8_t RCC_IT)
{
 8000f00:	b580      	push	{r7, lr}
 8000f02:	b084      	sub	sp, #16
 8000f04:	af00      	add	r7, sp, #0
 8000f06:	1c02      	adds	r2, r0, #0
 8000f08:	1dfb      	adds	r3, r7, #7
 8000f0a:	701a      	strb	r2, [r3, #0]
  ITStatus bitstatus = RESET;
 8000f0c:	230f      	movs	r3, #15
 8000f0e:	18fb      	adds	r3, r7, r3
 8000f10:	2200      	movs	r2, #0
 8000f12:	701a      	strb	r2, [r3, #0]
  
  /* Check the parameters */
  assert_param(IS_RCC_GET_IT(RCC_IT));
  
  /* Check the status of the specified RCC interrupt */
  if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
 8000f14:	4b0a      	ldr	r3, [pc, #40]	; (8000f40 <RCC_GetITStatus+0x40>)
 8000f16:	689b      	ldr	r3, [r3, #8]
 8000f18:	1dfa      	adds	r2, r7, #7
 8000f1a:	7812      	ldrb	r2, [r2, #0]
 8000f1c:	4013      	ands	r3, r2
 8000f1e:	d004      	beq.n	8000f2a <RCC_GetITStatus+0x2a>
  {
    bitstatus = SET;
 8000f20:	230f      	movs	r3, #15
 8000f22:	18fb      	adds	r3, r7, r3
 8000f24:	2201      	movs	r2, #1
 8000f26:	701a      	strb	r2, [r3, #0]
 8000f28:	e003      	b.n	8000f32 <RCC_GetITStatus+0x32>
  }
  else
  {
    bitstatus = RESET;
 8000f2a:	230f      	movs	r3, #15
 8000f2c:	18fb      	adds	r3, r7, r3
 8000f2e:	2200      	movs	r2, #0
 8000f30:	701a      	strb	r2, [r3, #0]
  }
  /* Return the RCC_IT status */
  return  bitstatus;
 8000f32:	230f      	movs	r3, #15
 8000f34:	18fb      	adds	r3, r7, r3
 8000f36:	781b      	ldrb	r3, [r3, #0]
}
 8000f38:	1c18      	adds	r0, r3, #0
 8000f3a:	46bd      	mov	sp, r7
 8000f3c:	b004      	add	sp, #16
 8000f3e:	bd80      	pop	{r7, pc}
 8000f40:	40021000 	.word	0x40021000

08000f44 <RCC_ClearITPendingBit>:
  *             @arg RCC_IT_HSI14RDY: HSI14 ready interrupt
  *             @arg RCC_IT_CSS: Clock Security System interrupt
  * @retval None
  */
void RCC_ClearITPendingBit(uint8_t RCC_IT)
{
 8000f44:	b580      	push	{r7, lr}
 8000f46:	b082      	sub	sp, #8
 8000f48:	af00      	add	r7, sp, #0
 8000f4a:	1c02      	adds	r2, r0, #0
 8000f4c:	1dfb      	adds	r3, r7, #7
 8000f4e:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_RCC_CLEAR_IT(RCC_IT));
  
  /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
     pending bits */
  *(__IO uint8_t *) CIR_BYTE2_ADDRESS = RCC_IT;
 8000f50:	4a03      	ldr	r2, [pc, #12]	; (8000f60 <RCC_ClearITPendingBit+0x1c>)
 8000f52:	1dfb      	adds	r3, r7, #7
 8000f54:	781b      	ldrb	r3, [r3, #0]
 8000f56:	7013      	strb	r3, [r2, #0]
}
 8000f58:	46bd      	mov	sp, r7
 8000f5a:	b002      	add	sp, #8
 8000f5c:	bd80      	pop	{r7, pc}
 8000f5e:	46c0      	nop			; (mov r8, r8)
 8000f60:	4002100a 	.word	0x4002100a

08000f64 <GPIO_DeInit>:
  * @note   GPIOE is available only for STM32F072.
  * @note   GPIOD is not available for STM32F031.    
  * @retval None
  */
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
{
 8000f64:	b580      	push	{r7, lr}
 8000f66:	b082      	sub	sp, #8
 8000f68:	af00      	add	r7, sp, #0
 8000f6a:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));

  if(GPIOx == GPIOA)
 8000f6c:	687a      	ldr	r2, [r7, #4]
 8000f6e:	2390      	movs	r3, #144	; 0x90
 8000f70:	05db      	lsls	r3, r3, #23
 8000f72:	429a      	cmp	r2, r3
 8000f74:	d10c      	bne.n	8000f90 <GPIO_DeInit+0x2c>
  {
    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);
 8000f76:	2380      	movs	r3, #128	; 0x80
 8000f78:	029b      	lsls	r3, r3, #10
 8000f7a:	1c18      	adds	r0, r3, #0
 8000f7c:	2101      	movs	r1, #1
 8000f7e:	f7ff fee5 	bl	8000d4c <RCC_AHBPeriphResetCmd>
    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE);
 8000f82:	2380      	movs	r3, #128	; 0x80
 8000f84:	029b      	lsls	r3, r3, #10
 8000f86:	1c18      	adds	r0, r3, #0
 8000f88:	2100      	movs	r1, #0
 8000f8a:	f7ff fedf 	bl	8000d4c <RCC_AHBPeriphResetCmd>
 8000f8e:	e053      	b.n	8001038 <GPIO_DeInit+0xd4>
  }
  else if(GPIOx == GPIOB)
 8000f90:	687b      	ldr	r3, [r7, #4]
 8000f92:	4a2b      	ldr	r2, [pc, #172]	; (8001040 <GPIO_DeInit+0xdc>)
 8000f94:	4293      	cmp	r3, r2
 8000f96:	d10c      	bne.n	8000fb2 <GPIO_DeInit+0x4e>
  {
    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);
 8000f98:	2380      	movs	r3, #128	; 0x80
 8000f9a:	02db      	lsls	r3, r3, #11
 8000f9c:	1c18      	adds	r0, r3, #0
 8000f9e:	2101      	movs	r1, #1
 8000fa0:	f7ff fed4 	bl	8000d4c <RCC_AHBPeriphResetCmd>
    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);
 8000fa4:	2380      	movs	r3, #128	; 0x80
 8000fa6:	02db      	lsls	r3, r3, #11
 8000fa8:	1c18      	adds	r0, r3, #0
 8000faa:	2100      	movs	r1, #0
 8000fac:	f7ff fece 	bl	8000d4c <RCC_AHBPeriphResetCmd>
 8000fb0:	e042      	b.n	8001038 <GPIO_DeInit+0xd4>
  }
  else if(GPIOx == GPIOC)
 8000fb2:	687b      	ldr	r3, [r7, #4]
 8000fb4:	4a23      	ldr	r2, [pc, #140]	; (8001044 <GPIO_DeInit+0xe0>)
 8000fb6:	4293      	cmp	r3, r2
 8000fb8:	d10c      	bne.n	8000fd4 <GPIO_DeInit+0x70>
  {
    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE);
 8000fba:	2380      	movs	r3, #128	; 0x80
 8000fbc:	031b      	lsls	r3, r3, #12
 8000fbe:	1c18      	adds	r0, r3, #0
 8000fc0:	2101      	movs	r1, #1
 8000fc2:	f7ff fec3 	bl	8000d4c <RCC_AHBPeriphResetCmd>
    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE);
 8000fc6:	2380      	movs	r3, #128	; 0x80
 8000fc8:	031b      	lsls	r3, r3, #12
 8000fca:	1c18      	adds	r0, r3, #0
 8000fcc:	2100      	movs	r1, #0
 8000fce:	f7ff febd 	bl	8000d4c <RCC_AHBPeriphResetCmd>
 8000fd2:	e031      	b.n	8001038 <GPIO_DeInit+0xd4>
  }
  else if(GPIOx == GPIOD)
 8000fd4:	687b      	ldr	r3, [r7, #4]
 8000fd6:	4a1c      	ldr	r2, [pc, #112]	; (8001048 <GPIO_DeInit+0xe4>)
 8000fd8:	4293      	cmp	r3, r2
 8000fda:	d10c      	bne.n	8000ff6 <GPIO_DeInit+0x92>
  {
    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE);
 8000fdc:	2380      	movs	r3, #128	; 0x80
 8000fde:	035b      	lsls	r3, r3, #13
 8000fe0:	1c18      	adds	r0, r3, #0
 8000fe2:	2101      	movs	r1, #1
 8000fe4:	f7ff feb2 	bl	8000d4c <RCC_AHBPeriphResetCmd>
    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE);
 8000fe8:	2380      	movs	r3, #128	; 0x80
 8000fea:	035b      	lsls	r3, r3, #13
 8000fec:	1c18      	adds	r0, r3, #0
 8000fee:	2100      	movs	r1, #0
 8000ff0:	f7ff feac 	bl	8000d4c <RCC_AHBPeriphResetCmd>
 8000ff4:	e020      	b.n	8001038 <GPIO_DeInit+0xd4>
  }
  else if(GPIOx == GPIOE)
 8000ff6:	687b      	ldr	r3, [r7, #4]
 8000ff8:	4a14      	ldr	r2, [pc, #80]	; (800104c <GPIO_DeInit+0xe8>)
 8000ffa:	4293      	cmp	r3, r2
 8000ffc:	d10c      	bne.n	8001018 <GPIO_DeInit+0xb4>
  {
    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE);
 8000ffe:	2380      	movs	r3, #128	; 0x80
 8001000:	039b      	lsls	r3, r3, #14
 8001002:	1c18      	adds	r0, r3, #0
 8001004:	2101      	movs	r1, #1
 8001006:	f7ff fea1 	bl	8000d4c <RCC_AHBPeriphResetCmd>
    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE);
 800100a:	2380      	movs	r3, #128	; 0x80
 800100c:	039b      	lsls	r3, r3, #14
 800100e:	1c18      	adds	r0, r3, #0
 8001010:	2100      	movs	r1, #0
 8001012:	f7ff fe9b 	bl	8000d4c <RCC_AHBPeriphResetCmd>
 8001016:	e00f      	b.n	8001038 <GPIO_DeInit+0xd4>
  }
  else
  {
    if(GPIOx == GPIOF)
 8001018:	687b      	ldr	r3, [r7, #4]
 800101a:	4a0d      	ldr	r2, [pc, #52]	; (8001050 <GPIO_DeInit+0xec>)
 800101c:	4293      	cmp	r3, r2
 800101e:	d10b      	bne.n	8001038 <GPIO_DeInit+0xd4>
    {
      RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, ENABLE);
 8001020:	2380      	movs	r3, #128	; 0x80
 8001022:	03db      	lsls	r3, r3, #15
 8001024:	1c18      	adds	r0, r3, #0
 8001026:	2101      	movs	r1, #1
 8001028:	f7ff fe90 	bl	8000d4c <RCC_AHBPeriphResetCmd>
      RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, DISABLE);
 800102c:	2380      	movs	r3, #128	; 0x80
 800102e:	03db      	lsls	r3, r3, #15
 8001030:	1c18      	adds	r0, r3, #0
 8001032:	2100      	movs	r1, #0
 8001034:	f7ff fe8a 	bl	8000d4c <RCC_AHBPeriphResetCmd>
    }
  }
}
 8001038:	46bd      	mov	sp, r7
 800103a:	b002      	add	sp, #8
 800103c:	bd80      	pop	{r7, pc}
 800103e:	46c0      	nop			; (mov r8, r8)
 8001040:	48000400 	.word	0x48000400
 8001044:	48000800 	.word	0x48000800
 8001048:	48000c00 	.word	0x48000c00
 800104c:	48001000 	.word	0x48001000
 8001050:	48001400 	.word	0x48001400

08001054 <GPIO_Init>:
  * @param  GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains
  *         the configuration information for the specified GPIO peripheral.
  * @retval None
  */
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
{
 8001054:	b580      	push	{r7, lr}
 8001056:	b086      	sub	sp, #24
 8001058:	af00      	add	r7, sp, #0
 800105a:	6078      	str	r0, [r7, #4]
 800105c:	6039      	str	r1, [r7, #0]
  uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
 800105e:	2300      	movs	r3, #0
 8001060:	617b      	str	r3, [r7, #20]
 8001062:	2300      	movs	r3, #0
 8001064:	613b      	str	r3, [r7, #16]
 8001066:	2300      	movs	r3, #0
 8001068:	60fb      	str	r3, [r7, #12]
  assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
  assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));

  /*-------------------------- Configure the port pins -----------------------*/
  /*-- GPIO Mode Configuration --*/
  for (pinpos = 0x00; pinpos < 0x10; pinpos++)
 800106a:	2300      	movs	r3, #0
 800106c:	617b      	str	r3, [r7, #20]
 800106e:	e07c      	b.n	800116a <GPIO_Init+0x116>
  {
    pos = ((uint32_t)0x01) << pinpos;
 8001070:	697b      	ldr	r3, [r7, #20]
 8001072:	2201      	movs	r2, #1
 8001074:	409a      	lsls	r2, r3
 8001076:	1c13      	adds	r3, r2, #0
 8001078:	613b      	str	r3, [r7, #16]

    /* Get the port pins position */
    currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
 800107a:	683b      	ldr	r3, [r7, #0]
 800107c:	681b      	ldr	r3, [r3, #0]
 800107e:	693a      	ldr	r2, [r7, #16]
 8001080:	4013      	ands	r3, r2
 8001082:	60fb      	str	r3, [r7, #12]

    if (currentpin == pos)
 8001084:	68fa      	ldr	r2, [r7, #12]
 8001086:	693b      	ldr	r3, [r7, #16]
 8001088:	429a      	cmp	r2, r3
 800108a:	d16b      	bne.n	8001164 <GPIO_Init+0x110>
    {
      if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
 800108c:	683b      	ldr	r3, [r7, #0]
 800108e:	791b      	ldrb	r3, [r3, #4]
 8001090:	2b01      	cmp	r3, #1
 8001092:	d003      	beq.n	800109c <GPIO_Init+0x48>
 8001094:	683b      	ldr	r3, [r7, #0]
 8001096:	791b      	ldrb	r3, [r3, #4]
 8001098:	2b02      	cmp	r3, #2
 800109a:	d134      	bne.n	8001106 <GPIO_Init+0xb2>
      {
        /* Check Speed mode parameters */
        assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));

        /* Speed mode configuration */
        GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
 800109c:	687b      	ldr	r3, [r7, #4]
 800109e:	689b      	ldr	r3, [r3, #8]
 80010a0:	697a      	ldr	r2, [r7, #20]
 80010a2:	0052      	lsls	r2, r2, #1
 80010a4:	1c11      	adds	r1, r2, #0
 80010a6:	2203      	movs	r2, #3
 80010a8:	408a      	lsls	r2, r1
 80010aa:	43d2      	mvns	r2, r2
 80010ac:	401a      	ands	r2, r3
 80010ae:	687b      	ldr	r3, [r7, #4]
 80010b0:	609a      	str	r2, [r3, #8]
        GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
 80010b2:	687b      	ldr	r3, [r7, #4]
 80010b4:	689a      	ldr	r2, [r3, #8]
 80010b6:	683b      	ldr	r3, [r7, #0]
 80010b8:	795b      	ldrb	r3, [r3, #5]
 80010ba:	1c19      	adds	r1, r3, #0
 80010bc:	697b      	ldr	r3, [r7, #20]
 80010be:	005b      	lsls	r3, r3, #1
 80010c0:	4099      	lsls	r1, r3
 80010c2:	1c0b      	adds	r3, r1, #0
 80010c4:	431a      	orrs	r2, r3
 80010c6:	687b      	ldr	r3, [r7, #4]
 80010c8:	609a      	str	r2, [r3, #8]

        /* Check Output mode parameters */
        assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));

        /* Output mode configuration */
        GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos));
 80010ca:	687b      	ldr	r3, [r7, #4]
 80010cc:	889b      	ldrh	r3, [r3, #4]
 80010ce:	b29b      	uxth	r3, r3
 80010d0:	697a      	ldr	r2, [r7, #20]
 80010d2:	b292      	uxth	r2, r2
 80010d4:	1c11      	adds	r1, r2, #0
 80010d6:	2201      	movs	r2, #1
 80010d8:	408a      	lsls	r2, r1
 80010da:	b292      	uxth	r2, r2
 80010dc:	43d2      	mvns	r2, r2
 80010de:	b292      	uxth	r2, r2
 80010e0:	4013      	ands	r3, r2
 80010e2:	b29a      	uxth	r2, r3
 80010e4:	687b      	ldr	r3, [r7, #4]
 80010e6:	809a      	strh	r2, [r3, #4]
        GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
 80010e8:	687b      	ldr	r3, [r7, #4]
 80010ea:	889b      	ldrh	r3, [r3, #4]
 80010ec:	b29a      	uxth	r2, r3
 80010ee:	683b      	ldr	r3, [r7, #0]
 80010f0:	799b      	ldrb	r3, [r3, #6]
 80010f2:	1c19      	adds	r1, r3, #0
 80010f4:	697b      	ldr	r3, [r7, #20]
 80010f6:	b29b      	uxth	r3, r3
 80010f8:	4099      	lsls	r1, r3
 80010fa:	1c0b      	adds	r3, r1, #0
 80010fc:	b29b      	uxth	r3, r3
 80010fe:	4313      	orrs	r3, r2
 8001100:	b29a      	uxth	r2, r3
 8001102:	687b      	ldr	r3, [r7, #4]
 8001104:	809a      	strh	r2, [r3, #4]
      }

      GPIOx->MODER  &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
 8001106:	687b      	ldr	r3, [r7, #4]
 8001108:	681b      	ldr	r3, [r3, #0]
 800110a:	697a      	ldr	r2, [r7, #20]
 800110c:	0052      	lsls	r2, r2, #1
 800110e:	1c11      	adds	r1, r2, #0
 8001110:	2203      	movs	r2, #3
 8001112:	408a      	lsls	r2, r1
 8001114:	43d2      	mvns	r2, r2
 8001116:	401a      	ands	r2, r3
 8001118:	687b      	ldr	r3, [r7, #4]
 800111a:	601a      	str	r2, [r3, #0]

      GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
 800111c:	687b      	ldr	r3, [r7, #4]
 800111e:	681a      	ldr	r2, [r3, #0]
 8001120:	683b      	ldr	r3, [r7, #0]
 8001122:	791b      	ldrb	r3, [r3, #4]
 8001124:	1c19      	adds	r1, r3, #0
 8001126:	697b      	ldr	r3, [r7, #20]
 8001128:	005b      	lsls	r3, r3, #1
 800112a:	4099      	lsls	r1, r3
 800112c:	1c0b      	adds	r3, r1, #0
 800112e:	431a      	orrs	r2, r3
 8001130:	687b      	ldr	r3, [r7, #4]
 8001132:	601a      	str	r2, [r3, #0]

      /* Pull-up Pull down resistor configuration */
      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
 8001134:	687b      	ldr	r3, [r7, #4]
 8001136:	68db      	ldr	r3, [r3, #12]
 8001138:	697a      	ldr	r2, [r7, #20]
 800113a:	b292      	uxth	r2, r2
 800113c:	0052      	lsls	r2, r2, #1
 800113e:	2103      	movs	r1, #3
 8001140:	4091      	lsls	r1, r2
 8001142:	1c0a      	adds	r2, r1, #0
 8001144:	43d2      	mvns	r2, r2
 8001146:	401a      	ands	r2, r3
 8001148:	687b      	ldr	r3, [r7, #4]
 800114a:	60da      	str	r2, [r3, #12]
      GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
 800114c:	687b      	ldr	r3, [r7, #4]
 800114e:	68da      	ldr	r2, [r3, #12]
 8001150:	683b      	ldr	r3, [r7, #0]
 8001152:	79db      	ldrb	r3, [r3, #7]
 8001154:	1c19      	adds	r1, r3, #0
 8001156:	697b      	ldr	r3, [r7, #20]
 8001158:	005b      	lsls	r3, r3, #1
 800115a:	4099      	lsls	r1, r3
 800115c:	1c0b      	adds	r3, r1, #0
 800115e:	431a      	orrs	r2, r3
 8001160:	687b      	ldr	r3, [r7, #4]
 8001162:	60da      	str	r2, [r3, #12]
  assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
  assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));

  /*-------------------------- Configure the port pins -----------------------*/
  /*-- GPIO Mode Configuration --*/
  for (pinpos = 0x00; pinpos < 0x10; pinpos++)
 8001164:	697b      	ldr	r3, [r7, #20]
 8001166:	3301      	adds	r3, #1
 8001168:	617b      	str	r3, [r7, #20]
 800116a:	697b      	ldr	r3, [r7, #20]
 800116c:	2b0f      	cmp	r3, #15
 800116e:	d800      	bhi.n	8001172 <GPIO_Init+0x11e>
 8001170:	e77e      	b.n	8001070 <GPIO_Init+0x1c>
      /* Pull-up Pull down resistor configuration */
      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
      GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
    }
  }
}
 8001172:	46bd      	mov	sp, r7
 8001174:	b006      	add	sp, #24
 8001176:	bd80      	pop	{r7, pc}

08001178 <GPIO_StructInit>:
  * @param  GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure which will 
  *         be initialized.
  * @retval None
  */
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
{
 8001178:	b580      	push	{r7, lr}
 800117a:	b082      	sub	sp, #8
 800117c:	af00      	add	r7, sp, #0
 800117e:	6078      	str	r0, [r7, #4]
  /* Reset GPIO init structure parameters values */
  GPIO_InitStruct->GPIO_Pin  = GPIO_Pin_All;
 8001180:	687b      	ldr	r3, [r7, #4]
 8001182:	4a08      	ldr	r2, [pc, #32]	; (80011a4 <GPIO_StructInit+0x2c>)
 8001184:	601a      	str	r2, [r3, #0]
  GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
 8001186:	687b      	ldr	r3, [r7, #4]
 8001188:	2200      	movs	r2, #0
 800118a:	711a      	strb	r2, [r3, #4]
  GPIO_InitStruct->GPIO_Speed = GPIO_Speed_Level_2;
 800118c:	687b      	ldr	r3, [r7, #4]
 800118e:	2201      	movs	r2, #1
 8001190:	715a      	strb	r2, [r3, #5]
  GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
 8001192:	687b      	ldr	r3, [r7, #4]
 8001194:	2200      	movs	r2, #0
 8001196:	719a      	strb	r2, [r3, #6]
  GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
 8001198:	687b      	ldr	r3, [r7, #4]
 800119a:	2200      	movs	r2, #0
 800119c:	71da      	strb	r2, [r3, #7]
}
 800119e:	46bd      	mov	sp, r7
 80011a0:	b002      	add	sp, #8
 80011a2:	bd80      	pop	{r7, pc}
 80011a4:	0000ffff 	.word	0x0000ffff

080011a8 <GPIO_PinLockConfig>:
  * @param  GPIO_Pin: specifies the port bit to be written.
  *          This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
  * @retval None
  */
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
 80011a8:	b580      	push	{r7, lr}
 80011aa:	b084      	sub	sp, #16
 80011ac:	af00      	add	r7, sp, #0
 80011ae:	6078      	str	r0, [r7, #4]
 80011b0:	1c0a      	adds	r2, r1, #0
 80011b2:	1cbb      	adds	r3, r7, #2
 80011b4:	801a      	strh	r2, [r3, #0]
  __IO uint32_t tmp = 0x00010000;
 80011b6:	2380      	movs	r3, #128	; 0x80
 80011b8:	025b      	lsls	r3, r3, #9
 80011ba:	60fb      	str	r3, [r7, #12]

  /* Check the parameters */
  assert_param(IS_GPIO_LIST_PERIPH(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Pin));

  tmp |= GPIO_Pin;
 80011bc:	1cbb      	adds	r3, r7, #2
 80011be:	881a      	ldrh	r2, [r3, #0]
 80011c0:	68fb      	ldr	r3, [r7, #12]
 80011c2:	4313      	orrs	r3, r2
 80011c4:	60fb      	str	r3, [r7, #12]
  /* Set LCKK bit */
  GPIOx->LCKR = tmp;
 80011c6:	68fa      	ldr	r2, [r7, #12]
 80011c8:	687b      	ldr	r3, [r7, #4]
 80011ca:	61da      	str	r2, [r3, #28]
  /* Reset LCKK bit */
  GPIOx->LCKR =  GPIO_Pin;
 80011cc:	1cbb      	adds	r3, r7, #2
 80011ce:	881a      	ldrh	r2, [r3, #0]
 80011d0:	687b      	ldr	r3, [r7, #4]
 80011d2:	61da      	str	r2, [r3, #28]
  /* Set LCKK bit */
  GPIOx->LCKR = tmp;
 80011d4:	68fa      	ldr	r2, [r7, #12]
 80011d6:	687b      	ldr	r3, [r7, #4]
 80011d8:	61da      	str	r2, [r3, #28]
  /* Read LCKK bit */
  tmp = GPIOx->LCKR;
 80011da:	687b      	ldr	r3, [r7, #4]
 80011dc:	69db      	ldr	r3, [r3, #28]
 80011de:	60fb      	str	r3, [r7, #12]
  /* Read LCKK bit */
  tmp = GPIOx->LCKR;
 80011e0:	687b      	ldr	r3, [r7, #4]
 80011e2:	69db      	ldr	r3, [r3, #28]
 80011e4:	60fb      	str	r3, [r7, #12]
}
 80011e6:	46bd      	mov	sp, r7
 80011e8:	b004      	add	sp, #16
 80011ea:	bd80      	pop	{r7, pc}

080011ec <GPIO_ReadInputDataBit>:
  *         For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
  *         For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF.  
  * @retval The input port pin value.
  */
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
 80011ec:	b580      	push	{r7, lr}
 80011ee:	b084      	sub	sp, #16
 80011f0:	af00      	add	r7, sp, #0
 80011f2:	6078      	str	r0, [r7, #4]
 80011f4:	1c0a      	adds	r2, r1, #0
 80011f6:	1cbb      	adds	r3, r7, #2
 80011f8:	801a      	strh	r2, [r3, #0]
  uint8_t bitstatus = 0x00;
 80011fa:	230f      	movs	r3, #15
 80011fc:	18fb      	adds	r3, r7, r3
 80011fe:	2200      	movs	r2, #0
 8001200:	701a      	strb	r2, [r3, #0]

  /* Check the parameters */
  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));

  if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
 8001202:	687b      	ldr	r3, [r7, #4]
 8001204:	8a1b      	ldrh	r3, [r3, #16]
 8001206:	b29b      	uxth	r3, r3
 8001208:	1cba      	adds	r2, r7, #2
 800120a:	8812      	ldrh	r2, [r2, #0]
 800120c:	4013      	ands	r3, r2
 800120e:	b29b      	uxth	r3, r3
 8001210:	2b00      	cmp	r3, #0
 8001212:	d004      	beq.n	800121e <GPIO_ReadInputDataBit+0x32>
  {
    bitstatus = (uint8_t)Bit_SET;
 8001214:	230f      	movs	r3, #15
 8001216:	18fb      	adds	r3, r7, r3
 8001218:	2201      	movs	r2, #1
 800121a:	701a      	strb	r2, [r3, #0]
 800121c:	e003      	b.n	8001226 <GPIO_ReadInputDataBit+0x3a>
  }
  else
  {
    bitstatus = (uint8_t)Bit_RESET;
 800121e:	230f      	movs	r3, #15
 8001220:	18fb      	adds	r3, r7, r3
 8001222:	2200      	movs	r2, #0
 8001224:	701a      	strb	r2, [r3, #0]
  }
  return bitstatus;
 8001226:	230f      	movs	r3, #15
 8001228:	18fb      	adds	r3, r7, r3
 800122a:	781b      	ldrb	r3, [r3, #0]
}
 800122c:	1c18      	adds	r0, r3, #0
 800122e:	46bd      	mov	sp, r7
 8001230:	b004      	add	sp, #16
 8001232:	bd80      	pop	{r7, pc}

08001234 <GPIO_ReadInputData>:
  * @note   GPIOE is available only for STM32F072.
  * @note   GPIOD is not available for STM32F031.   
  * @retval The input port pin value.
  */
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
{
 8001234:	b580      	push	{r7, lr}
 8001236:	b082      	sub	sp, #8
 8001238:	af00      	add	r7, sp, #0
 800123a:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));

  return ((uint16_t)GPIOx->IDR);
 800123c:	687b      	ldr	r3, [r7, #4]
 800123e:	8a1b      	ldrh	r3, [r3, #16]
 8001240:	b29b      	uxth	r3, r3
}
 8001242:	1c18      	adds	r0, r3, #0
 8001244:	46bd      	mov	sp, r7
 8001246:	b002      	add	sp, #8
 8001248:	bd80      	pop	{r7, pc}
 800124a:	46c0      	nop			; (mov r8, r8)

0800124c <GPIO_ReadOutputDataBit>:
  *         For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
  *         For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF. 
  * @retval The output port pin value.
  */
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
 800124c:	b580      	push	{r7, lr}
 800124e:	b084      	sub	sp, #16
 8001250:	af00      	add	r7, sp, #0
 8001252:	6078      	str	r0, [r7, #4]
 8001254:	1c0a      	adds	r2, r1, #0
 8001256:	1cbb      	adds	r3, r7, #2
 8001258:	801a      	strh	r2, [r3, #0]
  uint8_t bitstatus = 0x00;
 800125a:	230f      	movs	r3, #15
 800125c:	18fb      	adds	r3, r7, r3
 800125e:	2200      	movs	r2, #0
 8001260:	701a      	strb	r2, [r3, #0]

  /* Check the parameters */
  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));

  if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
 8001262:	687b      	ldr	r3, [r7, #4]
 8001264:	8a9b      	ldrh	r3, [r3, #20]
 8001266:	b29b      	uxth	r3, r3
 8001268:	1cba      	adds	r2, r7, #2
 800126a:	8812      	ldrh	r2, [r2, #0]
 800126c:	4013      	ands	r3, r2
 800126e:	b29b      	uxth	r3, r3
 8001270:	2b00      	cmp	r3, #0
 8001272:	d004      	beq.n	800127e <GPIO_ReadOutputDataBit+0x32>
  {
    bitstatus = (uint8_t)Bit_SET;
 8001274:	230f      	movs	r3, #15
 8001276:	18fb      	adds	r3, r7, r3
 8001278:	2201      	movs	r2, #1
 800127a:	701a      	strb	r2, [r3, #0]
 800127c:	e003      	b.n	8001286 <GPIO_ReadOutputDataBit+0x3a>
  }
  else
  {
    bitstatus = (uint8_t)Bit_RESET;
 800127e:	230f      	movs	r3, #15
 8001280:	18fb      	adds	r3, r7, r3
 8001282:	2200      	movs	r2, #0
 8001284:	701a      	strb	r2, [r3, #0]
  }
  return bitstatus;
 8001286:	230f      	movs	r3, #15
 8001288:	18fb      	adds	r3, r7, r3
 800128a:	781b      	ldrb	r3, [r3, #0]
}
 800128c:	1c18      	adds	r0, r3, #0
 800128e:	46bd      	mov	sp, r7
 8001290:	b004      	add	sp, #16
 8001292:	bd80      	pop	{r7, pc}

08001294 <GPIO_ReadOutputData>:
  * @note   GPIOE is available only for STM32F072.
  * @note   GPIOD is not available for STM32F031.    
  * @retval GPIO output data port value.
  */
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
{
 8001294:	b580      	push	{r7, lr}
 8001296:	b082      	sub	sp, #8
 8001298:	af00      	add	r7, sp, #0
 800129a:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));

  return ((uint16_t)GPIOx->ODR);
 800129c:	687b      	ldr	r3, [r7, #4]
 800129e:	8a9b      	ldrh	r3, [r3, #20]
 80012a0:	b29b      	uxth	r3, r3
}
 80012a2:	1c18      	adds	r0, r3, #0
 80012a4:	46bd      	mov	sp, r7
 80012a6:	b002      	add	sp, #8
 80012a8:	bd80      	pop	{r7, pc}
 80012aa:	46c0      	nop			; (mov r8, r8)

080012ac <GPIO_SetBits>:
  *         For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
  *         For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF. 
  * @retval None
  */
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
 80012ac:	b580      	push	{r7, lr}
 80012ae:	b082      	sub	sp, #8
 80012b0:	af00      	add	r7, sp, #0
 80012b2:	6078      	str	r0, [r7, #4]
 80012b4:	1c0a      	adds	r2, r1, #0
 80012b6:	1cbb      	adds	r3, r7, #2
 80012b8:	801a      	strh	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Pin));

  GPIOx->BSRR = GPIO_Pin;
 80012ba:	1cbb      	adds	r3, r7, #2
 80012bc:	881a      	ldrh	r2, [r3, #0]
 80012be:	687b      	ldr	r3, [r7, #4]
 80012c0:	619a      	str	r2, [r3, #24]
}
 80012c2:	46bd      	mov	sp, r7
 80012c4:	b002      	add	sp, #8
 80012c6:	bd80      	pop	{r7, pc}

080012c8 <GPIO_ResetBits>:
  *         For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
  *         For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF. 
  * @retval None
  */
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
 80012c8:	b580      	push	{r7, lr}
 80012ca:	b082      	sub	sp, #8
 80012cc:	af00      	add	r7, sp, #0
 80012ce:	6078      	str	r0, [r7, #4]
 80012d0:	1c0a      	adds	r2, r1, #0
 80012d2:	1cbb      	adds	r3, r7, #2
 80012d4:	801a      	strh	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Pin));

  GPIOx->BRR = GPIO_Pin;
 80012d6:	687b      	ldr	r3, [r7, #4]
 80012d8:	1cba      	adds	r2, r7, #2
 80012da:	8812      	ldrh	r2, [r2, #0]
 80012dc:	851a      	strh	r2, [r3, #40]	; 0x28
}
 80012de:	46bd      	mov	sp, r7
 80012e0:	b002      	add	sp, #8
 80012e2:	bd80      	pop	{r7, pc}

080012e4 <GPIO_WriteBit>:
  *         For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
  *         For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF.
  * @retval None
  */
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
{
 80012e4:	b580      	push	{r7, lr}
 80012e6:	b082      	sub	sp, #8
 80012e8:	af00      	add	r7, sp, #0
 80012ea:	6078      	str	r0, [r7, #4]
 80012ec:	1c08      	adds	r0, r1, #0
 80012ee:	1c11      	adds	r1, r2, #0
 80012f0:	1cbb      	adds	r3, r7, #2
 80012f2:	1c02      	adds	r2, r0, #0
 80012f4:	801a      	strh	r2, [r3, #0]
 80012f6:	1c7b      	adds	r3, r7, #1
 80012f8:	1c0a      	adds	r2, r1, #0
 80012fa:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
  assert_param(IS_GPIO_BIT_ACTION(BitVal));

  if (BitVal != Bit_RESET)
 80012fc:	1c7b      	adds	r3, r7, #1
 80012fe:	781b      	ldrb	r3, [r3, #0]
 8001300:	2b00      	cmp	r3, #0
 8001302:	d004      	beq.n	800130e <GPIO_WriteBit+0x2a>
  {
    GPIOx->BSRR = GPIO_Pin;
 8001304:	1cbb      	adds	r3, r7, #2
 8001306:	881a      	ldrh	r2, [r3, #0]
 8001308:	687b      	ldr	r3, [r7, #4]
 800130a:	619a      	str	r2, [r3, #24]
 800130c:	e003      	b.n	8001316 <GPIO_WriteBit+0x32>
  }
  else
  {
    GPIOx->BRR = GPIO_Pin ;
 800130e:	687b      	ldr	r3, [r7, #4]
 8001310:	1cba      	adds	r2, r7, #2
 8001312:	8812      	ldrh	r2, [r2, #0]
 8001314:	851a      	strh	r2, [r3, #40]	; 0x28
  }
}
 8001316:	46bd      	mov	sp, r7
 8001318:	b002      	add	sp, #8
 800131a:	bd80      	pop	{r7, pc}

0800131c <GPIO_Write>:
  * @note   GPIOD is not available for STM32F031.  
  * @param  PortVal: specifies the value to be written to the port output data register.
  * @retval None
  */
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
{
 800131c:	b580      	push	{r7, lr}
 800131e:	b082      	sub	sp, #8
 8001320:	af00      	add	r7, sp, #0
 8001322:	6078      	str	r0, [r7, #4]
 8001324:	1c0a      	adds	r2, r1, #0
 8001326:	1cbb      	adds	r3, r7, #2
 8001328:	801a      	strh	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));

  GPIOx->ODR = PortVal;
 800132a:	687b      	ldr	r3, [r7, #4]
 800132c:	1cba      	adds	r2, r7, #2
 800132e:	8812      	ldrh	r2, [r2, #0]
 8001330:	829a      	strh	r2, [r3, #20]
}
 8001332:	46bd      	mov	sp, r7
 8001334:	b002      	add	sp, #8
 8001336:	bd80      	pop	{r7, pc}

08001338 <GPIO_PinAFConfig>:
  *         for the detailed mapping of the system and peripherals'alternate 
  *         function I/O pins.
  * @retval None
  */
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
{
 8001338:	b580      	push	{r7, lr}
 800133a:	b084      	sub	sp, #16
 800133c:	af00      	add	r7, sp, #0
 800133e:	6078      	str	r0, [r7, #4]
 8001340:	1c08      	adds	r0, r1, #0
 8001342:	1c11      	adds	r1, r2, #0
 8001344:	1cbb      	adds	r3, r7, #2
 8001346:	1c02      	adds	r2, r0, #0
 8001348:	801a      	strh	r2, [r3, #0]
 800134a:	1c7b      	adds	r3, r7, #1
 800134c:	1c0a      	adds	r2, r1, #0
 800134e:	701a      	strb	r2, [r3, #0]
  uint32_t temp = 0x00;
 8001350:	2300      	movs	r3, #0
 8001352:	60fb      	str	r3, [r7, #12]
  uint32_t temp_2 = 0x00;
 8001354:	2300      	movs	r3, #0
 8001356:	60bb      	str	r3, [r7, #8]
  /* Check the parameters */
  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
  assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
  assert_param(IS_GPIO_AF(GPIO_AF));

  temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
 8001358:	1c7b      	adds	r3, r7, #1
 800135a:	781b      	ldrb	r3, [r3, #0]
 800135c:	1cba      	adds	r2, r7, #2
 800135e:	8812      	ldrh	r2, [r2, #0]
 8001360:	2107      	movs	r1, #7
 8001362:	400a      	ands	r2, r1
 8001364:	0092      	lsls	r2, r2, #2
 8001366:	4093      	lsls	r3, r2
 8001368:	60fb      	str	r3, [r7, #12]
  GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
 800136a:	1cbb      	adds	r3, r7, #2
 800136c:	881b      	ldrh	r3, [r3, #0]
 800136e:	08db      	lsrs	r3, r3, #3
 8001370:	b29b      	uxth	r3, r3
 8001372:	1c18      	adds	r0, r3, #0
 8001374:	1cbb      	adds	r3, r7, #2
 8001376:	881b      	ldrh	r3, [r3, #0]
 8001378:	08db      	lsrs	r3, r3, #3
 800137a:	b29b      	uxth	r3, r3
 800137c:	1c1a      	adds	r2, r3, #0
 800137e:	687b      	ldr	r3, [r7, #4]
 8001380:	3208      	adds	r2, #8
 8001382:	0092      	lsls	r2, r2, #2
 8001384:	58d3      	ldr	r3, [r2, r3]
 8001386:	1cba      	adds	r2, r7, #2
 8001388:	8812      	ldrh	r2, [r2, #0]
 800138a:	2107      	movs	r1, #7
 800138c:	400a      	ands	r2, r1
 800138e:	0092      	lsls	r2, r2, #2
 8001390:	1c11      	adds	r1, r2, #0
 8001392:	220f      	movs	r2, #15
 8001394:	408a      	lsls	r2, r1
 8001396:	43d2      	mvns	r2, r2
 8001398:	401a      	ands	r2, r3
 800139a:	1c11      	adds	r1, r2, #0
 800139c:	687b      	ldr	r3, [r7, #4]
 800139e:	1c02      	adds	r2, r0, #0
 80013a0:	3208      	adds	r2, #8
 80013a2:	0092      	lsls	r2, r2, #2
 80013a4:	50d1      	str	r1, [r2, r3]
  temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
 80013a6:	1cbb      	adds	r3, r7, #2
 80013a8:	881b      	ldrh	r3, [r3, #0]
 80013aa:	08db      	lsrs	r3, r3, #3
 80013ac:	b29b      	uxth	r3, r3
 80013ae:	1c1a      	adds	r2, r3, #0
 80013b0:	687b      	ldr	r3, [r7, #4]
 80013b2:	3208      	adds	r2, #8
 80013b4:	0092      	lsls	r2, r2, #2
 80013b6:	58d2      	ldr	r2, [r2, r3]
 80013b8:	68fb      	ldr	r3, [r7, #12]
 80013ba:	4313      	orrs	r3, r2
 80013bc:	60bb      	str	r3, [r7, #8]
  GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
 80013be:	1cbb      	adds	r3, r7, #2
 80013c0:	881b      	ldrh	r3, [r3, #0]
 80013c2:	08db      	lsrs	r3, r3, #3
 80013c4:	b29b      	uxth	r3, r3
 80013c6:	1c1a      	adds	r2, r3, #0
 80013c8:	687b      	ldr	r3, [r7, #4]
 80013ca:	3208      	adds	r2, #8
 80013cc:	0092      	lsls	r2, r2, #2
 80013ce:	68b9      	ldr	r1, [r7, #8]
 80013d0:	50d1      	str	r1, [r2, r3]
}
 80013d2:	46bd      	mov	sp, r7
 80013d4:	b004      	add	sp, #16
 80013d6:	bd80      	pop	{r7, pc}

080013d8 <SPI_I2S_DeInit>:
  * @note   SPI2 is not available for STM32F031 devices.
  *         I2S mode is not supported for STM32F030 devices.      
  * @retval None
  */
void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
{
 80013d8:	b580      	push	{r7, lr}
 80013da:	b082      	sub	sp, #8
 80013dc:	af00      	add	r7, sp, #0
 80013de:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_SPI_ALL_PERIPH(SPIx));

  if (SPIx == SPI1)
 80013e0:	687b      	ldr	r3, [r7, #4]
 80013e2:	4a11      	ldr	r2, [pc, #68]	; (8001428 <SPI_I2S_DeInit+0x50>)
 80013e4:	4293      	cmp	r3, r2
 80013e6:	d10c      	bne.n	8001402 <SPI_I2S_DeInit+0x2a>
  {
    /* Enable SPI1 reset state */
    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
 80013e8:	2380      	movs	r3, #128	; 0x80
 80013ea:	015b      	lsls	r3, r3, #5
 80013ec:	1c18      	adds	r0, r3, #0
 80013ee:	2101      	movs	r1, #1
 80013f0:	f7ff fcca 	bl	8000d88 <RCC_APB2PeriphResetCmd>
    /* Release SPI1 from reset state */
    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
 80013f4:	2380      	movs	r3, #128	; 0x80
 80013f6:	015b      	lsls	r3, r3, #5
 80013f8:	1c18      	adds	r0, r3, #0
 80013fa:	2100      	movs	r1, #0
 80013fc:	f7ff fcc4 	bl	8000d88 <RCC_APB2PeriphResetCmd>
 8001400:	e00f      	b.n	8001422 <SPI_I2S_DeInit+0x4a>
  }
  else
  {
    if (SPIx == SPI2)
 8001402:	687b      	ldr	r3, [r7, #4]
 8001404:	4a09      	ldr	r2, [pc, #36]	; (800142c <SPI_I2S_DeInit+0x54>)
 8001406:	4293      	cmp	r3, r2
 8001408:	d10b      	bne.n	8001422 <SPI_I2S_DeInit+0x4a>
    {
      /* Enable SPI2 reset state */
      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
 800140a:	2380      	movs	r3, #128	; 0x80
 800140c:	01db      	lsls	r3, r3, #7
 800140e:	1c18      	adds	r0, r3, #0
 8001410:	2101      	movs	r1, #1
 8001412:	f7ff fcd7 	bl	8000dc4 <RCC_APB1PeriphResetCmd>
      /* Release SPI2 from reset state */
      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
 8001416:	2380      	movs	r3, #128	; 0x80
 8001418:	01db      	lsls	r3, r3, #7
 800141a:	1c18      	adds	r0, r3, #0
 800141c:	2100      	movs	r1, #0
 800141e:	f7ff fcd1 	bl	8000dc4 <RCC_APB1PeriphResetCmd>
    }
  }
}
 8001422:	46bd      	mov	sp, r7
 8001424:	b002      	add	sp, #8
 8001426:	bd80      	pop	{r7, pc}
 8001428:	40013000 	.word	0x40013000
 800142c:	40003800 	.word	0x40003800

08001430 <SPI_StructInit>:
  * @brief  Fills each SPI_InitStruct member with its default value.
  * @param  SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized.
  * @retval None
  */
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
{
 8001430:	b580      	push	{r7, lr}
 8001432:	b082      	sub	sp, #8
 8001434:	af00      	add	r7, sp, #0
 8001436:	6078      	str	r0, [r7, #4]
/*--------------- Reset SPI init structure parameters values -----------------*/
  /* Initialize the SPI_Direction member */
  SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
 8001438:	687b      	ldr	r3, [r7, #4]
 800143a:	2200      	movs	r2, #0
 800143c:	801a      	strh	r2, [r3, #0]
  /* Initialize the SPI_Mode member */
  SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
 800143e:	687b      	ldr	r3, [r7, #4]
 8001440:	2200      	movs	r2, #0
 8001442:	805a      	strh	r2, [r3, #2]
  /* Initialize the SPI_DataSize member */
  SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
 8001444:	687b      	ldr	r3, [r7, #4]
 8001446:	22e0      	movs	r2, #224	; 0xe0
 8001448:	00d2      	lsls	r2, r2, #3
 800144a:	809a      	strh	r2, [r3, #4]
  /* Initialize the SPI_CPOL member */
  SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
 800144c:	687b      	ldr	r3, [r7, #4]
 800144e:	2200      	movs	r2, #0
 8001450:	80da      	strh	r2, [r3, #6]
  /* Initialize the SPI_CPHA member */
  SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
 8001452:	687b      	ldr	r3, [r7, #4]
 8001454:	2200      	movs	r2, #0
 8001456:	811a      	strh	r2, [r3, #8]
  /* Initialize the SPI_NSS member */
  SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
 8001458:	687b      	ldr	r3, [r7, #4]
 800145a:	2200      	movs	r2, #0
 800145c:	815a      	strh	r2, [r3, #10]
  /* Initialize the SPI_BaudRatePrescaler member */
  SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
 800145e:	687b      	ldr	r3, [r7, #4]
 8001460:	2200      	movs	r2, #0
 8001462:	819a      	strh	r2, [r3, #12]
  /* Initialize the SPI_FirstBit member */
  SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
 8001464:	687b      	ldr	r3, [r7, #4]
 8001466:	2200      	movs	r2, #0
 8001468:	81da      	strh	r2, [r3, #14]
  /* Initialize the SPI_CRCPolynomial member */
  SPI_InitStruct->SPI_CRCPolynomial = 7;
 800146a:	687b      	ldr	r3, [r7, #4]
 800146c:	2207      	movs	r2, #7
 800146e:	821a      	strh	r2, [r3, #16]
}
 8001470:	46bd      	mov	sp, r7
 8001472:	b002      	add	sp, #8
 8001474:	bd80      	pop	{r7, pc}
 8001476:	46c0      	nop			; (mov r8, r8)

08001478 <SPI_Init>:
  * @param  SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
  *         contains the configuration information for the specified SPI peripheral.
  * @retval None
  */
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
{
 8001478:	b580      	push	{r7, lr}
 800147a:	b084      	sub	sp, #16
 800147c:	af00      	add	r7, sp, #0
 800147e:	6078      	str	r0, [r7, #4]
 8001480:	6039      	str	r1, [r7, #0]
  uint16_t tmpreg = 0;
 8001482:	230e      	movs	r3, #14
 8001484:	18fb      	adds	r3, r7, r3
 8001486:	2200      	movs	r2, #0
 8001488:	801a      	strh	r2, [r3, #0]
  assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
  assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));

  /*---------------------------- SPIx CR1 Configuration ------------------------*/
  /* Get the SPIx CR1 value */
  tmpreg = SPIx->CR1;
 800148a:	230e      	movs	r3, #14
 800148c:	18fb      	adds	r3, r7, r3
 800148e:	687a      	ldr	r2, [r7, #4]
 8001490:	8812      	ldrh	r2, [r2, #0]
 8001492:	801a      	strh	r2, [r3, #0]
  /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, CPOL and CPHA bits */
  tmpreg &= CR1_CLEAR_MASK;
 8001494:	230e      	movs	r3, #14
 8001496:	18fb      	adds	r3, r7, r3
 8001498:	220e      	movs	r2, #14
 800149a:	18ba      	adds	r2, r7, r2
 800149c:	8811      	ldrh	r1, [r2, #0]
 800149e:	22c1      	movs	r2, #193	; 0xc1
 80014a0:	0192      	lsls	r2, r2, #6
 80014a2:	400a      	ands	r2, r1
 80014a4:	801a      	strh	r2, [r3, #0]
  /* Set SSM, SSI bit according to SPI_NSS values */
  /* Set LSBFirst bit according to SPI_FirstBit value */
  /* Set BR bits according to SPI_BaudRatePrescaler value */
  /* Set CPOL bit according to SPI_CPOL value */
  /* Set CPHA bit according to SPI_CPHA value */
  tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_FirstBit |
 80014a6:	683b      	ldr	r3, [r7, #0]
 80014a8:	881a      	ldrh	r2, [r3, #0]
 80014aa:	683b      	ldr	r3, [r7, #0]
 80014ac:	89db      	ldrh	r3, [r3, #14]
 80014ae:	4313      	orrs	r3, r2
 80014b0:	b29a      	uxth	r2, r3
                      SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA |
 80014b2:	683b      	ldr	r3, [r7, #0]
 80014b4:	88db      	ldrh	r3, [r3, #6]
  /* Set SSM, SSI bit according to SPI_NSS values */
  /* Set LSBFirst bit according to SPI_FirstBit value */
  /* Set BR bits according to SPI_BaudRatePrescaler value */
  /* Set CPOL bit according to SPI_CPOL value */
  /* Set CPHA bit according to SPI_CPHA value */
  tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_FirstBit |
 80014b6:	4313      	orrs	r3, r2
 80014b8:	b29a      	uxth	r2, r3
                      SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA |
 80014ba:	683b      	ldr	r3, [r7, #0]
 80014bc:	891b      	ldrh	r3, [r3, #8]
  /* Set SSM, SSI bit according to SPI_NSS values */
  /* Set LSBFirst bit according to SPI_FirstBit value */
  /* Set BR bits according to SPI_BaudRatePrescaler value */
  /* Set CPOL bit according to SPI_CPOL value */
  /* Set CPHA bit according to SPI_CPHA value */
  tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_FirstBit |
 80014be:	4313      	orrs	r3, r2
 80014c0:	b29a      	uxth	r2, r3
                      SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA |
                      SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler);  
 80014c2:	683b      	ldr	r3, [r7, #0]
 80014c4:	895b      	ldrh	r3, [r3, #10]
  /* Set SSM, SSI bit according to SPI_NSS values */
  /* Set LSBFirst bit according to SPI_FirstBit value */
  /* Set BR bits according to SPI_BaudRatePrescaler value */
  /* Set CPOL bit according to SPI_CPOL value */
  /* Set CPHA bit according to SPI_CPHA value */
  tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_FirstBit |
 80014c6:	4313      	orrs	r3, r2
 80014c8:	b29a      	uxth	r2, r3
                      SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA |
                      SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler);  
 80014ca:	683b      	ldr	r3, [r7, #0]
 80014cc:	899b      	ldrh	r3, [r3, #12]
  /* Set SSM, SSI bit according to SPI_NSS values */
  /* Set LSBFirst bit according to SPI_FirstBit value */
  /* Set BR bits according to SPI_BaudRatePrescaler value */
  /* Set CPOL bit according to SPI_CPOL value */
  /* Set CPHA bit according to SPI_CPHA value */
  tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_FirstBit |
 80014ce:	4313      	orrs	r3, r2
 80014d0:	b299      	uxth	r1, r3
 80014d2:	230e      	movs	r3, #14
 80014d4:	18fb      	adds	r3, r7, r3
 80014d6:	220e      	movs	r2, #14
 80014d8:	18ba      	adds	r2, r7, r2
 80014da:	8812      	ldrh	r2, [r2, #0]
 80014dc:	430a      	orrs	r2, r1
 80014de:	801a      	strh	r2, [r3, #0]
                      SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA |
                      SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler);  
  /* Write to SPIx CR1 */
  SPIx->CR1 = tmpreg;
 80014e0:	687b      	ldr	r3, [r7, #4]
 80014e2:	220e      	movs	r2, #14
 80014e4:	18ba      	adds	r2, r7, r2
 80014e6:	8812      	ldrh	r2, [r2, #0]
 80014e8:	801a      	strh	r2, [r3, #0]
  /*-------------------------Data Size Configuration -----------------------*/
  /* Get the SPIx CR2 value */
  tmpreg = SPIx->CR2;
 80014ea:	230e      	movs	r3, #14
 80014ec:	18fb      	adds	r3, r7, r3
 80014ee:	687a      	ldr	r2, [r7, #4]
 80014f0:	8892      	ldrh	r2, [r2, #4]
 80014f2:	801a      	strh	r2, [r3, #0]
  /* Clear DS[3:0] bits */
  tmpreg &=(uint16_t)~SPI_CR2_DS;
 80014f4:	230e      	movs	r3, #14
 80014f6:	18fb      	adds	r3, r7, r3
 80014f8:	220e      	movs	r2, #14
 80014fa:	18ba      	adds	r2, r7, r2
 80014fc:	8812      	ldrh	r2, [r2, #0]
 80014fe:	491d      	ldr	r1, [pc, #116]	; (8001574 <SPI_Init+0xfc>)
 8001500:	400a      	ands	r2, r1
 8001502:	801a      	strh	r2, [r3, #0]
  /* Configure SPIx: Data Size */
  tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize);
 8001504:	683b      	ldr	r3, [r7, #0]
 8001506:	8899      	ldrh	r1, [r3, #4]
 8001508:	230e      	movs	r3, #14
 800150a:	18fb      	adds	r3, r7, r3
 800150c:	220e      	movs	r2, #14
 800150e:	18ba      	adds	r2, r7, r2
 8001510:	8812      	ldrh	r2, [r2, #0]
 8001512:	430a      	orrs	r2, r1
 8001514:	801a      	strh	r2, [r3, #0]
  /* Write to SPIx CR2 */
  SPIx->CR2 = tmpreg;
 8001516:	687b      	ldr	r3, [r7, #4]
 8001518:	220e      	movs	r2, #14
 800151a:	18ba      	adds	r2, r7, r2
 800151c:	8812      	ldrh	r2, [r2, #0]
 800151e:	809a      	strh	r2, [r3, #4]
  
  /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
  /* Write to SPIx CRCPOLY */
  SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
 8001520:	683b      	ldr	r3, [r7, #0]
 8001522:	8a1a      	ldrh	r2, [r3, #16]
 8001524:	687b      	ldr	r3, [r7, #4]
 8001526:	821a      	strh	r2, [r3, #16]
  
  /*---------------------------- SPIx CR1 Configuration ------------------------*/
  /* Get the SPIx CR1 value */
  tmpreg = SPIx->CR1;
 8001528:	230e      	movs	r3, #14
 800152a:	18fb      	adds	r3, r7, r3
 800152c:	687a      	ldr	r2, [r7, #4]
 800152e:	8812      	ldrh	r2, [r2, #0]
 8001530:	801a      	strh	r2, [r3, #0]
  /* Clear MSTR bit */
  tmpreg &= CR1_CLEAR_MASK2;
 8001532:	230e      	movs	r3, #14
 8001534:	18fb      	adds	r3, r7, r3
 8001536:	220e      	movs	r2, #14
 8001538:	18ba      	adds	r2, r7, r2
 800153a:	8812      	ldrh	r2, [r2, #0]
 800153c:	2104      	movs	r1, #4
 800153e:	438a      	bics	r2, r1
 8001540:	801a      	strh	r2, [r3, #0]
  /* Configure SPIx: master/slave mode */  
  /* Set MSTR bit according to SPI_Mode */
  tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Mode);  
 8001542:	683b      	ldr	r3, [r7, #0]
 8001544:	8859      	ldrh	r1, [r3, #2]
 8001546:	230e      	movs	r3, #14
 8001548:	18fb      	adds	r3, r7, r3
 800154a:	220e      	movs	r2, #14
 800154c:	18ba      	adds	r2, r7, r2
 800154e:	8812      	ldrh	r2, [r2, #0]
 8001550:	430a      	orrs	r2, r1
 8001552:	801a      	strh	r2, [r3, #0]
  /* Write to SPIx CR1 */
  SPIx->CR1 = tmpreg;  
 8001554:	687b      	ldr	r3, [r7, #4]
 8001556:	220e      	movs	r2, #14
 8001558:	18ba      	adds	r2, r7, r2
 800155a:	8812      	ldrh	r2, [r2, #0]
 800155c:	801a      	strh	r2, [r3, #0]
  
  /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
  SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);
 800155e:	687b      	ldr	r3, [r7, #4]
 8001560:	8b9b      	ldrh	r3, [r3, #28]
 8001562:	b29b      	uxth	r3, r3
 8001564:	4a04      	ldr	r2, [pc, #16]	; (8001578 <SPI_Init+0x100>)
 8001566:	4013      	ands	r3, r2
 8001568:	b29a      	uxth	r2, r3
 800156a:	687b      	ldr	r3, [r7, #4]
 800156c:	839a      	strh	r2, [r3, #28]
}
 800156e:	46bd      	mov	sp, r7
 8001570:	b004      	add	sp, #16
 8001572:	bd80      	pop	{r7, pc}
 8001574:	fffff0ff 	.word	0xfffff0ff
 8001578:	fffff7ff 	.word	0xfffff7ff

0800157c <I2S_StructInit>:
  * @note   This mode is not supported for STM32F030 devices.  
  * @param  I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized.
  * @retval None
  */
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
{
 800157c:	b580      	push	{r7, lr}
 800157e:	b082      	sub	sp, #8
 8001580:	af00      	add	r7, sp, #0
 8001582:	6078      	str	r0, [r7, #4]
/*--------------- Reset I2S init structure parameters values -----------------*/
  /* Initialize the I2S_Mode member */
  I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
 8001584:	687b      	ldr	r3, [r7, #4]
 8001586:	2200      	movs	r2, #0
 8001588:	801a      	strh	r2, [r3, #0]

  /* Initialize the I2S_Standard member */
  I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
 800158a:	687b      	ldr	r3, [r7, #4]
 800158c:	2200      	movs	r2, #0
 800158e:	805a      	strh	r2, [r3, #2]

  /* Initialize the I2S_DataFormat member */
  I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
 8001590:	687b      	ldr	r3, [r7, #4]
 8001592:	2200      	movs	r2, #0
 8001594:	809a      	strh	r2, [r3, #4]

  /* Initialize the I2S_MCLKOutput member */
  I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
 8001596:	687b      	ldr	r3, [r7, #4]
 8001598:	2200      	movs	r2, #0
 800159a:	80da      	strh	r2, [r3, #6]

  /* Initialize the I2S_AudioFreq member */
  I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
 800159c:	687b      	ldr	r3, [r7, #4]
 800159e:	2202      	movs	r2, #2
 80015a0:	609a      	str	r2, [r3, #8]

  /* Initialize the I2S_CPOL member */
  I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
 80015a2:	687b      	ldr	r3, [r7, #4]
 80015a4:	2200      	movs	r2, #0
 80015a6:	819a      	strh	r2, [r3, #12]
}
 80015a8:	46bd      	mov	sp, r7
 80015aa:	b002      	add	sp, #8
 80015ac:	bd80      	pop	{r7, pc}
 80015ae:	46c0      	nop			; (mov r8, r8)

080015b0 <I2S_Init>:
  *         and the product configuration). But in case the prescaler value is greater 
  *         than 511, the default value (0x02) will be configured instead.
  * @retval None
  */
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
{
 80015b0:	b580      	push	{r7, lr}
 80015b2:	b092      	sub	sp, #72	; 0x48
 80015b4:	af00      	add	r7, sp, #0
 80015b6:	6078      	str	r0, [r7, #4]
 80015b8:	6039      	str	r1, [r7, #0]
  uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
 80015ba:	233a      	movs	r3, #58	; 0x3a
 80015bc:	18fb      	adds	r3, r7, r3
 80015be:	2200      	movs	r2, #0
 80015c0:	801a      	strh	r2, [r3, #0]
 80015c2:	2346      	movs	r3, #70	; 0x46
 80015c4:	18fb      	adds	r3, r7, r3
 80015c6:	2202      	movs	r2, #2
 80015c8:	801a      	strh	r2, [r3, #0]
 80015ca:	2344      	movs	r3, #68	; 0x44
 80015cc:	18fb      	adds	r3, r7, r3
 80015ce:	2200      	movs	r2, #0
 80015d0:	801a      	strh	r2, [r3, #0]
 80015d2:	2342      	movs	r3, #66	; 0x42
 80015d4:	18fb      	adds	r3, r7, r3
 80015d6:	2201      	movs	r2, #1
 80015d8:	801a      	strh	r2, [r3, #0]
  uint32_t tmp = 0;
 80015da:	2300      	movs	r3, #0
 80015dc:	63fb      	str	r3, [r7, #60]	; 0x3c
  RCC_ClocksTypeDef RCC_Clocks;
  uint32_t sourceclock = 0;
 80015de:	2300      	movs	r3, #0
 80015e0:	637b      	str	r3, [r7, #52]	; 0x34
  assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
  assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));  

/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
  SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; 
 80015e2:	687b      	ldr	r3, [r7, #4]
 80015e4:	8b9b      	ldrh	r3, [r3, #28]
 80015e6:	b29b      	uxth	r3, r3
 80015e8:	4a60      	ldr	r2, [pc, #384]	; (800176c <I2S_Init+0x1bc>)
 80015ea:	4013      	ands	r3, r2
 80015ec:	b29a      	uxth	r2, r3
 80015ee:	687b      	ldr	r3, [r7, #4]
 80015f0:	839a      	strh	r2, [r3, #28]
  SPIx->I2SPR = 0x0002;
 80015f2:	687b      	ldr	r3, [r7, #4]
 80015f4:	2202      	movs	r2, #2
 80015f6:	841a      	strh	r2, [r3, #32]

  /* Get the I2SCFGR register value */
  tmpreg = SPIx->I2SCFGR;
 80015f8:	233a      	movs	r3, #58	; 0x3a
 80015fa:	18fb      	adds	r3, r7, r3
 80015fc:	687a      	ldr	r2, [r7, #4]
 80015fe:	8b92      	ldrh	r2, [r2, #28]
 8001600:	801a      	strh	r2, [r3, #0]

  /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
  if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
 8001602:	683b      	ldr	r3, [r7, #0]
 8001604:	689b      	ldr	r3, [r3, #8]
 8001606:	2b02      	cmp	r3, #2
 8001608:	d108      	bne.n	800161c <I2S_Init+0x6c>
  {
    i2sodd = (uint16_t)0;
 800160a:	2344      	movs	r3, #68	; 0x44
 800160c:	18fb      	adds	r3, r7, r3
 800160e:	2200      	movs	r2, #0
 8001610:	801a      	strh	r2, [r3, #0]
    i2sdiv = (uint16_t)2;   
 8001612:	2346      	movs	r3, #70	; 0x46
 8001614:	18fb      	adds	r3, r7, r3
 8001616:	2202      	movs	r2, #2
 8001618:	801a      	strh	r2, [r3, #0]
 800161a:	e066      	b.n	80016ea <I2S_Init+0x13a>
  }
  /* If the requested audio frequency is not the default, compute the prescaler */
  else
  {
    /* Check the frame length (For the Prescaler computing) */
    if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
 800161c:	683b      	ldr	r3, [r7, #0]
 800161e:	889b      	ldrh	r3, [r3, #4]
 8001620:	2b00      	cmp	r3, #0
 8001622:	d104      	bne.n	800162e <I2S_Init+0x7e>
    {
      /* Packet length is 16 bits */
      packetlength = 1;
 8001624:	2342      	movs	r3, #66	; 0x42
 8001626:	18fb      	adds	r3, r7, r3
 8001628:	2201      	movs	r2, #1
 800162a:	801a      	strh	r2, [r3, #0]
 800162c:	e003      	b.n	8001636 <I2S_Init+0x86>
    }
    else
    {
      /* Packet length is 32 bits */
      packetlength = 2;
 800162e:	2342      	movs	r3, #66	; 0x42
 8001630:	18fb      	adds	r3, r7, r3
 8001632:	2202      	movs	r2, #2
 8001634:	801a      	strh	r2, [r3, #0]
    }

    /* I2S Clock source is System clock: Get System Clock frequency */
    RCC_GetClocksFreq(&RCC_Clocks);      
 8001636:	230c      	movs	r3, #12
 8001638:	18fb      	adds	r3, r7, r3
 800163a:	1c18      	adds	r0, r3, #0
 800163c:	f7ff f976 	bl	800092c <RCC_GetClocksFreq>

    /* Get the source clock value: based on System Clock value */
    sourceclock = RCC_Clocks.SYSCLK_Frequency;    
 8001640:	230c      	movs	r3, #12
 8001642:	18fb      	adds	r3, r7, r3
 8001644:	681b      	ldr	r3, [r3, #0]
 8001646:	637b      	str	r3, [r7, #52]	; 0x34

    /* Compute the Real divider depending on the MCLK output state with a floating point */
    if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
 8001648:	683b      	ldr	r3, [r7, #0]
 800164a:	88da      	ldrh	r2, [r3, #6]
 800164c:	2380      	movs	r3, #128	; 0x80
 800164e:	009b      	lsls	r3, r3, #2
 8001650:	429a      	cmp	r2, r3
 8001652:	d112      	bne.n	800167a <I2S_Init+0xca>
    {
      /* MCLK output is enabled */
      tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
 8001654:	6b7b      	ldr	r3, [r7, #52]	; 0x34
 8001656:	0a1a      	lsrs	r2, r3, #8
 8001658:	1c13      	adds	r3, r2, #0
 800165a:	009b      	lsls	r3, r3, #2
 800165c:	189b      	adds	r3, r3, r2
 800165e:	005b      	lsls	r3, r3, #1
 8001660:	1c1a      	adds	r2, r3, #0
 8001662:	683b      	ldr	r3, [r7, #0]
 8001664:	689b      	ldr	r3, [r3, #8]
 8001666:	1c10      	adds	r0, r2, #0
 8001668:	1c19      	adds	r1, r3, #0
 800166a:	f001 f85d 	bl	8002728 <____aeabi_uidiv_from_thumb>
 800166e:	1c03      	adds	r3, r0, #0
 8001670:	b29b      	uxth	r3, r3
 8001672:	3305      	adds	r3, #5
 8001674:	b29b      	uxth	r3, r3
 8001676:	63fb      	str	r3, [r7, #60]	; 0x3c
 8001678:	e019      	b.n	80016ae <I2S_Init+0xfe>
    }
    else
    {
      /* MCLK output is disabled */
      tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
 800167a:	2342      	movs	r3, #66	; 0x42
 800167c:	18fb      	adds	r3, r7, r3
 800167e:	881b      	ldrh	r3, [r3, #0]
 8001680:	015b      	lsls	r3, r3, #5
 8001682:	6b78      	ldr	r0, [r7, #52]	; 0x34
 8001684:	1c19      	adds	r1, r3, #0
 8001686:	f001 f84f 	bl	8002728 <____aeabi_uidiv_from_thumb>
 800168a:	1c03      	adds	r3, r0, #0
 800168c:	1c1a      	adds	r2, r3, #0
 800168e:	1c13      	adds	r3, r2, #0
 8001690:	009b      	lsls	r3, r3, #2
 8001692:	189b      	adds	r3, r3, r2
 8001694:	005b      	lsls	r3, r3, #1
 8001696:	1c1a      	adds	r2, r3, #0
 8001698:	683b      	ldr	r3, [r7, #0]
 800169a:	689b      	ldr	r3, [r3, #8]
 800169c:	1c10      	adds	r0, r2, #0
 800169e:	1c19      	adds	r1, r3, #0
 80016a0:	f001 f842 	bl	8002728 <____aeabi_uidiv_from_thumb>
 80016a4:	1c03      	adds	r3, r0, #0
 80016a6:	b29b      	uxth	r3, r3
 80016a8:	3305      	adds	r3, #5
 80016aa:	b29b      	uxth	r3, r3
 80016ac:	63fb      	str	r3, [r7, #60]	; 0x3c
    }
    
    /* Remove the floating point */
    tmp = tmp / 10;
 80016ae:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
 80016b0:	1c18      	adds	r0, r3, #0
 80016b2:	210a      	movs	r1, #10
 80016b4:	f001 f838 	bl	8002728 <____aeabi_uidiv_from_thumb>
 80016b8:	1c03      	adds	r3, r0, #0
 80016ba:	63fb      	str	r3, [r7, #60]	; 0x3c

    /* Check the parity of the divider */
    i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
 80016bc:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
 80016be:	b29a      	uxth	r2, r3
 80016c0:	2344      	movs	r3, #68	; 0x44
 80016c2:	18fb      	adds	r3, r7, r3
 80016c4:	2101      	movs	r1, #1
 80016c6:	400a      	ands	r2, r1
 80016c8:	801a      	strh	r2, [r3, #0]

    /* Compute the i2sdiv prescaler */
    i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
 80016ca:	2344      	movs	r3, #68	; 0x44
 80016cc:	18fb      	adds	r3, r7, r3
 80016ce:	881b      	ldrh	r3, [r3, #0]
 80016d0:	6bfa      	ldr	r2, [r7, #60]	; 0x3c
 80016d2:	1ad3      	subs	r3, r2, r3
 80016d4:	085a      	lsrs	r2, r3, #1
 80016d6:	2346      	movs	r3, #70	; 0x46
 80016d8:	18fb      	adds	r3, r7, r3
 80016da:	801a      	strh	r2, [r3, #0]

    /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
    i2sodd = (uint16_t) (i2sodd << 8);
 80016dc:	2344      	movs	r3, #68	; 0x44
 80016de:	18fb      	adds	r3, r7, r3
 80016e0:	2244      	movs	r2, #68	; 0x44
 80016e2:	18ba      	adds	r2, r7, r2
 80016e4:	8812      	ldrh	r2, [r2, #0]
 80016e6:	0212      	lsls	r2, r2, #8
 80016e8:	801a      	strh	r2, [r3, #0]
  }

  /* Test if the divider is 1 or 0 or greater than 0xFF */
  if ((i2sdiv < 2) || (i2sdiv > 0xFF))
 80016ea:	2346      	movs	r3, #70	; 0x46
 80016ec:	18fb      	adds	r3, r7, r3
 80016ee:	881b      	ldrh	r3, [r3, #0]
 80016f0:	2b01      	cmp	r3, #1
 80016f2:	d904      	bls.n	80016fe <I2S_Init+0x14e>
 80016f4:	2346      	movs	r3, #70	; 0x46
 80016f6:	18fb      	adds	r3, r7, r3
 80016f8:	881b      	ldrh	r3, [r3, #0]
 80016fa:	2bff      	cmp	r3, #255	; 0xff
 80016fc:	d907      	bls.n	800170e <I2S_Init+0x15e>
  {
    /* Set the default values */
    i2sdiv = 2;
 80016fe:	2346      	movs	r3, #70	; 0x46
 8001700:	18fb      	adds	r3, r7, r3
 8001702:	2202      	movs	r2, #2
 8001704:	801a      	strh	r2, [r3, #0]
    i2sodd = 0;
 8001706:	2344      	movs	r3, #68	; 0x44
 8001708:	18fb      	adds	r3, r7, r3
 800170a:	2200      	movs	r2, #0
 800170c:	801a      	strh	r2, [r3, #0]
  }

  /* Write to SPIx I2SPR register the computed value */
  SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
 800170e:	683b      	ldr	r3, [r7, #0]
 8001710:	88da      	ldrh	r2, [r3, #6]
 8001712:	2344      	movs	r3, #68	; 0x44
 8001714:	18fb      	adds	r3, r7, r3
 8001716:	881b      	ldrh	r3, [r3, #0]
 8001718:	4313      	orrs	r3, r2
 800171a:	b29a      	uxth	r2, r3
 800171c:	2346      	movs	r3, #70	; 0x46
 800171e:	18fb      	adds	r3, r7, r3
 8001720:	881b      	ldrh	r3, [r3, #0]
 8001722:	4313      	orrs	r3, r2
 8001724:	b29a      	uxth	r2, r3
 8001726:	687b      	ldr	r3, [r7, #4]
 8001728:	841a      	strh	r2, [r3, #32]

  /* Configure the I2S with the SPI_InitStruct values */
  tmpreg |= (uint16_t)(SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \
 800172a:	683b      	ldr	r3, [r7, #0]
 800172c:	881a      	ldrh	r2, [r3, #0]
                  (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
 800172e:	683b      	ldr	r3, [r7, #0]
 8001730:	8859      	ldrh	r1, [r3, #2]
 8001732:	683b      	ldr	r3, [r7, #0]
 8001734:	8898      	ldrh	r0, [r3, #4]
                  (uint16_t)I2S_InitStruct->I2S_CPOL))));
 8001736:	683b      	ldr	r3, [r7, #0]
 8001738:	899b      	ldrh	r3, [r3, #12]
  /* Write to SPIx I2SPR register the computed value */
  SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));

  /* Configure the I2S with the SPI_InitStruct values */
  tmpreg |= (uint16_t)(SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \
                  (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
 800173a:	4303      	orrs	r3, r0
 800173c:	b29b      	uxth	r3, r3
 800173e:	430b      	orrs	r3, r1
 8001740:	b29b      	uxth	r3, r3

  /* Write to SPIx I2SPR register the computed value */
  SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));

  /* Configure the I2S with the SPI_InitStruct values */
  tmpreg |= (uint16_t)(SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \
 8001742:	4313      	orrs	r3, r2
 8001744:	b29a      	uxth	r2, r3
 8001746:	233a      	movs	r3, #58	; 0x3a
 8001748:	18fb      	adds	r3, r7, r3
 800174a:	881b      	ldrh	r3, [r3, #0]
 800174c:	4313      	orrs	r3, r2
 800174e:	b29a      	uxth	r2, r3
 8001750:	233a      	movs	r3, #58	; 0x3a
 8001752:	18fb      	adds	r3, r7, r3
 8001754:	2180      	movs	r1, #128	; 0x80
 8001756:	0109      	lsls	r1, r1, #4
 8001758:	430a      	orrs	r2, r1
 800175a:	801a      	strh	r2, [r3, #0]
                  (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
                  (uint16_t)I2S_InitStruct->I2S_CPOL))));

  /* Write to SPIx I2SCFGR */
  SPIx->I2SCFGR = tmpreg;
 800175c:	687b      	ldr	r3, [r7, #4]
 800175e:	223a      	movs	r2, #58	; 0x3a
 8001760:	18ba      	adds	r2, r7, r2
 8001762:	8812      	ldrh	r2, [r2, #0]
 8001764:	839a      	strh	r2, [r3, #28]
}
 8001766:	46bd      	mov	sp, r7
 8001768:	b012      	add	sp, #72	; 0x48
 800176a:	bd80      	pop	{r7, pc}
 800176c:	fffff040 	.word	0xfffff040

08001770 <SPI_Cmd>:
  * @param  NewState: new state of the SPIx peripheral. 
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
{
 8001770:	b580      	push	{r7, lr}
 8001772:	b082      	sub	sp, #8
 8001774:	af00      	add	r7, sp, #0
 8001776:	6078      	str	r0, [r7, #4]
 8001778:	1c0a      	adds	r2, r1, #0
 800177a:	1cfb      	adds	r3, r7, #3
 800177c:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_SPI_ALL_PERIPH(SPIx));
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
 800177e:	1cfb      	adds	r3, r7, #3
 8001780:	781b      	ldrb	r3, [r3, #0]
 8001782:	2b00      	cmp	r3, #0
 8001784:	d008      	beq.n	8001798 <SPI_Cmd+0x28>
  {
    /* Enable the selected SPI peripheral */
    SPIx->CR1 |= SPI_CR1_SPE;
 8001786:	687b      	ldr	r3, [r7, #4]
 8001788:	881b      	ldrh	r3, [r3, #0]
 800178a:	b29b      	uxth	r3, r3
 800178c:	2240      	movs	r2, #64	; 0x40
 800178e:	4313      	orrs	r3, r2
 8001790:	b29a      	uxth	r2, r3
 8001792:	687b      	ldr	r3, [r7, #4]
 8001794:	801a      	strh	r2, [r3, #0]
 8001796:	e007      	b.n	80017a8 <SPI_Cmd+0x38>
  }
  else
  {
    /* Disable the selected SPI peripheral */
    SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);
 8001798:	687b      	ldr	r3, [r7, #4]
 800179a:	881b      	ldrh	r3, [r3, #0]
 800179c:	b29b      	uxth	r3, r3
 800179e:	2240      	movs	r2, #64	; 0x40
 80017a0:	4393      	bics	r3, r2
 80017a2:	b29a      	uxth	r2, r3
 80017a4:	687b      	ldr	r3, [r7, #4]
 80017a6:	801a      	strh	r2, [r3, #0]
  }
}
 80017a8:	46bd      	mov	sp, r7
 80017aa:	b002      	add	sp, #8
 80017ac:	bd80      	pop	{r7, pc}
 80017ae:	46c0      	nop			; (mov r8, r8)

080017b0 <SPI_TIModeCmd>:
  * @param  NewState: new state of the selected SPI TI communication mode.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
{
 80017b0:	b580      	push	{r7, lr}
 80017b2:	b082      	sub	sp, #8
 80017b4:	af00      	add	r7, sp, #0
 80017b6:	6078      	str	r0, [r7, #4]
 80017b8:	1c0a      	adds	r2, r1, #0
 80017ba:	1cfb      	adds	r3, r7, #3
 80017bc:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_SPI_ALL_PERIPH(SPIx));
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
 80017be:	1cfb      	adds	r3, r7, #3
 80017c0:	781b      	ldrb	r3, [r3, #0]
 80017c2:	2b00      	cmp	r3, #0
 80017c4:	d008      	beq.n	80017d8 <SPI_TIModeCmd+0x28>
  {
    /* Enable the TI mode for the selected SPI peripheral */
    SPIx->CR2 |= SPI_CR2_FRF;
 80017c6:	687b      	ldr	r3, [r7, #4]
 80017c8:	889b      	ldrh	r3, [r3, #4]
 80017ca:	b29b      	uxth	r3, r3
 80017cc:	2210      	movs	r2, #16
 80017ce:	4313      	orrs	r3, r2
 80017d0:	b29a      	uxth	r2, r3
 80017d2:	687b      	ldr	r3, [r7, #4]
 80017d4:	809a      	strh	r2, [r3, #4]
 80017d6:	e007      	b.n	80017e8 <SPI_TIModeCmd+0x38>
  }
  else
  {
    /* Disable the TI mode for the selected SPI peripheral */
    SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRF);
 80017d8:	687b      	ldr	r3, [r7, #4]
 80017da:	889b      	ldrh	r3, [r3, #4]
 80017dc:	b29b      	uxth	r3, r3
 80017de:	2210      	movs	r2, #16
 80017e0:	4393      	bics	r3, r2
 80017e2:	b29a      	uxth	r2, r3
 80017e4:	687b      	ldr	r3, [r7, #4]
 80017e6:	809a      	strh	r2, [r3, #4]
  }
}
 80017e8:	46bd      	mov	sp, r7
 80017ea:	b002      	add	sp, #8
 80017ec:	bd80      	pop	{r7, pc}
 80017ee:	46c0      	nop			; (mov r8, r8)

080017f0 <I2S_Cmd>:
  * @param  NewState: new state of the SPIx peripheral. 
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
{
 80017f0:	b580      	push	{r7, lr}
 80017f2:	b082      	sub	sp, #8
 80017f4:	af00      	add	r7, sp, #0
 80017f6:	6078      	str	r0, [r7, #4]
 80017f8:	1c0a      	adds	r2, r1, #0
 80017fa:	1cfb      	adds	r3, r7, #3
 80017fc:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_SPI_1_PERIPH(SPIx));
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  if (NewState != DISABLE)
 80017fe:	1cfb      	adds	r3, r7, #3
 8001800:	781b      	ldrb	r3, [r3, #0]
 8001802:	2b00      	cmp	r3, #0
 8001804:	d009      	beq.n	800181a <I2S_Cmd+0x2a>
  {
    /* Enable the selected SPI peripheral in I2S mode */
    SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE;
 8001806:	687b      	ldr	r3, [r7, #4]
 8001808:	8b9b      	ldrh	r3, [r3, #28]
 800180a:	b29b      	uxth	r3, r3
 800180c:	2280      	movs	r2, #128	; 0x80
 800180e:	00d2      	lsls	r2, r2, #3
 8001810:	4313      	orrs	r3, r2
 8001812:	b29a      	uxth	r2, r3
 8001814:	687b      	ldr	r3, [r7, #4]
 8001816:	839a      	strh	r2, [r3, #28]
 8001818:	e007      	b.n	800182a <I2S_Cmd+0x3a>
  }
  else
  {
    /* Disable the selected SPI peripheral in I2S mode */
    SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE);
 800181a:	687b      	ldr	r3, [r7, #4]
 800181c:	8b9b      	ldrh	r3, [r3, #28]
 800181e:	b29b      	uxth	r3, r3
 8001820:	4a03      	ldr	r2, [pc, #12]	; (8001830 <I2S_Cmd+0x40>)
 8001822:	4013      	ands	r3, r2
 8001824:	b29a      	uxth	r2, r3
 8001826:	687b      	ldr	r3, [r7, #4]
 8001828:	839a      	strh	r2, [r3, #28]
  }
}
 800182a:	46bd      	mov	sp, r7
 800182c:	b002      	add	sp, #8
 800182e:	bd80      	pop	{r7, pc}
 8001830:	fffffbff 	.word	0xfffffbff

08001834 <SPI_DataSizeConfig>:
  *            @arg SPI_DataSize_15b: Set data size to 15 bits
  *            @arg SPI_DataSize_16b: Set data size to 16 bits
  * @retval None
  */
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
{
 8001834:	b580      	push	{r7, lr}
 8001836:	b084      	sub	sp, #16
 8001838:	af00      	add	r7, sp, #0
 800183a:	6078      	str	r0, [r7, #4]
 800183c:	1c0a      	adds	r2, r1, #0
 800183e:	1cbb      	adds	r3, r7, #2
 8001840:	801a      	strh	r2, [r3, #0]
  uint16_t tmpreg = 0;
 8001842:	230e      	movs	r3, #14
 8001844:	18fb      	adds	r3, r7, r3
 8001846:	2200      	movs	r2, #0
 8001848:	801a      	strh	r2, [r3, #0]
  
  /* Check the parameters */
  assert_param(IS_SPI_ALL_PERIPH(SPIx));
  assert_param(IS_SPI_DATA_SIZE(SPI_DataSize));
  /* Read the CR2 register */
  tmpreg = SPIx->CR2;
 800184a:	230e      	movs	r3, #14
 800184c:	18fb      	adds	r3, r7, r3
 800184e:	687a      	ldr	r2, [r7, #4]
 8001850:	8892      	ldrh	r2, [r2, #4]
 8001852:	801a      	strh	r2, [r3, #0]
  /* Clear DS[3:0] bits */
  tmpreg &= (uint16_t)~SPI_CR2_DS;
 8001854:	230e      	movs	r3, #14
 8001856:	18fb      	adds	r3, r7, r3
 8001858:	220e      	movs	r2, #14
 800185a:	18ba      	adds	r2, r7, r2
 800185c:	8812      	ldrh	r2, [r2, #0]
 800185e:	490a      	ldr	r1, [pc, #40]	; (8001888 <SPI_DataSizeConfig+0x54>)
 8001860:	400a      	ands	r2, r1
 8001862:	801a      	strh	r2, [r3, #0]
  /* Set new DS[3:0] bits value */
  tmpreg |= SPI_DataSize;
 8001864:	230e      	movs	r3, #14
 8001866:	18fb      	adds	r3, r7, r3
 8001868:	220e      	movs	r2, #14
 800186a:	18b9      	adds	r1, r7, r2
 800186c:	1cba      	adds	r2, r7, #2
 800186e:	8809      	ldrh	r1, [r1, #0]
 8001870:	8812      	ldrh	r2, [r2, #0]
 8001872:	430a      	orrs	r2, r1
 8001874:	801a      	strh	r2, [r3, #0]
  SPIx->CR2 = tmpreg;
 8001876:	687b      	ldr	r3, [r7, #4]
 8001878:	220e      	movs	r2, #14
 800187a:	18ba      	adds	r2, r7, r2
 800187c:	8812      	ldrh	r2, [r2, #0]
 800187e:	809a      	strh	r2, [r3, #4]
}
 8001880:	46bd      	mov	sp, r7
 8001882:	b004      	add	sp, #16
 8001884:	bd80      	pop	{r7, pc}
 8001886:	46c0      	nop			; (mov r8, r8)
 8001888:	fffff0ff 	.word	0xfffff0ff

0800188c <SPI_RxFIFOThresholdConfig>:
  *            @arg SPI_RxFIFOThreshold_QF: RXNE event is generated if the FIFO 
  *                                         level is greater or equal to 1/4. 
  * @retval None
  */
void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold)
{
 800188c:	b580      	push	{r7, lr}
 800188e:	b082      	sub	sp, #8
 8001890:	af00      	add	r7, sp, #0
 8001892:	6078      	str	r0, [r7, #4]
 8001894:	1c0a      	adds	r2, r1, #0
 8001896:	1cbb      	adds	r3, r7, #2
 8001898:	801a      	strh	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_SPI_ALL_PERIPH(SPIx));
  assert_param(IS_SPI_RX_FIFO_THRESHOLD(SPI_RxFIFOThreshold));

  /* Clear FRXTH bit */
  SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRXTH);
 800189a:	687b      	ldr	r3, [r7, #4]
 800189c:	889b      	ldrh	r3, [r3, #4]
 800189e:	b29b      	uxth	r3, r3
 80018a0:	4a08      	ldr	r2, [pc, #32]	; (80018c4 <SPI_RxFIFOThresholdConfig+0x38>)
 80018a2:	4013      	ands	r3, r2
 80018a4:	b29a      	uxth	r2, r3
 80018a6:	687b      	ldr	r3, [r7, #4]
 80018a8:	809a      	strh	r2, [r3, #4]

  /* Set new FRXTH bit value */
  SPIx->CR2 |= SPI_RxFIFOThreshold;
 80018aa:	687b      	ldr	r3, [r7, #4]
 80018ac:	889b      	ldrh	r3, [r3, #4]
 80018ae:	b29a      	uxth	r2, r3
 80018b0:	1cbb      	adds	r3, r7, #2
 80018b2:	881b      	ldrh	r3, [r3, #0]
 80018b4:	4313      	orrs	r3, r2
 80018b6:	b29a      	uxth	r2, r3
 80018b8:	687b      	ldr	r3, [r7, #4]
 80018ba:	809a      	strh	r2, [r3, #4]
}
 80018bc:	46bd      	mov	sp, r7
 80018be:	b002      	add	sp, #8
 80018c0:	bd80      	pop	{r7, pc}
 80018c2:	46c0      	nop			; (mov r8, r8)
 80018c4:	ffffefff 	.word	0xffffefff

080018c8 <SPI_BiDirectionalLineConfig>:
  *            @arg SPI_Direction_Tx: Selects Tx transmission direction
  *            @arg SPI_Direction_Rx: Selects Rx receive direction
  * @retval None
  */
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
{
 80018c8:	b580      	push	{r7, lr}
 80018ca:	b082      	sub	sp, #8
 80018cc:	af00      	add	r7, sp, #0
 80018ce:	6078      	str	r0, [r7, #4]
 80018d0:	1c0a      	adds	r2, r1, #0
 80018d2:	1cbb      	adds	r3, r7, #2
 80018d4:	801a      	strh	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_SPI_ALL_PERIPH(SPIx));
  assert_param(IS_SPI_DIRECTION(SPI_Direction));
  if (SPI_Direction == SPI_Direction_Tx)
 80018d6:	1cbb      	adds	r3, r7, #2
 80018d8:	881a      	ldrh	r2, [r3, #0]
 80018da:	2380      	movs	r3, #128	; 0x80
 80018dc:	01db      	lsls	r3, r3, #7
 80018de:	429a      	cmp	r2, r3
 80018e0:	d109      	bne.n	80018f6 <SPI_BiDirectionalLineConfig+0x2e>
  {
    /* Set the Tx only mode */
    SPIx->CR1 |= SPI_Direction_Tx;
 80018e2:	687b      	ldr	r3, [r7, #4]
 80018e4:	881b      	ldrh	r3, [r3, #0]
 80018e6:	b29b      	uxth	r3, r3
 80018e8:	2280      	movs	r2, #128	; 0x80
 80018ea:	01d2      	lsls	r2, r2, #7
 80018ec:	4313      	orrs	r3, r2
 80018ee:	b29a      	uxth	r2, r3
 80018f0:	687b      	ldr	r3, [r7, #4]
 80018f2:	801a      	strh	r2, [r3, #0]
 80018f4:	e007      	b.n	8001906 <SPI_BiDirectionalLineConfig+0x3e>
  }
  else
  {
    /* Set the Rx only mode */
    SPIx->CR1 &= SPI_Direction_Rx;
 80018f6:	687b      	ldr	r3, [r7, #4]
 80018f8:	881b      	ldrh	r3, [r3, #0]
 80018fa:	b29b      	uxth	r3, r3
 80018fc:	4a03      	ldr	r2, [pc, #12]	; (800190c <SPI_BiDirectionalLineConfig+0x44>)
 80018fe:	4013      	ands	r3, r2
 8001900:	b29a      	uxth	r2, r3
 8001902:	687b      	ldr	r3, [r7, #4]
 8001904:	801a      	strh	r2, [r3, #0]
  }
}
 8001906:	46bd      	mov	sp, r7
 8001908:	b002      	add	sp, #8
 800190a:	bd80      	pop	{r7, pc}
 800190c:	ffffbfff 	.word	0xffffbfff

08001910 <SPI_NSSInternalSoftwareConfig>:
  *            @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
  *            @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
  * @retval None
  */
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
{
 8001910:	b580      	push	{r7, lr}
 8001912:	b082      	sub	sp, #8
 8001914:	af00      	add	r7, sp, #0
 8001916:	6078      	str	r0, [r7, #4]
 8001918:	1c0a      	adds	r2, r1, #0
 800191a:	1cbb      	adds	r3, r7, #2
 800191c:	801a      	strh	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_SPI_ALL_PERIPH(SPIx));
  assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));

  if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
 800191e:	1cbb      	adds	r3, r7, #2
 8001920:	881b      	ldrh	r3, [r3, #0]
 8001922:	4a0c      	ldr	r2, [pc, #48]	; (8001954 <SPI_NSSInternalSoftwareConfig+0x44>)
 8001924:	4293      	cmp	r3, r2
 8001926:	d009      	beq.n	800193c <SPI_NSSInternalSoftwareConfig+0x2c>
  {
    /* Set NSS pin internally by software */
    SPIx->CR1 |= SPI_NSSInternalSoft_Set;
 8001928:	687b      	ldr	r3, [r7, #4]
 800192a:	881b      	ldrh	r3, [r3, #0]
 800192c:	b29b      	uxth	r3, r3
 800192e:	2280      	movs	r2, #128	; 0x80
 8001930:	0052      	lsls	r2, r2, #1
 8001932:	4313      	orrs	r3, r2
 8001934:	b29a      	uxth	r2, r3
 8001936:	687b      	ldr	r3, [r7, #4]
 8001938:	801a      	strh	r2, [r3, #0]
 800193a:	e007      	b.n	800194c <SPI_NSSInternalSoftwareConfig+0x3c>
  }
  else
  {
    /* Reset NSS pin internally by software */
    SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
 800193c:	687b      	ldr	r3, [r7, #4]
 800193e:	881b      	ldrh	r3, [r3, #0]
 8001940:	b29b      	uxth	r3, r3
 8001942:	4a05      	ldr	r2, [pc, #20]	; (8001958 <SPI_NSSInternalSoftwareConfig+0x48>)
 8001944:	4013      	ands	r3, r2
 8001946:	b29a      	uxth	r2, r3
 8001948:	687b      	ldr	r3, [r7, #4]
 800194a:	801a      	strh	r2, [r3, #0]
  }
}
 800194c:	46bd      	mov	sp, r7
 800194e:	b002      	add	sp, #8
 8001950:	bd80      	pop	{r7, pc}
 8001952:	46c0      	nop			; (mov r8, r8)
 8001954:	0000feff 	.word	0x0000feff
 8001958:	fffffeff 	.word	0xfffffeff

0800195c <SPI_SSOutputCmd>:
  * @param  NewState: new state of the SPIx SS output. 
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
{
 800195c:	b580      	push	{r7, lr}
 800195e:	b082      	sub	sp, #8
 8001960:	af00      	add	r7, sp, #0
 8001962:	6078      	str	r0, [r7, #4]
 8001964:	1c0a      	adds	r2, r1, #0
 8001966:	1cfb      	adds	r3, r7, #3
 8001968:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_SPI_ALL_PERIPH(SPIx));
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  if (NewState != DISABLE)
 800196a:	1cfb      	adds	r3, r7, #3
 800196c:	781b      	ldrb	r3, [r3, #0]
 800196e:	2b00      	cmp	r3, #0
 8001970:	d008      	beq.n	8001984 <SPI_SSOutputCmd+0x28>
  {
    /* Enable the selected SPI SS output */
    SPIx->CR2 |= SPI_CR2_SSOE;
 8001972:	687b      	ldr	r3, [r7, #4]
 8001974:	889b      	ldrh	r3, [r3, #4]
 8001976:	b29b      	uxth	r3, r3
 8001978:	2204      	movs	r2, #4
 800197a:	4313      	orrs	r3, r2
 800197c:	b29a      	uxth	r2, r3
 800197e:	687b      	ldr	r3, [r7, #4]
 8001980:	809a      	strh	r2, [r3, #4]
 8001982:	e007      	b.n	8001994 <SPI_SSOutputCmd+0x38>
  }
  else
  {
    /* Disable the selected SPI SS output */
    SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);
 8001984:	687b      	ldr	r3, [r7, #4]
 8001986:	889b      	ldrh	r3, [r3, #4]
 8001988:	b29b      	uxth	r3, r3
 800198a:	2204      	movs	r2, #4
 800198c:	4393      	bics	r3, r2
 800198e:	b29a      	uxth	r2, r3
 8001990:	687b      	ldr	r3, [r7, #4]
 8001992:	809a      	strh	r2, [r3, #4]
  }
}
 8001994:	46bd      	mov	sp, r7
 8001996:	b002      	add	sp, #8
 8001998:	bd80      	pop	{r7, pc}
 800199a:	46c0      	nop			; (mov r8, r8)

0800199c <SPI_NSSPulseModeCmd>:
  * @param  NewState: new state of the NSS pulse management mode.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
{
 800199c:	b580      	push	{r7, lr}
 800199e:	b082      	sub	sp, #8
 80019a0:	af00      	add	r7, sp, #0
 80019a2:	6078      	str	r0, [r7, #4]
 80019a4:	1c0a      	adds	r2, r1, #0
 80019a6:	1cfb      	adds	r3, r7, #3
 80019a8:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_SPI_ALL_PERIPH(SPIx));
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
 80019aa:	1cfb      	adds	r3, r7, #3
 80019ac:	781b      	ldrb	r3, [r3, #0]
 80019ae:	2b00      	cmp	r3, #0
 80019b0:	d008      	beq.n	80019c4 <SPI_NSSPulseModeCmd+0x28>
  {
    /* Enable the NSS pulse management mode */
    SPIx->CR2 |= SPI_CR2_NSSP;
 80019b2:	687b      	ldr	r3, [r7, #4]
 80019b4:	889b      	ldrh	r3, [r3, #4]
 80019b6:	b29b      	uxth	r3, r3
 80019b8:	2208      	movs	r2, #8
 80019ba:	4313      	orrs	r3, r2
 80019bc:	b29a      	uxth	r2, r3
 80019be:	687b      	ldr	r3, [r7, #4]
 80019c0:	809a      	strh	r2, [r3, #4]
 80019c2:	e007      	b.n	80019d4 <SPI_NSSPulseModeCmd+0x38>
  }
  else
  {
    /* Disable the NSS pulse management mode */
    SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_NSSP);    
 80019c4:	687b      	ldr	r3, [r7, #4]
 80019c6:	889b      	ldrh	r3, [r3, #4]
 80019c8:	b29b      	uxth	r3, r3
 80019ca:	2208      	movs	r2, #8
 80019cc:	4393      	bics	r3, r2
 80019ce:	b29a      	uxth	r2, r3
 80019d0:	687b      	ldr	r3, [r7, #4]
 80019d2:	809a      	strh	r2, [r3, #4]
  }
}
 80019d4:	46bd      	mov	sp, r7
 80019d6:	b002      	add	sp, #8
 80019d8:	bd80      	pop	{r7, pc}
 80019da:	46c0      	nop			; (mov r8, r8)

080019dc <SPI_SendData8>:
  * @note   SPI2 is not available for STM32F031 devices.
  * @param  Data: Data to be transmitted.
  * @retval None
  */
void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data)
{
 80019dc:	b580      	push	{r7, lr}
 80019de:	b084      	sub	sp, #16
 80019e0:	af00      	add	r7, sp, #0
 80019e2:	6078      	str	r0, [r7, #4]
 80019e4:	1c0a      	adds	r2, r1, #0
 80019e6:	1cfb      	adds	r3, r7, #3
 80019e8:	701a      	strb	r2, [r3, #0]
  uint32_t spixbase = 0x00;
 80019ea:	2300      	movs	r3, #0
 80019ec:	60fb      	str	r3, [r7, #12]

  /* Check the parameters */
  assert_param(IS_SPI_ALL_PERIPH(SPIx));

  spixbase = (uint32_t)SPIx; 
 80019ee:	687b      	ldr	r3, [r7, #4]
 80019f0:	60fb      	str	r3, [r7, #12]
  spixbase += 0x0C;
 80019f2:	68fb      	ldr	r3, [r7, #12]
 80019f4:	330c      	adds	r3, #12
 80019f6:	60fb      	str	r3, [r7, #12]
  
  *(__IO uint8_t *) spixbase = Data;
 80019f8:	68fb      	ldr	r3, [r7, #12]
 80019fa:	1cfa      	adds	r2, r7, #3
 80019fc:	7812      	ldrb	r2, [r2, #0]
 80019fe:	701a      	strb	r2, [r3, #0]
}
 8001a00:	46bd      	mov	sp, r7
 8001a02:	b004      	add	sp, #16
 8001a04:	bd80      	pop	{r7, pc}
 8001a06:	46c0      	nop			; (mov r8, r8)

08001a08 <SPI_I2S_SendData16>:
  * @note   SPI2 is not available for STM32F031 devices. 
  * @param  Data: Data to be transmitted.
  * @retval None
  */
void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data)
{
 8001a08:	b580      	push	{r7, lr}
 8001a0a:	b082      	sub	sp, #8
 8001a0c:	af00      	add	r7, sp, #0
 8001a0e:	6078      	str	r0, [r7, #4]
 8001a10:	1c0a      	adds	r2, r1, #0
 8001a12:	1cbb      	adds	r3, r7, #2
 8001a14:	801a      	strh	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_SPI_ALL_PERIPH(SPIx));
  
  SPIx->DR = (uint16_t)Data;
 8001a16:	687b      	ldr	r3, [r7, #4]
 8001a18:	1cba      	adds	r2, r7, #2
 8001a1a:	8812      	ldrh	r2, [r2, #0]
 8001a1c:	819a      	strh	r2, [r3, #12]
}
 8001a1e:	46bd      	mov	sp, r7
 8001a20:	b002      	add	sp, #8
 8001a22:	bd80      	pop	{r7, pc}

08001a24 <SPI_ReceiveData8>:
  * @param  SPIx: where x can be 1 or 2 in SPI mode to select the SPI peripheral. 
  * @note   SPI2 is not available for STM32F031 devices.
  * @retval The value of the received data.
  */
uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx)
{
 8001a24:	b580      	push	{r7, lr}
 8001a26:	b084      	sub	sp, #16
 8001a28:	af00      	add	r7, sp, #0
 8001a2a:	6078      	str	r0, [r7, #4]
  uint32_t spixbase = 0x00;
 8001a2c:	2300      	movs	r3, #0
 8001a2e:	60fb      	str	r3, [r7, #12]
  
  spixbase = (uint32_t)SPIx; 
 8001a30:	687b      	ldr	r3, [r7, #4]
 8001a32:	60fb      	str	r3, [r7, #12]
  spixbase += 0x0C;
 8001a34:	68fb      	ldr	r3, [r7, #12]
 8001a36:	330c      	adds	r3, #12
 8001a38:	60fb      	str	r3, [r7, #12]
  
  return *(__IO uint8_t *) spixbase;
 8001a3a:	68fb      	ldr	r3, [r7, #12]
 8001a3c:	781b      	ldrb	r3, [r3, #0]
 8001a3e:	b2db      	uxtb	r3, r3
}
 8001a40:	1c18      	adds	r0, r3, #0
 8001a42:	46bd      	mov	sp, r7
 8001a44:	b004      	add	sp, #16
 8001a46:	bd80      	pop	{r7, pc}

08001a48 <SPI_I2S_ReceiveData16>:
  * @note   SPI2 is not available for STM32F031 devices.
  *         the SPI peripheral.  
  * @retval The value of the received data.
  */
uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx)
{
 8001a48:	b580      	push	{r7, lr}
 8001a4a:	b082      	sub	sp, #8
 8001a4c:	af00      	add	r7, sp, #0
 8001a4e:	6078      	str	r0, [r7, #4]
  return SPIx->DR;
 8001a50:	687b      	ldr	r3, [r7, #4]
 8001a52:	899b      	ldrh	r3, [r3, #12]
 8001a54:	b29b      	uxth	r3, r3
}
 8001a56:	1c18      	adds	r0, r3, #0
 8001a58:	46bd      	mov	sp, r7
 8001a5a:	b002      	add	sp, #8
 8001a5c:	bd80      	pop	{r7, pc}
 8001a5e:	46c0      	nop			; (mov r8, r8)

08001a60 <SPI_CRCLengthConfig>:
  *            @arg SPI_CRCLength_8b: Set CRC Calculation to 8 bits
  *            @arg SPI_CRCLength_16b: Set CRC Calculation to 16 bits
  * @retval None
  */
void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength)
{
 8001a60:	b580      	push	{r7, lr}
 8001a62:	b082      	sub	sp, #8
 8001a64:	af00      	add	r7, sp, #0
 8001a66:	6078      	str	r0, [r7, #4]
 8001a68:	1c0a      	adds	r2, r1, #0
 8001a6a:	1cbb      	adds	r3, r7, #2
 8001a6c:	801a      	strh	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_SPI_ALL_PERIPH(SPIx));
  assert_param(IS_SPI_CRC_LENGTH(SPI_CRCLength));

  /* Clear CRCL bit */
  SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCL);
 8001a6e:	687b      	ldr	r3, [r7, #4]
 8001a70:	881b      	ldrh	r3, [r3, #0]
 8001a72:	b29b      	uxth	r3, r3
 8001a74:	4a08      	ldr	r2, [pc, #32]	; (8001a98 <SPI_CRCLengthConfig+0x38>)
 8001a76:	4013      	ands	r3, r2
 8001a78:	b29a      	uxth	r2, r3
 8001a7a:	687b      	ldr	r3, [r7, #4]
 8001a7c:	801a      	strh	r2, [r3, #0]

  /* Set new CRCL bit value */
  SPIx->CR1 |= SPI_CRCLength;
 8001a7e:	687b      	ldr	r3, [r7, #4]
 8001a80:	881b      	ldrh	r3, [r3, #0]
 8001a82:	b29a      	uxth	r2, r3
 8001a84:	1cbb      	adds	r3, r7, #2
 8001a86:	881b      	ldrh	r3, [r3, #0]
 8001a88:	4313      	orrs	r3, r2
 8001a8a:	b29a      	uxth	r2, r3
 8001a8c:	687b      	ldr	r3, [r7, #4]
 8001a8e:	801a      	strh	r2, [r3, #0]
}
 8001a90:	46bd      	mov	sp, r7
 8001a92:	b002      	add	sp, #8
 8001a94:	bd80      	pop	{r7, pc}
 8001a96:	46c0      	nop			; (mov r8, r8)
 8001a98:	fffff7ff 	.word	0xfffff7ff

08001a9c <SPI_CalculateCRC>:
  * @param  NewState: new state of the SPIx CRC value calculation.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
{
 8001a9c:	b580      	push	{r7, lr}
 8001a9e:	b082      	sub	sp, #8
 8001aa0:	af00      	add	r7, sp, #0
 8001aa2:	6078      	str	r0, [r7, #4]
 8001aa4:	1c0a      	adds	r2, r1, #0
 8001aa6:	1cfb      	adds	r3, r7, #3
 8001aa8:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_SPI_ALL_PERIPH(SPIx));
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
 8001aaa:	1cfb      	adds	r3, r7, #3
 8001aac:	781b      	ldrb	r3, [r3, #0]
 8001aae:	2b00      	cmp	r3, #0
 8001ab0:	d009      	beq.n	8001ac6 <SPI_CalculateCRC+0x2a>
  {
    /* Enable the selected SPI CRC calculation */
    SPIx->CR1 |= SPI_CR1_CRCEN;
 8001ab2:	687b      	ldr	r3, [r7, #4]
 8001ab4:	881b      	ldrh	r3, [r3, #0]
 8001ab6:	b29b      	uxth	r3, r3
 8001ab8:	2280      	movs	r2, #128	; 0x80
 8001aba:	0192      	lsls	r2, r2, #6
 8001abc:	4313      	orrs	r3, r2
 8001abe:	b29a      	uxth	r2, r3
 8001ac0:	687b      	ldr	r3, [r7, #4]
 8001ac2:	801a      	strh	r2, [r3, #0]
 8001ac4:	e007      	b.n	8001ad6 <SPI_CalculateCRC+0x3a>
  }
  else
  {
    /* Disable the selected SPI CRC calculation */
    SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);
 8001ac6:	687b      	ldr	r3, [r7, #4]
 8001ac8:	881b      	ldrh	r3, [r3, #0]
 8001aca:	b29b      	uxth	r3, r3
 8001acc:	4a03      	ldr	r2, [pc, #12]	; (8001adc <SPI_CalculateCRC+0x40>)
 8001ace:	4013      	ands	r3, r2
 8001ad0:	b29a      	uxth	r2, r3
 8001ad2:	687b      	ldr	r3, [r7, #4]
 8001ad4:	801a      	strh	r2, [r3, #0]
  }
}
 8001ad6:	46bd      	mov	sp, r7
 8001ad8:	b002      	add	sp, #8
 8001ada:	bd80      	pop	{r7, pc}
 8001adc:	ffffdfff 	.word	0xffffdfff

08001ae0 <SPI_TransmitCRC>:
  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
  * @note   SPI2 is not available for STM32F031 devices. 
  * @retval None
  */
void SPI_TransmitCRC(SPI_TypeDef* SPIx)
{
 8001ae0:	b580      	push	{r7, lr}
 8001ae2:	b082      	sub	sp, #8
 8001ae4:	af00      	add	r7, sp, #0
 8001ae6:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_SPI_ALL_PERIPH(SPIx));

  /* Enable the selected SPI CRC transmission */
  SPIx->CR1 |= SPI_CR1_CRCNEXT;
 8001ae8:	687b      	ldr	r3, [r7, #4]
 8001aea:	881b      	ldrh	r3, [r3, #0]
 8001aec:	b29b      	uxth	r3, r3
 8001aee:	2280      	movs	r2, #128	; 0x80
 8001af0:	0152      	lsls	r2, r2, #5
 8001af2:	4313      	orrs	r3, r2
 8001af4:	b29a      	uxth	r2, r3
 8001af6:	687b      	ldr	r3, [r7, #4]
 8001af8:	801a      	strh	r2, [r3, #0]
}
 8001afa:	46bd      	mov	sp, r7
 8001afc:	b002      	add	sp, #8
 8001afe:	bd80      	pop	{r7, pc}

08001b00 <SPI_GetCRC>:
  *            @arg SPI_CRC_Tx: Selects Tx CRC register
  *            @arg SPI_CRC_Rx: Selects Rx CRC register
  * @retval The selected CRC register value..
  */
uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
{
 8001b00:	b580      	push	{r7, lr}
 8001b02:	b084      	sub	sp, #16
 8001b04:	af00      	add	r7, sp, #0
 8001b06:	6078      	str	r0, [r7, #4]
 8001b08:	1c0a      	adds	r2, r1, #0
 8001b0a:	1cfb      	adds	r3, r7, #3
 8001b0c:	701a      	strb	r2, [r3, #0]
  uint16_t crcreg = 0;
 8001b0e:	230e      	movs	r3, #14
 8001b10:	18fb      	adds	r3, r7, r3
 8001b12:	2200      	movs	r2, #0
 8001b14:	801a      	strh	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_SPI_ALL_PERIPH(SPIx));
  assert_param(IS_SPI_CRC(SPI_CRC));

  if (SPI_CRC != SPI_CRC_Rx)
 8001b16:	1cfb      	adds	r3, r7, #3
 8001b18:	781b      	ldrb	r3, [r3, #0]
 8001b1a:	2b01      	cmp	r3, #1
 8001b1c:	d005      	beq.n	8001b2a <SPI_GetCRC+0x2a>
  {
    /* Get the Tx CRC register */
    crcreg = SPIx->TXCRCR;
 8001b1e:	230e      	movs	r3, #14
 8001b20:	18fb      	adds	r3, r7, r3
 8001b22:	687a      	ldr	r2, [r7, #4]
 8001b24:	8b12      	ldrh	r2, [r2, #24]
 8001b26:	801a      	strh	r2, [r3, #0]
 8001b28:	e004      	b.n	8001b34 <SPI_GetCRC+0x34>
  }
  else
  {
    /* Get the Rx CRC register */
    crcreg = SPIx->RXCRCR;
 8001b2a:	230e      	movs	r3, #14
 8001b2c:	18fb      	adds	r3, r7, r3
 8001b2e:	687a      	ldr	r2, [r7, #4]
 8001b30:	8a92      	ldrh	r2, [r2, #20]
 8001b32:	801a      	strh	r2, [r3, #0]
  }
  /* Return the selected CRC register */
  return crcreg;
 8001b34:	230e      	movs	r3, #14
 8001b36:	18fb      	adds	r3, r7, r3
 8001b38:	881b      	ldrh	r3, [r3, #0]
}
 8001b3a:	1c18      	adds	r0, r3, #0
 8001b3c:	46bd      	mov	sp, r7
 8001b3e:	b004      	add	sp, #16
 8001b40:	bd80      	pop	{r7, pc}
 8001b42:	46c0      	nop			; (mov r8, r8)

08001b44 <SPI_GetCRCPolynomial>:
  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
  * @note   SPI2 is not available for STM32F031 devices. 
  * @retval The CRC Polynomial register value.
  */
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
{
 8001b44:	b580      	push	{r7, lr}
 8001b46:	b082      	sub	sp, #8
 8001b48:	af00      	add	r7, sp, #0
 8001b4a:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_SPI_ALL_PERIPH(SPIx));

  /* Return the CRC polynomial register */
  return SPIx->CRCPR;
 8001b4c:	687b      	ldr	r3, [r7, #4]
 8001b4e:	8a1b      	ldrh	r3, [r3, #16]
 8001b50:	b29b      	uxth	r3, r3
}
 8001b52:	1c18      	adds	r0, r3, #0
 8001b54:	46bd      	mov	sp, r7
 8001b56:	b002      	add	sp, #8
 8001b58:	bd80      	pop	{r7, pc}
 8001b5a:	46c0      	nop			; (mov r8, r8)

08001b5c <SPI_I2S_DMACmd>:
  * @param  NewState: new state of the selected SPI DMA transfer request.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
{
 8001b5c:	b580      	push	{r7, lr}
 8001b5e:	b082      	sub	sp, #8
 8001b60:	af00      	add	r7, sp, #0
 8001b62:	6078      	str	r0, [r7, #4]
 8001b64:	1c08      	adds	r0, r1, #0
 8001b66:	1c11      	adds	r1, r2, #0
 8001b68:	1cbb      	adds	r3, r7, #2
 8001b6a:	1c02      	adds	r2, r0, #0
 8001b6c:	801a      	strh	r2, [r3, #0]
 8001b6e:	1c7b      	adds	r3, r7, #1
 8001b70:	1c0a      	adds	r2, r1, #0
 8001b72:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_SPI_ALL_PERIPH(SPIx));
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  assert_param(IS_SPI_I2S_DMA_REQ(SPI_I2S_DMAReq));

  if (NewState != DISABLE)
 8001b74:	1c7b      	adds	r3, r7, #1
 8001b76:	781b      	ldrb	r3, [r3, #0]
 8001b78:	2b00      	cmp	r3, #0
 8001b7a:	d009      	beq.n	8001b90 <SPI_I2S_DMACmd+0x34>
  {
    /* Enable the selected SPI DMA requests */
    SPIx->CR2 |= SPI_I2S_DMAReq;
 8001b7c:	687b      	ldr	r3, [r7, #4]
 8001b7e:	889b      	ldrh	r3, [r3, #4]
 8001b80:	b29a      	uxth	r2, r3
 8001b82:	1cbb      	adds	r3, r7, #2
 8001b84:	881b      	ldrh	r3, [r3, #0]
 8001b86:	4313      	orrs	r3, r2
 8001b88:	b29a      	uxth	r2, r3
 8001b8a:	687b      	ldr	r3, [r7, #4]
 8001b8c:	809a      	strh	r2, [r3, #4]
 8001b8e:	e00a      	b.n	8001ba6 <SPI_I2S_DMACmd+0x4a>
  }
  else
  {
    /* Disable the selected SPI DMA requests */
    SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
 8001b90:	687b      	ldr	r3, [r7, #4]
 8001b92:	889b      	ldrh	r3, [r3, #4]
 8001b94:	b29b      	uxth	r3, r3
 8001b96:	1cba      	adds	r2, r7, #2
 8001b98:	8812      	ldrh	r2, [r2, #0]
 8001b9a:	43d2      	mvns	r2, r2
 8001b9c:	b292      	uxth	r2, r2
 8001b9e:	4013      	ands	r3, r2
 8001ba0:	b29a      	uxth	r2, r3
 8001ba2:	687b      	ldr	r3, [r7, #4]
 8001ba4:	809a      	strh	r2, [r3, #4]
  }
}
 8001ba6:	46bd      	mov	sp, r7
 8001ba8:	b002      	add	sp, #8
 8001baa:	bd80      	pop	{r7, pc}

08001bac <SPI_LastDMATransferCmd>:
  *            @arg SPI_LastDMATransfer_TxOddRxOdd: Number of data for transmission Odd
  *                                                 and number of data for reception Odd.
  * @retval None
  */
void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer)
{
 8001bac:	b580      	push	{r7, lr}
 8001bae:	b082      	sub	sp, #8
 8001bb0:	af00      	add	r7, sp, #0
 8001bb2:	6078      	str	r0, [r7, #4]
 8001bb4:	1c0a      	adds	r2, r1, #0
 8001bb6:	1cbb      	adds	r3, r7, #2
 8001bb8:	801a      	strh	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_SPI_ALL_PERIPH(SPIx));
  assert_param(IS_SPI_LAST_DMA_TRANSFER(SPI_LastDMATransfer));

  /* Clear LDMA_TX and LDMA_RX bits */
  SPIx->CR2 &= CR2_LDMA_MASK;
 8001bba:	687b      	ldr	r3, [r7, #4]
 8001bbc:	889b      	ldrh	r3, [r3, #4]
 8001bbe:	b29b      	uxth	r3, r3
 8001bc0:	4a08      	ldr	r2, [pc, #32]	; (8001be4 <SPI_LastDMATransferCmd+0x38>)
 8001bc2:	4013      	ands	r3, r2
 8001bc4:	b29a      	uxth	r2, r3
 8001bc6:	687b      	ldr	r3, [r7, #4]
 8001bc8:	809a      	strh	r2, [r3, #4]

  /* Set new LDMA_TX and LDMA_RX bits value */
  SPIx->CR2 |= SPI_LastDMATransfer; 
 8001bca:	687b      	ldr	r3, [r7, #4]
 8001bcc:	889b      	ldrh	r3, [r3, #4]
 8001bce:	b29a      	uxth	r2, r3
 8001bd0:	1cbb      	adds	r3, r7, #2
 8001bd2:	881b      	ldrh	r3, [r3, #0]
 8001bd4:	4313      	orrs	r3, r2
 8001bd6:	b29a      	uxth	r2, r3
 8001bd8:	687b      	ldr	r3, [r7, #4]
 8001bda:	809a      	strh	r2, [r3, #4]
}
 8001bdc:	46bd      	mov	sp, r7
 8001bde:	b002      	add	sp, #8
 8001be0:	bd80      	pop	{r7, pc}
 8001be2:	46c0      	nop			; (mov r8, r8)
 8001be4:	ffff9fff 	.word	0xffff9fff

08001be8 <SPI_I2S_ITConfig>:
  * @param  NewState: new state of the specified SPI interrupt.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
{
 8001be8:	b580      	push	{r7, lr}
 8001bea:	b084      	sub	sp, #16
 8001bec:	af00      	add	r7, sp, #0
 8001bee:	6078      	str	r0, [r7, #4]
 8001bf0:	1c08      	adds	r0, r1, #0
 8001bf2:	1c11      	adds	r1, r2, #0
 8001bf4:	1cfb      	adds	r3, r7, #3
 8001bf6:	1c02      	adds	r2, r0, #0
 8001bf8:	701a      	strb	r2, [r3, #0]
 8001bfa:	1cbb      	adds	r3, r7, #2
 8001bfc:	1c0a      	adds	r2, r1, #0
 8001bfe:	701a      	strb	r2, [r3, #0]
  uint16_t itpos = 0, itmask = 0 ;
 8001c00:	230e      	movs	r3, #14
 8001c02:	18fb      	adds	r3, r7, r3
 8001c04:	2200      	movs	r2, #0
 8001c06:	801a      	strh	r2, [r3, #0]
 8001c08:	230c      	movs	r3, #12
 8001c0a:	18fb      	adds	r3, r7, r3
 8001c0c:	2200      	movs	r2, #0
 8001c0e:	801a      	strh	r2, [r3, #0]
  assert_param(IS_SPI_ALL_PERIPH(SPIx));
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));

  /* Get the SPI IT index */
  itpos = SPI_I2S_IT >> 4;
 8001c10:	1cfb      	adds	r3, r7, #3
 8001c12:	781b      	ldrb	r3, [r3, #0]
 8001c14:	091b      	lsrs	r3, r3, #4
 8001c16:	b2da      	uxtb	r2, r3
 8001c18:	230e      	movs	r3, #14
 8001c1a:	18fb      	adds	r3, r7, r3
 8001c1c:	801a      	strh	r2, [r3, #0]

  /* Set the IT mask */
  itmask = (uint16_t)1 << (uint16_t)itpos;
 8001c1e:	230e      	movs	r3, #14
 8001c20:	18fb      	adds	r3, r7, r3
 8001c22:	881b      	ldrh	r3, [r3, #0]
 8001c24:	2201      	movs	r2, #1
 8001c26:	409a      	lsls	r2, r3
 8001c28:	230c      	movs	r3, #12
 8001c2a:	18fb      	adds	r3, r7, r3
 8001c2c:	801a      	strh	r2, [r3, #0]

  if (NewState != DISABLE)
 8001c2e:	1cbb      	adds	r3, r7, #2
 8001c30:	781b      	ldrb	r3, [r3, #0]
 8001c32:	2b00      	cmp	r3, #0
 8001c34:	d00a      	beq.n	8001c4c <SPI_I2S_ITConfig+0x64>
  {
    /* Enable the selected SPI interrupt */
    SPIx->CR2 |= itmask;
 8001c36:	687b      	ldr	r3, [r7, #4]
 8001c38:	889b      	ldrh	r3, [r3, #4]
 8001c3a:	b29a      	uxth	r2, r3
 8001c3c:	230c      	movs	r3, #12
 8001c3e:	18fb      	adds	r3, r7, r3
 8001c40:	881b      	ldrh	r3, [r3, #0]
 8001c42:	4313      	orrs	r3, r2
 8001c44:	b29a      	uxth	r2, r3
 8001c46:	687b      	ldr	r3, [r7, #4]
 8001c48:	809a      	strh	r2, [r3, #4]
 8001c4a:	e00b      	b.n	8001c64 <SPI_I2S_ITConfig+0x7c>
  }
  else
  {
    /* Disable the selected SPI interrupt */
    SPIx->CR2 &= (uint16_t)~itmask;
 8001c4c:	687b      	ldr	r3, [r7, #4]
 8001c4e:	889b      	ldrh	r3, [r3, #4]
 8001c50:	b29b      	uxth	r3, r3
 8001c52:	220c      	movs	r2, #12
 8001c54:	18ba      	adds	r2, r7, r2
 8001c56:	8812      	ldrh	r2, [r2, #0]
 8001c58:	43d2      	mvns	r2, r2
 8001c5a:	b292      	uxth	r2, r2
 8001c5c:	4013      	ands	r3, r2
 8001c5e:	b29a      	uxth	r2, r3
 8001c60:	687b      	ldr	r3, [r7, #4]
 8001c62:	809a      	strh	r2, [r3, #4]
  }
}
 8001c64:	46bd      	mov	sp, r7
 8001c66:	b004      	add	sp, #16
 8001c68:	bd80      	pop	{r7, pc}
 8001c6a:	46c0      	nop			; (mov r8, r8)

08001c6c <SPI_GetTransmissionFIFOStatus>:
  *          - SPI_TransmissionFIFOStatus_1QuarterFull: if more than 1 quarter-full.
  *          - SPI_TransmissionFIFOStatus_HalfFull: if more than 1 half-full.
  *          - SPI_TransmissionFIFOStatus_Full: when FIFO is full.
  */
uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx)
{
 8001c6c:	b580      	push	{r7, lr}
 8001c6e:	b082      	sub	sp, #8
 8001c70:	af00      	add	r7, sp, #0
 8001c72:	6078      	str	r0, [r7, #4]
  /* Get the SPIx Transmission FIFO level bits */
  return (uint16_t)((SPIx->SR & SPI_SR_FTLVL));
 8001c74:	687b      	ldr	r3, [r7, #4]
 8001c76:	891b      	ldrh	r3, [r3, #8]
 8001c78:	b29a      	uxth	r2, r3
 8001c7a:	23c0      	movs	r3, #192	; 0xc0
 8001c7c:	015b      	lsls	r3, r3, #5
 8001c7e:	4013      	ands	r3, r2
 8001c80:	b29b      	uxth	r3, r3
}
 8001c82:	1c18      	adds	r0, r3, #0
 8001c84:	46bd      	mov	sp, r7
 8001c86:	b002      	add	sp, #8
 8001c88:	bd80      	pop	{r7, pc}
 8001c8a:	46c0      	nop			; (mov r8, r8)

08001c8c <SPI_GetReceptionFIFOStatus>:
  *          - SPI_ReceptionFIFOStatus_1QuarterFull: if more than 1 quarter-full.
  *          - SPI_ReceptionFIFOStatus_HalfFull: if more than 1 half-full.
  *          - SPI_ReceptionFIFOStatus_Full: when FIFO is full.
  */
uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx)
{
 8001c8c:	b580      	push	{r7, lr}
 8001c8e:	b082      	sub	sp, #8
 8001c90:	af00      	add	r7, sp, #0
 8001c92:	6078      	str	r0, [r7, #4]
  /* Get the SPIx Reception FIFO level bits */
  return (uint16_t)((SPIx->SR & SPI_SR_FRLVL));
 8001c94:	687b      	ldr	r3, [r7, #4]
 8001c96:	891b      	ldrh	r3, [r3, #8]
 8001c98:	b29a      	uxth	r2, r3
 8001c9a:	23c0      	movs	r3, #192	; 0xc0
 8001c9c:	00db      	lsls	r3, r3, #3
 8001c9e:	4013      	ands	r3, r2
 8001ca0:	b29b      	uxth	r3, r3
}
 8001ca2:	1c18      	adds	r0, r3, #0
 8001ca4:	46bd      	mov	sp, r7
 8001ca6:	b002      	add	sp, #8
 8001ca8:	bd80      	pop	{r7, pc}
 8001caa:	46c0      	nop			; (mov r8, r8)

08001cac <SPI_I2S_GetFlagStatus>:
  *            @arg I2S_FLAG_UDR: Underrun Error flag.
  *            @arg I2S_FLAG_CHSIDE: Channel Side flag.   
  * @retval The new state of SPI_I2S_FLAG (SET or RESET).
  */
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
{
 8001cac:	b580      	push	{r7, lr}
 8001cae:	b084      	sub	sp, #16
 8001cb0:	af00      	add	r7, sp, #0
 8001cb2:	6078      	str	r0, [r7, #4]
 8001cb4:	1c0a      	adds	r2, r1, #0
 8001cb6:	1cbb      	adds	r3, r7, #2
 8001cb8:	801a      	strh	r2, [r3, #0]
  FlagStatus bitstatus = RESET;
 8001cba:	230f      	movs	r3, #15
 8001cbc:	18fb      	adds	r3, r7, r3
 8001cbe:	2200      	movs	r2, #0
 8001cc0:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_SPI_ALL_PERIPH(SPIx));
  assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));

  /* Check the status of the specified SPI flag */
  if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
 8001cc2:	687b      	ldr	r3, [r7, #4]
 8001cc4:	891b      	ldrh	r3, [r3, #8]
 8001cc6:	b29b      	uxth	r3, r3
 8001cc8:	1cba      	adds	r2, r7, #2
 8001cca:	8812      	ldrh	r2, [r2, #0]
 8001ccc:	4013      	ands	r3, r2
 8001cce:	b29b      	uxth	r3, r3
 8001cd0:	2b00      	cmp	r3, #0
 8001cd2:	d004      	beq.n	8001cde <SPI_I2S_GetFlagStatus+0x32>
  {
    /* SPI_I2S_FLAG is set */
    bitstatus = SET;
 8001cd4:	230f      	movs	r3, #15
 8001cd6:	18fb      	adds	r3, r7, r3
 8001cd8:	2201      	movs	r2, #1
 8001cda:	701a      	strb	r2, [r3, #0]
 8001cdc:	e003      	b.n	8001ce6 <SPI_I2S_GetFlagStatus+0x3a>
  }
  else
  {
    /* SPI_I2S_FLAG is reset */
    bitstatus = RESET;
 8001cde:	230f      	movs	r3, #15
 8001ce0:	18fb      	adds	r3, r7, r3
 8001ce2:	2200      	movs	r2, #0
 8001ce4:	701a      	strb	r2, [r3, #0]
  }
  /* Return the SPI_I2S_FLAG status */
  return  bitstatus;
 8001ce6:	230f      	movs	r3, #15
 8001ce8:	18fb      	adds	r3, r7, r3
 8001cea:	781b      	ldrb	r3, [r3, #0]
}
 8001cec:	1c18      	adds	r0, r3, #0
 8001cee:	46bd      	mov	sp, r7
 8001cf0:	b004      	add	sp, #16
 8001cf2:	bd80      	pop	{r7, pc}

08001cf4 <SPI_I2S_ClearFlag>:
  *         operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by
  *         a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
  * @retval None
  */
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
{
 8001cf4:	b580      	push	{r7, lr}
 8001cf6:	b082      	sub	sp, #8
 8001cf8:	af00      	add	r7, sp, #0
 8001cfa:	6078      	str	r0, [r7, #4]
 8001cfc:	1c0a      	adds	r2, r1, #0
 8001cfe:	1cbb      	adds	r3, r7, #2
 8001d00:	801a      	strh	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_SPI_ALL_PERIPH(SPIx));
  assert_param(IS_SPI_CLEAR_FLAG(SPI_I2S_FLAG));

  /* Clear the selected SPI CRC Error (CRCERR) flag */
  SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
 8001d02:	1cbb      	adds	r3, r7, #2
 8001d04:	881b      	ldrh	r3, [r3, #0]
 8001d06:	43db      	mvns	r3, r3
 8001d08:	b29a      	uxth	r2, r3
 8001d0a:	687b      	ldr	r3, [r7, #4]
 8001d0c:	811a      	strh	r2, [r3, #8]
}
 8001d0e:	46bd      	mov	sp, r7
 8001d10:	b002      	add	sp, #8
 8001d12:	bd80      	pop	{r7, pc}

08001d14 <SPI_I2S_GetITStatus>:
  *            @arg I2S_IT_UDR: Underrun interrupt.  
  *            @arg SPI_I2S_IT_FRE: Format Error interrupt.  
  * @retval The new state of SPI_I2S_IT (SET or RESET).
  */
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
{
 8001d14:	b580      	push	{r7, lr}
 8001d16:	b084      	sub	sp, #16
 8001d18:	af00      	add	r7, sp, #0
 8001d1a:	6078      	str	r0, [r7, #4]
 8001d1c:	1c0a      	adds	r2, r1, #0
 8001d1e:	1cfb      	adds	r3, r7, #3
 8001d20:	701a      	strb	r2, [r3, #0]
  ITStatus bitstatus = RESET;
 8001d22:	230f      	movs	r3, #15
 8001d24:	18fb      	adds	r3, r7, r3
 8001d26:	2200      	movs	r2, #0
 8001d28:	701a      	strb	r2, [r3, #0]
  uint16_t itpos = 0, itmask = 0, enablestatus = 0;
 8001d2a:	230c      	movs	r3, #12
 8001d2c:	18fb      	adds	r3, r7, r3
 8001d2e:	2200      	movs	r2, #0
 8001d30:	801a      	strh	r2, [r3, #0]
 8001d32:	230a      	movs	r3, #10
 8001d34:	18fb      	adds	r3, r7, r3
 8001d36:	2200      	movs	r2, #0
 8001d38:	801a      	strh	r2, [r3, #0]
 8001d3a:	2308      	movs	r3, #8
 8001d3c:	18fb      	adds	r3, r7, r3
 8001d3e:	2200      	movs	r2, #0
 8001d40:	801a      	strh	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_SPI_ALL_PERIPH(SPIx));
  assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));

  /* Get the SPI_I2S_IT index */
  itpos = 0x01 << (SPI_I2S_IT & 0x0F);
 8001d42:	1cfb      	adds	r3, r7, #3
 8001d44:	781b      	ldrb	r3, [r3, #0]
 8001d46:	220f      	movs	r2, #15
 8001d48:	4013      	ands	r3, r2
 8001d4a:	2201      	movs	r2, #1
 8001d4c:	409a      	lsls	r2, r3
 8001d4e:	230c      	movs	r3, #12
 8001d50:	18fb      	adds	r3, r7, r3
 8001d52:	801a      	strh	r2, [r3, #0]

  /* Get the SPI_I2S_IT IT mask */
  itmask = SPI_I2S_IT >> 4;
 8001d54:	1cfb      	adds	r3, r7, #3
 8001d56:	781b      	ldrb	r3, [r3, #0]
 8001d58:	091b      	lsrs	r3, r3, #4
 8001d5a:	b2da      	uxtb	r2, r3
 8001d5c:	230a      	movs	r3, #10
 8001d5e:	18fb      	adds	r3, r7, r3
 8001d60:	801a      	strh	r2, [r3, #0]

  /* Set the IT mask */
  itmask = 0x01 << itmask;
 8001d62:	230a      	movs	r3, #10
 8001d64:	18fb      	adds	r3, r7, r3
 8001d66:	881b      	ldrh	r3, [r3, #0]
 8001d68:	2201      	movs	r2, #1
 8001d6a:	409a      	lsls	r2, r3
 8001d6c:	230a      	movs	r3, #10
 8001d6e:	18fb      	adds	r3, r7, r3
 8001d70:	801a      	strh	r2, [r3, #0]

  /* Get the SPI_I2S_IT enable bit status */
  enablestatus = (SPIx->CR2 & itmask) ;
 8001d72:	687b      	ldr	r3, [r7, #4]
 8001d74:	889b      	ldrh	r3, [r3, #4]
 8001d76:	b29a      	uxth	r2, r3
 8001d78:	2308      	movs	r3, #8
 8001d7a:	18fb      	adds	r3, r7, r3
 8001d7c:	210a      	movs	r1, #10
 8001d7e:	1879      	adds	r1, r7, r1
 8001d80:	8809      	ldrh	r1, [r1, #0]
 8001d82:	400a      	ands	r2, r1
 8001d84:	801a      	strh	r2, [r3, #0]

  /* Check the status of the specified SPI interrupt */
  if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
 8001d86:	687b      	ldr	r3, [r7, #4]
 8001d88:	891b      	ldrh	r3, [r3, #8]
 8001d8a:	b29b      	uxth	r3, r3
 8001d8c:	220c      	movs	r2, #12
 8001d8e:	18ba      	adds	r2, r7, r2
 8001d90:	8812      	ldrh	r2, [r2, #0]
 8001d92:	4013      	ands	r3, r2
 8001d94:	b29b      	uxth	r3, r3
 8001d96:	2b00      	cmp	r3, #0
 8001d98:	d009      	beq.n	8001dae <SPI_I2S_GetITStatus+0x9a>
 8001d9a:	2308      	movs	r3, #8
 8001d9c:	18fb      	adds	r3, r7, r3
 8001d9e:	881b      	ldrh	r3, [r3, #0]
 8001da0:	2b00      	cmp	r3, #0
 8001da2:	d004      	beq.n	8001dae <SPI_I2S_GetITStatus+0x9a>
  {
    /* SPI_I2S_IT is set */
    bitstatus = SET;
 8001da4:	230f      	movs	r3, #15
 8001da6:	18fb      	adds	r3, r7, r3
 8001da8:	2201      	movs	r2, #1
 8001daa:	701a      	strb	r2, [r3, #0]
 8001dac:	e003      	b.n	8001db6 <SPI_I2S_GetITStatus+0xa2>
  }
  else
  {
    /* SPI_I2S_IT is reset */
    bitstatus = RESET;
 8001dae:	230f      	movs	r3, #15
 8001db0:	18fb      	adds	r3, r7, r3
 8001db2:	2200      	movs	r2, #0
 8001db4:	701a      	strb	r2, [r3, #0]
  }
  /* Return the SPI_I2S_IT status */
  return bitstatus;
 8001db6:	230f      	movs	r3, #15
 8001db8:	18fb      	adds	r3, r7, r3
 8001dba:	781b      	ldrb	r3, [r3, #0]
}
 8001dbc:	1c18      	adds	r0, r3, #0
 8001dbe:	46bd      	mov	sp, r7
 8001dc0:	b004      	add	sp, #16
 8001dc2:	bd80      	pop	{r7, pc}

08001dc4 <ADC_DeInit>:
  * @brief  Deinitializes ADC1 peripheral registers to their default reset values.
  * @param  ADCx: where x can be 1 to select the ADC peripheral.
  * @retval None
  */
void ADC_DeInit(ADC_TypeDef* ADCx)
{
 8001dc4:	b580      	push	{r7, lr}
 8001dc6:	b082      	sub	sp, #8
 8001dc8:	af00      	add	r7, sp, #0
 8001dca:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_ADC_ALL_PERIPH(ADCx));

  if(ADCx == ADC1)
 8001dcc:	687b      	ldr	r3, [r7, #4]
 8001dce:	4a09      	ldr	r2, [pc, #36]	; (8001df4 <ADC_DeInit+0x30>)
 8001dd0:	4293      	cmp	r3, r2
 8001dd2:	d10b      	bne.n	8001dec <ADC_DeInit+0x28>
  {
    /* Enable ADC1 reset state */
    RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
 8001dd4:	2380      	movs	r3, #128	; 0x80
 8001dd6:	009b      	lsls	r3, r3, #2
 8001dd8:	1c18      	adds	r0, r3, #0
 8001dda:	2101      	movs	r1, #1
 8001ddc:	f7fe ffd4 	bl	8000d88 <RCC_APB2PeriphResetCmd>

    /* Release ADC1 from reset state */
    RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
 8001de0:	2380      	movs	r3, #128	; 0x80
 8001de2:	009b      	lsls	r3, r3, #2
 8001de4:	1c18      	adds	r0, r3, #0
 8001de6:	2100      	movs	r1, #0
 8001de8:	f7fe ffce 	bl	8000d88 <RCC_APB2PeriphResetCmd>
  }
}
 8001dec:	46bd      	mov	sp, r7
 8001dee:	b002      	add	sp, #8
 8001df0:	bd80      	pop	{r7, pc}
 8001df2:	46c0      	nop			; (mov r8, r8)
 8001df4:	40012400 	.word	0x40012400

08001df8 <ADC_Init>:
  * @param  ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains 
  *         the configuration information for the specified ADC peripheral.
  * @retval None
  */
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
{
 8001df8:	b580      	push	{r7, lr}
 8001dfa:	b084      	sub	sp, #16
 8001dfc:	af00      	add	r7, sp, #0
 8001dfe:	6078      	str	r0, [r7, #4]
 8001e00:	6039      	str	r1, [r7, #0]
  uint32_t tmpreg = 0;
 8001e02:	2300      	movs	r3, #0
 8001e04:	60fb      	str	r3, [r7, #12]
  assert_param(IS_ADC_EXTERNAL_TRIG_CONV(ADC_InitStruct->ADC_ExternalTrigConv));
  assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
  assert_param(IS_ADC_SCAN_DIRECTION(ADC_InitStruct->ADC_ScanDirection)); 

  /* Get the ADCx CFGR value */
  tmpreg = ADCx->CFGR1;
 8001e06:	687b      	ldr	r3, [r7, #4]
 8001e08:	68db      	ldr	r3, [r3, #12]
 8001e0a:	60fb      	str	r3, [r7, #12]

  /* Clear SCANDIR, RES[1:0], ALIGN, EXTSEL[2:0], EXTEN[1:0] and CONT bits */
  tmpreg &= CFGR1_CLEAR_MASK;
 8001e0c:	68fb      	ldr	r3, [r7, #12]
 8001e0e:	4a0f      	ldr	r2, [pc, #60]	; (8001e4c <ADC_Init+0x54>)
 8001e10:	4013      	ands	r3, r2
 8001e12:	60fb      	str	r3, [r7, #12]
  /* Set EXTEN[1:0] bits according to ADC_ExternalTrigConvEdge value */
  /* Set EXTSEL[2:0] bits according to ADC_ExternalTrigConv value */
  /* Set ALIGN bit according to ADC_DataAlign value */
  /* Set SCANDIR bit according to ADC_ScanDirection value */
 
  tmpreg  |= (uint32_t)(ADC_InitStruct->ADC_Resolution | ((uint32_t)(ADC_InitStruct->ADC_ContinuousConvMode) << 13) |
 8001e14:	683b      	ldr	r3, [r7, #0]
 8001e16:	681a      	ldr	r2, [r3, #0]
 8001e18:	683b      	ldr	r3, [r7, #0]
 8001e1a:	791b      	ldrb	r3, [r3, #4]
 8001e1c:	035b      	lsls	r3, r3, #13
 8001e1e:	431a      	orrs	r2, r3
             ADC_InitStruct->ADC_ExternalTrigConvEdge | ADC_InitStruct->ADC_ExternalTrigConv |
 8001e20:	683b      	ldr	r3, [r7, #0]
 8001e22:	689b      	ldr	r3, [r3, #8]
  /* Set EXTEN[1:0] bits according to ADC_ExternalTrigConvEdge value */
  /* Set EXTSEL[2:0] bits according to ADC_ExternalTrigConv value */
  /* Set ALIGN bit according to ADC_DataAlign value */
  /* Set SCANDIR bit according to ADC_ScanDirection value */
 
  tmpreg  |= (uint32_t)(ADC_InitStruct->ADC_Resolution | ((uint32_t)(ADC_InitStruct->ADC_ContinuousConvMode) << 13) |
 8001e24:	431a      	orrs	r2, r3
             ADC_InitStruct->ADC_ExternalTrigConvEdge | ADC_InitStruct->ADC_ExternalTrigConv |
 8001e26:	683b      	ldr	r3, [r7, #0]
 8001e28:	68db      	ldr	r3, [r3, #12]
 8001e2a:	431a      	orrs	r2, r3
             ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ScanDirection);
 8001e2c:	683b      	ldr	r3, [r7, #0]
 8001e2e:	691b      	ldr	r3, [r3, #16]
  /* Set EXTSEL[2:0] bits according to ADC_ExternalTrigConv value */
  /* Set ALIGN bit according to ADC_DataAlign value */
  /* Set SCANDIR bit according to ADC_ScanDirection value */
 
  tmpreg  |= (uint32_t)(ADC_InitStruct->ADC_Resolution | ((uint32_t)(ADC_InitStruct->ADC_ContinuousConvMode) << 13) |
             ADC_InitStruct->ADC_ExternalTrigConvEdge | ADC_InitStruct->ADC_ExternalTrigConv |
 8001e30:	431a      	orrs	r2, r3
             ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ScanDirection);
 8001e32:	683b      	ldr	r3, [r7, #0]
 8001e34:	695b      	ldr	r3, [r3, #20]
  /* Set EXTEN[1:0] bits according to ADC_ExternalTrigConvEdge value */
  /* Set EXTSEL[2:0] bits according to ADC_ExternalTrigConv value */
  /* Set ALIGN bit according to ADC_DataAlign value */
  /* Set SCANDIR bit according to ADC_ScanDirection value */
 
  tmpreg  |= (uint32_t)(ADC_InitStruct->ADC_Resolution | ((uint32_t)(ADC_InitStruct->ADC_ContinuousConvMode) << 13) |
 8001e36:	4313      	orrs	r3, r2
 8001e38:	68fa      	ldr	r2, [r7, #12]
 8001e3a:	4313      	orrs	r3, r2
 8001e3c:	60fb      	str	r3, [r7, #12]
             ADC_InitStruct->ADC_ExternalTrigConvEdge | ADC_InitStruct->ADC_ExternalTrigConv |
             ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ScanDirection);

  /* Write to ADCx CFGR */
  ADCx->CFGR1 = tmpreg;
 8001e3e:	687b      	ldr	r3, [r7, #4]
 8001e40:	68fa      	ldr	r2, [r7, #12]
 8001e42:	60da      	str	r2, [r3, #12]
}
 8001e44:	46bd      	mov	sp, r7
 8001e46:	b004      	add	sp, #16
 8001e48:	bd80      	pop	{r7, pc}
 8001e4a:	46c0      	nop			; (mov r8, r8)
 8001e4c:	ffffd203 	.word	0xffffd203

08001e50 <ADC_StructInit>:
  * @param  ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will 
  *         be initialized.
  * @retval None
  */
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
{
 8001e50:	b580      	push	{r7, lr}
 8001e52:	b082      	sub	sp, #8
 8001e54:	af00      	add	r7, sp, #0
 8001e56:	6078      	str	r0, [r7, #4]
  /* Reset ADC init structure parameters values */
  /* Initialize the ADC_Resolution member */
  ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;
 8001e58:	687b      	ldr	r3, [r7, #4]
 8001e5a:	2200      	movs	r2, #0
 8001e5c:	601a      	str	r2, [r3, #0]

   /* Initialize the ADC_ContinuousConvMode member */
  ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
 8001e5e:	687b      	ldr	r3, [r7, #4]
 8001e60:	2200      	movs	r2, #0
 8001e62:	711a      	strb	r2, [r3, #4]

  /* Initialize the ADC_ExternalTrigConvEdge member */
  ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
 8001e64:	687b      	ldr	r3, [r7, #4]
 8001e66:	2200      	movs	r2, #0
 8001e68:	609a      	str	r2, [r3, #8]

  /* Initialize the ADC_ExternalTrigConv member */
  ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_TRGO;
 8001e6a:	687b      	ldr	r3, [r7, #4]
 8001e6c:	2200      	movs	r2, #0
 8001e6e:	60da      	str	r2, [r3, #12]

  /* Initialize the ADC_DataAlign member */
  ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
 8001e70:	687b      	ldr	r3, [r7, #4]
 8001e72:	2200      	movs	r2, #0
 8001e74:	611a      	str	r2, [r3, #16]

  /* Initialize the ADC_ScanDirection member */
  ADC_InitStruct->ADC_ScanDirection = ADC_ScanDirection_Upward;
 8001e76:	687b      	ldr	r3, [r7, #4]
 8001e78:	2200      	movs	r2, #0
 8001e7a:	615a      	str	r2, [r3, #20]
}
 8001e7c:	46bd      	mov	sp, r7
 8001e7e:	b002      	add	sp, #8
 8001e80:	bd80      	pop	{r7, pc}
 8001e82:	46c0      	nop			; (mov r8, r8)

08001e84 <ADC_Cmd>:
  * @param  NewState: new state of the ADCx peripheral. 
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
{
 8001e84:	b580      	push	{r7, lr}
 8001e86:	b082      	sub	sp, #8
 8001e88:	af00      	add	r7, sp, #0
 8001e8a:	6078      	str	r0, [r7, #4]
 8001e8c:	1c0a      	adds	r2, r1, #0
 8001e8e:	1cfb      	adds	r3, r7, #3
 8001e90:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_ADC_ALL_PERIPH(ADCx));
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
 8001e92:	1cfb      	adds	r3, r7, #3
 8001e94:	781b      	ldrb	r3, [r3, #0]
 8001e96:	2b00      	cmp	r3, #0
 8001e98:	d006      	beq.n	8001ea8 <ADC_Cmd+0x24>
  {
    /* Set the ADEN bit to Enable the ADC peripheral */
    ADCx->CR |= (uint32_t)ADC_CR_ADEN;
 8001e9a:	687b      	ldr	r3, [r7, #4]
 8001e9c:	689b      	ldr	r3, [r3, #8]
 8001e9e:	2201      	movs	r2, #1
 8001ea0:	431a      	orrs	r2, r3
 8001ea2:	687b      	ldr	r3, [r7, #4]
 8001ea4:	609a      	str	r2, [r3, #8]
 8001ea6:	e005      	b.n	8001eb4 <ADC_Cmd+0x30>
  }
  else
  {
    /* Set the ADDIS to Disable the ADC peripheral */
    ADCx->CR |= (uint32_t)ADC_CR_ADDIS;
 8001ea8:	687b      	ldr	r3, [r7, #4]
 8001eaa:	689b      	ldr	r3, [r3, #8]
 8001eac:	2202      	movs	r2, #2
 8001eae:	431a      	orrs	r2, r3
 8001eb0:	687b      	ldr	r3, [r7, #4]
 8001eb2:	609a      	str	r2, [r3, #8]
  }
}
 8001eb4:	46bd      	mov	sp, r7
 8001eb6:	b002      	add	sp, #8
 8001eb8:	bd80      	pop	{r7, pc}
 8001eba:	46c0      	nop			; (mov r8, r8)

08001ebc <ADC_ClockModeConfig>:
  *            @arg ADC_ClockMode_SynClkDiv2: ADC clocked by PCLK/2
  *            @arg ADC_ClockMode_SynClkDiv4: ADC clocked by PCLK/4  
  * @retval None
  */
void ADC_ClockModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ClockMode)
{
 8001ebc:	b580      	push	{r7, lr}
 8001ebe:	b082      	sub	sp, #8
 8001ec0:	af00      	add	r7, sp, #0
 8001ec2:	6078      	str	r0, [r7, #4]
 8001ec4:	6039      	str	r1, [r7, #0]
  /* Check the parameters */
  assert_param(IS_ADC_ALL_PERIPH(ADCx));
  assert_param(IS_ADC_CLOCKMODE(ADC_ClockMode));

    /* Configure the ADC Clock mode according to ADC_ClockMode */
    ADCx->CFGR2 = (uint32_t)ADC_ClockMode;
 8001ec6:	687b      	ldr	r3, [r7, #4]
 8001ec8:	683a      	ldr	r2, [r7, #0]
 8001eca:	611a      	str	r2, [r3, #16]

}
 8001ecc:	46bd      	mov	sp, r7
 8001ece:	b002      	add	sp, #8
 8001ed0:	bd80      	pop	{r7, pc}
 8001ed2:	46c0      	nop			; (mov r8, r8)

08001ed4 <ADC_JitterCmd>:
  * @param  NewState: new state of the ADCx jitter. 
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void ADC_JitterCmd(ADC_TypeDef* ADCx, uint32_t ADC_JitterOff, FunctionalState NewState)
{
 8001ed4:	b580      	push	{r7, lr}
 8001ed6:	b084      	sub	sp, #16
 8001ed8:	af00      	add	r7, sp, #0
 8001eda:	60f8      	str	r0, [r7, #12]
 8001edc:	60b9      	str	r1, [r7, #8]
 8001ede:	1dfb      	adds	r3, r7, #7
 8001ee0:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_ADC_ALL_PERIPH(ADCx));
  assert_param(IS_ADC_JITTEROFF(ADC_JitterOff));
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
 8001ee2:	1dfb      	adds	r3, r7, #7
 8001ee4:	781b      	ldrb	r3, [r3, #0]
 8001ee6:	2b00      	cmp	r3, #0
 8001ee8:	d006      	beq.n	8001ef8 <ADC_JitterCmd+0x24>
  {
    /* Disable Jitter */
    ADCx->CFGR2 |= (uint32_t)ADC_JitterOff;
 8001eea:	68fb      	ldr	r3, [r7, #12]
 8001eec:	691a      	ldr	r2, [r3, #16]
 8001eee:	68bb      	ldr	r3, [r7, #8]
 8001ef0:	431a      	orrs	r2, r3
 8001ef2:	68fb      	ldr	r3, [r7, #12]
 8001ef4:	611a      	str	r2, [r3, #16]
 8001ef6:	e006      	b.n	8001f06 <ADC_JitterCmd+0x32>
  }
  else
  {
    /* Enable Jitter */
    ADCx->CFGR2 &= (uint32_t)(~ADC_JitterOff);
 8001ef8:	68fb      	ldr	r3, [r7, #12]
 8001efa:	691b      	ldr	r3, [r3, #16]
 8001efc:	68ba      	ldr	r2, [r7, #8]
 8001efe:	43d2      	mvns	r2, r2
 8001f00:	401a      	ands	r2, r3
 8001f02:	68fb      	ldr	r3, [r7, #12]
 8001f04:	611a      	str	r2, [r3, #16]
  }
}
 8001f06:	46bd      	mov	sp, r7
 8001f08:	b004      	add	sp, #16
 8001f0a:	bd80      	pop	{r7, pc}

08001f0c <ADC_AutoPowerOffCmd>:
  * @param  NewState: new state of the ADCx power Off. 
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
{
 8001f0c:	b580      	push	{r7, lr}
 8001f0e:	b082      	sub	sp, #8
 8001f10:	af00      	add	r7, sp, #0
 8001f12:	6078      	str	r0, [r7, #4]
 8001f14:	1c0a      	adds	r2, r1, #0
 8001f16:	1cfb      	adds	r3, r7, #3
 8001f18:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_ADC_ALL_PERIPH(ADCx));
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  
  if (NewState != DISABLE)
 8001f1a:	1cfb      	adds	r3, r7, #3
 8001f1c:	781b      	ldrb	r3, [r3, #0]
 8001f1e:	2b00      	cmp	r3, #0
 8001f20:	d007      	beq.n	8001f32 <ADC_AutoPowerOffCmd+0x26>
  {
    /* Enable the ADC Automatic Power-Off */
    ADCx->CFGR1 |= ADC_CFGR1_AUTOFF;
 8001f22:	687b      	ldr	r3, [r7, #4]
 8001f24:	68db      	ldr	r3, [r3, #12]
 8001f26:	2280      	movs	r2, #128	; 0x80
 8001f28:	0212      	lsls	r2, r2, #8
 8001f2a:	431a      	orrs	r2, r3
 8001f2c:	687b      	ldr	r3, [r7, #4]
 8001f2e:	60da      	str	r2, [r3, #12]
 8001f30:	e005      	b.n	8001f3e <ADC_AutoPowerOffCmd+0x32>
  }
  else
  {
    /* Disable the ADC Automatic Power-Off */
    ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AUTOFF;
 8001f32:	687b      	ldr	r3, [r7, #4]
 8001f34:	68db      	ldr	r3, [r3, #12]
 8001f36:	4a03      	ldr	r2, [pc, #12]	; (8001f44 <ADC_AutoPowerOffCmd+0x38>)
 8001f38:	401a      	ands	r2, r3
 8001f3a:	687b      	ldr	r3, [r7, #4]
 8001f3c:	60da      	str	r2, [r3, #12]
  }
}
 8001f3e:	46bd      	mov	sp, r7
 8001f40:	b002      	add	sp, #8
 8001f42:	bd80      	pop	{r7, pc}
 8001f44:	ffff7fff 	.word	0xffff7fff

08001f48 <ADC_WaitModeCmd>:
  * @param  NewState: new state of the ADCx Auto-Delay.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
{
 8001f48:	b580      	push	{r7, lr}
 8001f4a:	b082      	sub	sp, #8
 8001f4c:	af00      	add	r7, sp, #0
 8001f4e:	6078      	str	r0, [r7, #4]
 8001f50:	1c0a      	adds	r2, r1, #0
 8001f52:	1cfb      	adds	r3, r7, #3
 8001f54:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_ADC_ALL_PERIPH(ADCx));
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  
  if (NewState != DISABLE)
 8001f56:	1cfb      	adds	r3, r7, #3
 8001f58:	781b      	ldrb	r3, [r3, #0]
 8001f5a:	2b00      	cmp	r3, #0
 8001f5c:	d007      	beq.n	8001f6e <ADC_WaitModeCmd+0x26>
  {
    /* Enable the ADC Automatic Delayed conversion */
    ADCx->CFGR1 |= ADC_CFGR1_WAIT;
 8001f5e:	687b      	ldr	r3, [r7, #4]
 8001f60:	68db      	ldr	r3, [r3, #12]
 8001f62:	2280      	movs	r2, #128	; 0x80
 8001f64:	01d2      	lsls	r2, r2, #7
 8001f66:	431a      	orrs	r2, r3
 8001f68:	687b      	ldr	r3, [r7, #4]
 8001f6a:	60da      	str	r2, [r3, #12]
 8001f6c:	e005      	b.n	8001f7a <ADC_WaitModeCmd+0x32>
  }
  else
  {
    /* Disable the ADC Automatic Delayed conversion */
    ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_WAIT;
 8001f6e:	687b      	ldr	r3, [r7, #4]
 8001f70:	68db      	ldr	r3, [r3, #12]
 8001f72:	4a03      	ldr	r2, [pc, #12]	; (8001f80 <ADC_WaitModeCmd+0x38>)
 8001f74:	401a      	ands	r2, r3
 8001f76:	687b      	ldr	r3, [r7, #4]
 8001f78:	60da      	str	r2, [r3, #12]
  }
}
 8001f7a:	46bd      	mov	sp, r7
 8001f7c:	b002      	add	sp, #8
 8001f7e:	bd80      	pop	{r7, pc}
 8001f80:	ffffbfff 	.word	0xffffbfff

08001f84 <ADC_AnalogWatchdogCmd>:
  * @param  NewState: new state of the ADCx Analog Watchdog.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
{
 8001f84:	b580      	push	{r7, lr}
 8001f86:	b082      	sub	sp, #8
 8001f88:	af00      	add	r7, sp, #0
 8001f8a:	6078      	str	r0, [r7, #4]
 8001f8c:	1c0a      	adds	r2, r1, #0
 8001f8e:	1cfb      	adds	r3, r7, #3
 8001f90:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_ADC_ALL_PERIPH(ADCx));
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  
  if (NewState != DISABLE)
 8001f92:	1cfb      	adds	r3, r7, #3
 8001f94:	781b      	ldrb	r3, [r3, #0]
 8001f96:	2b00      	cmp	r3, #0
 8001f98:	d007      	beq.n	8001faa <ADC_AnalogWatchdogCmd+0x26>
  {
    /* Enable the ADC Analog Watchdog */
    ADCx->CFGR1 |= ADC_CFGR1_AWDEN;
 8001f9a:	687b      	ldr	r3, [r7, #4]
 8001f9c:	68db      	ldr	r3, [r3, #12]
 8001f9e:	2280      	movs	r2, #128	; 0x80
 8001fa0:	0412      	lsls	r2, r2, #16
 8001fa2:	431a      	orrs	r2, r3
 8001fa4:	687b      	ldr	r3, [r7, #4]
 8001fa6:	60da      	str	r2, [r3, #12]
 8001fa8:	e005      	b.n	8001fb6 <ADC_AnalogWatchdogCmd+0x32>
  }
  else
  {
    /* Disable the ADC Analog Watchdog */
    ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AWDEN;
 8001faa:	687b      	ldr	r3, [r7, #4]
 8001fac:	68db      	ldr	r3, [r3, #12]
 8001fae:	4a03      	ldr	r2, [pc, #12]	; (8001fbc <ADC_AnalogWatchdogCmd+0x38>)
 8001fb0:	401a      	ands	r2, r3
 8001fb2:	687b      	ldr	r3, [r7, #4]
 8001fb4:	60da      	str	r2, [r3, #12]
  }
}
 8001fb6:	46bd      	mov	sp, r7
 8001fb8:	b002      	add	sp, #8
 8001fba:	bd80      	pop	{r7, pc}
 8001fbc:	ff7fffff 	.word	0xff7fffff

08001fc0 <ADC_AnalogWatchdogThresholdsConfig>:
  *          This parameter must be a 12bit value.
  * @retval None
  */
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
                                        uint16_t LowThreshold)
{
 8001fc0:	b580      	push	{r7, lr}
 8001fc2:	b082      	sub	sp, #8
 8001fc4:	af00      	add	r7, sp, #0
 8001fc6:	6078      	str	r0, [r7, #4]
 8001fc8:	1c08      	adds	r0, r1, #0
 8001fca:	1c11      	adds	r1, r2, #0
 8001fcc:	1cbb      	adds	r3, r7, #2
 8001fce:	1c02      	adds	r2, r0, #0
 8001fd0:	801a      	strh	r2, [r3, #0]
 8001fd2:	1c3b      	adds	r3, r7, #0
 8001fd4:	1c0a      	adds	r2, r1, #0
 8001fd6:	801a      	strh	r2, [r3, #0]
  assert_param(IS_ADC_ALL_PERIPH(ADCx));
  assert_param(IS_ADC_THRESHOLD(HighThreshold));
  assert_param(IS_ADC_THRESHOLD(LowThreshold));

  /* Set the ADCx high and low threshold */
  ADCx->TR = LowThreshold | ((uint32_t)HighThreshold << 16);
 8001fd8:	1c3b      	adds	r3, r7, #0
 8001fda:	881a      	ldrh	r2, [r3, #0]
 8001fdc:	1cbb      	adds	r3, r7, #2
 8001fde:	881b      	ldrh	r3, [r3, #0]
 8001fe0:	041b      	lsls	r3, r3, #16
 8001fe2:	431a      	orrs	r2, r3
 8001fe4:	687b      	ldr	r3, [r7, #4]
 8001fe6:	621a      	str	r2, [r3, #32]

}
 8001fe8:	46bd      	mov	sp, r7
 8001fea:	b002      	add	sp, #8
 8001fec:	bd80      	pop	{r7, pc}
 8001fee:	46c0      	nop			; (mov r8, r8)

08001ff0 <ADC_AnalogWatchdogSingleChannelConfig>:
  * @note   The channel selected on the AWDCH must be also set into the CHSELR 
  *         register 
  * @retval None
  */
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog_Channel)
{
 8001ff0:	b580      	push	{r7, lr}
 8001ff2:	b084      	sub	sp, #16
 8001ff4:	af00      	add	r7, sp, #0
 8001ff6:	6078      	str	r0, [r7, #4]
 8001ff8:	6039      	str	r1, [r7, #0]
  uint32_t tmpreg = 0;
 8001ffa:	2300      	movs	r3, #0
 8001ffc:	60fb      	str	r3, [r7, #12]
  /* Check the parameters */
  assert_param(IS_ADC_ALL_PERIPH(ADCx));
  assert_param(IS_ADC_ANALOG_WATCHDOG_CHANNEL(ADC_AnalogWatchdog_Channel));

  /* Get the old register value */
  tmpreg = ADCx->CFGR1;
 8001ffe:	687b      	ldr	r3, [r7, #4]
 8002000:	68db      	ldr	r3, [r3, #12]
 8002002:	60fb      	str	r3, [r7, #12]

  /* Clear the Analog watchdog channel select bits */
  tmpreg &= ~ADC_CFGR1_AWDCH;
 8002004:	68fb      	ldr	r3, [r7, #12]
 8002006:	4a06      	ldr	r2, [pc, #24]	; (8002020 <ADC_AnalogWatchdogSingleChannelConfig+0x30>)
 8002008:	4013      	ands	r3, r2
 800200a:	60fb      	str	r3, [r7, #12]

  /* Set the Analog watchdog channel */
  tmpreg |= ADC_AnalogWatchdog_Channel;
 800200c:	68fa      	ldr	r2, [r7, #12]
 800200e:	683b      	ldr	r3, [r7, #0]
 8002010:	4313      	orrs	r3, r2
 8002012:	60fb      	str	r3, [r7, #12]

  /* Store the new register value */
  ADCx->CFGR1 = tmpreg;
 8002014:	687b      	ldr	r3, [r7, #4]
 8002016:	68fa      	ldr	r2, [r7, #12]
 8002018:	60da      	str	r2, [r3, #12]
}
 800201a:	46bd      	mov	sp, r7
 800201c:	b004      	add	sp, #16
 800201e:	bd80      	pop	{r7, pc}
 8002020:	83ffffff 	.word	0x83ffffff

08002024 <ADC_AnalogWatchdogSingleChannelCmd>:
  * @param  NewState: new state of the ADCx ADC Analog Watchdog Single Channel.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void ADC_AnalogWatchdogSingleChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
{
 8002024:	b580      	push	{r7, lr}
 8002026:	b082      	sub	sp, #8
 8002028:	af00      	add	r7, sp, #0
 800202a:	6078      	str	r0, [r7, #4]
 800202c:	1c0a      	adds	r2, r1, #0
 800202e:	1cfb      	adds	r3, r7, #3
 8002030:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_ADC_ALL_PERIPH(ADCx));
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
 8002032:	1cfb      	adds	r3, r7, #3
 8002034:	781b      	ldrb	r3, [r3, #0]
 8002036:	2b00      	cmp	r3, #0
 8002038:	d007      	beq.n	800204a <ADC_AnalogWatchdogSingleChannelCmd+0x26>
  {
    /* Enable the ADC Analog Watchdog Single Channel */
    ADCx->CFGR1 |= ADC_CFGR1_AWDSGL;
 800203a:	687b      	ldr	r3, [r7, #4]
 800203c:	68db      	ldr	r3, [r3, #12]
 800203e:	2280      	movs	r2, #128	; 0x80
 8002040:	03d2      	lsls	r2, r2, #15
 8002042:	431a      	orrs	r2, r3
 8002044:	687b      	ldr	r3, [r7, #4]
 8002046:	60da      	str	r2, [r3, #12]
 8002048:	e005      	b.n	8002056 <ADC_AnalogWatchdogSingleChannelCmd+0x32>
  }
  else
  {
    /* Disable the ADC Analog Watchdog Single Channel */
    ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AWDSGL;
 800204a:	687b      	ldr	r3, [r7, #4]
 800204c:	68db      	ldr	r3, [r3, #12]
 800204e:	4a03      	ldr	r2, [pc, #12]	; (800205c <ADC_AnalogWatchdogSingleChannelCmd+0x38>)
 8002050:	401a      	ands	r2, r3
 8002052:	687b      	ldr	r3, [r7, #4]
 8002054:	60da      	str	r2, [r3, #12]
  }
}
 8002056:	46bd      	mov	sp, r7
 8002058:	b002      	add	sp, #8
 800205a:	bd80      	pop	{r7, pc}
 800205c:	ffbfffff 	.word	0xffbfffff

08002060 <ADC_TempSensorCmd>:
  * @param  NewState: new state of the temperature sensor input channel.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void ADC_TempSensorCmd(FunctionalState NewState)
{
 8002060:	b580      	push	{r7, lr}
 8002062:	b082      	sub	sp, #8
 8002064:	af00      	add	r7, sp, #0
 8002066:	1c02      	adds	r2, r0, #0
 8002068:	1dfb      	adds	r3, r7, #7
 800206a:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
 800206c:	1dfb      	adds	r3, r7, #7
 800206e:	781b      	ldrb	r3, [r3, #0]
 8002070:	2b00      	cmp	r3, #0
 8002072:	d007      	beq.n	8002084 <ADC_TempSensorCmd+0x24>
  {
    /* Enable the temperature sensor channel*/
    ADC->CCR |= (uint32_t)ADC_CCR_TSEN;
 8002074:	4b08      	ldr	r3, [pc, #32]	; (8002098 <ADC_TempSensorCmd+0x38>)
 8002076:	4a08      	ldr	r2, [pc, #32]	; (8002098 <ADC_TempSensorCmd+0x38>)
 8002078:	6812      	ldr	r2, [r2, #0]
 800207a:	2180      	movs	r1, #128	; 0x80
 800207c:	0409      	lsls	r1, r1, #16
 800207e:	430a      	orrs	r2, r1
 8002080:	601a      	str	r2, [r3, #0]
 8002082:	e005      	b.n	8002090 <ADC_TempSensorCmd+0x30>
  }
  else
  {
    /* Disable the temperature sensor channel*/
    ADC->CCR &= (uint32_t)(~ADC_CCR_TSEN);
 8002084:	4b04      	ldr	r3, [pc, #16]	; (8002098 <ADC_TempSensorCmd+0x38>)
 8002086:	4a04      	ldr	r2, [pc, #16]	; (8002098 <ADC_TempSensorCmd+0x38>)
 8002088:	6812      	ldr	r2, [r2, #0]
 800208a:	4904      	ldr	r1, [pc, #16]	; (800209c <ADC_TempSensorCmd+0x3c>)
 800208c:	400a      	ands	r2, r1
 800208e:	601a      	str	r2, [r3, #0]
  }
}
 8002090:	46bd      	mov	sp, r7
 8002092:	b002      	add	sp, #8
 8002094:	bd80      	pop	{r7, pc}
 8002096:	46c0      	nop			; (mov r8, r8)
 8002098:	40012708 	.word	0x40012708
 800209c:	ff7fffff 	.word	0xff7fffff

080020a0 <ADC_VrefintCmd>:
  * @param  NewState: new state of the Vref input channel.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void ADC_VrefintCmd(FunctionalState NewState)
{
 80020a0:	b580      	push	{r7, lr}
 80020a2:	b082      	sub	sp, #8
 80020a4:	af00      	add	r7, sp, #0
 80020a6:	1c02      	adds	r2, r0, #0
 80020a8:	1dfb      	adds	r3, r7, #7
 80020aa:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
 80020ac:	1dfb      	adds	r3, r7, #7
 80020ae:	781b      	ldrb	r3, [r3, #0]
 80020b0:	2b00      	cmp	r3, #0
 80020b2:	d007      	beq.n	80020c4 <ADC_VrefintCmd+0x24>
  {
    /* Enable the Vrefint channel*/
    ADC->CCR |= (uint32_t)ADC_CCR_VREFEN;
 80020b4:	4b08      	ldr	r3, [pc, #32]	; (80020d8 <ADC_VrefintCmd+0x38>)
 80020b6:	4a08      	ldr	r2, [pc, #32]	; (80020d8 <ADC_VrefintCmd+0x38>)
 80020b8:	6812      	ldr	r2, [r2, #0]
 80020ba:	2180      	movs	r1, #128	; 0x80
 80020bc:	03c9      	lsls	r1, r1, #15
 80020be:	430a      	orrs	r2, r1
 80020c0:	601a      	str	r2, [r3, #0]
 80020c2:	e005      	b.n	80020d0 <ADC_VrefintCmd+0x30>
  }
  else
  {
    /* Disable the Vrefint channel*/
    ADC->CCR &= (uint32_t)(~ADC_CCR_VREFEN);
 80020c4:	4b04      	ldr	r3, [pc, #16]	; (80020d8 <ADC_VrefintCmd+0x38>)
 80020c6:	4a04      	ldr	r2, [pc, #16]	; (80020d8 <ADC_VrefintCmd+0x38>)
 80020c8:	6812      	ldr	r2, [r2, #0]
 80020ca:	4904      	ldr	r1, [pc, #16]	; (80020dc <ADC_VrefintCmd+0x3c>)
 80020cc:	400a      	ands	r2, r1
 80020ce:	601a      	str	r2, [r3, #0]
  }
}
 80020d0:	46bd      	mov	sp, r7
 80020d2:	b002      	add	sp, #8
 80020d4:	bd80      	pop	{r7, pc}
 80020d6:	46c0      	nop			; (mov r8, r8)
 80020d8:	40012708 	.word	0x40012708
 80020dc:	ffbfffff 	.word	0xffbfffff

080020e0 <ADC_VbatCmd>:
  * @param  NewState: new state of the Vbat input channel.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void ADC_VbatCmd(FunctionalState NewState)
{
 80020e0:	b580      	push	{r7, lr}
 80020e2:	b082      	sub	sp, #8
 80020e4:	af00      	add	r7, sp, #0
 80020e6:	1c02      	adds	r2, r0, #0
 80020e8:	1dfb      	adds	r3, r7, #7
 80020ea:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
 80020ec:	1dfb      	adds	r3, r7, #7
 80020ee:	781b      	ldrb	r3, [r3, #0]
 80020f0:	2b00      	cmp	r3, #0
 80020f2:	d007      	beq.n	8002104 <ADC_VbatCmd+0x24>
  {
    /* Enable the Vbat channel*/
    ADC->CCR |= (uint32_t)ADC_CCR_VBATEN;
 80020f4:	4b08      	ldr	r3, [pc, #32]	; (8002118 <ADC_VbatCmd+0x38>)
 80020f6:	4a08      	ldr	r2, [pc, #32]	; (8002118 <ADC_VbatCmd+0x38>)
 80020f8:	6812      	ldr	r2, [r2, #0]
 80020fa:	2180      	movs	r1, #128	; 0x80
 80020fc:	0449      	lsls	r1, r1, #17
 80020fe:	430a      	orrs	r2, r1
 8002100:	601a      	str	r2, [r3, #0]
 8002102:	e005      	b.n	8002110 <ADC_VbatCmd+0x30>
  }
  else
  {
    /* Disable the Vbat channel*/
    ADC->CCR &= (uint32_t)(~ADC_CCR_VBATEN);
 8002104:	4b04      	ldr	r3, [pc, #16]	; (8002118 <ADC_VbatCmd+0x38>)
 8002106:	4a04      	ldr	r2, [pc, #16]	; (8002118 <ADC_VbatCmd+0x38>)
 8002108:	6812      	ldr	r2, [r2, #0]
 800210a:	4904      	ldr	r1, [pc, #16]	; (800211c <ADC_VbatCmd+0x3c>)
 800210c:	400a      	ands	r2, r1
 800210e:	601a      	str	r2, [r3, #0]
  }
}
 8002110:	46bd      	mov	sp, r7
 8002112:	b002      	add	sp, #8
 8002114:	bd80      	pop	{r7, pc}
 8002116:	46c0      	nop			; (mov r8, r8)
 8002118:	40012708 	.word	0x40012708
 800211c:	feffffff 	.word	0xfeffffff

08002120 <ADC_ChannelConfig>:
  *            @arg ADC_SampleTime_71_5Cycles: Sample time equal to 71.5 cycles
  *            @arg ADC_SampleTime_239_5Cycles: Sample time equal to 239.5 cycles
  * @retval None
  */
void ADC_ChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_Channel, uint32_t ADC_SampleTime)
{
 8002120:	b580      	push	{r7, lr}
 8002122:	b086      	sub	sp, #24
 8002124:	af00      	add	r7, sp, #0
 8002126:	60f8      	str	r0, [r7, #12]
 8002128:	60b9      	str	r1, [r7, #8]
 800212a:	607a      	str	r2, [r7, #4]
  uint32_t tmpreg = 0;
 800212c:	2300      	movs	r3, #0
 800212e:	617b      	str	r3, [r7, #20]
  assert_param(IS_ADC_ALL_PERIPH(ADCx));
  assert_param(IS_ADC_CHANNEL(ADC_Channel));
  assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));

  /* Configure the ADC Channel */
  ADCx->CHSELR |= (uint32_t)ADC_Channel;
 8002130:	68fb      	ldr	r3, [r7, #12]
 8002132:	6a9a      	ldr	r2, [r3, #40]	; 0x28
 8002134:	68bb      	ldr	r3, [r7, #8]
 8002136:	431a      	orrs	r2, r3
 8002138:	68fb      	ldr	r3, [r7, #12]
 800213a:	629a      	str	r2, [r3, #40]	; 0x28

  /* Clear the Sampling time Selection bits */
  tmpreg &= ~ADC_SMPR1_SMPR;
 800213c:	697b      	ldr	r3, [r7, #20]
 800213e:	2207      	movs	r2, #7
 8002140:	4393      	bics	r3, r2
 8002142:	617b      	str	r3, [r7, #20]

  /* Set the ADC Sampling Time register */
  tmpreg |= (uint32_t)ADC_SampleTime;
 8002144:	697a      	ldr	r2, [r7, #20]
 8002146:	687b      	ldr	r3, [r7, #4]
 8002148:	4313      	orrs	r3, r2
 800214a:	617b      	str	r3, [r7, #20]

  /* Configure the ADC Sample time register */
  ADCx->SMPR = tmpreg ;
 800214c:	68fb      	ldr	r3, [r7, #12]
 800214e:	697a      	ldr	r2, [r7, #20]
 8002150:	615a      	str	r2, [r3, #20]
}
 8002152:	46bd      	mov	sp, r7
 8002154:	b006      	add	sp, #24
 8002156:	bd80      	pop	{r7, pc}

08002158 <ADC_ContinuousModeCmd>:
  *         enabled. In this case (If DISCEN and CONT are Set), the ADC behaves 
  *         as if continuous mode was disabled
  * @retval None
  */
void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
{
 8002158:	b580      	push	{r7, lr}
 800215a:	b082      	sub	sp, #8
 800215c:	af00      	add	r7, sp, #0
 800215e:	6078      	str	r0, [r7, #4]
 8002160:	1c0a      	adds	r2, r1, #0
 8002162:	1cfb      	adds	r3, r7, #3
 8002164:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_ADC_ALL_PERIPH(ADCx));
  assert_param(IS_FUNCTIONAL_STATE(NewState));

    if (NewState != DISABLE)
 8002166:	1cfb      	adds	r3, r7, #3
 8002168:	781b      	ldrb	r3, [r3, #0]
 800216a:	2b00      	cmp	r3, #0
 800216c:	d007      	beq.n	800217e <ADC_ContinuousModeCmd+0x26>
  {
    /* Enable the Continuous mode*/
    ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_CONT;
 800216e:	687b      	ldr	r3, [r7, #4]
 8002170:	68db      	ldr	r3, [r3, #12]
 8002172:	2280      	movs	r2, #128	; 0x80
 8002174:	0192      	lsls	r2, r2, #6
 8002176:	431a      	orrs	r2, r3
 8002178:	687b      	ldr	r3, [r7, #4]
 800217a:	60da      	str	r2, [r3, #12]
 800217c:	e005      	b.n	800218a <ADC_ContinuousModeCmd+0x32>
  }
  else
  {
    /* Disable the Continuous mode */
    ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_CONT);
 800217e:	687b      	ldr	r3, [r7, #4]
 8002180:	68db      	ldr	r3, [r3, #12]
 8002182:	4a03      	ldr	r2, [pc, #12]	; (8002190 <ADC_ContinuousModeCmd+0x38>)
 8002184:	401a      	ands	r2, r3
 8002186:	687b      	ldr	r3, [r7, #4]
 8002188:	60da      	str	r2, [r3, #12]
  }
}
 800218a:	46bd      	mov	sp, r7
 800218c:	b002      	add	sp, #8
 800218e:	bd80      	pop	{r7, pc}
 8002190:	ffffdfff 	.word	0xffffdfff

08002194 <ADC_DiscModeCmd>:
  *         enabled. In this case (If DISCEN and CONT are Set), the ADC behaves 
  *         as if continuous mode was disabled
  * @retval None
  */
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
{
 8002194:	b580      	push	{r7, lr}
 8002196:	b082      	sub	sp, #8
 8002198:	af00      	add	r7, sp, #0
 800219a:	6078      	str	r0, [r7, #4]
 800219c:	1c0a      	adds	r2, r1, #0
 800219e:	1cfb      	adds	r3, r7, #3
 80021a0:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_ADC_ALL_PERIPH(ADCx));
  assert_param(IS_FUNCTIONAL_STATE(NewState));

    if (NewState != DISABLE)
 80021a2:	1cfb      	adds	r3, r7, #3
 80021a4:	781b      	ldrb	r3, [r3, #0]
 80021a6:	2b00      	cmp	r3, #0
 80021a8:	d007      	beq.n	80021ba <ADC_DiscModeCmd+0x26>
  {
    /* Enable the Discontinuous mode */
    ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_DISCEN;
 80021aa:	687b      	ldr	r3, [r7, #4]
 80021ac:	68db      	ldr	r3, [r3, #12]
 80021ae:	2280      	movs	r2, #128	; 0x80
 80021b0:	0252      	lsls	r2, r2, #9
 80021b2:	431a      	orrs	r2, r3
 80021b4:	687b      	ldr	r3, [r7, #4]
 80021b6:	60da      	str	r2, [r3, #12]
 80021b8:	e005      	b.n	80021c6 <ADC_DiscModeCmd+0x32>
  }
  else
  {
    /* Disable the Discontinuous mode */
    ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_DISCEN);
 80021ba:	687b      	ldr	r3, [r7, #4]
 80021bc:	68db      	ldr	r3, [r3, #12]
 80021be:	4a03      	ldr	r2, [pc, #12]	; (80021cc <ADC_DiscModeCmd+0x38>)
 80021c0:	401a      	ands	r2, r3
 80021c2:	687b      	ldr	r3, [r7, #4]
 80021c4:	60da      	str	r2, [r3, #12]
  }
}
 80021c6:	46bd      	mov	sp, r7
 80021c8:	b002      	add	sp, #8
 80021ca:	bd80      	pop	{r7, pc}
 80021cc:	fffeffff 	.word	0xfffeffff

080021d0 <ADC_OverrunModeCmd>:
  * @param  NewState: new state of the Overrun mode.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void ADC_OverrunModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
{
 80021d0:	b580      	push	{r7, lr}
 80021d2:	b082      	sub	sp, #8
 80021d4:	af00      	add	r7, sp, #0
 80021d6:	6078      	str	r0, [r7, #4]
 80021d8:	1c0a      	adds	r2, r1, #0
 80021da:	1cfb      	adds	r3, r7, #3
 80021dc:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_ADC_ALL_PERIPH(ADCx));
  assert_param(IS_FUNCTIONAL_STATE(NewState));

    if (NewState != DISABLE)
 80021de:	1cfb      	adds	r3, r7, #3
 80021e0:	781b      	ldrb	r3, [r3, #0]
 80021e2:	2b00      	cmp	r3, #0
 80021e4:	d007      	beq.n	80021f6 <ADC_OverrunModeCmd+0x26>
  {
    /* Enable the Overrun mode */
    ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_OVRMOD;
 80021e6:	687b      	ldr	r3, [r7, #4]
 80021e8:	68db      	ldr	r3, [r3, #12]
 80021ea:	2280      	movs	r2, #128	; 0x80
 80021ec:	0152      	lsls	r2, r2, #5
 80021ee:	431a      	orrs	r2, r3
 80021f0:	687b      	ldr	r3, [r7, #4]
 80021f2:	60da      	str	r2, [r3, #12]
 80021f4:	e005      	b.n	8002202 <ADC_OverrunModeCmd+0x32>
  }
  else
  {
    /* Disable the Overrun mode */
    ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_OVRMOD);
 80021f6:	687b      	ldr	r3, [r7, #4]
 80021f8:	68db      	ldr	r3, [r3, #12]
 80021fa:	4a03      	ldr	r2, [pc, #12]	; (8002208 <ADC_OverrunModeCmd+0x38>)
 80021fc:	401a      	ands	r2, r3
 80021fe:	687b      	ldr	r3, [r7, #4]
 8002200:	60da      	str	r2, [r3, #12]
  }
}
 8002202:	46bd      	mov	sp, r7
 8002204:	b002      	add	sp, #8
 8002206:	bd80      	pop	{r7, pc}
 8002208:	ffffefff 	.word	0xffffefff

0800220c <ADC_GetCalibrationFactor>:
  *         reset configuration (ADEN must be equal to 0).
  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
  * @retval ADC Calibration factor 
  */
uint32_t ADC_GetCalibrationFactor(ADC_TypeDef* ADCx)
{
 800220c:	b580      	push	{r7, lr}
 800220e:	b086      	sub	sp, #24
 8002210:	af00      	add	r7, sp, #0
 8002212:	6078      	str	r0, [r7, #4]
  uint32_t tmpreg = 0, calibrationcounter = 0, calibrationstatus = 0;
 8002214:	2300      	movs	r3, #0
 8002216:	617b      	str	r3, [r7, #20]
 8002218:	2300      	movs	r3, #0
 800221a:	613b      	str	r3, [r7, #16]
 800221c:	2300      	movs	r3, #0
 800221e:	60fb      	str	r3, [r7, #12]

  /* Check the parameters */
  assert_param(IS_ADC_ALL_PERIPH(ADCx));
  
  /* Set the ADC calibartion */
  ADCx->CR |= (uint32_t)ADC_CR_ADCAL;
 8002220:	687b      	ldr	r3, [r7, #4]
 8002222:	689b      	ldr	r3, [r3, #8]
 8002224:	2280      	movs	r2, #128	; 0x80
 8002226:	0612      	lsls	r2, r2, #24
 8002228:	431a      	orrs	r2, r3
 800222a:	687b      	ldr	r3, [r7, #4]
 800222c:	609a      	str	r2, [r3, #8]
  
  /* Wait until no ADC calibration is completed */
  do
  {
    calibrationstatus = ADCx->CR & ADC_CR_ADCAL;
 800222e:	687b      	ldr	r3, [r7, #4]
 8002230:	689b      	ldr	r3, [r3, #8]
 8002232:	0fdb      	lsrs	r3, r3, #31
 8002234:	07db      	lsls	r3, r3, #31
 8002236:	60fb      	str	r3, [r7, #12]
    calibrationcounter++;  
 8002238:	693b      	ldr	r3, [r7, #16]
 800223a:	3301      	adds	r3, #1
 800223c:	613b      	str	r3, [r7, #16]
  } while((calibrationcounter != CALIBRATION_TIMEOUT) && (calibrationstatus != 0x00));
 800223e:	693a      	ldr	r2, [r7, #16]
 8002240:	23f0      	movs	r3, #240	; 0xf0
 8002242:	021b      	lsls	r3, r3, #8
 8002244:	429a      	cmp	r2, r3
 8002246:	d002      	beq.n	800224e <ADC_GetCalibrationFactor+0x42>
 8002248:	68fb      	ldr	r3, [r7, #12]
 800224a:	2b00      	cmp	r3, #0
 800224c:	d1ef      	bne.n	800222e <ADC_GetCalibrationFactor+0x22>
    
  if((uint32_t)(ADCx->CR & ADC_CR_ADCAL) == RESET)
 800224e:	687b      	ldr	r3, [r7, #4]
 8002250:	689b      	ldr	r3, [r3, #8]
 8002252:	2b00      	cmp	r3, #0
 8002254:	db03      	blt.n	800225e <ADC_GetCalibrationFactor+0x52>
  {
    /*Get the calibration factor from the ADC data register */
    tmpreg = ADCx->DR;
 8002256:	687b      	ldr	r3, [r7, #4]
 8002258:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 800225a:	617b      	str	r3, [r7, #20]
 800225c:	e001      	b.n	8002262 <ADC_GetCalibrationFactor+0x56>
  }
  else
  {
    /* Error factor */
    tmpreg = 0x00000000;
 800225e:	2300      	movs	r3, #0
 8002260:	617b      	str	r3, [r7, #20]
  }
  return tmpreg;
 8002262:	697b      	ldr	r3, [r7, #20]
}
 8002264:	1c18      	adds	r0, r3, #0
 8002266:	46bd      	mov	sp, r7
 8002268:	b006      	add	sp, #24
 800226a:	bd80      	pop	{r7, pc}

0800226c <ADC_StopOfConversion>:
  *         data register is not updated with current conversion. 
  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
  * @retval None
  */
void ADC_StopOfConversion(ADC_TypeDef* ADCx)
{
 800226c:	b580      	push	{r7, lr}
 800226e:	b082      	sub	sp, #8
 8002270:	af00      	add	r7, sp, #0
 8002272:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_ADC_ALL_PERIPH(ADCx));
  
  ADCx->CR |= (uint32_t)ADC_CR_ADSTP;
 8002274:	687b      	ldr	r3, [r7, #4]
 8002276:	689b      	ldr	r3, [r3, #8]
 8002278:	2210      	movs	r2, #16
 800227a:	431a      	orrs	r2, r3
 800227c:	687b      	ldr	r3, [r7, #4]
 800227e:	609a      	str	r2, [r3, #8]
}
 8002280:	46bd      	mov	sp, r7
 8002282:	b002      	add	sp, #8
 8002284:	bd80      	pop	{r7, pc}
 8002286:	46c0      	nop			; (mov r8, r8)

08002288 <ADC_StartOfConversion>:
  *         assertion of EOSEQ because the sequence is automatic relaunched
  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
  * @retval None
  */
void ADC_StartOfConversion(ADC_TypeDef* ADCx)
{
 8002288:	b580      	push	{r7, lr}
 800228a:	b082      	sub	sp, #8
 800228c:	af00      	add	r7, sp, #0
 800228e:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_ADC_ALL_PERIPH(ADCx));
  
  ADCx->CR |= (uint32_t)ADC_CR_ADSTART;
 8002290:	687b      	ldr	r3, [r7, #4]
 8002292:	689b      	ldr	r3, [r3, #8]
 8002294:	2204      	movs	r2, #4
 8002296:	431a      	orrs	r2, r3
 8002298:	687b      	ldr	r3, [r7, #4]
 800229a:	609a      	str	r2, [r3, #8]
}
 800229c:	46bd      	mov	sp, r7
 800229e:	b002      	add	sp, #8
 80022a0:	bd80      	pop	{r7, pc}
 80022a2:	46c0      	nop			; (mov r8, r8)

080022a4 <ADC_GetConversionValue>:
  * @brief  Returns the last ADCx conversion result data for ADC channel.  
  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
  * @retval The Data conversion value.
  */
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
{
 80022a4:	b580      	push	{r7, lr}
 80022a6:	b082      	sub	sp, #8
 80022a8:	af00      	add	r7, sp, #0
 80022aa:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_ADC_ALL_PERIPH(ADCx));

  /* Return the selected ADC conversion value */
  return (uint16_t) ADCx->DR;
 80022ac:	687b      	ldr	r3, [r7, #4]
 80022ae:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80022b0:	b29b      	uxth	r3, r3
}
 80022b2:	1c18      	adds	r0, r3, #0
 80022b4:	46bd      	mov	sp, r7
 80022b6:	b002      	add	sp, #8
 80022b8:	bd80      	pop	{r7, pc}
 80022ba:	46c0      	nop			; (mov r8, r8)

080022bc <ADC_DMACmd>:
  * @param  NewState: new state of the selected ADC DMA transfer.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
{
 80022bc:	b580      	push	{r7, lr}
 80022be:	b082      	sub	sp, #8
 80022c0:	af00      	add	r7, sp, #0
 80022c2:	6078      	str	r0, [r7, #4]
 80022c4:	1c0a      	adds	r2, r1, #0
 80022c6:	1cfb      	adds	r3, r7, #3
 80022c8:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_ADC_ALL_PERIPH(ADCx));
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
 80022ca:	1cfb      	adds	r3, r7, #3
 80022cc:	781b      	ldrb	r3, [r3, #0]
 80022ce:	2b00      	cmp	r3, #0
 80022d0:	d006      	beq.n	80022e0 <ADC_DMACmd+0x24>
  {
    /* Enable the selected ADC DMA request */
    ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_DMAEN;
 80022d2:	687b      	ldr	r3, [r7, #4]
 80022d4:	68db      	ldr	r3, [r3, #12]
 80022d6:	2201      	movs	r2, #1
 80022d8:	431a      	orrs	r2, r3
 80022da:	687b      	ldr	r3, [r7, #4]
 80022dc:	60da      	str	r2, [r3, #12]
 80022de:	e006      	b.n	80022ee <ADC_DMACmd+0x32>
  }
  else
  {
    /* Disable the selected ADC DMA request */
    ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_DMAEN);
 80022e0:	687b      	ldr	r3, [r7, #4]
 80022e2:	68db      	ldr	r3, [r3, #12]
 80022e4:	2201      	movs	r2, #1
 80022e6:	4393      	bics	r3, r2
 80022e8:	1c1a      	adds	r2, r3, #0
 80022ea:	687b      	ldr	r3, [r7, #4]
 80022ec:	60da      	str	r2, [r3, #12]
  }
}
 80022ee:	46bd      	mov	sp, r7
 80022f0:	b002      	add	sp, #8
 80022f2:	bd80      	pop	{r7, pc}

080022f4 <ADC_DMARequestModeConfig>:
  *            @arg ADC_DMAMode_OneShot: DMA One Shot Mode 
  *            @arg ADC_DMAMode_Circular: DMA Circular Mode  
  *  @retval None
  */
void ADC_DMARequestModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMARequestMode)
{
 80022f4:	b580      	push	{r7, lr}
 80022f6:	b082      	sub	sp, #8
 80022f8:	af00      	add	r7, sp, #0
 80022fa:	6078      	str	r0, [r7, #4]
 80022fc:	6039      	str	r1, [r7, #0]
  /* Check the parameters */
  assert_param(IS_ADC_ALL_PERIPH(ADCx));

  ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_DMACFG;
 80022fe:	687b      	ldr	r3, [r7, #4]
 8002300:	68db      	ldr	r3, [r3, #12]
 8002302:	2202      	movs	r2, #2
 8002304:	4393      	bics	r3, r2
 8002306:	1c1a      	adds	r2, r3, #0
 8002308:	687b      	ldr	r3, [r7, #4]
 800230a:	60da      	str	r2, [r3, #12]
  ADCx->CFGR1 |= (uint32_t)ADC_DMARequestMode;
 800230c:	687b      	ldr	r3, [r7, #4]
 800230e:	68da      	ldr	r2, [r3, #12]
 8002310:	683b      	ldr	r3, [r7, #0]
 8002312:	431a      	orrs	r2, r3
 8002314:	687b      	ldr	r3, [r7, #4]
 8002316:	60da      	str	r2, [r3, #12]
}
 8002318:	46bd      	mov	sp, r7
 800231a:	b002      	add	sp, #8
 800231c:	bd80      	pop	{r7, pc}
 800231e:	46c0      	nop			; (mov r8, r8)

08002320 <ADC_ITConfig>:
  * @param  NewState: new state of the specified ADC interrupts.
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState)
{
 8002320:	b580      	push	{r7, lr}
 8002322:	b084      	sub	sp, #16
 8002324:	af00      	add	r7, sp, #0
 8002326:	60f8      	str	r0, [r7, #12]
 8002328:	60b9      	str	r1, [r7, #8]
 800232a:	1dfb      	adds	r3, r7, #7
 800232c:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_ADC_ALL_PERIPH(ADCx));
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  assert_param(IS_ADC_CONFIG_IT(ADC_IT)); 

  if (NewState != DISABLE)
 800232e:	1dfb      	adds	r3, r7, #7
 8002330:	781b      	ldrb	r3, [r3, #0]
 8002332:	2b00      	cmp	r3, #0
 8002334:	d006      	beq.n	8002344 <ADC_ITConfig+0x24>
  {
    /* Enable the selected ADC interrupts */
    ADCx->IER |= ADC_IT;
 8002336:	68fb      	ldr	r3, [r7, #12]
 8002338:	685a      	ldr	r2, [r3, #4]
 800233a:	68bb      	ldr	r3, [r7, #8]
 800233c:	431a      	orrs	r2, r3
 800233e:	68fb      	ldr	r3, [r7, #12]
 8002340:	605a      	str	r2, [r3, #4]
 8002342:	e006      	b.n	8002352 <ADC_ITConfig+0x32>
  }
  else
  {
    /* Disable the selected ADC interrupts */
    ADCx->IER &= (~(uint32_t)ADC_IT);
 8002344:	68fb      	ldr	r3, [r7, #12]
 8002346:	685b      	ldr	r3, [r3, #4]
 8002348:	68ba      	ldr	r2, [r7, #8]
 800234a:	43d2      	mvns	r2, r2
 800234c:	401a      	ands	r2, r3
 800234e:	68fb      	ldr	r3, [r7, #12]
 8002350:	605a      	str	r2, [r3, #4]
  }
}
 8002352:	46bd      	mov	sp, r7
 8002354:	b004      	add	sp, #16
 8002356:	bd80      	pop	{r7, pc}

08002358 <ADC_GetFlagStatus>:
  *            @arg ADC_FLAG_ADSTP: ADC stop flag
  *            @arg ADC_FLAG_ADCAL: ADC Calibration flag
  * @retval The new state of ADC_FLAG (SET or RESET).
  */
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)
{
 8002358:	b580      	push	{r7, lr}
 800235a:	b084      	sub	sp, #16
 800235c:	af00      	add	r7, sp, #0
 800235e:	6078      	str	r0, [r7, #4]
 8002360:	6039      	str	r1, [r7, #0]
  FlagStatus bitstatus = RESET;
 8002362:	230f      	movs	r3, #15
 8002364:	18fb      	adds	r3, r7, r3
 8002366:	2200      	movs	r2, #0
 8002368:	701a      	strb	r2, [r3, #0]
  uint32_t tmpreg = 0;
 800236a:	2300      	movs	r3, #0
 800236c:	60bb      	str	r3, [r7, #8]

  /* Check the parameters */
  assert_param(IS_ADC_ALL_PERIPH(ADCx));
  assert_param(IS_ADC_GET_FLAG(ADC_FLAG));

  if((uint32_t)(ADC_FLAG & 0x01000000))
 800236e:	683a      	ldr	r2, [r7, #0]
 8002370:	2380      	movs	r3, #128	; 0x80
 8002372:	045b      	lsls	r3, r3, #17
 8002374:	4013      	ands	r3, r2
 8002376:	d005      	beq.n	8002384 <ADC_GetFlagStatus+0x2c>
  {
    tmpreg = ADCx->CR & 0xFEFFFFFF;
 8002378:	687b      	ldr	r3, [r7, #4]
 800237a:	689b      	ldr	r3, [r3, #8]
 800237c:	4a0d      	ldr	r2, [pc, #52]	; (80023b4 <ADC_GetFlagStatus+0x5c>)
 800237e:	4013      	ands	r3, r2
 8002380:	60bb      	str	r3, [r7, #8]
 8002382:	e002      	b.n	800238a <ADC_GetFlagStatus+0x32>
  }
  else
  {
    tmpreg = ADCx->ISR;
 8002384:	687b      	ldr	r3, [r7, #4]
 8002386:	681b      	ldr	r3, [r3, #0]
 8002388:	60bb      	str	r3, [r7, #8]
  }
  
  /* Check the status of the specified ADC flag */
  if ((tmpreg & ADC_FLAG) != (uint32_t)RESET)
 800238a:	68bb      	ldr	r3, [r7, #8]
 800238c:	683a      	ldr	r2, [r7, #0]
 800238e:	4013      	ands	r3, r2
 8002390:	d004      	beq.n	800239c <ADC_GetFlagStatus+0x44>
  {
    /* ADC_FLAG is set */
    bitstatus = SET;
 8002392:	230f      	movs	r3, #15
 8002394:	18fb      	adds	r3, r7, r3
 8002396:	2201      	movs	r2, #1
 8002398:	701a      	strb	r2, [r3, #0]
 800239a:	e003      	b.n	80023a4 <ADC_GetFlagStatus+0x4c>
  }
  else
  {
    /* ADC_FLAG is reset */
    bitstatus = RESET;
 800239c:	230f      	movs	r3, #15
 800239e:	18fb      	adds	r3, r7, r3
 80023a0:	2200      	movs	r2, #0
 80023a2:	701a      	strb	r2, [r3, #0]
  }
  /* Return the ADC_FLAG status */
  return  bitstatus;
 80023a4:	230f      	movs	r3, #15
 80023a6:	18fb      	adds	r3, r7, r3
 80023a8:	781b      	ldrb	r3, [r3, #0]
}
 80023aa:	1c18      	adds	r0, r3, #0
 80023ac:	46bd      	mov	sp, r7
 80023ae:	b004      	add	sp, #16
 80023b0:	bd80      	pop	{r7, pc}
 80023b2:	46c0      	nop			; (mov r8, r8)
 80023b4:	feffffff 	.word	0xfeffffff

080023b8 <ADC_ClearFlag>:
  *            @arg ADC_FLAG_EOSEQ: End of Sequence flag
  *            @arg ADC_FLAG_OVR: Overrun flag 
  * @retval None
  */
void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)
{
 80023b8:	b580      	push	{r7, lr}
 80023ba:	b082      	sub	sp, #8
 80023bc:	af00      	add	r7, sp, #0
 80023be:	6078      	str	r0, [r7, #4]
 80023c0:	6039      	str	r1, [r7, #0]
  /* Check the parameters */
  assert_param(IS_ADC_ALL_PERIPH(ADCx));
  assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));

  /* Clear the selected ADC flags */
  ADCx->ISR = (uint32_t)ADC_FLAG;
 80023c2:	687b      	ldr	r3, [r7, #4]
 80023c4:	683a      	ldr	r2, [r7, #0]
 80023c6:	601a      	str	r2, [r3, #0]
}
 80023c8:	46bd      	mov	sp, r7
 80023ca:	b002      	add	sp, #8
 80023cc:	bd80      	pop	{r7, pc}
 80023ce:	46c0      	nop			; (mov r8, r8)

080023d0 <ADC_GetITStatus>:
  *            @arg ADC_IT_OVR: overrun interrupt
  *            @arg ADC_IT_AWD: Analog watchdog interrupt
  * @retval The new state of ADC_IT (SET or RESET).
  */
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT)
{
 80023d0:	b580      	push	{r7, lr}
 80023d2:	b084      	sub	sp, #16
 80023d4:	af00      	add	r7, sp, #0
 80023d6:	6078      	str	r0, [r7, #4]
 80023d8:	6039      	str	r1, [r7, #0]
  ITStatus bitstatus = RESET;
 80023da:	230f      	movs	r3, #15
 80023dc:	18fb      	adds	r3, r7, r3
 80023de:	2200      	movs	r2, #0
 80023e0:	701a      	strb	r2, [r3, #0]
  uint32_t enablestatus = 0;
 80023e2:	2300      	movs	r3, #0
 80023e4:	60bb      	str	r3, [r7, #8]
  /* Check the parameters */
  assert_param(IS_ADC_ALL_PERIPH(ADCx));
  assert_param(IS_ADC_GET_IT(ADC_IT));

  /* Get the ADC_IT enable bit status */
  enablestatus = (uint32_t)(ADCx->IER & ADC_IT); 
 80023e6:	687b      	ldr	r3, [r7, #4]
 80023e8:	685b      	ldr	r3, [r3, #4]
 80023ea:	683a      	ldr	r2, [r7, #0]
 80023ec:	4013      	ands	r3, r2
 80023ee:	60bb      	str	r3, [r7, #8]

  /* Check the status of the specified ADC interrupt */
  if (((uint32_t)(ADCx->ISR & ADC_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
 80023f0:	687b      	ldr	r3, [r7, #4]
 80023f2:	681b      	ldr	r3, [r3, #0]
 80023f4:	683a      	ldr	r2, [r7, #0]
 80023f6:	4013      	ands	r3, r2
 80023f8:	d007      	beq.n	800240a <ADC_GetITStatus+0x3a>
 80023fa:	68bb      	ldr	r3, [r7, #8]
 80023fc:	2b00      	cmp	r3, #0
 80023fe:	d004      	beq.n	800240a <ADC_GetITStatus+0x3a>
  {
    /* ADC_IT is set */
    bitstatus = SET;
 8002400:	230f      	movs	r3, #15
 8002402:	18fb      	adds	r3, r7, r3
 8002404:	2201      	movs	r2, #1
 8002406:	701a      	strb	r2, [r3, #0]
 8002408:	e003      	b.n	8002412 <ADC_GetITStatus+0x42>
  }
  else
  {
    /* ADC_IT is reset */
    bitstatus = RESET;
 800240a:	230f      	movs	r3, #15
 800240c:	18fb      	adds	r3, r7, r3
 800240e:	2200      	movs	r2, #0
 8002410:	701a      	strb	r2, [r3, #0]
  }
  /* Return the ADC_IT status */
  return  bitstatus;
 8002412:	230f      	movs	r3, #15
 8002414:	18fb      	adds	r3, r7, r3
 8002416:	781b      	ldrb	r3, [r3, #0]
}
 8002418:	1c18      	adds	r0, r3, #0
 800241a:	46bd      	mov	sp, r7
 800241c:	b004      	add	sp, #16
 800241e:	bd80      	pop	{r7, pc}

08002420 <ADC_ClearITPendingBit>:
  *            @arg ADC_IT_OVR: overrun interrupt
  *            @arg ADC_IT_AWD: Analog watchdog interrupt
  * @retval None
  */
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT)
{
 8002420:	b580      	push	{r7, lr}
 8002422:	b082      	sub	sp, #8
 8002424:	af00      	add	r7, sp, #0
 8002426:	6078      	str	r0, [r7, #4]
 8002428:	6039      	str	r1, [r7, #0]
  /* Check the parameters */
  assert_param(IS_ADC_ALL_PERIPH(ADCx));
  assert_param(IS_ADC_CLEAR_IT(ADC_IT));

  /* Clear the selected ADC interrupt pending bits */
  ADCx->ISR = (uint32_t)ADC_IT; 
 800242a:	687b      	ldr	r3, [r7, #4]
 800242c:	683a      	ldr	r2, [r7, #0]
 800242e:	601a      	str	r2, [r3, #0]
}
 8002430:	46bd      	mov	sp, r7
 8002432:	b002      	add	sp, #8
 8002434:	bd80      	pop	{r7, pc}
 8002436:	46c0      	nop			; (mov r8, r8)

08002438 <initAll>:
uint8_t sendData;
uint16_t counter = 0;
uint16_t data;

void initAll()
{
 8002438:	b580      	push	{r7, lr}
 800243a:	af00      	add	r7, sp, #0
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
 800243c:	2380      	movs	r3, #128	; 0x80
 800243e:	029b      	lsls	r3, r3, #10
 8002440:	1c18      	adds	r0, r3, #0
 8002442:	2101      	movs	r1, #1
 8002444:	f7fe fc28 	bl	8000c98 <RCC_AHBPeriphClockCmd>
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
 8002448:	2380      	movs	r3, #128	; 0x80
 800244a:	015b      	lsls	r3, r3, #5
 800244c:	1c18      	adds	r0, r3, #0
 800244e:	2101      	movs	r1, #1
 8002450:	f7fe fc40 	bl	8000cd4 <RCC_APB2PeriphClockCmd>
RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);
 8002454:	2380      	movs	r3, #128	; 0x80
 8002456:	009b      	lsls	r3, r3, #2
 8002458:	1c18      	adds	r0, r3, #0
 800245a:	2101      	movs	r1, #1
 800245c:	f7fe fc3a 	bl	8000cd4 <RCC_APB2PeriphClockCmd>

port.GPIO_Mode = GPIO_Mode_AF;
 8002460:	4b30      	ldr	r3, [pc, #192]	; (8002524 <initAll+0xec>)
 8002462:	2202      	movs	r2, #2
 8002464:	711a      	strb	r2, [r3, #4]
port.GPIO_OType = GPIO_OType_PP;
 8002466:	4b2f      	ldr	r3, [pc, #188]	; (8002524 <initAll+0xec>)
 8002468:	2200      	movs	r2, #0
 800246a:	719a      	strb	r2, [r3, #6]
port.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7;
 800246c:	4b2d      	ldr	r3, [pc, #180]	; (8002524 <initAll+0xec>)
 800246e:	22f1      	movs	r2, #241	; 0xf1
 8002470:	601a      	str	r2, [r3, #0]
port.GPIO_Speed = GPIO_Speed_50MHz;
 8002472:	4b2c      	ldr	r3, [pc, #176]	; (8002524 <initAll+0xec>)
 8002474:	2203      	movs	r2, #3
 8002476:	715a      	strb	r2, [r3, #5]
GPIO_Init(GPIOA, &port);
 8002478:	2390      	movs	r3, #144	; 0x90
 800247a:	05da      	lsls	r2, r3, #23
 800247c:	4b29      	ldr	r3, [pc, #164]	; (8002524 <initAll+0xec>)
 800247e:	1c10      	adds	r0, r2, #0
 8002480:	1c19      	adds	r1, r3, #0
 8002482:	f7fe fde7 	bl	8001054 <GPIO_Init>

ADC_StructInit(&adc);
 8002486:	4b28      	ldr	r3, [pc, #160]	; (8002528 <initAll+0xf0>)
 8002488:	1c18      	adds	r0, r3, #0
 800248a:	f7ff fce1 	bl	8001e50 <ADC_StructInit>
adc.ADC_ContinuousConvMode = ENABLE;
 800248e:	4b26      	ldr	r3, [pc, #152]	; (8002528 <initAll+0xf0>)
 8002490:	2201      	movs	r2, #1
 8002492:	711a      	strb	r2, [r3, #4]
adc.ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_TRGO;
 8002494:	4b24      	ldr	r3, [pc, #144]	; (8002528 <initAll+0xf0>)
 8002496:	2200      	movs	r2, #0
 8002498:	60da      	str	r2, [r3, #12]
ADC_Init(ADC1, &adc);
 800249a:	4a24      	ldr	r2, [pc, #144]	; (800252c <initAll+0xf4>)
 800249c:	4b22      	ldr	r3, [pc, #136]	; (8002528 <initAll+0xf0>)
 800249e:	1c10      	adds	r0, r2, #0
 80024a0:	1c19      	adds	r1, r3, #0
 80024a2:	f7ff fca9 	bl	8001df8 <ADC_Init>

SPI_StructInit(&spi);
 80024a6:	4b22      	ldr	r3, [pc, #136]	; (8002530 <initAll+0xf8>)
 80024a8:	1c18      	adds	r0, r3, #0
 80024aa:	f7fe ffc1 	bl	8001430 <SPI_StructInit>
spi.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
 80024ae:	4b20      	ldr	r3, [pc, #128]	; (8002530 <initAll+0xf8>)
 80024b0:	2200      	movs	r2, #0
 80024b2:	801a      	strh	r2, [r3, #0]
spi.SPI_Mode = SPI_Mode_Master;
 80024b4:	4b1e      	ldr	r3, [pc, #120]	; (8002530 <initAll+0xf8>)
 80024b6:	2282      	movs	r2, #130	; 0x82
 80024b8:	0052      	lsls	r2, r2, #1
 80024ba:	805a      	strh	r2, [r3, #2]
spi.SPI_DataSize = SPI_DataSize_8b;
 80024bc:	4b1c      	ldr	r3, [pc, #112]	; (8002530 <initAll+0xf8>)
 80024be:	22e0      	movs	r2, #224	; 0xe0
 80024c0:	00d2      	lsls	r2, r2, #3
 80024c2:	809a      	strh	r2, [r3, #4]
spi.SPI_CPOL = SPI_CPOL_Low;
 80024c4:	4b1a      	ldr	r3, [pc, #104]	; (8002530 <initAll+0xf8>)
 80024c6:	2200      	movs	r2, #0
 80024c8:	80da      	strh	r2, [r3, #6]
spi.SPI_CPHA = SPI_CPHA_2Edge;
 80024ca:	4b19      	ldr	r3, [pc, #100]	; (8002530 <initAll+0xf8>)
 80024cc:	2201      	movs	r2, #1
 80024ce:	811a      	strh	r2, [r3, #8]
spi.SPI_NSS = SPI_NSS_Soft;
 80024d0:	4b17      	ldr	r3, [pc, #92]	; (8002530 <initAll+0xf8>)
 80024d2:	2280      	movs	r2, #128	; 0x80
 80024d4:	0092      	lsls	r2, r2, #2
 80024d6:	815a      	strh	r2, [r3, #10]
spi.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
 80024d8:	4b15      	ldr	r3, [pc, #84]	; (8002530 <initAll+0xf8>)
 80024da:	2208      	movs	r2, #8
 80024dc:	819a      	strh	r2, [r3, #12]
spi.SPI_FirstBit = SPI_FirstBit_MSB;
 80024de:	4b14      	ldr	r3, [pc, #80]	; (8002530 <initAll+0xf8>)
 80024e0:	2200      	movs	r2, #0
 80024e2:	81da      	strh	r2, [r3, #14]
spi.SPI_CRCPolynomial = 7;
 80024e4:	4b12      	ldr	r3, [pc, #72]	; (8002530 <initAll+0xf8>)
 80024e6:	2207      	movs	r2, #7
 80024e8:	821a      	strh	r2, [r3, #16]
SPI_Init(SPI1, &spi);
 80024ea:	4a12      	ldr	r2, [pc, #72]	; (8002534 <initAll+0xfc>)
 80024ec:	4b10      	ldr	r3, [pc, #64]	; (8002530 <initAll+0xf8>)
 80024ee:	1c10      	adds	r0, r2, #0
 80024f0:	1c19      	adds	r1, r3, #0
 80024f2:	f7fe ffc1 	bl	8001478 <SPI_Init>

GPIO_StructInit(&port);
 80024f6:	4b0b      	ldr	r3, [pc, #44]	; (8002524 <initAll+0xec>)
 80024f8:	1c18      	adds	r0, r3, #0
 80024fa:	f7fe fe3d 	bl	8001178 <GPIO_StructInit>
port.GPIO_PuPd = GPIO_PuPd_DOWN;
 80024fe:	4b09      	ldr	r3, [pc, #36]	; (8002524 <initAll+0xec>)
 8002500:	2202      	movs	r2, #2
 8002502:	71da      	strb	r2, [r3, #7]
port.GPIO_Pin = GPIO_Pin_0;
 8002504:	4b07      	ldr	r3, [pc, #28]	; (8002524 <initAll+0xec>)
 8002506:	2201      	movs	r2, #1
 8002508:	601a      	str	r2, [r3, #0]
port.GPIO_Speed = GPIO_Speed_2MHz;
 800250a:	4b06      	ldr	r3, [pc, #24]	; (8002524 <initAll+0xec>)
 800250c:	2200      	movs	r2, #0
 800250e:	715a      	strb	r2, [r3, #5]
GPIO_Init(GPIOA, &port);
 8002510:	2390      	movs	r3, #144	; 0x90
 8002512:	05da      	lsls	r2, r3, #23
 8002514:	4b03      	ldr	r3, [pc, #12]	; (8002524 <initAll+0xec>)
 8002516:	1c10      	adds	r0, r2, #0
 8002518:	1c19      	adds	r1, r3, #0
 800251a:	f7fe fd9b 	bl	8001054 <GPIO_Init>
}
 800251e:	46bd      	mov	sp, r7
 8002520:	bd80      	pop	{r7, pc}
 8002522:	46c0      	nop			; (mov r8, r8)
 8002524:	20000024 	.word	0x20000024
 8002528:	20000040 	.word	0x20000040
 800252c:	40012400 	.word	0x40012400
 8002530:	2000002c 	.word	0x2000002c
 8002534:	40013000 	.word	0x40013000

08002538 <main>:

int main()
{
 8002538:	b580      	push	{r7, lr}
 800253a:	af00      	add	r7, sp, #0
  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
  Can only be executed in Privileged modes.
 */
__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
{
  __ASM volatile ("cpsie i");
 800253c:	b662      	cpsie	i
    __enable_irq();
    initAll();
 800253e:	f7ff ff7b 	bl	8002438 <initAll>
    //Включаем АЦП
//    ADC_Cmd(ADC1, ENABLE);
//    ADC_SoftwareStartConvCmd(ADC1, ENABLE);
    //И конечно же включаем SPI
    SPI_Cmd(SPI1, ENABLE);
 8002542:	4b20      	ldr	r3, [pc, #128]	; (80025c4 <main+0x8c>)
 8002544:	1c18      	adds	r0, r3, #0
 8002546:	2101      	movs	r1, #1
 8002548:	f7ff f912 	bl	8001770 <SPI_Cmd>
    while(1)
    {
        //Это просто счетчик, чтобы отсылать на шину данные только когда счетчик 
    //досчитает до 15000, число взято абсолютно "от балды" ))
        counter++;
 800254c:	4b1e      	ldr	r3, [pc, #120]	; (80025c8 <main+0x90>)
 800254e:	881b      	ldrh	r3, [r3, #0]
 8002550:	3301      	adds	r3, #1
 8002552:	b29a      	uxth	r2, r3
 8002554:	4b1c      	ldr	r3, [pc, #112]	; (80025c8 <main+0x90>)
 8002556:	801a      	strh	r2, [r3, #0]
//    data = ADC_GetConversionValue(ADC1);
        //Сделали АЦП, анализируем данные
    if (data == 0xFFF)
 8002558:	4b1c      	ldr	r3, [pc, #112]	; (80025cc <main+0x94>)
 800255a:	881b      	ldrh	r3, [r3, #0]
 800255c:	4a1c      	ldr	r2, [pc, #112]	; (80025d0 <main+0x98>)
 800255e:	4293      	cmp	r3, r2
 8002560:	d103      	bne.n	800256a <main+0x32>
    {
    sendData = 0x04;
 8002562:	4b1c      	ldr	r3, [pc, #112]	; (80025d4 <main+0x9c>)
 8002564:	2204      	movs	r2, #4
 8002566:	701a      	strb	r2, [r3, #0]
 8002568:	e01d      	b.n	80025a6 <main+0x6e>
    }
    else if (data > 0xE8B)
 800256a:	4b18      	ldr	r3, [pc, #96]	; (80025cc <main+0x94>)
 800256c:	881b      	ldrh	r3, [r3, #0]
 800256e:	4a1a      	ldr	r2, [pc, #104]	; (80025d8 <main+0xa0>)
 8002570:	4293      	cmp	r3, r2
 8002572:	d903      	bls.n	800257c <main+0x44>
    {
            sendData = 0x03;
 8002574:	4b17      	ldr	r3, [pc, #92]	; (80025d4 <main+0x9c>)
 8002576:	2203      	movs	r2, #3
 8002578:	701a      	strb	r2, [r3, #0]
 800257a:	e014      	b.n	80025a6 <main+0x6e>
    }
    else if (data > 0x9B2)
 800257c:	4b13      	ldr	r3, [pc, #76]	; (80025cc <main+0x94>)
 800257e:	881b      	ldrh	r3, [r3, #0]
 8002580:	4a16      	ldr	r2, [pc, #88]	; (80025dc <main+0xa4>)
 8002582:	4293      	cmp	r3, r2
 8002584:	d903      	bls.n	800258e <main+0x56>
    {
        sendData = 0x02;
 8002586:	4b13      	ldr	r3, [pc, #76]	; (80025d4 <main+0x9c>)
 8002588:	2202      	movs	r2, #2
 800258a:	701a      	strb	r2, [r3, #0]
 800258c:	e00b      	b.n	80025a6 <main+0x6e>
    }
    else if (data > 0x4D9)
 800258e:	4b0f      	ldr	r3, [pc, #60]	; (80025cc <main+0x94>)
 8002590:	881b      	ldrh	r3, [r3, #0]
 8002592:	4a13      	ldr	r2, [pc, #76]	; (80025e0 <main+0xa8>)
 8002594:	4293      	cmp	r3, r2
 8002596:	d903      	bls.n	80025a0 <main+0x68>
    {
        sendData = 0x01;
 8002598:	4b0e      	ldr	r3, [pc, #56]	; (80025d4 <main+0x9c>)
 800259a:	2201      	movs	r2, #1
 800259c:	701a      	strb	r2, [r3, #0]
 800259e:	e002      	b.n	80025a6 <main+0x6e>
    }
    else
    {
        sendData = 0x00;
 80025a0:	4b0c      	ldr	r3, [pc, #48]	; (80025d4 <main+0x9c>)
 80025a2:	2200      	movs	r2, #0
 80025a4:	701a      	strb	r2, [r3, #0]
    }
        if(counter == 15000)
 80025a6:	4b08      	ldr	r3, [pc, #32]	; (80025c8 <main+0x90>)
 80025a8:	881b      	ldrh	r3, [r3, #0]
 80025aa:	4a0e      	ldr	r2, [pc, #56]	; (80025e4 <main+0xac>)
 80025ac:	4293      	cmp	r3, r2
 80025ae:	d107      	bne.n	80025c0 <main+0x88>
    {
            //Отсылаем, ради этого все и затеивалось
        SPI_I2S_SendData16(SPI1, sendData);
 80025b0:	4b08      	ldr	r3, [pc, #32]	; (80025d4 <main+0x9c>)
 80025b2:	781b      	ldrb	r3, [r3, #0]
 80025b4:	b29b      	uxth	r3, r3
 80025b6:	4a03      	ldr	r2, [pc, #12]	; (80025c4 <main+0x8c>)
 80025b8:	1c10      	adds	r0, r2, #0
 80025ba:	1c19      	adds	r1, r3, #0
 80025bc:	f7ff fa24 	bl	8001a08 <SPI_I2S_SendData16>
    }
    }
 80025c0:	e7c4      	b.n	800254c <main+0x14>
 80025c2:	46c0      	nop			; (mov r8, r8)
 80025c4:	40013000 	.word	0x40013000
 80025c8:	2000005a 	.word	0x2000005a
 80025cc:	2000005c 	.word	0x2000005c
 80025d0:	00000fff 	.word	0x00000fff
 80025d4:	20000058 	.word	0x20000058
 80025d8:	00000e8b 	.word	0x00000e8b
 80025dc:	000009b2 	.word	0x000009b2
 80025e0:	000004d9 	.word	0x000004d9
 80025e4:	00003a98 	.word	0x00003a98
 80025e8:	08002730 	.word	0x08002730
 80025ec:	20000000 	.word	0x20000000
 80025f0:	20000024 	.word	0x20000024
 80025f4:	20000024 	.word	0x20000024
 80025f8:	20000060 	.word	0x20000060

080025fc <__aeabi_uidiv>:
 80025fc:	e2512001 	subs	r2, r1, #1
 8002600:	012fff1e 	bxeq	lr
 8002604:	3a000036 	bcc	80026e4 <__aeabi_uidiv+0xe8>
 8002608:	e1500001 	cmp	r0, r1
 800260c:	9a000022 	bls	800269c <__aeabi_uidiv+0xa0>
 8002610:	e1110002 	tst	r1, r2
 8002614:	0a000023 	beq	80026a8 <__aeabi_uidiv+0xac>
 8002618:	e311020e 	tst	r1, #-536870912	; 0xe0000000
 800261c:	01a01181 	lsleq	r1, r1, #3
 8002620:	03a03008 	moveq	r3, #8
 8002624:	13a03001 	movne	r3, #1
 8002628:	e3510201 	cmp	r1, #268435456	; 0x10000000
 800262c:	31510000 	cmpcc	r1, r0
 8002630:	31a01201 	lslcc	r1, r1, #4
 8002634:	31a03203 	lslcc	r3, r3, #4
 8002638:	3afffffa 	bcc	8002628 <__aeabi_uidiv+0x2c>
 800263c:	e3510102 	cmp	r1, #-2147483648	; 0x80000000
 8002640:	31510000 	cmpcc	r1, r0
 8002644:	31a01081 	lslcc	r1, r1, #1
 8002648:	31a03083 	lslcc	r3, r3, #1
 800264c:	3afffffa 	bcc	800263c <__aeabi_uidiv+0x40>
 8002650:	e3a02000 	mov	r2, #0
 8002654:	e1500001 	cmp	r0, r1
 8002658:	20400001 	subcs	r0, r0, r1
 800265c:	21822003 	orrcs	r2, r2, r3
 8002660:	e15000a1 	cmp	r0, r1, lsr #1
 8002664:	204000a1 	subcs	r0, r0, r1, lsr #1
 8002668:	218220a3 	orrcs	r2, r2, r3, lsr #1
 800266c:	e1500121 	cmp	r0, r1, lsr #2
 8002670:	20400121 	subcs	r0, r0, r1, lsr #2
 8002674:	21822123 	orrcs	r2, r2, r3, lsr #2
 8002678:	e15001a1 	cmp	r0, r1, lsr #3
 800267c:	204001a1 	subcs	r0, r0, r1, lsr #3
 8002680:	218221a3 	orrcs	r2, r2, r3, lsr #3
 8002684:	e3500000 	cmp	r0, #0
 8002688:	11b03223 	lsrsne	r3, r3, #4
 800268c:	11a01221 	lsrne	r1, r1, #4
 8002690:	1affffef 	bne	8002654 <__aeabi_uidiv+0x58>
 8002694:	e1a00002 	mov	r0, r2
 8002698:	e12fff1e 	bx	lr
 800269c:	03a00001 	moveq	r0, #1
 80026a0:	13a00000 	movne	r0, #0
 80026a4:	e12fff1e 	bx	lr
 80026a8:	e3510801 	cmp	r1, #65536	; 0x10000
 80026ac:	21a01821 	lsrcs	r1, r1, #16
 80026b0:	23a02010 	movcs	r2, #16
 80026b4:	33a02000 	movcc	r2, #0
 80026b8:	e3510c01 	cmp	r1, #256	; 0x100
 80026bc:	21a01421 	lsrcs	r1, r1, #8
 80026c0:	22822008 	addcs	r2, r2, #8
 80026c4:	e3510010 	cmp	r1, #16
 80026c8:	21a01221 	lsrcs	r1, r1, #4
 80026cc:	22822004 	addcs	r2, r2, #4
 80026d0:	e3510004 	cmp	r1, #4
 80026d4:	82822003 	addhi	r2, r2, #3
 80026d8:	908220a1 	addls	r2, r2, r1, lsr #1
 80026dc:	e1a00230 	lsr	r0, r0, r2
 80026e0:	e12fff1e 	bx	lr
 80026e4:	e3500000 	cmp	r0, #0
 80026e8:	13e00000 	mvnne	r0, #0
 80026ec:	ea000007 	b	8002710 <__aeabi_idiv0>

080026f0 <__aeabi_uidivmod>:
 80026f0:	e3510000 	cmp	r1, #0
 80026f4:	0afffffa 	beq	80026e4 <__aeabi_uidiv+0xe8>
 80026f8:	e92d4003 	push	{r0, r1, lr}
 80026fc:	ebffffbe 	bl	80025fc <__aeabi_uidiv>
 8002700:	e8bd4006 	pop	{r1, r2, lr}
 8002704:	e0030092 	mul	r3, r2, r0
 8002708:	e0411003 	sub	r1, r1, r3
 800270c:	e12fff1e 	bx	lr

08002710 <__aeabi_idiv0>:
 8002710:	e12fff1e 	bx	lr

08002714 <Reset_Handler>:
    
LoopFillZerobss:
/*  ldr r3, = _ebss */
/*  cmp r2, r3 */
/*  bcc FillZerobss */
  nop
 8002714:	46c0      	nop			; (mov r8, r8)
  nop
 8002716:	46c0      	nop			; (mov r8, r8)
  nop
 8002718:	46c0      	nop			; (mov r8, r8)
/* Call the clock system intitialization function.*/
  bl  SystemInit
 800271a:	f7fd fcd5 	bl	80000c8 <SystemInit>
/* Call the application's entry point.*/
  bl main
 800271e:	f7ff ff0b 	bl	8002538 <main>
  bx lr
 8002722:	4770      	bx	lr

08002724 <ADC1_COMP_IRQHandler>:
 * @retval None
*/
    .section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
  b Infinite_Loop
 8002724:	e7fe      	b.n	8002724 <ADC1_COMP_IRQHandler>
	...

08002728 <____aeabi_uidiv_from_thumb>:
 8002728:	4778      	bx	pc
 800272a:	46c0      	nop			; (mov r8, r8)
 800272c:	eaffffb2 	b	80025fc <__aeabi_uidiv>