STM32_Devel/SOFT/stm32_f0_4/build/main.lst

build/main.elf:     file format elf32-littlearm


Disassembly of section .text:

0800010c <SystemInit>:
  *         SystemCoreClock variable.
  * @param  None
  * @retval None
  */
void SystemInit (void)
{    
 800010c:	b580      	push	{r7, lr}
 800010e:	af00      	add	r7, sp, #0
  /* Set HSION bit */
  RCC->CR |= (uint32_t)0x00000001;
 8000110:	4b1b      	ldr	r3, [pc, #108]	; (8000180 <SystemInit+0x74>)
 8000112:	4a1b      	ldr	r2, [pc, #108]	; (8000180 <SystemInit+0x74>)
 8000114:	6812      	ldr	r2, [r2, #0]
 8000116:	2101      	movs	r1, #1
 8000118:	430a      	orrs	r2, r1
 800011a:	601a      	str	r2, [r3, #0]
#if defined(STM32F051)   
  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
  RCC->CFGR &= (uint32_t)0xF8FFB80C;
#else
  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
  RCC->CFGR &= (uint32_t)0x08FFB80C;
 800011c:	4b18      	ldr	r3, [pc, #96]	; (8000180 <SystemInit+0x74>)
 800011e:	4a18      	ldr	r2, [pc, #96]	; (8000180 <SystemInit+0x74>)
 8000120:	6852      	ldr	r2, [r2, #4]
 8000122:	4918      	ldr	r1, [pc, #96]	; (8000184 <SystemInit+0x78>)
 8000124:	400a      	ands	r2, r1
 8000126:	605a      	str	r2, [r3, #4]
#endif /* STM32F051 */
  
  /* Reset HSEON, CSSON and PLLON bits */
  RCC->CR &= (uint32_t)0xFEF6FFFF;
 8000128:	4b15      	ldr	r3, [pc, #84]	; (8000180 <SystemInit+0x74>)
 800012a:	4a15      	ldr	r2, [pc, #84]	; (8000180 <SystemInit+0x74>)
 800012c:	6812      	ldr	r2, [r2, #0]
 800012e:	4916      	ldr	r1, [pc, #88]	; (8000188 <SystemInit+0x7c>)
 8000130:	400a      	ands	r2, r1
 8000132:	601a      	str	r2, [r3, #0]

  /* Reset HSEBYP bit */
  RCC->CR &= (uint32_t)0xFFFBFFFF;
 8000134:	4b12      	ldr	r3, [pc, #72]	; (8000180 <SystemInit+0x74>)
 8000136:	4a12      	ldr	r2, [pc, #72]	; (8000180 <SystemInit+0x74>)
 8000138:	6812      	ldr	r2, [r2, #0]
 800013a:	4914      	ldr	r1, [pc, #80]	; (800018c <SystemInit+0x80>)
 800013c:	400a      	ands	r2, r1
 800013e:	601a      	str	r2, [r3, #0]

  /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
  RCC->CFGR &= (uint32_t)0xFFC0FFFF;
 8000140:	4b0f      	ldr	r3, [pc, #60]	; (8000180 <SystemInit+0x74>)
 8000142:	4a0f      	ldr	r2, [pc, #60]	; (8000180 <SystemInit+0x74>)
 8000144:	6852      	ldr	r2, [r2, #4]
 8000146:	4912      	ldr	r1, [pc, #72]	; (8000190 <SystemInit+0x84>)
 8000148:	400a      	ands	r2, r1
 800014a:	605a      	str	r2, [r3, #4]

  /* Reset PREDIV1[3:0] bits */
  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
 800014c:	4b0c      	ldr	r3, [pc, #48]	; (8000180 <SystemInit+0x74>)
 800014e:	4a0c      	ldr	r2, [pc, #48]	; (8000180 <SystemInit+0x74>)
 8000150:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
 8000152:	210f      	movs	r1, #15
 8000154:	438a      	bics	r2, r1
 8000156:	62da      	str	r2, [r3, #44]	; 0x2c

  /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
  RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
 8000158:	4b09      	ldr	r3, [pc, #36]	; (8000180 <SystemInit+0x74>)
 800015a:	4a09      	ldr	r2, [pc, #36]	; (8000180 <SystemInit+0x74>)
 800015c:	6b12      	ldr	r2, [r2, #48]	; 0x30
 800015e:	490d      	ldr	r1, [pc, #52]	; (8000194 <SystemInit+0x88>)
 8000160:	400a      	ands	r2, r1
 8000162:	631a      	str	r2, [r3, #48]	; 0x30

  /* Reset HSI14 bit */
  RCC->CR2 &= (uint32_t)0xFFFFFFFE;
 8000164:	4b06      	ldr	r3, [pc, #24]	; (8000180 <SystemInit+0x74>)
 8000166:	4a06      	ldr	r2, [pc, #24]	; (8000180 <SystemInit+0x74>)
 8000168:	6b52      	ldr	r2, [r2, #52]	; 0x34
 800016a:	2101      	movs	r1, #1
 800016c:	438a      	bics	r2, r1
 800016e:	635a      	str	r2, [r3, #52]	; 0x34

  /* Disable all interrupts */
  RCC->CIR = 0x00000000;
 8000170:	4b03      	ldr	r3, [pc, #12]	; (8000180 <SystemInit+0x74>)
 8000172:	2200      	movs	r2, #0
 8000174:	609a      	str	r2, [r3, #8]

  /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
  SetSysClock();
 8000176:	f000 f879 	bl	800026c <SetSysClock>
}
 800017a:	46c0      	nop			; (mov r8, r8)
 800017c:	46bd      	mov	sp, r7
 800017e:	bd80      	pop	{r7, pc}
 8000180:	40021000 	.word	0x40021000
 8000184:	08ffb80c 	.word	0x08ffb80c
 8000188:	fef6ffff 	.word	0xfef6ffff
 800018c:	fffbffff 	.word	0xfffbffff
 8000190:	ffc0ffff 	.word	0xffc0ffff
 8000194:	fffffeac 	.word	0xfffffeac

08000198 <SystemCoreClockUpdate>:
  *           value for HSE crystal.
  * @param  None
  * @retval None
  */
void SystemCoreClockUpdate (void)
{
 8000198:	b580      	push	{r7, lr}
 800019a:	b084      	sub	sp, #16
 800019c:	af00      	add	r7, sp, #0
  uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
 800019e:	2300      	movs	r3, #0
 80001a0:	60fb      	str	r3, [r7, #12]
 80001a2:	2300      	movs	r3, #0
 80001a4:	60bb      	str	r3, [r7, #8]
 80001a6:	2300      	movs	r3, #0
 80001a8:	607b      	str	r3, [r7, #4]
 80001aa:	2300      	movs	r3, #0
 80001ac:	603b      	str	r3, [r7, #0]

  /* Get SYSCLK source -------------------------------------------------------*/
  tmp = RCC->CFGR & RCC_CFGR_SWS;
 80001ae:	4b2a      	ldr	r3, [pc, #168]	; (8000258 <SystemCoreClockUpdate+0xc0>)
 80001b0:	685b      	ldr	r3, [r3, #4]
 80001b2:	220c      	movs	r2, #12
 80001b4:	4013      	ands	r3, r2
 80001b6:	60fb      	str	r3, [r7, #12]
  
  switch (tmp)
 80001b8:	68fb      	ldr	r3, [r7, #12]
 80001ba:	2b04      	cmp	r3, #4
 80001bc:	d007      	beq.n	80001ce <SystemCoreClockUpdate+0x36>
 80001be:	2b08      	cmp	r3, #8
 80001c0:	d009      	beq.n	80001d6 <SystemCoreClockUpdate+0x3e>
 80001c2:	2b00      	cmp	r3, #0
 80001c4:	d131      	bne.n	800022a <SystemCoreClockUpdate+0x92>
  {
    case 0x00:  /* HSI used as system clock */
      SystemCoreClock = HSI_VALUE;
 80001c6:	4b25      	ldr	r3, [pc, #148]	; (800025c <SystemCoreClockUpdate+0xc4>)
 80001c8:	4a25      	ldr	r2, [pc, #148]	; (8000260 <SystemCoreClockUpdate+0xc8>)
 80001ca:	601a      	str	r2, [r3, #0]
      break;
 80001cc:	e031      	b.n	8000232 <SystemCoreClockUpdate+0x9a>
    case 0x04:  /* HSE used as system clock */
      SystemCoreClock = HSE_VALUE;
 80001ce:	4b23      	ldr	r3, [pc, #140]	; (800025c <SystemCoreClockUpdate+0xc4>)
 80001d0:	4a23      	ldr	r2, [pc, #140]	; (8000260 <SystemCoreClockUpdate+0xc8>)
 80001d2:	601a      	str	r2, [r3, #0]
      break;
 80001d4:	e02d      	b.n	8000232 <SystemCoreClockUpdate+0x9a>
    case 0x08:  /* PLL used as system clock */
      /* Get PLL clock source and multiplication factor ----------------------*/
      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
 80001d6:	4b20      	ldr	r3, [pc, #128]	; (8000258 <SystemCoreClockUpdate+0xc0>)
 80001d8:	685a      	ldr	r2, [r3, #4]
 80001da:	23f0      	movs	r3, #240	; 0xf0
 80001dc:	039b      	lsls	r3, r3, #14
 80001de:	4013      	ands	r3, r2
 80001e0:	60bb      	str	r3, [r7, #8]
      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
 80001e2:	4b1d      	ldr	r3, [pc, #116]	; (8000258 <SystemCoreClockUpdate+0xc0>)
 80001e4:	685a      	ldr	r2, [r3, #4]
 80001e6:	23c0      	movs	r3, #192	; 0xc0
 80001e8:	025b      	lsls	r3, r3, #9
 80001ea:	4013      	ands	r3, r2
 80001ec:	607b      	str	r3, [r7, #4]
      pllmull = ( pllmull >> 18) + 2;
 80001ee:	68bb      	ldr	r3, [r7, #8]
 80001f0:	0c9b      	lsrs	r3, r3, #18
 80001f2:	3302      	adds	r3, #2
 80001f4:	60bb      	str	r3, [r7, #8]
      
      if (pllsource == 0x00)
 80001f6:	687b      	ldr	r3, [r7, #4]
 80001f8:	2b00      	cmp	r3, #0
 80001fa:	d105      	bne.n	8000208 <SystemCoreClockUpdate+0x70>
      {
        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
 80001fc:	68bb      	ldr	r3, [r7, #8]
 80001fe:	4a19      	ldr	r2, [pc, #100]	; (8000264 <SystemCoreClockUpdate+0xcc>)
 8000200:	435a      	muls	r2, r3
 8000202:	4b16      	ldr	r3, [pc, #88]	; (800025c <SystemCoreClockUpdate+0xc4>)
 8000204:	601a      	str	r2, [r3, #0]
      {
        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
        /* HSE oscillator clock selected as PREDIV1 clock entry */
        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
      }      
      break;
 8000206:	e014      	b.n	8000232 <SystemCoreClockUpdate+0x9a>
        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
      }
      else
      {
        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
 8000208:	4b13      	ldr	r3, [pc, #76]	; (8000258 <SystemCoreClockUpdate+0xc0>)
 800020a:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 800020c:	220f      	movs	r2, #15
 800020e:	4013      	ands	r3, r2
 8000210:	3301      	adds	r3, #1
 8000212:	603b      	str	r3, [r7, #0]
        /* HSE oscillator clock selected as PREDIV1 clock entry */
        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
 8000214:	6839      	ldr	r1, [r7, #0]
 8000216:	4812      	ldr	r0, [pc, #72]	; (8000260 <SystemCoreClockUpdate+0xc8>)
 8000218:	f000 f8ba 	bl	8000390 <__aeabi_uidiv>
 800021c:	0003      	movs	r3, r0
 800021e:	001a      	movs	r2, r3
 8000220:	68bb      	ldr	r3, [r7, #8]
 8000222:	435a      	muls	r2, r3
 8000224:	4b0d      	ldr	r3, [pc, #52]	; (800025c <SystemCoreClockUpdate+0xc4>)
 8000226:	601a      	str	r2, [r3, #0]
      }      
      break;
 8000228:	e003      	b.n	8000232 <SystemCoreClockUpdate+0x9a>
    default: /* HSI used as system clock */
      SystemCoreClock = HSI_VALUE;
 800022a:	4b0c      	ldr	r3, [pc, #48]	; (800025c <SystemCoreClockUpdate+0xc4>)
 800022c:	4a0c      	ldr	r2, [pc, #48]	; (8000260 <SystemCoreClockUpdate+0xc8>)
 800022e:	601a      	str	r2, [r3, #0]
      break;
 8000230:	46c0      	nop			; (mov r8, r8)
  }
  /* Compute HCLK clock frequency ----------------*/
  /* Get HCLK prescaler */
  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
 8000232:	4b09      	ldr	r3, [pc, #36]	; (8000258 <SystemCoreClockUpdate+0xc0>)
 8000234:	685b      	ldr	r3, [r3, #4]
 8000236:	22f0      	movs	r2, #240	; 0xf0
 8000238:	4013      	ands	r3, r2
 800023a:	091b      	lsrs	r3, r3, #4
 800023c:	4a0a      	ldr	r2, [pc, #40]	; (8000268 <SystemCoreClockUpdate+0xd0>)
 800023e:	5cd3      	ldrb	r3, [r2, r3]
 8000240:	b2db      	uxtb	r3, r3
 8000242:	60fb      	str	r3, [r7, #12]
  /* HCLK clock frequency */
  SystemCoreClock >>= tmp;  
 8000244:	4b05      	ldr	r3, [pc, #20]	; (800025c <SystemCoreClockUpdate+0xc4>)
 8000246:	681a      	ldr	r2, [r3, #0]
 8000248:	68fb      	ldr	r3, [r7, #12]
 800024a:	40da      	lsrs	r2, r3
 800024c:	4b03      	ldr	r3, [pc, #12]	; (800025c <SystemCoreClockUpdate+0xc4>)
 800024e:	601a      	str	r2, [r3, #0]
}
 8000250:	46c0      	nop			; (mov r8, r8)
 8000252:	46bd      	mov	sp, r7
 8000254:	b004      	add	sp, #16
 8000256:	bd80      	pop	{r7, pc}
 8000258:	40021000 	.word	0x40021000
 800025c:	20000000 	.word	0x20000000
 8000260:	007a1200 	.word	0x007a1200
 8000264:	003d0900 	.word	0x003d0900
 8000268:	20000004 	.word	0x20000004

0800026c <SetSysClock>:
  *         is reset to the default reset state (done in SystemInit() function).
  * @param  None
  * @retval None
  */
static void SetSysClock(void)
{
 800026c:	b580      	push	{r7, lr}
 800026e:	b082      	sub	sp, #8
 8000270:	af00      	add	r7, sp, #0
  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
 8000272:	2300      	movs	r3, #0
 8000274:	607b      	str	r3, [r7, #4]
 8000276:	2300      	movs	r3, #0
 8000278:	603b      	str	r3, [r7, #0]
/*            PLL (clocked by HSE) used as System clock source                */
/******************************************************************************/
  
  /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
  /* Enable HSE */    
  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
 800027a:	4b31      	ldr	r3, [pc, #196]	; (8000340 <SetSysClock+0xd4>)
 800027c:	4a30      	ldr	r2, [pc, #192]	; (8000340 <SetSysClock+0xd4>)
 800027e:	6812      	ldr	r2, [r2, #0]
 8000280:	2180      	movs	r1, #128	; 0x80
 8000282:	0249      	lsls	r1, r1, #9
 8000284:	430a      	orrs	r2, r1
 8000286:	601a      	str	r2, [r3, #0]
 
  /* Wait till HSE is ready and if Time out is reached exit */
  do
  {
    HSEStatus = RCC->CR & RCC_CR_HSERDY;
 8000288:	4b2d      	ldr	r3, [pc, #180]	; (8000340 <SetSysClock+0xd4>)
 800028a:	681a      	ldr	r2, [r3, #0]
 800028c:	2380      	movs	r3, #128	; 0x80
 800028e:	029b      	lsls	r3, r3, #10
 8000290:	4013      	ands	r3, r2
 8000292:	603b      	str	r3, [r7, #0]
    StartUpCounter++;  
 8000294:	687b      	ldr	r3, [r7, #4]
 8000296:	3301      	adds	r3, #1
 8000298:	607b      	str	r3, [r7, #4]
  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
 800029a:	683b      	ldr	r3, [r7, #0]
 800029c:	2b00      	cmp	r3, #0
 800029e:	d104      	bne.n	80002aa <SetSysClock+0x3e>
 80002a0:	687a      	ldr	r2, [r7, #4]
 80002a2:	23a0      	movs	r3, #160	; 0xa0
 80002a4:	01db      	lsls	r3, r3, #7
 80002a6:	429a      	cmp	r2, r3
 80002a8:	d1ee      	bne.n	8000288 <SetSysClock+0x1c>

  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
 80002aa:	4b25      	ldr	r3, [pc, #148]	; (8000340 <SetSysClock+0xd4>)
 80002ac:	681a      	ldr	r2, [r3, #0]
 80002ae:	2380      	movs	r3, #128	; 0x80
 80002b0:	029b      	lsls	r3, r3, #10
 80002b2:	4013      	ands	r3, r2
 80002b4:	d002      	beq.n	80002bc <SetSysClock+0x50>
  {
    HSEStatus = (uint32_t)0x01;
 80002b6:	2301      	movs	r3, #1
 80002b8:	603b      	str	r3, [r7, #0]
 80002ba:	e001      	b.n	80002c0 <SetSysClock+0x54>
  }
  else
  {
    HSEStatus = (uint32_t)0x00;
 80002bc:	2300      	movs	r3, #0
 80002be:	603b      	str	r3, [r7, #0]
  }  

  if (HSEStatus == (uint32_t)0x01)
 80002c0:	683b      	ldr	r3, [r7, #0]
 80002c2:	2b01      	cmp	r3, #1
 80002c4:	d138      	bne.n	8000338 <SetSysClock+0xcc>
  {
    /* Enable Prefetch Buffer and set Flash Latency */
    FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
 80002c6:	4b1f      	ldr	r3, [pc, #124]	; (8000344 <SetSysClock+0xd8>)
 80002c8:	2211      	movs	r2, #17
 80002ca:	601a      	str	r2, [r3, #0]
 
    /* HCLK = SYSCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
 80002cc:	4b1c      	ldr	r3, [pc, #112]	; (8000340 <SetSysClock+0xd4>)
 80002ce:	4a1c      	ldr	r2, [pc, #112]	; (8000340 <SetSysClock+0xd4>)
 80002d0:	6852      	ldr	r2, [r2, #4]
 80002d2:	605a      	str	r2, [r3, #4]
      
    /* PCLK = HCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
 80002d4:	4b1a      	ldr	r3, [pc, #104]	; (8000340 <SetSysClock+0xd4>)
 80002d6:	4a1a      	ldr	r2, [pc, #104]	; (8000340 <SetSysClock+0xd4>)
 80002d8:	6852      	ldr	r2, [r2, #4]
 80002da:	605a      	str	r2, [r3, #4]

    /* PLL configuration */
    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
 80002dc:	4b18      	ldr	r3, [pc, #96]	; (8000340 <SetSysClock+0xd4>)
 80002de:	4a18      	ldr	r2, [pc, #96]	; (8000340 <SetSysClock+0xd4>)
 80002e0:	6852      	ldr	r2, [r2, #4]
 80002e2:	4919      	ldr	r1, [pc, #100]	; (8000348 <SetSysClock+0xdc>)
 80002e4:	400a      	ands	r2, r1
 80002e6:	605a      	str	r2, [r3, #4]
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6);
 80002e8:	4b15      	ldr	r3, [pc, #84]	; (8000340 <SetSysClock+0xd4>)
 80002ea:	4a15      	ldr	r2, [pc, #84]	; (8000340 <SetSysClock+0xd4>)
 80002ec:	6852      	ldr	r2, [r2, #4]
 80002ee:	2188      	movs	r1, #136	; 0x88
 80002f0:	0349      	lsls	r1, r1, #13
 80002f2:	430a      	orrs	r2, r1
 80002f4:	605a      	str	r2, [r3, #4]
            
    /* Enable PLL */
    RCC->CR |= RCC_CR_PLLON;
 80002f6:	4b12      	ldr	r3, [pc, #72]	; (8000340 <SetSysClock+0xd4>)
 80002f8:	4a11      	ldr	r2, [pc, #68]	; (8000340 <SetSysClock+0xd4>)
 80002fa:	6812      	ldr	r2, [r2, #0]
 80002fc:	2180      	movs	r1, #128	; 0x80
 80002fe:	0449      	lsls	r1, r1, #17
 8000300:	430a      	orrs	r2, r1
 8000302:	601a      	str	r2, [r3, #0]

    /* Wait till PLL is ready */
    while((RCC->CR & RCC_CR_PLLRDY) == 0)
 8000304:	46c0      	nop			; (mov r8, r8)
 8000306:	4b0e      	ldr	r3, [pc, #56]	; (8000340 <SetSysClock+0xd4>)
 8000308:	681a      	ldr	r2, [r3, #0]
 800030a:	2380      	movs	r3, #128	; 0x80
 800030c:	049b      	lsls	r3, r3, #18
 800030e:	4013      	ands	r3, r2
 8000310:	d0f9      	beq.n	8000306 <SetSysClock+0x9a>
    {
    }

    /* Select PLL as system clock source */
    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
 8000312:	4b0b      	ldr	r3, [pc, #44]	; (8000340 <SetSysClock+0xd4>)
 8000314:	4a0a      	ldr	r2, [pc, #40]	; (8000340 <SetSysClock+0xd4>)
 8000316:	6852      	ldr	r2, [r2, #4]
 8000318:	2103      	movs	r1, #3
 800031a:	438a      	bics	r2, r1
 800031c:	605a      	str	r2, [r3, #4]
    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
 800031e:	4b08      	ldr	r3, [pc, #32]	; (8000340 <SetSysClock+0xd4>)
 8000320:	4a07      	ldr	r2, [pc, #28]	; (8000340 <SetSysClock+0xd4>)
 8000322:	6852      	ldr	r2, [r2, #4]
 8000324:	2102      	movs	r1, #2
 8000326:	430a      	orrs	r2, r1
 8000328:	605a      	str	r2, [r3, #4]

    /* Wait till PLL is used as system clock source */
    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
 800032a:	46c0      	nop			; (mov r8, r8)
 800032c:	4b04      	ldr	r3, [pc, #16]	; (8000340 <SetSysClock+0xd4>)
 800032e:	685b      	ldr	r3, [r3, #4]
 8000330:	220c      	movs	r2, #12
 8000332:	4013      	ands	r3, r2
 8000334:	2b08      	cmp	r3, #8
 8000336:	d1f9      	bne.n	800032c <SetSysClock+0xc0>
  }
  else
  { /* If HSE fails to start-up, the application will have wrong clock 
         configuration. User can add here some code to deal with this error */
  }  
}
 8000338:	46c0      	nop			; (mov r8, r8)
 800033a:	46bd      	mov	sp, r7
 800033c:	b002      	add	sp, #8
 800033e:	bd80      	pop	{r7, pc}
 8000340:	40021000 	.word	0x40021000
 8000344:	40022000 	.word	0x40022000
 8000348:	ffc07fff 	.word	0xffc07fff

0800034c <main>:
*/

volatile int iee=0;

int main()
{
 800034c:	b580      	push	{r7, lr}
 800034e:	b082      	sub	sp, #8
 8000350:	af00      	add	r7, sp, #0
    while(1)
    {
//	GPIOA -> BSRR = GPIO_Pin_1;
//	for (int i=0; i<100000 ; i++);
//	GPIOA -> BSRR = GPIO_Pin_1;
	for (int i=0; i<10000000 ; i++);
 8000352:	2300      	movs	r3, #0
 8000354:	607b      	str	r3, [r7, #4]
 8000356:	e002      	b.n	800035e <main+0x12>
 8000358:	687b      	ldr	r3, [r7, #4]
 800035a:	3301      	adds	r3, #1
 800035c:	607b      	str	r3, [r7, #4]
 800035e:	687b      	ldr	r3, [r7, #4]
 8000360:	4a04      	ldr	r2, [pc, #16]	; (8000374 <main+0x28>)
 8000362:	4293      	cmp	r3, r2
 8000364:	ddf8      	ble.n	8000358 <main+0xc>
    iee++;
 8000366:	4b04      	ldr	r3, [pc, #16]	; (8000378 <main+0x2c>)
 8000368:	681b      	ldr	r3, [r3, #0]
 800036a:	1c5a      	adds	r2, r3, #1
 800036c:	4b02      	ldr	r3, [pc, #8]	; (8000378 <main+0x2c>)
 800036e:	601a      	str	r2, [r3, #0]
    }
 8000370:	e7ef      	b.n	8000352 <main+0x6>
 8000372:	46c0      	nop			; (mov r8, r8)
 8000374:	0098967f 	.word	0x0098967f
 8000378:	20000014 	.word	0x20000014
 800037c:	080004f0 	.word	0x080004f0
 8000380:	20000000 	.word	0x20000000
 8000384:	20000014 	.word	0x20000014
 8000388:	20000014 	.word	0x20000014
 800038c:	20000018 	.word	0x20000018

08000390 <__aeabi_uidiv>:
 8000390:	e2512001 	subs	r2, r1, #1
 8000394:	012fff1e 	bxeq	lr
 8000398:	3a000036 	bcc	8000478 <__aeabi_uidiv+0xe8>
 800039c:	e1500001 	cmp	r0, r1
 80003a0:	9a000022 	bls	8000430 <__aeabi_uidiv+0xa0>
 80003a4:	e1110002 	tst	r1, r2
 80003a8:	0a000023 	beq	800043c <__aeabi_uidiv+0xac>
 80003ac:	e311020e 	tst	r1, #-536870912	; 0xe0000000
 80003b0:	01a01181 	lsleq	r1, r1, #3
 80003b4:	03a03008 	moveq	r3, #8
 80003b8:	13a03001 	movne	r3, #1
 80003bc:	e3510201 	cmp	r1, #268435456	; 0x10000000
 80003c0:	31510000 	cmpcc	r1, r0
 80003c4:	31a01201 	lslcc	r1, r1, #4
 80003c8:	31a03203 	lslcc	r3, r3, #4
 80003cc:	3afffffa 	bcc	80003bc <__aeabi_uidiv+0x2c>
 80003d0:	e3510102 	cmp	r1, #-2147483648	; 0x80000000
 80003d4:	31510000 	cmpcc	r1, r0
 80003d8:	31a01081 	lslcc	r1, r1, #1
 80003dc:	31a03083 	lslcc	r3, r3, #1
 80003e0:	3afffffa 	bcc	80003d0 <__aeabi_uidiv+0x40>
 80003e4:	e3a02000 	mov	r2, #0
 80003e8:	e1500001 	cmp	r0, r1
 80003ec:	20400001 	subcs	r0, r0, r1
 80003f0:	21822003 	orrcs	r2, r2, r3
 80003f4:	e15000a1 	cmp	r0, r1, lsr #1
 80003f8:	204000a1 	subcs	r0, r0, r1, lsr #1
 80003fc:	218220a3 	orrcs	r2, r2, r3, lsr #1
 8000400:	e1500121 	cmp	r0, r1, lsr #2
 8000404:	20400121 	subcs	r0, r0, r1, lsr #2
 8000408:	21822123 	orrcs	r2, r2, r3, lsr #2
 800040c:	e15001a1 	cmp	r0, r1, lsr #3
 8000410:	204001a1 	subcs	r0, r0, r1, lsr #3
 8000414:	218221a3 	orrcs	r2, r2, r3, lsr #3
 8000418:	e3500000 	cmp	r0, #0
 800041c:	11b03223 	lsrsne	r3, r3, #4
 8000420:	11a01221 	lsrne	r1, r1, #4
 8000424:	1affffef 	bne	80003e8 <__aeabi_uidiv+0x58>
 8000428:	e1a00002 	mov	r0, r2
 800042c:	e12fff1e 	bx	lr
 8000430:	03a00001 	moveq	r0, #1
 8000434:	13a00000 	movne	r0, #0
 8000438:	e12fff1e 	bx	lr
 800043c:	e3510801 	cmp	r1, #65536	; 0x10000
 8000440:	21a01821 	lsrcs	r1, r1, #16
 8000444:	23a02010 	movcs	r2, #16
 8000448:	33a02000 	movcc	r2, #0
 800044c:	e3510c01 	cmp	r1, #256	; 0x100
 8000450:	21a01421 	lsrcs	r1, r1, #8
 8000454:	22822008 	addcs	r2, r2, #8
 8000458:	e3510010 	cmp	r1, #16
 800045c:	21a01221 	lsrcs	r1, r1, #4
 8000460:	22822004 	addcs	r2, r2, #4
 8000464:	e3510004 	cmp	r1, #4
 8000468:	82822003 	addhi	r2, r2, #3
 800046c:	908220a1 	addls	r2, r2, r1, lsr #1
 8000470:	e1a00230 	lsr	r0, r0, r2
 8000474:	e12fff1e 	bx	lr
 8000478:	e3500000 	cmp	r0, #0
 800047c:	13e00000 	mvnne	r0, #0
 8000480:	ea000007 	b	80004a4 <__aeabi_idiv0>

08000484 <__aeabi_uidivmod>:
 8000484:	e3510000 	cmp	r1, #0
 8000488:	0afffffa 	beq	8000478 <__aeabi_uidiv+0xe8>
 800048c:	e92d4003 	push	{r0, r1, lr}
 8000490:	ebffffbe 	bl	8000390 <__aeabi_uidiv>
 8000494:	e8bd4006 	pop	{r1, r2, lr}
 8000498:	e0030092 	mul	r3, r2, r0
 800049c:	e0411003 	sub	r1, r1, r3
 80004a0:	e12fff1e 	bx	lr

080004a4 <__aeabi_idiv0>:
 80004a4:	e12fff1e 	bx	lr

080004a8 <Reset_Handler>:
	.weak	Reset_Handler
	.type	Reset_Handler, %function
Reset_Handler:	

/* Copy the data segment initializers from flash to SRAM */  
  movs	r1, #0
 80004a8:	2100      	movs	r1, #0
  b	LoopCopyDataInit
 80004aa:	e003      	b.n	80004b4 <LoopCopyDataInit>

080004ac <CopyDataInit>:

CopyDataInit:
	ldr	r3, =_sidata
 80004ac:	4b0a      	ldr	r3, [pc, #40]	; (80004d8 <LoopFillZerobss+0x10>)
	ldr	r3, [r3, r1]
 80004ae:	585b      	ldr	r3, [r3, r1]
	str	r3, [r0, r1]
 80004b0:	5043      	str	r3, [r0, r1]
	adds	r1, r1, #4
 80004b2:	3104      	adds	r1, #4

080004b4 <LoopCopyDataInit>:
    
LoopCopyDataInit:
	ldr	r0, =_sdata
 80004b4:	4809      	ldr	r0, [pc, #36]	; (80004dc <LoopFillZerobss+0x14>)
	ldr	r3, =_edata
 80004b6:	4b0a      	ldr	r3, [pc, #40]	; (80004e0 <LoopFillZerobss+0x18>)
	adds	r2, r0, r1
 80004b8:	1842      	adds	r2, r0, r1
	cmp	r2, r3
 80004ba:	429a      	cmp	r2, r3
	bcc	CopyDataInit
 80004bc:	d3f6      	bcc.n	80004ac <CopyDataInit>
	ldr	r2, =_sbss
 80004be:	4a09      	ldr	r2, [pc, #36]	; (80004e4 <LoopFillZerobss+0x1c>)
	b	LoopFillZerobss
 80004c0:	e002      	b.n	80004c8 <LoopFillZerobss>

080004c2 <FillZerobss>:
/* Zero fill the bss segment. */  
FillZerobss:
	movs	r3, #0
 80004c2:	2300      	movs	r3, #0
	str	r3, [r2], #4
 80004c4:	f842 3b04 	str.w	r3, [r2], #4

080004c8 <LoopFillZerobss>:
    
LoopFillZerobss:
	ldr	r3, = _ebss
 80004c8:	4b07      	ldr	r3, [pc, #28]	; (80004e8 <LoopFillZerobss+0x20>)
	cmp	r2, r3
 80004ca:	429a      	cmp	r2, r3
	bcc	FillZerobss
 80004cc:	d3f9      	bcc.n	80004c2 <FillZerobss>
/* Call the clock system intitialization function.*/
  bl  SystemInit  
 80004ce:	f7ff fe1d 	bl	800010c <SystemInit>
/* Call the application's entry point.*/
	bl	main
 80004d2:	f7ff ff3b 	bl	800034c <main>
	bx	lr    
 80004d6:	4770      	bx	lr
/* Copy the data segment initializers from flash to SRAM */  
  movs	r1, #0
  b	LoopCopyDataInit

CopyDataInit:
	ldr	r3, =_sidata
 80004d8:	080004f0 	.word	0x080004f0
	ldr	r3, [r3, r1]
	str	r3, [r0, r1]
	adds	r1, r1, #4
    
LoopCopyDataInit:
	ldr	r0, =_sdata
 80004dc:	20000000 	.word	0x20000000
	ldr	r3, =_edata
 80004e0:	20000014 	.word	0x20000014
	adds	r2, r0, r1
	cmp	r2, r3
	bcc	CopyDataInit
	ldr	r2, =_sbss
 80004e4:	20000014 	.word	0x20000014
FillZerobss:
	movs	r3, #0
	str	r3, [r2], #4
    
LoopFillZerobss:
	ldr	r3, = _ebss
 80004e8:	20000018 	.word	0x20000018

080004ec <ADC1_2_IRQHandler>:
 * @retval None       
*/
    .section	.text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
	b	Infinite_Loop
 80004ec:	e7fe      	b.n	80004ec <ADC1_2_IRQHandler>
	...