main.c 22 KB

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  1. #include <stdint.h>
  2. #include "system_stm32f10x.h"
  3. #include "system_stm32f10x.c"
  4. #define SD_BUFSIZE 512
  5. #define SD_BUFVALUES (SD_BUFSIZE / (sizeof(uint16_t)))
  6. #define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
  7. #define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
  8. #define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
  9. #define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
  10. #define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
  11. #define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
  12. #define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
  13. #define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
  14. #define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
  15. #define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
  16. #define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
  17. #define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
  18. #define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
  19. #define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
  20. #define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
  21. #define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
  22. #define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
  23. #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
  24. #define SPI_Mode_Master ((uint16_t)0x0104)
  25. #define SPI_DataSize_8b ((uint16_t)0x0000)
  26. #define SPI_CPOL_High ((uint16_t)0x0002)
  27. #define SPI_CPHA_2Edge ((uint16_t)0x0001)
  28. #define SPI_NSS_Soft ((uint16_t)0x0200)
  29. #define SPI_NSS_Hard ((uint16_t)0x0000)
  30. #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || ((NSS) == SPI_NSS_Hard))
  31. #define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
  32. #define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
  33. #define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
  34. #define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
  35. #define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
  36. #define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
  37. #define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
  38. #define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
  39. #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
  40. ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
  41. ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
  42. ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
  43. ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
  44. ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
  45. ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
  46. ((PRESCALER) == SPI_BaudRatePrescaler_256))
  47. #define SPI_FirstBit_MSB ((uint16_t)0x0000)
  48. #define SPI_FirstBit_LSB ((uint16_t)0x0080)
  49. #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || ((BIT) == SPI_FirstBit_LSB))
  50. #define SD_CMD_GO_IDLE_STATE 0 /*!< CMD0 = 0x40 */
  51. #define SD_CMD_SEND_OP_COND 1 /*!< CMD1 = 0x41 */
  52. #define SD_CMD_SEND_CSD 9 /*!< CMD9 = 0x49 */
  53. #define SD_CMD_SEND_CID 10 /*!< CMD10 = 0x4A */
  54. #define SD_CMD_STOP_TRANSMISSION 12 /*!< CMD12 = 0x4C */
  55. #define SD_CMD_SEND_STATUS 13 /*!< CMD13 = 0x4D */
  56. #define SD_CMD_SET_BLOCKLEN 16 /*!< CMD16 = 0x50 */
  57. #define SD_CMD_READ_SINGLE_BLOCK 17 /*!< CMD17 = 0x51 */
  58. #define SD_CMD_READ_MULT_BLOCK 18 /*!< CMD18 = 0x52 */
  59. #define SD_CMD_SET_BLOCK_COUNT 23 /*!< CMD23 = 0x57 */
  60. #define SD_CMD_WRITE_SINGLE_BLOCK 24 /*!< CMD24 = 0x58 */
  61. #define SD_CMD_WRITE_MULT_BLOCK 25 /*!< CMD25 = 0x59 */
  62. #define SD_CMD_PROG_CSD 27 /*!< CMD27 = 0x5B */
  63. #define SD_CMD_SET_WRITE_PROT 28 /*!< CMD28 = 0x5C */
  64. #define SD_CMD_CLR_WRITE_PROT 29 /*!< CMD29 = 0x5D */
  65. #define SD_CMD_SEND_WRITE_PROT 30 /*!< CMD30 = 0x5E */
  66. #define SD_CMD_SD_ERASE_GRP_START 32 /*!< CMD32 = 0x60 */
  67. #define SD_CMD_SD_ERASE_GRP_END 33 /*!< CMD33 = 0x61 */
  68. #define SD_CMD_UNTAG_SECTOR 34 /*!< CMD34 = 0x62 */
  69. #define SD_CMD_ERASE_GRP_START 35 /*!< CMD35 = 0x63 */
  70. #define SD_CMD_ERASE_GRP_END 36 /*!< CMD36 = 0x64 */
  71. #define SD_CMD_UNTAG_ERASE_GROUP 37 /*!< CMD37 = 0x65 */
  72. #define SD_CMD_ERASE 38 /*!< CMD38 = 0x66 */
  73. #define SD_SPI SPI1
  74. #define SD_SPI_CLK RCC_APB2Periph_SPI1
  75. #define SD_SPI_SCK_PIN GPIO_Pin_5 /* PA.05 */
  76. #define SD_SPI_SCK_GPIO_PORT GPIOA /* GPIOA */
  77. #define SD_SPI_SCK_GPIO_CLK RCC_APB2Periph_GPIOA
  78. #define SD_SPI_MISO_PIN GPIO_Pin_6 /* PA.06 */
  79. #define SD_SPI_MISO_GPIO_PORT GPIOA /* GPIOA */
  80. #define SD_SPI_MISO_GPIO_CLK RCC_APB2Periph_GPIOA
  81. #define SD_SPI_MOSI_PIN GPIO_Pin_7 /* PA.07 */
  82. #define SD_SPI_MOSI_GPIO_PORT GPIOA /* GPIOA */
  83. #define SD_SPI_MOSI_GPIO_CLK RCC_APB2Periph_GPIOA
  84. #define SD_CS_PIN GPIO_Pin_4 /* PC.12 */
  85. #define SD_CS_GPIO_PORT GPIOA /* GPIOC */
  86. #define SD_CS_GPIO_CLK RCC_APB2Periph_GPIOA
  87. #define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
  88. #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
  89. #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00))
  90. #define CR1_CLEAR_Mask ((uint16_t)0x3040)
  91. #define SPI_Mode_Select ((uint16_t)0xF7FF)
  92. #define CR1_SPE_Set ((uint16_t)0x0040)
  93. #define CR1_SPE_Reset ((uint16_t)0xFFBF)
  94. #define SD_CS_LOW() GPIO_ResetBits(SD_CS_GPIO_PORT, SD_CS_PIN)
  95. #define SD_CS_HIGH() GPIO_SetBits(SD_CS_GPIO_PORT, SD_CS_PIN)
  96. #define SD_DUMMY_BYTE 0xFF
  97. #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
  98. #define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
  99. #define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
  100. #define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
  101. #define I2S_FLAG_UDR ((uint16_t)0x0008)
  102. #define SPI_FLAG_CRCERR ((uint16_t)0x0010)
  103. #define SPI_FLAG_MODF ((uint16_t)0x0020)
  104. #define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
  105. #define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
  106. #define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
  107. #define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
  108. ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
  109. ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
  110. ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))
  111. #define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */
  112. #define ADC_DataAlign_Right ((uint32_t)0x00000000)
  113. #define ADC_Channel_0 ((uint8_t)0x00)
  114. #define ADC_Mode_Independent ((uint32_t)0x00000000)
  115. #ifdef USE_FULL_ASSERT
  116. #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
  117. void assert_failed(uint8_t* file, uint32_t line);
  118. #else
  119. #define assert_param(expr) ((void)0)
  120. #endif /* USE_FULL_ASSERT */
  121. typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
  122. int status = 10;
  123. volatile long int aa=0, bb;
  124. uint16_t SDWriteBuffer[SD_BUFVALUES];
  125. TestStatus TransferStatus = FAILED;
  126. uint16_t SD_Status = 0xFFFF;
  127. uint16_t writeBufFilled = 0;
  128. volatile uint32_t SDWriteOffset = 0;
  129. volatile uint16_t ADC1ConvertedValue = 0;
  130. uint16_t Buffer1[256] = {0}, Buffer2[256] = {0};
  131. uint8_t BuffReady = 0, BuffCount = 0, Rstatus = 1, Wstatus = 2, check = 0;
  132. uint16_t TMSTP = 0;
  133. typedef struct
  134. {
  135. uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or
  136. dual mode.
  137. This parameter can be a value of @ref ADC_mode */
  138. FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in
  139. Scan (multichannels) or Single (one channel) mode.
  140. This parameter can be set to ENABLE or DISABLE */
  141. FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
  142. Continuous or Single mode.
  143. This parameter can be set to ENABLE or DISABLE. */
  144. uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog
  145. to digital conversion of regular channels. This parameter
  146. can be a value of @ref ADC_external_trigger_sources_for_regular_channels_convers*/
  147. uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
  148. This parameter can be a value of @ref ADC_data_align */
  149. uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted
  150. using the sequencer for regular channel group.
  151. This parameter must range from 1 to 16. */
  152. }ADC_InitTypeDef;
  153. typedef struct
  154. {
  155. uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */
  156. uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */
  157. uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */
  158. uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */
  159. uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */
  160. }RCC_ClocksTypeDef;
  161. typedef struct
  162. {
  163. uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
  164. This parameter can be a value of @ref SPI_data_direction */
  165. uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.
  166. This parameter can be a value of @ref SPI_mode */
  167. uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
  168. This parameter can be a value of @ref SPI_data_size */
  169. uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
  170. This parameter can be a value of @ref SPI_Clock_Polarity */
  171. uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
  172. This parameter can be a value of @ref SPI_Clock_Phase */
  173. uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
  174. hardware (NSS pin) or by software using the SSI bit.
  175. This parameter can be a value of @ref SPI_Slave_Select_management */
  176. uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
  177. used to configure the transmit and receive SCK clock.
  178. This parameter can be a value of @ref SPI_BaudRate_Prescaler.
  179. @note The communication clock is derived from the master
  180. clock. The slave clock does not need to be set. */
  181. uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
  182. This parameter can be a value of @ref SPI_MSB_LSB_transmission */
  183. uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
  184. }SPI_InitTypeDef;
  185. typedef enum
  186. { Bit_RESET = 0,
  187. Bit_SET
  188. }BitAction;
  189. typedef enum
  190. {
  191. GPIO_Speed_10MHz = 1,
  192. GPIO_Speed_2MHz,
  193. GPIO_Speed_50MHz
  194. }GPIOSpeed_TypeDef;
  195. /**
  196. * @brief Configuration Mode enumeration
  197. */
  198. typedef enum
  199. { GPIO_Mode_AIN = 0x0,
  200. GPIO_Mode_IN_FLOATING = 0x04,
  201. GPIO_Mode_IPD = 0x28,
  202. GPIO_Mode_IPU = 0x48,
  203. GPIO_Mode_Out_OD = 0x14,
  204. GPIO_Mode_Out_PP = 0x10,
  205. GPIO_Mode_AF_OD = 0x1C,
  206. GPIO_Mode_AF_PP = 0x18
  207. }GPIOMode_TypeDef;
  208. typedef struct
  209. {
  210. uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
  211. This parameter can be any value of @ref GPIO_pins_define */
  212. GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
  213. This parameter can be a value of @ref GPIOSpeed_TypeDef */
  214. GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
  215. This parameter can be a value of @ref GPIOMode_TypeDef */
  216. }GPIO_InitTypeDef;
  217. typedef enum
  218. {
  219. /**
  220. * @brief SD reponses and error flags
  221. */
  222. SD_RESPONSE_NO_ERROR = (0x00),
  223. SD_IN_IDLE_STATE = (0x01),
  224. SD_ERASE_RESET = (0x02),
  225. SD_ILLEGAL_COMMAND = (0x04),
  226. SD_COM_CRC_ERROR = (0x08),
  227. SD_ERASE_SEQUENCE_ERROR = (0x10),
  228. SD_ADDRESS_ERROR = (0x20),
  229. SD_PARAMETER_ERROR = (0x40),
  230. SD_RESPONSE_FAILURE = (0xFF),
  231. /**
  232. * @brief Data response error
  233. */
  234. SD_DATA_OK = (0x05),
  235. SD_DATA_CRC_ERROR = (0x0B),
  236. SD_DATA_WRITE_ERROR = (0x0D),
  237. SD_DATA_OTHER_ERROR = (0xFF)
  238. } SD_Error;
  239. void SD_LowLevel_Init(void);
  240. void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
  241. void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
  242. void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
  243. void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
  244. void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
  245. void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
  246. void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
  247. void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
  248. uint8_t SD_WriteByte(uint8_t byte);
  249. uint8_t SD_ReadByte(void);
  250. FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
  251. void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
  252. uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
  253. SD_Error SD_GoIdleState(void);
  254. void SD_SendCmd(uint8_t Cmd, uint32_t Arg, uint8_t Crc);
  255. SD_Error SD_GetResponse(uint8_t Response);
  256. uint8_t SD_GetDataResponse(void);
  257. void ADC_DeInit(ADC_TypeDef* ADCx);
  258. void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
  259. void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
  260. void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
  261. void ADC_ResetCalibration(ADC_TypeDef* ADCx);
  262. FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
  263. void ADC_StartCalibration(ADC_TypeDef* ADCx);
  264. FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
  265. void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
  266. void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
  267. {
  268. uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
  269. uint32_t tmpreg = 0x00, pinmask = 0x00;
  270. /* Check the parameters */
  271. assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
  272. assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
  273. assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
  274. /*---------------------------- GPIO Mode Configuration -----------------------*/
  275. currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
  276. if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
  277. {
  278. /* Check the parameters */
  279. assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
  280. /* Output mode */
  281. currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
  282. }
  283. /*---------------------------- GPIO CRL Configuration ------------------------*/
  284. /* Configure the eight low port pins */
  285. if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
  286. {
  287. tmpreg = GPIOx->CRL;
  288. for (pinpos = 0x00; pinpos < 0x08; pinpos++)
  289. {
  290. pos = ((uint32_t)0x01) << pinpos;
  291. /* Get the port pins position */
  292. currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
  293. if (currentpin == pos)
  294. {
  295. pos = pinpos << 2;
  296. /* Clear the corresponding low control register bits */
  297. pinmask = ((uint32_t)0x0F) << pos;
  298. tmpreg &= ~pinmask;
  299. /* Write the mode configuration in the corresponding bits */
  300. tmpreg |= (currentmode << pos);
  301. /* Reset the corresponding ODR bit */
  302. if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
  303. {
  304. GPIOx->BRR = (((uint32_t)0x01) << pinpos);
  305. }
  306. else
  307. {
  308. /* Set the corresponding ODR bit */
  309. if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
  310. {
  311. GPIOx->BSRR = (((uint32_t)0x01) << pinpos);
  312. }
  313. }
  314. }
  315. }
  316. GPIOx->CRL = tmpreg;
  317. }
  318. /*---------------------------- GPIO CRH Configuration ------------------------*/
  319. /* Configure the eight high port pins */
  320. if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
  321. {
  322. tmpreg = GPIOx->CRH;
  323. for (pinpos = 0x00; pinpos < 0x08; pinpos++)
  324. {
  325. pos = (((uint32_t)0x01) << (pinpos + 0x08));
  326. /* Get the port pins position */
  327. currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
  328. if (currentpin == pos)
  329. {
  330. pos = pinpos << 2;
  331. /* Clear the corresponding high control register bits */
  332. pinmask = ((uint32_t)0x0F) << pos;
  333. tmpreg &= ~pinmask;
  334. /* Write the mode configuration in the corresponding bits */
  335. tmpreg |= (currentmode << pos);
  336. /* Reset the corresponding ODR bit */
  337. if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
  338. {
  339. GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08));
  340. }
  341. /* Set the corresponding ODR bit */
  342. if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
  343. {
  344. GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08));
  345. }
  346. }
  347. }
  348. GPIOx->CRH = tmpreg;
  349. }
  350. }
  351. int main(void) {
  352. ADC_InitTypeDef ADC_InitStructure;
  353. GPIO_InitTypeDef GPIO_InitStructure;
  354. RCC_AHBPeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
  355. RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);
  356. GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 ;
  357. GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
  358. GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz ;
  359. GPIO_Init(GPIOA, &GPIO_InitStructure);
  360. ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
  361. ADC_InitStructure.ADC_ScanConvMode = ENABLE;
  362. ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
  363. ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
  364. ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
  365. ADC_InitStructure.ADC_NbrOfChannel = 0;
  366. ADC_Init(ADC1, &ADC_InitStructure);
  367. ADC_Cmd(ADC1, ENABLE);
  368. ADC_ResetCalibration(ADC1);
  369. while(ADC_GetResetCalibrationStatus(ADC1));
  370. ADC_StartCalibration(ADC1);
  371. while(ADC_GetCalibrationStatus(ADC1));
  372. ADC_SoftwareStartConvCmd(ADC1, ENABLE);
  373. RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1 | RCC_APB2Periph_GPIOA, ENABLE);
  374. while (1)
  375. {
  376. }
  377. }
  378. void SysTick_Handler(void) {
  379. if (Rstatus == 1 && Wstatus != 1){
  380. ADC1ConvertedValue = 0xB1;
  381. Buffer1[BuffCount] = TMSTP;
  382. BuffCount++;
  383. Buffer1[BuffCount] = ADC1ConvertedValue;
  384. BuffCount++;
  385. TMSTP++;
  386. }
  387. if (Rstatus == 2 && Wstatus != 2){
  388. ADC1ConvertedValue = 0xB2;
  389. Buffer2[BuffCount] = TMSTP;
  390. BuffCount++;
  391. Buffer2[BuffCount] = ADC1ConvertedValue;
  392. BuffCount++;
  393. TMSTP++;
  394. }
  395. if ( BuffCount == 254 && Rstatus == 1 ){
  396. Rstatus = 2;
  397. BuffReady = 1;
  398. BuffCount = 0;
  399. }
  400. if (BuffCount == 254 && Rstatus == 2){
  401. Rstatus = 1;
  402. BuffReady = 2;
  403. BuffCount = 0;
  404. }
  405. }