stm32f030x6.h 420 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f030x6.h
  4. * @author MCD Application Team
  5. * @version V2.3.1
  6. * @date 04-November-2016
  7. * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
  8. * This file contains all the peripheral register's definitions, bits
  9. * definitions and memory mapping for STM32F0xx devices.
  10. *
  11. * This file contains:
  12. * - Data structures and the address mapping for all peripherals
  13. * - Peripheral's registers declarations and bits definition
  14. * - Macros to access peripheral’s registers hardware
  15. *
  16. ******************************************************************************
  17. * @attention
  18. *
  19. * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  20. *
  21. * Redistribution and use in source and binary forms, with or without modification,
  22. * are permitted provided that the following conditions are met:
  23. * 1. Redistributions of source code must retain the above copyright notice,
  24. * this list of conditions and the following disclaimer.
  25. * 2. Redistributions in binary form must reproduce the above copyright notice,
  26. * this list of conditions and the following disclaimer in the documentation
  27. * and/or other materials provided with the distribution.
  28. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  29. * may be used to endorse or promote products derived from this software
  30. * without specific prior written permission.
  31. *
  32. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  33. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  34. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  36. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  37. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  38. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  39. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  40. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  41. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42. *
  43. ******************************************************************************
  44. */
  45. /** @addtogroup CMSIS
  46. * @{
  47. */
  48. /** @addtogroup stm32f030x6
  49. * @{
  50. */
  51. #ifndef __STM32F030x6_H
  52. #define __STM32F030x6_H
  53. #ifdef __cplusplus
  54. extern "C" {
  55. #endif /* __cplusplus */
  56. /** @addtogroup Configuration_section_for_CMSIS
  57. * @{
  58. */
  59. /**
  60. * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
  61. */
  62. #define __CM0_REV 0 /*!< Core Revision r0p0 */
  63. #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
  64. #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
  65. #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
  66. /**
  67. * @}
  68. */
  69. /** @addtogroup Peripheral_interrupt_number_definition
  70. * @{
  71. */
  72. /**
  73. * @brief STM32F0xx Interrupt Number Definition, according to the selected device
  74. * in @ref Library_configuration_section
  75. */
  76. /*!< Interrupt Number Definition */
  77. typedef enum
  78. {
  79. /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
  80. NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
  81. HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
  82. SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
  83. PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
  84. SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
  85. /****** STM32F0 specific Interrupt Numbers ******************************************************************/
  86. WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
  87. RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
  88. FLASH_IRQn = 3, /*!< FLASH global Interrupt */
  89. RCC_IRQn = 4, /*!< RCC global Interrupt */
  90. EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupt */
  91. EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupt */
  92. EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupt */
  93. DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
  94. DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupt */
  95. DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt */
  96. ADC1_IRQn = 12, /*!< ADC1 Interrupt */
  97. TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupt */
  98. TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
  99. TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
  100. TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
  101. TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
  102. TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
  103. I2C1_IRQn = 23, /*!< I2C1 Event Interrupt */
  104. SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
  105. USART1_IRQn = 27 /*!< USART1 global Interrupt */
  106. } IRQn_Type;
  107. /**
  108. * @}
  109. */
  110. #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
  111. #include "system_stm32f0xx.h" /* STM32F0xx System Header */
  112. #include <stdint.h>
  113. /** @addtogroup Peripheral_registers_structures
  114. * @{
  115. */
  116. /**
  117. * @brief Analog to Digital Converter
  118. */
  119. typedef struct
  120. {
  121. __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
  122. __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
  123. __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
  124. __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */
  125. __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
  126. __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */
  127. uint32_t RESERVED1; /*!< Reserved, 0x18 */
  128. uint32_t RESERVED2; /*!< Reserved, 0x1C */
  129. __IO uint32_t TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
  130. uint32_t RESERVED3; /*!< Reserved, 0x24 */
  131. __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */
  132. uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
  133. __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
  134. } ADC_TypeDef;
  135. typedef struct
  136. {
  137. __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
  138. } ADC_Common_TypeDef;
  139. /**
  140. * @brief CRC calculation unit
  141. */
  142. typedef struct
  143. {
  144. __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
  145. __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
  146. uint8_t RESERVED0; /*!< Reserved, 0x05 */
  147. uint16_t RESERVED1; /*!< Reserved, 0x06 */
  148. __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
  149. uint32_t RESERVED2; /*!< Reserved, 0x0C */
  150. __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
  151. __IO uint32_t RESERVED3; /*!< Reserved, 0x14 */
  152. } CRC_TypeDef;
  153. /**
  154. * @brief Debug MCU
  155. */
  156. typedef struct
  157. {
  158. __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
  159. __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
  160. __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
  161. __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
  162. }DBGMCU_TypeDef;
  163. /**
  164. * @brief DMA Controller
  165. */
  166. typedef struct
  167. {
  168. __IO uint32_t CCR; /*!< DMA channel x configuration register */
  169. __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
  170. __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
  171. __IO uint32_t CMAR; /*!< DMA channel x memory address register */
  172. } DMA_Channel_TypeDef;
  173. typedef struct
  174. {
  175. __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
  176. __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
  177. } DMA_TypeDef;
  178. /**
  179. * @brief External Interrupt/Event Controller
  180. */
  181. typedef struct
  182. {
  183. __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
  184. __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
  185. __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
  186. __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
  187. __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
  188. __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
  189. } EXTI_TypeDef;
  190. /**
  191. * @brief FLASH Registers
  192. */
  193. typedef struct
  194. {
  195. __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
  196. __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
  197. __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
  198. __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
  199. __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
  200. __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
  201. __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
  202. __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
  203. __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
  204. } FLASH_TypeDef;
  205. /**
  206. * @brief Option Bytes Registers
  207. */
  208. typedef struct
  209. {
  210. __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
  211. __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
  212. __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
  213. __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
  214. __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
  215. } OB_TypeDef;
  216. /**
  217. * @brief General Purpose I/O
  218. */
  219. typedef struct
  220. {
  221. __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
  222. __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
  223. __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
  224. __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
  225. __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
  226. __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
  227. __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
  228. __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
  229. __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
  230. __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
  231. } GPIO_TypeDef;
  232. /**
  233. * @brief SysTem Configuration
  234. */
  235. typedef struct
  236. {
  237. __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
  238. uint32_t RESERVED; /*!< Reserved, 0x04 */
  239. __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
  240. __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
  241. } SYSCFG_TypeDef;
  242. /**
  243. * @brief Inter-integrated Circuit Interface
  244. */
  245. typedef struct
  246. {
  247. __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
  248. __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
  249. __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
  250. __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
  251. __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
  252. __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
  253. __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
  254. __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
  255. __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
  256. __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
  257. __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
  258. } I2C_TypeDef;
  259. /**
  260. * @brief Independent WATCHDOG
  261. */
  262. typedef struct
  263. {
  264. __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
  265. __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
  266. __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
  267. __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
  268. __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
  269. } IWDG_TypeDef;
  270. /**
  271. * @brief Power Control
  272. */
  273. typedef struct
  274. {
  275. __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
  276. __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
  277. } PWR_TypeDef;
  278. /**
  279. * @brief Reset and Clock Control
  280. */
  281. typedef struct
  282. {
  283. __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
  284. __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
  285. __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
  286. __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
  287. __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
  288. __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
  289. __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
  290. __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
  291. __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
  292. __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
  293. __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
  294. __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
  295. __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
  296. __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
  297. } RCC_TypeDef;
  298. /**
  299. * @brief Real-Time Clock
  300. */
  301. typedef struct
  302. {
  303. __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
  304. __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
  305. __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
  306. __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
  307. __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
  308. uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
  309. uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */
  310. __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
  311. uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */
  312. __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
  313. __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
  314. __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
  315. __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
  316. __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
  317. __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
  318. __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
  319. __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
  320. __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
  321. } RTC_TypeDef;
  322. /**
  323. * @brief Serial Peripheral Interface
  324. */
  325. typedef struct
  326. {
  327. __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
  328. __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
  329. __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
  330. __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
  331. __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
  332. __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
  333. __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
  334. __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
  335. } SPI_TypeDef;
  336. /**
  337. * @brief TIM
  338. */
  339. typedef struct
  340. {
  341. __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
  342. __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
  343. __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
  344. __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
  345. __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
  346. __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
  347. __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
  348. __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
  349. __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
  350. __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
  351. __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
  352. __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
  353. __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
  354. __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
  355. __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
  356. __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
  357. __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
  358. __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
  359. __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
  360. __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
  361. __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
  362. } TIM_TypeDef;
  363. /**
  364. * @brief Universal Synchronous Asynchronous Receiver Transmitter
  365. */
  366. typedef struct
  367. {
  368. __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
  369. __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
  370. __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
  371. __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
  372. __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
  373. __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
  374. __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
  375. __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
  376. __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
  377. __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
  378. uint16_t RESERVED1; /*!< Reserved, 0x26 */
  379. __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
  380. uint16_t RESERVED2; /*!< Reserved, 0x2A */
  381. } USART_TypeDef;
  382. /**
  383. * @brief Window WATCHDOG
  384. */
  385. typedef struct
  386. {
  387. __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
  388. __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
  389. __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
  390. } WWDG_TypeDef;
  391. /**
  392. * @}
  393. */
  394. /** @addtogroup Peripheral_memory_map
  395. * @{
  396. */
  397. #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
  398. #define FLASH_BANK1_END ((uint32_t)0x08007FFFU) /*!< FLASH END address of bank1 */
  399. #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
  400. #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
  401. /*!< Peripheral memory map */
  402. #define APBPERIPH_BASE PERIPH_BASE
  403. #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
  404. #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
  405. /*!< APB peripherals */
  406. #define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
  407. #define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
  408. #define RTC_BASE (APBPERIPH_BASE + 0x00002800)
  409. #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
  410. #define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
  411. #define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
  412. #define PWR_BASE (APBPERIPH_BASE + 0x00007000)
  413. #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
  414. #define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
  415. #define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
  416. #define ADC_BASE (APBPERIPH_BASE + 0x00012708)
  417. #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
  418. #define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
  419. #define USART1_BASE (APBPERIPH_BASE + 0x00013800)
  420. #define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
  421. #define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
  422. #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
  423. /*!< AHB peripherals */
  424. #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
  425. #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
  426. #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
  427. #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
  428. #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
  429. #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
  430. #define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
  431. #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
  432. #define OB_BASE ((uint32_t)0x1FFFF800U) /*!< FLASH Option Bytes base address */
  433. #define FLASHSIZE_BASE ((uint32_t)0x1FFFF7CCU) /*!< FLASH Size register base address */
  434. #define UID_BASE ((uint32_t)0x1FFFF7ACU) /*!< Unique device ID register base address */
  435. #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
  436. /*!< AHB2 peripherals */
  437. #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
  438. #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
  439. #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
  440. #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
  441. #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
  442. /**
  443. * @}
  444. */
  445. /** @addtogroup Peripheral_declaration
  446. * @{
  447. */
  448. #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
  449. #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
  450. #define RTC ((RTC_TypeDef *) RTC_BASE)
  451. #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
  452. #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
  453. #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
  454. #define PWR ((PWR_TypeDef *) PWR_BASE)
  455. #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
  456. #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
  457. #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
  458. #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
  459. #define ADC ((ADC_Common_TypeDef *) ADC_BASE) /* Kept for legacy purpose */
  460. #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
  461. #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
  462. #define USART1 ((USART_TypeDef *) USART1_BASE)
  463. #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
  464. #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
  465. #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
  466. #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
  467. #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
  468. #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
  469. #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
  470. #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
  471. #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
  472. #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
  473. #define OB ((OB_TypeDef *) OB_BASE)
  474. #define RCC ((RCC_TypeDef *) RCC_BASE)
  475. #define CRC ((CRC_TypeDef *) CRC_BASE)
  476. #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
  477. #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
  478. #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
  479. #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
  480. #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
  481. /**
  482. * @}
  483. */
  484. /** @addtogroup Exported_constants
  485. * @{
  486. */
  487. /** @addtogroup Peripheral_Registers_Bits_Definition
  488. * @{
  489. */
  490. /******************************************************************************/
  491. /* Peripheral Registers Bits Definition */
  492. /******************************************************************************/
  493. /******************************************************************************/
  494. /* */
  495. /* Analog to Digital Converter (ADC) */
  496. /* */
  497. /******************************************************************************/
  498. /*
  499. * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
  500. */
  501. /* Note: No specific macro feature on this device */
  502. /******************** Bits definition for ADC_ISR register ******************/
  503. #define ADC_ISR_ADRDY_Pos (0U)
  504. #define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
  505. #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
  506. #define ADC_ISR_EOSMP_Pos (1U)
  507. #define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
  508. #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
  509. #define ADC_ISR_EOC_Pos (2U)
  510. #define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
  511. #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
  512. #define ADC_ISR_EOS_Pos (3U)
  513. #define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
  514. #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
  515. #define ADC_ISR_OVR_Pos (4U)
  516. #define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
  517. #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
  518. #define ADC_ISR_AWD1_Pos (7U)
  519. #define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
  520. #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
  521. /* Legacy defines */
  522. #define ADC_ISR_AWD (ADC_ISR_AWD1)
  523. #define ADC_ISR_EOSEQ (ADC_ISR_EOS)
  524. /******************** Bits definition for ADC_IER register ******************/
  525. #define ADC_IER_ADRDYIE_Pos (0U)
  526. #define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
  527. #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
  528. #define ADC_IER_EOSMPIE_Pos (1U)
  529. #define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
  530. #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
  531. #define ADC_IER_EOCIE_Pos (2U)
  532. #define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
  533. #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
  534. #define ADC_IER_EOSIE_Pos (3U)
  535. #define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
  536. #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
  537. #define ADC_IER_OVRIE_Pos (4U)
  538. #define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
  539. #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
  540. #define ADC_IER_AWD1IE_Pos (7U)
  541. #define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
  542. #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
  543. /* Legacy defines */
  544. #define ADC_IER_AWDIE (ADC_IER_AWD1IE)
  545. #define ADC_IER_EOSEQIE (ADC_IER_EOSIE)
  546. /******************** Bits definition for ADC_CR register *******************/
  547. #define ADC_CR_ADEN_Pos (0U)
  548. #define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
  549. #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
  550. #define ADC_CR_ADDIS_Pos (1U)
  551. #define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
  552. #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
  553. #define ADC_CR_ADSTART_Pos (2U)
  554. #define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
  555. #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
  556. #define ADC_CR_ADSTP_Pos (4U)
  557. #define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
  558. #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
  559. #define ADC_CR_ADCAL_Pos (31U)
  560. #define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
  561. #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
  562. /******************* Bits definition for ADC_CFGR1 register *****************/
  563. #define ADC_CFGR1_DMAEN_Pos (0U)
  564. #define ADC_CFGR1_DMAEN_Msk (0x1U << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
  565. #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */
  566. #define ADC_CFGR1_DMACFG_Pos (1U)
  567. #define ADC_CFGR1_DMACFG_Msk (0x1U << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
  568. #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */
  569. #define ADC_CFGR1_SCANDIR_Pos (2U)
  570. #define ADC_CFGR1_SCANDIR_Msk (0x1U << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
  571. #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */
  572. #define ADC_CFGR1_RES_Pos (3U)
  573. #define ADC_CFGR1_RES_Msk (0x3U << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
  574. #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */
  575. #define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
  576. #define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
  577. #define ADC_CFGR1_ALIGN_Pos (5U)
  578. #define ADC_CFGR1_ALIGN_Msk (0x1U << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
  579. #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */
  580. #define ADC_CFGR1_EXTSEL_Pos (6U)
  581. #define ADC_CFGR1_EXTSEL_Msk (0x7U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
  582. #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */
  583. #define ADC_CFGR1_EXTSEL_0 (0x1U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
  584. #define ADC_CFGR1_EXTSEL_1 (0x2U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
  585. #define ADC_CFGR1_EXTSEL_2 (0x4U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
  586. #define ADC_CFGR1_EXTEN_Pos (10U)
  587. #define ADC_CFGR1_EXTEN_Msk (0x3U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
  588. #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */
  589. #define ADC_CFGR1_EXTEN_0 (0x1U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
  590. #define ADC_CFGR1_EXTEN_1 (0x2U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
  591. #define ADC_CFGR1_OVRMOD_Pos (12U)
  592. #define ADC_CFGR1_OVRMOD_Msk (0x1U << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
  593. #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */
  594. #define ADC_CFGR1_CONT_Pos (13U)
  595. #define ADC_CFGR1_CONT_Msk (0x1U << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
  596. #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */
  597. #define ADC_CFGR1_WAIT_Pos (14U)
  598. #define ADC_CFGR1_WAIT_Msk (0x1U << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
  599. #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */
  600. #define ADC_CFGR1_AUTOFF_Pos (15U)
  601. #define ADC_CFGR1_AUTOFF_Msk (0x1U << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
  602. #define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */
  603. #define ADC_CFGR1_DISCEN_Pos (16U)
  604. #define ADC_CFGR1_DISCEN_Msk (0x1U << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
  605. #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
  606. #define ADC_CFGR1_AWD1SGL_Pos (22U)
  607. #define ADC_CFGR1_AWD1SGL_Msk (0x1U << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
  608. #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
  609. #define ADC_CFGR1_AWD1EN_Pos (23U)
  610. #define ADC_CFGR1_AWD1EN_Msk (0x1U << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
  611. #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
  612. #define ADC_CFGR1_AWD1CH_Pos (26U)
  613. #define ADC_CFGR1_AWD1CH_Msk (0x1FU << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */
  614. #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
  615. #define ADC_CFGR1_AWD1CH_0 (0x01U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */
  616. #define ADC_CFGR1_AWD1CH_1 (0x02U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */
  617. #define ADC_CFGR1_AWD1CH_2 (0x04U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */
  618. #define ADC_CFGR1_AWD1CH_3 (0x08U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */
  619. #define ADC_CFGR1_AWD1CH_4 (0x10U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */
  620. /* Legacy defines */
  621. #define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT)
  622. #define ADC_CFGR1_AWDSGL (ADC_CFGR1_AWD1SGL)
  623. #define ADC_CFGR1_AWDEN (ADC_CFGR1_AWD1EN)
  624. #define ADC_CFGR1_AWDCH (ADC_CFGR1_AWD1CH)
  625. #define ADC_CFGR1_AWDCH_0 (ADC_CFGR1_AWD1CH_0)
  626. #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1)
  627. #define ADC_CFGR1_AWDCH_2 (ADC_CFGR1_AWD1CH_2)
  628. #define ADC_CFGR1_AWDCH_3 (ADC_CFGR1_AWD1CH_3)
  629. #define ADC_CFGR1_AWDCH_4 (ADC_CFGR1_AWD1CH_4)
  630. /******************* Bits definition for ADC_CFGR2 register *****************/
  631. #define ADC_CFGR2_CKMODE_Pos (30U)
  632. #define ADC_CFGR2_CKMODE_Msk (0x3U << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
  633. #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */
  634. #define ADC_CFGR2_CKMODE_1 (0x2U << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
  635. #define ADC_CFGR2_CKMODE_0 (0x1U << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
  636. /* Legacy defines */
  637. #define ADC_CFGR2_JITOFFDIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC clocked by PCLK div4 */
  638. #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */
  639. /****************** Bit definition for ADC_SMPR register ********************/
  640. #define ADC_SMPR_SMP_Pos (0U)
  641. #define ADC_SMPR_SMP_Msk (0x7U << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
  642. #define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< ADC group of channels sampling time 2 */
  643. #define ADC_SMPR_SMP_0 (0x1U << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
  644. #define ADC_SMPR_SMP_1 (0x2U << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
  645. #define ADC_SMPR_SMP_2 (0x4U << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
  646. /* Legacy defines */
  647. #define ADC_SMPR1_SMPR (ADC_SMPR_SMP) /*!< SMP[2:0] bits (Sampling time selection) */
  648. #define ADC_SMPR1_SMPR_0 (ADC_SMPR_SMP_0) /*!< bit 0 */
  649. #define ADC_SMPR1_SMPR_1 (ADC_SMPR_SMP_1) /*!< bit 1 */
  650. #define ADC_SMPR1_SMPR_2 (ADC_SMPR_SMP_2) /*!< bit 2 */
  651. /******************* Bit definition for ADC_TR register ********************/
  652. #define ADC_TR1_LT1_Pos (0U)
  653. #define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
  654. #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
  655. #define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
  656. #define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
  657. #define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
  658. #define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
  659. #define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
  660. #define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
  661. #define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
  662. #define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
  663. #define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
  664. #define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
  665. #define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
  666. #define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
  667. #define ADC_TR1_HT1_Pos (16U)
  668. #define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
  669. #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
  670. #define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
  671. #define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
  672. #define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
  673. #define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
  674. #define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
  675. #define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
  676. #define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
  677. #define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
  678. #define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
  679. #define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
  680. #define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
  681. #define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
  682. /* Legacy defines */
  683. #define ADC_TR_HT (ADC_TR1_HT1)
  684. #define ADC_TR_LT (ADC_TR1_LT1)
  685. #define ADC_HTR_HT (ADC_TR1_HT1)
  686. #define ADC_LTR_LT (ADC_TR1_LT1)
  687. /****************** Bit definition for ADC_CHSELR register ******************/
  688. #define ADC_CHSELR_CHSEL_Pos (0U)
  689. #define ADC_CHSELR_CHSEL_Msk (0x7FFFFU << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
  690. #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */
  691. #define ADC_CHSELR_CHSEL18_Pos (18U)
  692. #define ADC_CHSELR_CHSEL18_Msk (0x1U << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
  693. #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
  694. #define ADC_CHSELR_CHSEL17_Pos (17U)
  695. #define ADC_CHSELR_CHSEL17_Msk (0x1U << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
  696. #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */
  697. #define ADC_CHSELR_CHSEL16_Pos (16U)
  698. #define ADC_CHSELR_CHSEL16_Msk (0x1U << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */
  699. #define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */
  700. #define ADC_CHSELR_CHSEL15_Pos (15U)
  701. #define ADC_CHSELR_CHSEL15_Msk (0x1U << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
  702. #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */
  703. #define ADC_CHSELR_CHSEL14_Pos (14U)
  704. #define ADC_CHSELR_CHSEL14_Msk (0x1U << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
  705. #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */
  706. #define ADC_CHSELR_CHSEL13_Pos (13U)
  707. #define ADC_CHSELR_CHSEL13_Msk (0x1U << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
  708. #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */
  709. #define ADC_CHSELR_CHSEL12_Pos (12U)
  710. #define ADC_CHSELR_CHSEL12_Msk (0x1U << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
  711. #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */
  712. #define ADC_CHSELR_CHSEL11_Pos (11U)
  713. #define ADC_CHSELR_CHSEL11_Msk (0x1U << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
  714. #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */
  715. #define ADC_CHSELR_CHSEL10_Pos (10U)
  716. #define ADC_CHSELR_CHSEL10_Msk (0x1U << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
  717. #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */
  718. #define ADC_CHSELR_CHSEL9_Pos (9U)
  719. #define ADC_CHSELR_CHSEL9_Msk (0x1U << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
  720. #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */
  721. #define ADC_CHSELR_CHSEL8_Pos (8U)
  722. #define ADC_CHSELR_CHSEL8_Msk (0x1U << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
  723. #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */
  724. #define ADC_CHSELR_CHSEL7_Pos (7U)
  725. #define ADC_CHSELR_CHSEL7_Msk (0x1U << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
  726. #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */
  727. #define ADC_CHSELR_CHSEL6_Pos (6U)
  728. #define ADC_CHSELR_CHSEL6_Msk (0x1U << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
  729. #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */
  730. #define ADC_CHSELR_CHSEL5_Pos (5U)
  731. #define ADC_CHSELR_CHSEL5_Msk (0x1U << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
  732. #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */
  733. #define ADC_CHSELR_CHSEL4_Pos (4U)
  734. #define ADC_CHSELR_CHSEL4_Msk (0x1U << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
  735. #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */
  736. #define ADC_CHSELR_CHSEL3_Pos (3U)
  737. #define ADC_CHSELR_CHSEL3_Msk (0x1U << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
  738. #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */
  739. #define ADC_CHSELR_CHSEL2_Pos (2U)
  740. #define ADC_CHSELR_CHSEL2_Msk (0x1U << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
  741. #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */
  742. #define ADC_CHSELR_CHSEL1_Pos (1U)
  743. #define ADC_CHSELR_CHSEL1_Msk (0x1U << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
  744. #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */
  745. #define ADC_CHSELR_CHSEL0_Pos (0U)
  746. #define ADC_CHSELR_CHSEL0_Msk (0x1U << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
  747. #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */
  748. /******************** Bit definition for ADC_DR register ********************/
  749. #define ADC_DR_DATA_Pos (0U)
  750. #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
  751. #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
  752. #define ADC_DR_DATA_0 (0x0001U << ADC_DR_DATA_Pos) /*!< 0x00000001 */
  753. #define ADC_DR_DATA_1 (0x0002U << ADC_DR_DATA_Pos) /*!< 0x00000002 */
  754. #define ADC_DR_DATA_2 (0x0004U << ADC_DR_DATA_Pos) /*!< 0x00000004 */
  755. #define ADC_DR_DATA_3 (0x0008U << ADC_DR_DATA_Pos) /*!< 0x00000008 */
  756. #define ADC_DR_DATA_4 (0x0010U << ADC_DR_DATA_Pos) /*!< 0x00000010 */
  757. #define ADC_DR_DATA_5 (0x0020U << ADC_DR_DATA_Pos) /*!< 0x00000020 */
  758. #define ADC_DR_DATA_6 (0x0040U << ADC_DR_DATA_Pos) /*!< 0x00000040 */
  759. #define ADC_DR_DATA_7 (0x0080U << ADC_DR_DATA_Pos) /*!< 0x00000080 */
  760. #define ADC_DR_DATA_8 (0x0100U << ADC_DR_DATA_Pos) /*!< 0x00000100 */
  761. #define ADC_DR_DATA_9 (0x0200U << ADC_DR_DATA_Pos) /*!< 0x00000200 */
  762. #define ADC_DR_DATA_10 (0x0400U << ADC_DR_DATA_Pos) /*!< 0x00000400 */
  763. #define ADC_DR_DATA_11 (0x0800U << ADC_DR_DATA_Pos) /*!< 0x00000800 */
  764. #define ADC_DR_DATA_12 (0x1000U << ADC_DR_DATA_Pos) /*!< 0x00001000 */
  765. #define ADC_DR_DATA_13 (0x2000U << ADC_DR_DATA_Pos) /*!< 0x00002000 */
  766. #define ADC_DR_DATA_14 (0x4000U << ADC_DR_DATA_Pos) /*!< 0x00004000 */
  767. #define ADC_DR_DATA_15 (0x8000U << ADC_DR_DATA_Pos) /*!< 0x00008000 */
  768. /************************* ADC Common registers *****************************/
  769. /******************* Bit definition for ADC_CCR register ********************/
  770. #define ADC_CCR_VREFEN_Pos (22U)
  771. #define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
  772. #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
  773. #define ADC_CCR_TSEN_Pos (23U)
  774. #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
  775. #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
  776. /******************************************************************************/
  777. /* */
  778. /* CRC calculation unit (CRC) */
  779. /* */
  780. /******************************************************************************/
  781. /******************* Bit definition for CRC_DR register *********************/
  782. #define CRC_DR_DR_Pos (0U)
  783. #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
  784. #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
  785. /******************* Bit definition for CRC_IDR register ********************/
  786. #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
  787. /******************** Bit definition for CRC_CR register ********************/
  788. #define CRC_CR_RESET_Pos (0U)
  789. #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
  790. #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
  791. #define CRC_CR_REV_IN_Pos (5U)
  792. #define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
  793. #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
  794. #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
  795. #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
  796. #define CRC_CR_REV_OUT_Pos (7U)
  797. #define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
  798. #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
  799. /******************* Bit definition for CRC_INIT register *******************/
  800. #define CRC_INIT_INIT_Pos (0U)
  801. #define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
  802. #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
  803. /******************************************************************************/
  804. /* */
  805. /* Debug MCU (DBGMCU) */
  806. /* */
  807. /******************************************************************************/
  808. /**************** Bit definition for DBGMCU_IDCODE register *****************/
  809. #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
  810. #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
  811. #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
  812. #define DBGMCU_IDCODE_REV_ID_Pos (16U)
  813. #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
  814. #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
  815. #define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
  816. #define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
  817. #define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
  818. #define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
  819. #define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
  820. #define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
  821. #define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
  822. #define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
  823. #define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
  824. #define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
  825. #define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
  826. #define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
  827. #define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
  828. #define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
  829. #define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
  830. #define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
  831. /****************** Bit definition for DBGMCU_CR register *******************/
  832. #define DBGMCU_CR_DBG_STOP_Pos (1U)
  833. #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
  834. #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
  835. #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
  836. #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
  837. #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
  838. /****************** Bit definition for DBGMCU_APB1_FZ register **************/
  839. #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
  840. #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
  841. #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
  842. #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
  843. #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
  844. #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk /*!< TIM14 counter stopped when core is halted */
  845. #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
  846. #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
  847. #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
  848. #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
  849. #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
  850. #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
  851. #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
  852. #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
  853. #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
  854. #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
  855. #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
  856. #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
  857. /****************** Bit definition for DBGMCU_APB2_FZ register **************/
  858. #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (11U)
  859. #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
  860. #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */
  861. #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (17U)
  862. #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
  863. #define DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk /*!< TIM16 counter stopped when core is halted */
  864. #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (18U)
  865. #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
  866. #define DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk /*!< TIM17 counter stopped when core is halted */
  867. /******************************************************************************/
  868. /* */
  869. /* DMA Controller (DMA) */
  870. /* */
  871. /******************************************************************************/
  872. /******************* Bit definition for DMA_ISR register ********************/
  873. #define DMA_ISR_GIF1_Pos (0U)
  874. #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
  875. #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
  876. #define DMA_ISR_TCIF1_Pos (1U)
  877. #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
  878. #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
  879. #define DMA_ISR_HTIF1_Pos (2U)
  880. #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
  881. #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
  882. #define DMA_ISR_TEIF1_Pos (3U)
  883. #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
  884. #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
  885. #define DMA_ISR_GIF2_Pos (4U)
  886. #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
  887. #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
  888. #define DMA_ISR_TCIF2_Pos (5U)
  889. #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
  890. #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
  891. #define DMA_ISR_HTIF2_Pos (6U)
  892. #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
  893. #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
  894. #define DMA_ISR_TEIF2_Pos (7U)
  895. #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
  896. #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
  897. #define DMA_ISR_GIF3_Pos (8U)
  898. #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
  899. #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
  900. #define DMA_ISR_TCIF3_Pos (9U)
  901. #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
  902. #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
  903. #define DMA_ISR_HTIF3_Pos (10U)
  904. #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
  905. #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
  906. #define DMA_ISR_TEIF3_Pos (11U)
  907. #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
  908. #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
  909. #define DMA_ISR_GIF4_Pos (12U)
  910. #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
  911. #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
  912. #define DMA_ISR_TCIF4_Pos (13U)
  913. #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
  914. #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
  915. #define DMA_ISR_HTIF4_Pos (14U)
  916. #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
  917. #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
  918. #define DMA_ISR_TEIF4_Pos (15U)
  919. #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
  920. #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
  921. #define DMA_ISR_GIF5_Pos (16U)
  922. #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
  923. #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
  924. #define DMA_ISR_TCIF5_Pos (17U)
  925. #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
  926. #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
  927. #define DMA_ISR_HTIF5_Pos (18U)
  928. #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
  929. #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
  930. #define DMA_ISR_TEIF5_Pos (19U)
  931. #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
  932. #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
  933. /******************* Bit definition for DMA_IFCR register *******************/
  934. #define DMA_IFCR_CGIF1_Pos (0U)
  935. #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
  936. #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
  937. #define DMA_IFCR_CTCIF1_Pos (1U)
  938. #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
  939. #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
  940. #define DMA_IFCR_CHTIF1_Pos (2U)
  941. #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
  942. #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
  943. #define DMA_IFCR_CTEIF1_Pos (3U)
  944. #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
  945. #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
  946. #define DMA_IFCR_CGIF2_Pos (4U)
  947. #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
  948. #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
  949. #define DMA_IFCR_CTCIF2_Pos (5U)
  950. #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
  951. #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
  952. #define DMA_IFCR_CHTIF2_Pos (6U)
  953. #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
  954. #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
  955. #define DMA_IFCR_CTEIF2_Pos (7U)
  956. #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
  957. #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
  958. #define DMA_IFCR_CGIF3_Pos (8U)
  959. #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
  960. #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
  961. #define DMA_IFCR_CTCIF3_Pos (9U)
  962. #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
  963. #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
  964. #define DMA_IFCR_CHTIF3_Pos (10U)
  965. #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
  966. #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
  967. #define DMA_IFCR_CTEIF3_Pos (11U)
  968. #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
  969. #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
  970. #define DMA_IFCR_CGIF4_Pos (12U)
  971. #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
  972. #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
  973. #define DMA_IFCR_CTCIF4_Pos (13U)
  974. #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
  975. #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
  976. #define DMA_IFCR_CHTIF4_Pos (14U)
  977. #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
  978. #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
  979. #define DMA_IFCR_CTEIF4_Pos (15U)
  980. #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
  981. #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
  982. #define DMA_IFCR_CGIF5_Pos (16U)
  983. #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
  984. #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
  985. #define DMA_IFCR_CTCIF5_Pos (17U)
  986. #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
  987. #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
  988. #define DMA_IFCR_CHTIF5_Pos (18U)
  989. #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
  990. #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
  991. #define DMA_IFCR_CTEIF5_Pos (19U)
  992. #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
  993. #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
  994. /******************* Bit definition for DMA_CCR register ********************/
  995. #define DMA_CCR_EN_Pos (0U)
  996. #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
  997. #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
  998. #define DMA_CCR_TCIE_Pos (1U)
  999. #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
  1000. #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
  1001. #define DMA_CCR_HTIE_Pos (2U)
  1002. #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
  1003. #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
  1004. #define DMA_CCR_TEIE_Pos (3U)
  1005. #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
  1006. #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
  1007. #define DMA_CCR_DIR_Pos (4U)
  1008. #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
  1009. #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
  1010. #define DMA_CCR_CIRC_Pos (5U)
  1011. #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
  1012. #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
  1013. #define DMA_CCR_PINC_Pos (6U)
  1014. #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
  1015. #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
  1016. #define DMA_CCR_MINC_Pos (7U)
  1017. #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
  1018. #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
  1019. #define DMA_CCR_PSIZE_Pos (8U)
  1020. #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
  1021. #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
  1022. #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
  1023. #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
  1024. #define DMA_CCR_MSIZE_Pos (10U)
  1025. #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
  1026. #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
  1027. #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
  1028. #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
  1029. #define DMA_CCR_PL_Pos (12U)
  1030. #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
  1031. #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
  1032. #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
  1033. #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
  1034. #define DMA_CCR_MEM2MEM_Pos (14U)
  1035. #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
  1036. #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
  1037. /****************** Bit definition for DMA_CNDTR register *******************/
  1038. #define DMA_CNDTR_NDT_Pos (0U)
  1039. #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
  1040. #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
  1041. /****************** Bit definition for DMA_CPAR register ********************/
  1042. #define DMA_CPAR_PA_Pos (0U)
  1043. #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
  1044. #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
  1045. /****************** Bit definition for DMA_CMAR register ********************/
  1046. #define DMA_CMAR_MA_Pos (0U)
  1047. #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
  1048. #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
  1049. /******************************************************************************/
  1050. /* */
  1051. /* External Interrupt/Event Controller (EXTI) */
  1052. /* */
  1053. /******************************************************************************/
  1054. /******************* Bit definition for EXTI_IMR register *******************/
  1055. #define EXTI_IMR_MR0_Pos (0U)
  1056. #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
  1057. #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
  1058. #define EXTI_IMR_MR1_Pos (1U)
  1059. #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
  1060. #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
  1061. #define EXTI_IMR_MR2_Pos (2U)
  1062. #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
  1063. #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
  1064. #define EXTI_IMR_MR3_Pos (3U)
  1065. #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
  1066. #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
  1067. #define EXTI_IMR_MR4_Pos (4U)
  1068. #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
  1069. #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
  1070. #define EXTI_IMR_MR5_Pos (5U)
  1071. #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
  1072. #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
  1073. #define EXTI_IMR_MR6_Pos (6U)
  1074. #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
  1075. #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
  1076. #define EXTI_IMR_MR7_Pos (7U)
  1077. #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
  1078. #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
  1079. #define EXTI_IMR_MR8_Pos (8U)
  1080. #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
  1081. #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
  1082. #define EXTI_IMR_MR9_Pos (9U)
  1083. #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
  1084. #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
  1085. #define EXTI_IMR_MR10_Pos (10U)
  1086. #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
  1087. #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
  1088. #define EXTI_IMR_MR11_Pos (11U)
  1089. #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
  1090. #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
  1091. #define EXTI_IMR_MR12_Pos (12U)
  1092. #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
  1093. #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
  1094. #define EXTI_IMR_MR13_Pos (13U)
  1095. #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
  1096. #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
  1097. #define EXTI_IMR_MR14_Pos (14U)
  1098. #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
  1099. #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
  1100. #define EXTI_IMR_MR15_Pos (15U)
  1101. #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
  1102. #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
  1103. #define EXTI_IMR_MR17_Pos (17U)
  1104. #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
  1105. #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
  1106. #define EXTI_IMR_MR18_Pos (18U)
  1107. #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
  1108. #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
  1109. #define EXTI_IMR_MR19_Pos (19U)
  1110. #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
  1111. #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
  1112. #define EXTI_IMR_MR23_Pos (23U)
  1113. #define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
  1114. #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
  1115. /* References Defines */
  1116. #define EXTI_IMR_IM0 EXTI_IMR_MR0
  1117. #define EXTI_IMR_IM1 EXTI_IMR_MR1
  1118. #define EXTI_IMR_IM2 EXTI_IMR_MR2
  1119. #define EXTI_IMR_IM3 EXTI_IMR_MR3
  1120. #define EXTI_IMR_IM4 EXTI_IMR_MR4
  1121. #define EXTI_IMR_IM5 EXTI_IMR_MR5
  1122. #define EXTI_IMR_IM6 EXTI_IMR_MR6
  1123. #define EXTI_IMR_IM7 EXTI_IMR_MR7
  1124. #define EXTI_IMR_IM8 EXTI_IMR_MR8
  1125. #define EXTI_IMR_IM9 EXTI_IMR_MR9
  1126. #define EXTI_IMR_IM10 EXTI_IMR_MR10
  1127. #define EXTI_IMR_IM11 EXTI_IMR_MR11
  1128. #define EXTI_IMR_IM12 EXTI_IMR_MR12
  1129. #define EXTI_IMR_IM13 EXTI_IMR_MR13
  1130. #define EXTI_IMR_IM14 EXTI_IMR_MR14
  1131. #define EXTI_IMR_IM15 EXTI_IMR_MR15
  1132. #define EXTI_IMR_IM17 EXTI_IMR_MR17
  1133. #define EXTI_IMR_IM18 EXTI_IMR_MR18
  1134. #define EXTI_IMR_IM19 EXTI_IMR_MR19
  1135. #define EXTI_IMR_IM23 EXTI_IMR_MR23
  1136. #define EXTI_IMR_IM_Pos (0U)
  1137. #define EXTI_IMR_IM_Msk (0x8EFFFFU << EXTI_IMR_IM_Pos) /*!< 0x008EFFFF */
  1138. #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
  1139. /****************** Bit definition for EXTI_EMR register ********************/
  1140. #define EXTI_EMR_MR0_Pos (0U)
  1141. #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
  1142. #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
  1143. #define EXTI_EMR_MR1_Pos (1U)
  1144. #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
  1145. #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
  1146. #define EXTI_EMR_MR2_Pos (2U)
  1147. #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
  1148. #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
  1149. #define EXTI_EMR_MR3_Pos (3U)
  1150. #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
  1151. #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
  1152. #define EXTI_EMR_MR4_Pos (4U)
  1153. #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
  1154. #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
  1155. #define EXTI_EMR_MR5_Pos (5U)
  1156. #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
  1157. #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
  1158. #define EXTI_EMR_MR6_Pos (6U)
  1159. #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
  1160. #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
  1161. #define EXTI_EMR_MR7_Pos (7U)
  1162. #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
  1163. #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
  1164. #define EXTI_EMR_MR8_Pos (8U)
  1165. #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
  1166. #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
  1167. #define EXTI_EMR_MR9_Pos (9U)
  1168. #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
  1169. #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
  1170. #define EXTI_EMR_MR10_Pos (10U)
  1171. #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
  1172. #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
  1173. #define EXTI_EMR_MR11_Pos (11U)
  1174. #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
  1175. #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
  1176. #define EXTI_EMR_MR12_Pos (12U)
  1177. #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
  1178. #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
  1179. #define EXTI_EMR_MR13_Pos (13U)
  1180. #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
  1181. #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
  1182. #define EXTI_EMR_MR14_Pos (14U)
  1183. #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
  1184. #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
  1185. #define EXTI_EMR_MR15_Pos (15U)
  1186. #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
  1187. #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
  1188. #define EXTI_EMR_MR17_Pos (17U)
  1189. #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
  1190. #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
  1191. #define EXTI_EMR_MR18_Pos (18U)
  1192. #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
  1193. #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
  1194. #define EXTI_EMR_MR19_Pos (19U)
  1195. #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
  1196. #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
  1197. #define EXTI_EMR_MR23_Pos (23U)
  1198. #define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
  1199. #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
  1200. /* References Defines */
  1201. #define EXTI_EMR_EM0 EXTI_EMR_MR0
  1202. #define EXTI_EMR_EM1 EXTI_EMR_MR1
  1203. #define EXTI_EMR_EM2 EXTI_EMR_MR2
  1204. #define EXTI_EMR_EM3 EXTI_EMR_MR3
  1205. #define EXTI_EMR_EM4 EXTI_EMR_MR4
  1206. #define EXTI_EMR_EM5 EXTI_EMR_MR5
  1207. #define EXTI_EMR_EM6 EXTI_EMR_MR6
  1208. #define EXTI_EMR_EM7 EXTI_EMR_MR7
  1209. #define EXTI_EMR_EM8 EXTI_EMR_MR8
  1210. #define EXTI_EMR_EM9 EXTI_EMR_MR9
  1211. #define EXTI_EMR_EM10 EXTI_EMR_MR10
  1212. #define EXTI_EMR_EM11 EXTI_EMR_MR11
  1213. #define EXTI_EMR_EM12 EXTI_EMR_MR12
  1214. #define EXTI_EMR_EM13 EXTI_EMR_MR13
  1215. #define EXTI_EMR_EM14 EXTI_EMR_MR14
  1216. #define EXTI_EMR_EM15 EXTI_EMR_MR15
  1217. #define EXTI_EMR_EM17 EXTI_EMR_MR17
  1218. #define EXTI_EMR_EM18 EXTI_EMR_MR18
  1219. #define EXTI_EMR_EM19 EXTI_EMR_MR19
  1220. #define EXTI_EMR_EM23 EXTI_EMR_MR23
  1221. /******************* Bit definition for EXTI_RTSR register ******************/
  1222. #define EXTI_RTSR_TR0_Pos (0U)
  1223. #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
  1224. #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
  1225. #define EXTI_RTSR_TR1_Pos (1U)
  1226. #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
  1227. #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
  1228. #define EXTI_RTSR_TR2_Pos (2U)
  1229. #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
  1230. #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
  1231. #define EXTI_RTSR_TR3_Pos (3U)
  1232. #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
  1233. #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
  1234. #define EXTI_RTSR_TR4_Pos (4U)
  1235. #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
  1236. #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
  1237. #define EXTI_RTSR_TR5_Pos (5U)
  1238. #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
  1239. #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
  1240. #define EXTI_RTSR_TR6_Pos (6U)
  1241. #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
  1242. #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
  1243. #define EXTI_RTSR_TR7_Pos (7U)
  1244. #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
  1245. #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
  1246. #define EXTI_RTSR_TR8_Pos (8U)
  1247. #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
  1248. #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
  1249. #define EXTI_RTSR_TR9_Pos (9U)
  1250. #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
  1251. #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
  1252. #define EXTI_RTSR_TR10_Pos (10U)
  1253. #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
  1254. #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
  1255. #define EXTI_RTSR_TR11_Pos (11U)
  1256. #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
  1257. #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
  1258. #define EXTI_RTSR_TR12_Pos (12U)
  1259. #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
  1260. #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
  1261. #define EXTI_RTSR_TR13_Pos (13U)
  1262. #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
  1263. #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
  1264. #define EXTI_RTSR_TR14_Pos (14U)
  1265. #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
  1266. #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
  1267. #define EXTI_RTSR_TR15_Pos (15U)
  1268. #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
  1269. #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
  1270. #define EXTI_RTSR_TR16_Pos (16U)
  1271. #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
  1272. #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
  1273. #define EXTI_RTSR_TR17_Pos (17U)
  1274. #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
  1275. #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
  1276. #define EXTI_RTSR_TR19_Pos (19U)
  1277. #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
  1278. #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
  1279. /* References Defines */
  1280. #define EXTI_RTSR_RT0 EXTI_RTSR_TR0
  1281. #define EXTI_RTSR_RT1 EXTI_RTSR_TR1
  1282. #define EXTI_RTSR_RT2 EXTI_RTSR_TR2
  1283. #define EXTI_RTSR_RT3 EXTI_RTSR_TR3
  1284. #define EXTI_RTSR_RT4 EXTI_RTSR_TR4
  1285. #define EXTI_RTSR_RT5 EXTI_RTSR_TR5
  1286. #define EXTI_RTSR_RT6 EXTI_RTSR_TR6
  1287. #define EXTI_RTSR_RT7 EXTI_RTSR_TR7
  1288. #define EXTI_RTSR_RT8 EXTI_RTSR_TR8
  1289. #define EXTI_RTSR_RT9 EXTI_RTSR_TR9
  1290. #define EXTI_RTSR_RT10 EXTI_RTSR_TR10
  1291. #define EXTI_RTSR_RT11 EXTI_RTSR_TR11
  1292. #define EXTI_RTSR_RT12 EXTI_RTSR_TR12
  1293. #define EXTI_RTSR_RT13 EXTI_RTSR_TR13
  1294. #define EXTI_RTSR_RT14 EXTI_RTSR_TR14
  1295. #define EXTI_RTSR_RT15 EXTI_RTSR_TR15
  1296. #define EXTI_RTSR_RT16 EXTI_RTSR_TR16
  1297. #define EXTI_RTSR_RT17 EXTI_RTSR_TR17
  1298. #define EXTI_RTSR_RT19 EXTI_RTSR_TR19
  1299. /******************* Bit definition for EXTI_FTSR register *******************/
  1300. #define EXTI_FTSR_TR0_Pos (0U)
  1301. #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
  1302. #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
  1303. #define EXTI_FTSR_TR1_Pos (1U)
  1304. #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
  1305. #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
  1306. #define EXTI_FTSR_TR2_Pos (2U)
  1307. #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
  1308. #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
  1309. #define EXTI_FTSR_TR3_Pos (3U)
  1310. #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
  1311. #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
  1312. #define EXTI_FTSR_TR4_Pos (4U)
  1313. #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
  1314. #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
  1315. #define EXTI_FTSR_TR5_Pos (5U)
  1316. #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
  1317. #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
  1318. #define EXTI_FTSR_TR6_Pos (6U)
  1319. #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
  1320. #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
  1321. #define EXTI_FTSR_TR7_Pos (7U)
  1322. #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
  1323. #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
  1324. #define EXTI_FTSR_TR8_Pos (8U)
  1325. #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
  1326. #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
  1327. #define EXTI_FTSR_TR9_Pos (9U)
  1328. #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
  1329. #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
  1330. #define EXTI_FTSR_TR10_Pos (10U)
  1331. #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
  1332. #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
  1333. #define EXTI_FTSR_TR11_Pos (11U)
  1334. #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
  1335. #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
  1336. #define EXTI_FTSR_TR12_Pos (12U)
  1337. #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
  1338. #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
  1339. #define EXTI_FTSR_TR13_Pos (13U)
  1340. #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
  1341. #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
  1342. #define EXTI_FTSR_TR14_Pos (14U)
  1343. #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
  1344. #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
  1345. #define EXTI_FTSR_TR15_Pos (15U)
  1346. #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
  1347. #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
  1348. #define EXTI_FTSR_TR16_Pos (16U)
  1349. #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
  1350. #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
  1351. #define EXTI_FTSR_TR17_Pos (17U)
  1352. #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
  1353. #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
  1354. #define EXTI_FTSR_TR19_Pos (19U)
  1355. #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
  1356. #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
  1357. /* References Defines */
  1358. #define EXTI_FTSR_FT0 EXTI_FTSR_TR0
  1359. #define EXTI_FTSR_FT1 EXTI_FTSR_TR1
  1360. #define EXTI_FTSR_FT2 EXTI_FTSR_TR2
  1361. #define EXTI_FTSR_FT3 EXTI_FTSR_TR3
  1362. #define EXTI_FTSR_FT4 EXTI_FTSR_TR4
  1363. #define EXTI_FTSR_FT5 EXTI_FTSR_TR5
  1364. #define EXTI_FTSR_FT6 EXTI_FTSR_TR6
  1365. #define EXTI_FTSR_FT7 EXTI_FTSR_TR7
  1366. #define EXTI_FTSR_FT8 EXTI_FTSR_TR8
  1367. #define EXTI_FTSR_FT9 EXTI_FTSR_TR9
  1368. #define EXTI_FTSR_FT10 EXTI_FTSR_TR10
  1369. #define EXTI_FTSR_FT11 EXTI_FTSR_TR11
  1370. #define EXTI_FTSR_FT12 EXTI_FTSR_TR12
  1371. #define EXTI_FTSR_FT13 EXTI_FTSR_TR13
  1372. #define EXTI_FTSR_FT14 EXTI_FTSR_TR14
  1373. #define EXTI_FTSR_FT15 EXTI_FTSR_TR15
  1374. #define EXTI_FTSR_FT16 EXTI_FTSR_TR16
  1375. #define EXTI_FTSR_FT17 EXTI_FTSR_TR17
  1376. #define EXTI_FTSR_FT19 EXTI_FTSR_TR19
  1377. /******************* Bit definition for EXTI_SWIER register *******************/
  1378. #define EXTI_SWIER_SWIER0_Pos (0U)
  1379. #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
  1380. #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
  1381. #define EXTI_SWIER_SWIER1_Pos (1U)
  1382. #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
  1383. #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
  1384. #define EXTI_SWIER_SWIER2_Pos (2U)
  1385. #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
  1386. #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
  1387. #define EXTI_SWIER_SWIER3_Pos (3U)
  1388. #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
  1389. #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
  1390. #define EXTI_SWIER_SWIER4_Pos (4U)
  1391. #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
  1392. #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
  1393. #define EXTI_SWIER_SWIER5_Pos (5U)
  1394. #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
  1395. #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
  1396. #define EXTI_SWIER_SWIER6_Pos (6U)
  1397. #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
  1398. #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
  1399. #define EXTI_SWIER_SWIER7_Pos (7U)
  1400. #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
  1401. #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
  1402. #define EXTI_SWIER_SWIER8_Pos (8U)
  1403. #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
  1404. #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
  1405. #define EXTI_SWIER_SWIER9_Pos (9U)
  1406. #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
  1407. #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
  1408. #define EXTI_SWIER_SWIER10_Pos (10U)
  1409. #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
  1410. #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
  1411. #define EXTI_SWIER_SWIER11_Pos (11U)
  1412. #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
  1413. #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
  1414. #define EXTI_SWIER_SWIER12_Pos (12U)
  1415. #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
  1416. #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
  1417. #define EXTI_SWIER_SWIER13_Pos (13U)
  1418. #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
  1419. #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
  1420. #define EXTI_SWIER_SWIER14_Pos (14U)
  1421. #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
  1422. #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
  1423. #define EXTI_SWIER_SWIER15_Pos (15U)
  1424. #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
  1425. #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
  1426. #define EXTI_SWIER_SWIER16_Pos (16U)
  1427. #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
  1428. #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
  1429. #define EXTI_SWIER_SWIER17_Pos (17U)
  1430. #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
  1431. #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
  1432. #define EXTI_SWIER_SWIER19_Pos (19U)
  1433. #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
  1434. #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
  1435. /* References Defines */
  1436. #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
  1437. #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
  1438. #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
  1439. #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
  1440. #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
  1441. #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
  1442. #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
  1443. #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
  1444. #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
  1445. #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
  1446. #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
  1447. #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
  1448. #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
  1449. #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
  1450. #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
  1451. #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
  1452. #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
  1453. #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
  1454. #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
  1455. /****************** Bit definition for EXTI_PR register *********************/
  1456. #define EXTI_PR_PR0_Pos (0U)
  1457. #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
  1458. #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit 0 */
  1459. #define EXTI_PR_PR1_Pos (1U)
  1460. #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
  1461. #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit 1 */
  1462. #define EXTI_PR_PR2_Pos (2U)
  1463. #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
  1464. #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit 2 */
  1465. #define EXTI_PR_PR3_Pos (3U)
  1466. #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
  1467. #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit 3 */
  1468. #define EXTI_PR_PR4_Pos (4U)
  1469. #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
  1470. #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit 4 */
  1471. #define EXTI_PR_PR5_Pos (5U)
  1472. #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
  1473. #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit 5 */
  1474. #define EXTI_PR_PR6_Pos (6U)
  1475. #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
  1476. #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit 6 */
  1477. #define EXTI_PR_PR7_Pos (7U)
  1478. #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
  1479. #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit 7 */
  1480. #define EXTI_PR_PR8_Pos (8U)
  1481. #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
  1482. #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit 8 */
  1483. #define EXTI_PR_PR9_Pos (9U)
  1484. #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
  1485. #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit 9 */
  1486. #define EXTI_PR_PR10_Pos (10U)
  1487. #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
  1488. #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit 10 */
  1489. #define EXTI_PR_PR11_Pos (11U)
  1490. #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
  1491. #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit 11 */
  1492. #define EXTI_PR_PR12_Pos (12U)
  1493. #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
  1494. #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit 12 */
  1495. #define EXTI_PR_PR13_Pos (13U)
  1496. #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
  1497. #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit 13 */
  1498. #define EXTI_PR_PR14_Pos (14U)
  1499. #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
  1500. #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit 14 */
  1501. #define EXTI_PR_PR15_Pos (15U)
  1502. #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
  1503. #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit 15 */
  1504. #define EXTI_PR_PR16_Pos (16U)
  1505. #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
  1506. #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit 16 */
  1507. #define EXTI_PR_PR17_Pos (17U)
  1508. #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
  1509. #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit 17 */
  1510. #define EXTI_PR_PR19_Pos (19U)
  1511. #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
  1512. #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit 19 */
  1513. /* References Defines */
  1514. #define EXTI_PR_PIF0 EXTI_PR_PR0
  1515. #define EXTI_PR_PIF1 EXTI_PR_PR1
  1516. #define EXTI_PR_PIF2 EXTI_PR_PR2
  1517. #define EXTI_PR_PIF3 EXTI_PR_PR3
  1518. #define EXTI_PR_PIF4 EXTI_PR_PR4
  1519. #define EXTI_PR_PIF5 EXTI_PR_PR5
  1520. #define EXTI_PR_PIF6 EXTI_PR_PR6
  1521. #define EXTI_PR_PIF7 EXTI_PR_PR7
  1522. #define EXTI_PR_PIF8 EXTI_PR_PR8
  1523. #define EXTI_PR_PIF9 EXTI_PR_PR9
  1524. #define EXTI_PR_PIF10 EXTI_PR_PR10
  1525. #define EXTI_PR_PIF11 EXTI_PR_PR11
  1526. #define EXTI_PR_PIF12 EXTI_PR_PR12
  1527. #define EXTI_PR_PIF13 EXTI_PR_PR13
  1528. #define EXTI_PR_PIF14 EXTI_PR_PR14
  1529. #define EXTI_PR_PIF15 EXTI_PR_PR15
  1530. #define EXTI_PR_PIF16 EXTI_PR_PR16
  1531. #define EXTI_PR_PIF17 EXTI_PR_PR17
  1532. #define EXTI_PR_PIF19 EXTI_PR_PR19
  1533. /******************************************************************************/
  1534. /* */
  1535. /* FLASH and Option Bytes Registers */
  1536. /* */
  1537. /******************************************************************************/
  1538. /******************* Bit definition for FLASH_ACR register ******************/
  1539. #define FLASH_ACR_LATENCY_Pos (0U)
  1540. #define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
  1541. #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
  1542. #define FLASH_ACR_PRFTBE_Pos (4U)
  1543. #define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
  1544. #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
  1545. #define FLASH_ACR_PRFTBS_Pos (5U)
  1546. #define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
  1547. #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
  1548. /****************** Bit definition for FLASH_KEYR register ******************/
  1549. #define FLASH_KEYR_FKEYR_Pos (0U)
  1550. #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
  1551. #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
  1552. /***************** Bit definition for FLASH_OPTKEYR register ****************/
  1553. #define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
  1554. #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
  1555. #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
  1556. /****************** FLASH Keys **********************************************/
  1557. #define FLASH_KEY1_Pos (0U)
  1558. #define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
  1559. #define FLASH_KEY1 FLASH_KEY1_Msk /*!< Flash program erase key1 */
  1560. #define FLASH_KEY2_Pos (0U)
  1561. #define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
  1562. #define FLASH_KEY2 FLASH_KEY2_Msk /*!< Flash program erase key2: used with FLASH_PEKEY1
  1563. to unlock the write access to the FPEC. */
  1564. #define FLASH_OPTKEY1_Pos (0U)
  1565. #define FLASH_OPTKEY1_Msk (0x45670123U << FLASH_OPTKEY1_Pos) /*!< 0x45670123 */
  1566. #define FLASH_OPTKEY1 FLASH_OPTKEY1_Msk /*!< Flash option key1 */
  1567. #define FLASH_OPTKEY2_Pos (0U)
  1568. #define FLASH_OPTKEY2_Msk (0xCDEF89ABU << FLASH_OPTKEY2_Pos) /*!< 0xCDEF89AB */
  1569. #define FLASH_OPTKEY2 FLASH_OPTKEY2_Msk /*!< Flash option key2: used with FLASH_OPTKEY1 to
  1570. unlock the write access to the option byte block */
  1571. /****************** Bit definition for FLASH_SR register *******************/
  1572. #define FLASH_SR_BSY_Pos (0U)
  1573. #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
  1574. #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
  1575. #define FLASH_SR_PGERR_Pos (2U)
  1576. #define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
  1577. #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
  1578. #define FLASH_SR_WRPRTERR_Pos (4U)
  1579. #define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
  1580. #define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
  1581. #define FLASH_SR_EOP_Pos (5U)
  1582. #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
  1583. #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
  1584. #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
  1585. /******************* Bit definition for FLASH_CR register *******************/
  1586. #define FLASH_CR_PG_Pos (0U)
  1587. #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
  1588. #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
  1589. #define FLASH_CR_PER_Pos (1U)
  1590. #define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
  1591. #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
  1592. #define FLASH_CR_MER_Pos (2U)
  1593. #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
  1594. #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
  1595. #define FLASH_CR_OPTPG_Pos (4U)
  1596. #define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
  1597. #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
  1598. #define FLASH_CR_OPTER_Pos (5U)
  1599. #define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
  1600. #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
  1601. #define FLASH_CR_STRT_Pos (6U)
  1602. #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
  1603. #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
  1604. #define FLASH_CR_LOCK_Pos (7U)
  1605. #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
  1606. #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
  1607. #define FLASH_CR_OPTWRE_Pos (9U)
  1608. #define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
  1609. #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
  1610. #define FLASH_CR_ERRIE_Pos (10U)
  1611. #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
  1612. #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
  1613. #define FLASH_CR_EOPIE_Pos (12U)
  1614. #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
  1615. #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
  1616. #define FLASH_CR_OBL_LAUNCH_Pos (13U)
  1617. #define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x00002000 */
  1618. #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Option Bytes Loader Launch */
  1619. /******************* Bit definition for FLASH_AR register *******************/
  1620. #define FLASH_AR_FAR_Pos (0U)
  1621. #define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
  1622. #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
  1623. /****************** Bit definition for FLASH_OBR register *******************/
  1624. #define FLASH_OBR_OPTERR_Pos (0U)
  1625. #define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
  1626. #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
  1627. #define FLASH_OBR_RDPRT1_Pos (1U)
  1628. #define FLASH_OBR_RDPRT1_Msk (0x1U << FLASH_OBR_RDPRT1_Pos) /*!< 0x00000002 */
  1629. #define FLASH_OBR_RDPRT1 FLASH_OBR_RDPRT1_Msk /*!< Read protection Level 1 */
  1630. #define FLASH_OBR_RDPRT2_Pos (2U)
  1631. #define FLASH_OBR_RDPRT2_Msk (0x1U << FLASH_OBR_RDPRT2_Pos) /*!< 0x00000004 */
  1632. #define FLASH_OBR_RDPRT2 FLASH_OBR_RDPRT2_Msk /*!< Read protection Level 2 */
  1633. #define FLASH_OBR_USER_Pos (8U)
  1634. #define FLASH_OBR_USER_Msk (0x77U << FLASH_OBR_USER_Pos) /*!< 0x00007700 */
  1635. #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
  1636. #define FLASH_OBR_IWDG_SW_Pos (8U)
  1637. #define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000100 */
  1638. #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
  1639. #define FLASH_OBR_nRST_STOP_Pos (9U)
  1640. #define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000200 */
  1641. #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
  1642. #define FLASH_OBR_nRST_STDBY_Pos (10U)
  1643. #define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000400 */
  1644. #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
  1645. #define FLASH_OBR_nBOOT1_Pos (12U)
  1646. #define FLASH_OBR_nBOOT1_Msk (0x1U << FLASH_OBR_nBOOT1_Pos) /*!< 0x00001000 */
  1647. #define FLASH_OBR_nBOOT1 FLASH_OBR_nBOOT1_Msk /*!< nBOOT1 */
  1648. #define FLASH_OBR_VDDA_MONITOR_Pos (13U)
  1649. #define FLASH_OBR_VDDA_MONITOR_Msk (0x1U << FLASH_OBR_VDDA_MONITOR_Pos) /*!< 0x00002000 */
  1650. #define FLASH_OBR_VDDA_MONITOR FLASH_OBR_VDDA_MONITOR_Msk /*!< VDDA power supply supervisor */
  1651. #define FLASH_OBR_RAM_PARITY_CHECK_Pos (14U)
  1652. #define FLASH_OBR_RAM_PARITY_CHECK_Msk (0x1U << FLASH_OBR_RAM_PARITY_CHECK_Pos) /*!< 0x00004000 */
  1653. #define FLASH_OBR_RAM_PARITY_CHECK FLASH_OBR_RAM_PARITY_CHECK_Msk /*!< RAM parity check */
  1654. #define FLASH_OBR_DATA0_Pos (16U)
  1655. #define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x00FF0000 */
  1656. #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
  1657. #define FLASH_OBR_DATA1_Pos (24U)
  1658. #define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0xFF000000 */
  1659. #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
  1660. /* Old BOOT1 bit definition, maintained for legacy purpose */
  1661. #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
  1662. /* Old OBR_VDDA bit definition, maintained for legacy purpose */
  1663. #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
  1664. /****************** Bit definition for FLASH_WRPR register ******************/
  1665. #define FLASH_WRPR_WRP_Pos (0U)
  1666. #define FLASH_WRPR_WRP_Msk (0xFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
  1667. #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
  1668. /*----------------------------------------------------------------------------*/
  1669. /****************** Bit definition for OB_RDP register **********************/
  1670. #define OB_RDP_RDP_Pos (0U)
  1671. #define OB_RDP_RDP_Msk (0xFFU << OB_RDP_RDP_Pos) /*!< 0x000000FF */
  1672. #define OB_RDP_RDP OB_RDP_RDP_Msk /*!< Read protection option byte */
  1673. #define OB_RDP_nRDP_Pos (8U)
  1674. #define OB_RDP_nRDP_Msk (0xFFU << OB_RDP_nRDP_Pos) /*!< 0x0000FF00 */
  1675. #define OB_RDP_nRDP OB_RDP_nRDP_Msk /*!< Read protection complemented option byte */
  1676. /****************** Bit definition for OB_USER register *********************/
  1677. #define OB_USER_USER_Pos (16U)
  1678. #define OB_USER_USER_Msk (0xFFU << OB_USER_USER_Pos) /*!< 0x00FF0000 */
  1679. #define OB_USER_USER OB_USER_USER_Msk /*!< User option byte */
  1680. #define OB_USER_nUSER_Pos (24U)
  1681. #define OB_USER_nUSER_Msk (0xFFU << OB_USER_nUSER_Pos) /*!< 0xFF000000 */
  1682. #define OB_USER_nUSER OB_USER_nUSER_Msk /*!< User complemented option byte */
  1683. /****************** Bit definition for OB_WRP0 register *********************/
  1684. #define OB_WRP0_WRP0_Pos (0U)
  1685. #define OB_WRP0_WRP0_Msk (0xFFU << OB_WRP0_WRP0_Pos) /*!< 0x000000FF */
  1686. #define OB_WRP0_WRP0 OB_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
  1687. #define OB_WRP0_nWRP0_Pos (8U)
  1688. #define OB_WRP0_nWRP0_Msk (0xFFU << OB_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
  1689. #define OB_WRP0_nWRP0 OB_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
  1690. /******************************************************************************/
  1691. /* */
  1692. /* General Purpose IOs (GPIO) */
  1693. /* */
  1694. /******************************************************************************/
  1695. /******************* Bit definition for GPIO_MODER register *****************/
  1696. #define GPIO_MODER_MODER0_Pos (0U)
  1697. #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
  1698. #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
  1699. #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
  1700. #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
  1701. #define GPIO_MODER_MODER1_Pos (2U)
  1702. #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
  1703. #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
  1704. #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
  1705. #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
  1706. #define GPIO_MODER_MODER2_Pos (4U)
  1707. #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
  1708. #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
  1709. #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
  1710. #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
  1711. #define GPIO_MODER_MODER3_Pos (6U)
  1712. #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
  1713. #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
  1714. #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
  1715. #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
  1716. #define GPIO_MODER_MODER4_Pos (8U)
  1717. #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
  1718. #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
  1719. #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
  1720. #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
  1721. #define GPIO_MODER_MODER5_Pos (10U)
  1722. #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
  1723. #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
  1724. #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
  1725. #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
  1726. #define GPIO_MODER_MODER6_Pos (12U)
  1727. #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
  1728. #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
  1729. #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
  1730. #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
  1731. #define GPIO_MODER_MODER7_Pos (14U)
  1732. #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
  1733. #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
  1734. #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
  1735. #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
  1736. #define GPIO_MODER_MODER8_Pos (16U)
  1737. #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
  1738. #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
  1739. #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
  1740. #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
  1741. #define GPIO_MODER_MODER9_Pos (18U)
  1742. #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
  1743. #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
  1744. #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
  1745. #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
  1746. #define GPIO_MODER_MODER10_Pos (20U)
  1747. #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
  1748. #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
  1749. #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
  1750. #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
  1751. #define GPIO_MODER_MODER11_Pos (22U)
  1752. #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
  1753. #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
  1754. #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
  1755. #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
  1756. #define GPIO_MODER_MODER12_Pos (24U)
  1757. #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
  1758. #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
  1759. #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
  1760. #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
  1761. #define GPIO_MODER_MODER13_Pos (26U)
  1762. #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
  1763. #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
  1764. #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
  1765. #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
  1766. #define GPIO_MODER_MODER14_Pos (28U)
  1767. #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
  1768. #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
  1769. #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
  1770. #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
  1771. #define GPIO_MODER_MODER15_Pos (30U)
  1772. #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
  1773. #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
  1774. #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
  1775. #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
  1776. /****************** Bit definition for GPIO_OTYPER register *****************/
  1777. #define GPIO_OTYPER_OT_0 (0x00000001U)
  1778. #define GPIO_OTYPER_OT_1 (0x00000002U)
  1779. #define GPIO_OTYPER_OT_2 (0x00000004U)
  1780. #define GPIO_OTYPER_OT_3 (0x00000008U)
  1781. #define GPIO_OTYPER_OT_4 (0x00000010U)
  1782. #define GPIO_OTYPER_OT_5 (0x00000020U)
  1783. #define GPIO_OTYPER_OT_6 (0x00000040U)
  1784. #define GPIO_OTYPER_OT_7 (0x00000080U)
  1785. #define GPIO_OTYPER_OT_8 (0x00000100U)
  1786. #define GPIO_OTYPER_OT_9 (0x00000200U)
  1787. #define GPIO_OTYPER_OT_10 (0x00000400U)
  1788. #define GPIO_OTYPER_OT_11 (0x00000800U)
  1789. #define GPIO_OTYPER_OT_12 (0x00001000U)
  1790. #define GPIO_OTYPER_OT_13 (0x00002000U)
  1791. #define GPIO_OTYPER_OT_14 (0x00004000U)
  1792. #define GPIO_OTYPER_OT_15 (0x00008000U)
  1793. /**************** Bit definition for GPIO_OSPEEDR register ******************/
  1794. #define GPIO_OSPEEDR_OSPEEDR0_Pos (0U)
  1795. #define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */
  1796. #define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk
  1797. #define GPIO_OSPEEDR_OSPEEDR0_0 (0x1U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */
  1798. #define GPIO_OSPEEDR_OSPEEDR0_1 (0x2U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */
  1799. #define GPIO_OSPEEDR_OSPEEDR1_Pos (2U)
  1800. #define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */
  1801. #define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk
  1802. #define GPIO_OSPEEDR_OSPEEDR1_0 (0x1U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */
  1803. #define GPIO_OSPEEDR_OSPEEDR1_1 (0x2U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */
  1804. #define GPIO_OSPEEDR_OSPEEDR2_Pos (4U)
  1805. #define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */
  1806. #define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk
  1807. #define GPIO_OSPEEDR_OSPEEDR2_0 (0x1U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */
  1808. #define GPIO_OSPEEDR_OSPEEDR2_1 (0x2U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */
  1809. #define GPIO_OSPEEDR_OSPEEDR3_Pos (6U)
  1810. #define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */
  1811. #define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk
  1812. #define GPIO_OSPEEDR_OSPEEDR3_0 (0x1U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */
  1813. #define GPIO_OSPEEDR_OSPEEDR3_1 (0x2U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */
  1814. #define GPIO_OSPEEDR_OSPEEDR4_Pos (8U)
  1815. #define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */
  1816. #define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk
  1817. #define GPIO_OSPEEDR_OSPEEDR4_0 (0x1U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */
  1818. #define GPIO_OSPEEDR_OSPEEDR4_1 (0x2U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */
  1819. #define GPIO_OSPEEDR_OSPEEDR5_Pos (10U)
  1820. #define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */
  1821. #define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk
  1822. #define GPIO_OSPEEDR_OSPEEDR5_0 (0x1U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */
  1823. #define GPIO_OSPEEDR_OSPEEDR5_1 (0x2U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */
  1824. #define GPIO_OSPEEDR_OSPEEDR6_Pos (12U)
  1825. #define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */
  1826. #define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk
  1827. #define GPIO_OSPEEDR_OSPEEDR6_0 (0x1U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */
  1828. #define GPIO_OSPEEDR_OSPEEDR6_1 (0x2U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */
  1829. #define GPIO_OSPEEDR_OSPEEDR7_Pos (14U)
  1830. #define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */
  1831. #define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk
  1832. #define GPIO_OSPEEDR_OSPEEDR7_0 (0x1U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */
  1833. #define GPIO_OSPEEDR_OSPEEDR7_1 (0x2U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */
  1834. #define GPIO_OSPEEDR_OSPEEDR8_Pos (16U)
  1835. #define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */
  1836. #define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk
  1837. #define GPIO_OSPEEDR_OSPEEDR8_0 (0x1U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */
  1838. #define GPIO_OSPEEDR_OSPEEDR8_1 (0x2U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */
  1839. #define GPIO_OSPEEDR_OSPEEDR9_Pos (18U)
  1840. #define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */
  1841. #define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk
  1842. #define GPIO_OSPEEDR_OSPEEDR9_0 (0x1U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */
  1843. #define GPIO_OSPEEDR_OSPEEDR9_1 (0x2U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */
  1844. #define GPIO_OSPEEDR_OSPEEDR10_Pos (20U)
  1845. #define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */
  1846. #define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk
  1847. #define GPIO_OSPEEDR_OSPEEDR10_0 (0x1U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */
  1848. #define GPIO_OSPEEDR_OSPEEDR10_1 (0x2U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */
  1849. #define GPIO_OSPEEDR_OSPEEDR11_Pos (22U)
  1850. #define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */
  1851. #define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk
  1852. #define GPIO_OSPEEDR_OSPEEDR11_0 (0x1U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */
  1853. #define GPIO_OSPEEDR_OSPEEDR11_1 (0x2U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */
  1854. #define GPIO_OSPEEDR_OSPEEDR12_Pos (24U)
  1855. #define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */
  1856. #define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk
  1857. #define GPIO_OSPEEDR_OSPEEDR12_0 (0x1U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */
  1858. #define GPIO_OSPEEDR_OSPEEDR12_1 (0x2U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */
  1859. #define GPIO_OSPEEDR_OSPEEDR13_Pos (26U)
  1860. #define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */
  1861. #define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk
  1862. #define GPIO_OSPEEDR_OSPEEDR13_0 (0x1U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */
  1863. #define GPIO_OSPEEDR_OSPEEDR13_1 (0x2U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */
  1864. #define GPIO_OSPEEDR_OSPEEDR14_Pos (28U)
  1865. #define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */
  1866. #define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk
  1867. #define GPIO_OSPEEDR_OSPEEDR14_0 (0x1U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */
  1868. #define GPIO_OSPEEDR_OSPEEDR14_1 (0x2U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */
  1869. #define GPIO_OSPEEDR_OSPEEDR15_Pos (30U)
  1870. #define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */
  1871. #define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk
  1872. #define GPIO_OSPEEDR_OSPEEDR15_0 (0x1U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */
  1873. #define GPIO_OSPEEDR_OSPEEDR15_1 (0x2U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */
  1874. /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
  1875. #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
  1876. #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
  1877. #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
  1878. #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
  1879. #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
  1880. #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
  1881. #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
  1882. #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
  1883. #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
  1884. #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
  1885. #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
  1886. #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
  1887. #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
  1888. #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
  1889. #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
  1890. #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
  1891. #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
  1892. #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
  1893. #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
  1894. #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
  1895. #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
  1896. #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
  1897. #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
  1898. #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
  1899. #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
  1900. #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
  1901. #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
  1902. #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
  1903. #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
  1904. #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
  1905. #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
  1906. #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
  1907. #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
  1908. #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
  1909. #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
  1910. #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
  1911. #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
  1912. #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
  1913. #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
  1914. #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
  1915. #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
  1916. #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
  1917. #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
  1918. #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
  1919. #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
  1920. #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
  1921. #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
  1922. #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
  1923. /******************* Bit definition for GPIO_PUPDR register ******************/
  1924. #define GPIO_PUPDR_PUPDR0_Pos (0U)
  1925. #define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */
  1926. #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
  1927. #define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */
  1928. #define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */
  1929. #define GPIO_PUPDR_PUPDR1_Pos (2U)
  1930. #define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */
  1931. #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
  1932. #define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */
  1933. #define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */
  1934. #define GPIO_PUPDR_PUPDR2_Pos (4U)
  1935. #define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */
  1936. #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
  1937. #define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */
  1938. #define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */
  1939. #define GPIO_PUPDR_PUPDR3_Pos (6U)
  1940. #define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */
  1941. #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
  1942. #define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */
  1943. #define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */
  1944. #define GPIO_PUPDR_PUPDR4_Pos (8U)
  1945. #define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */
  1946. #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
  1947. #define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */
  1948. #define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */
  1949. #define GPIO_PUPDR_PUPDR5_Pos (10U)
  1950. #define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */
  1951. #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
  1952. #define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */
  1953. #define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */
  1954. #define GPIO_PUPDR_PUPDR6_Pos (12U)
  1955. #define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */
  1956. #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
  1957. #define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */
  1958. #define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */
  1959. #define GPIO_PUPDR_PUPDR7_Pos (14U)
  1960. #define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */
  1961. #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
  1962. #define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */
  1963. #define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */
  1964. #define GPIO_PUPDR_PUPDR8_Pos (16U)
  1965. #define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */
  1966. #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
  1967. #define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */
  1968. #define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */
  1969. #define GPIO_PUPDR_PUPDR9_Pos (18U)
  1970. #define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */
  1971. #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
  1972. #define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */
  1973. #define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */
  1974. #define GPIO_PUPDR_PUPDR10_Pos (20U)
  1975. #define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */
  1976. #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
  1977. #define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */
  1978. #define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */
  1979. #define GPIO_PUPDR_PUPDR11_Pos (22U)
  1980. #define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */
  1981. #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
  1982. #define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */
  1983. #define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */
  1984. #define GPIO_PUPDR_PUPDR12_Pos (24U)
  1985. #define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */
  1986. #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
  1987. #define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */
  1988. #define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */
  1989. #define GPIO_PUPDR_PUPDR13_Pos (26U)
  1990. #define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */
  1991. #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
  1992. #define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */
  1993. #define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */
  1994. #define GPIO_PUPDR_PUPDR14_Pos (28U)
  1995. #define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */
  1996. #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
  1997. #define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */
  1998. #define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */
  1999. #define GPIO_PUPDR_PUPDR15_Pos (30U)
  2000. #define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */
  2001. #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
  2002. #define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */
  2003. #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
  2004. /******************* Bit definition for GPIO_IDR register *******************/
  2005. #define GPIO_IDR_0 (0x00000001U)
  2006. #define GPIO_IDR_1 (0x00000002U)
  2007. #define GPIO_IDR_2 (0x00000004U)
  2008. #define GPIO_IDR_3 (0x00000008U)
  2009. #define GPIO_IDR_4 (0x00000010U)
  2010. #define GPIO_IDR_5 (0x00000020U)
  2011. #define GPIO_IDR_6 (0x00000040U)
  2012. #define GPIO_IDR_7 (0x00000080U)
  2013. #define GPIO_IDR_8 (0x00000100U)
  2014. #define GPIO_IDR_9 (0x00000200U)
  2015. #define GPIO_IDR_10 (0x00000400U)
  2016. #define GPIO_IDR_11 (0x00000800U)
  2017. #define GPIO_IDR_12 (0x00001000U)
  2018. #define GPIO_IDR_13 (0x00002000U)
  2019. #define GPIO_IDR_14 (0x00004000U)
  2020. #define GPIO_IDR_15 (0x00008000U)
  2021. /****************** Bit definition for GPIO_ODR register ********************/
  2022. #define GPIO_ODR_0 (0x00000001U)
  2023. #define GPIO_ODR_1 (0x00000002U)
  2024. #define GPIO_ODR_2 (0x00000004U)
  2025. #define GPIO_ODR_3 (0x00000008U)
  2026. #define GPIO_ODR_4 (0x00000010U)
  2027. #define GPIO_ODR_5 (0x00000020U)
  2028. #define GPIO_ODR_6 (0x00000040U)
  2029. #define GPIO_ODR_7 (0x00000080U)
  2030. #define GPIO_ODR_8 (0x00000100U)
  2031. #define GPIO_ODR_9 (0x00000200U)
  2032. #define GPIO_ODR_10 (0x00000400U)
  2033. #define GPIO_ODR_11 (0x00000800U)
  2034. #define GPIO_ODR_12 (0x00001000U)
  2035. #define GPIO_ODR_13 (0x00002000U)
  2036. #define GPIO_ODR_14 (0x00004000U)
  2037. #define GPIO_ODR_15 (0x00008000U)
  2038. /****************** Bit definition for GPIO_BSRR register ********************/
  2039. #define GPIO_BSRR_BS_0 (0x00000001U)
  2040. #define GPIO_BSRR_BS_1 (0x00000002U)
  2041. #define GPIO_BSRR_BS_2 (0x00000004U)
  2042. #define GPIO_BSRR_BS_3 (0x00000008U)
  2043. #define GPIO_BSRR_BS_4 (0x00000010U)
  2044. #define GPIO_BSRR_BS_5 (0x00000020U)
  2045. #define GPIO_BSRR_BS_6 (0x00000040U)
  2046. #define GPIO_BSRR_BS_7 (0x00000080U)
  2047. #define GPIO_BSRR_BS_8 (0x00000100U)
  2048. #define GPIO_BSRR_BS_9 (0x00000200U)
  2049. #define GPIO_BSRR_BS_10 (0x00000400U)
  2050. #define GPIO_BSRR_BS_11 (0x00000800U)
  2051. #define GPIO_BSRR_BS_12 (0x00001000U)
  2052. #define GPIO_BSRR_BS_13 (0x00002000U)
  2053. #define GPIO_BSRR_BS_14 (0x00004000U)
  2054. #define GPIO_BSRR_BS_15 (0x00008000U)
  2055. #define GPIO_BSRR_BR_0 (0x00010000U)
  2056. #define GPIO_BSRR_BR_1 (0x00020000U)
  2057. #define GPIO_BSRR_BR_2 (0x00040000U)
  2058. #define GPIO_BSRR_BR_3 (0x00080000U)
  2059. #define GPIO_BSRR_BR_4 (0x00100000U)
  2060. #define GPIO_BSRR_BR_5 (0x00200000U)
  2061. #define GPIO_BSRR_BR_6 (0x00400000U)
  2062. #define GPIO_BSRR_BR_7 (0x00800000U)
  2063. #define GPIO_BSRR_BR_8 (0x01000000U)
  2064. #define GPIO_BSRR_BR_9 (0x02000000U)
  2065. #define GPIO_BSRR_BR_10 (0x04000000U)
  2066. #define GPIO_BSRR_BR_11 (0x08000000U)
  2067. #define GPIO_BSRR_BR_12 (0x10000000U)
  2068. #define GPIO_BSRR_BR_13 (0x20000000U)
  2069. #define GPIO_BSRR_BR_14 (0x40000000U)
  2070. #define GPIO_BSRR_BR_15 (0x80000000U)
  2071. /****************** Bit definition for GPIO_LCKR register ********************/
  2072. #define GPIO_LCKR_LCK0_Pos (0U)
  2073. #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
  2074. #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
  2075. #define GPIO_LCKR_LCK1_Pos (1U)
  2076. #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
  2077. #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
  2078. #define GPIO_LCKR_LCK2_Pos (2U)
  2079. #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
  2080. #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
  2081. #define GPIO_LCKR_LCK3_Pos (3U)
  2082. #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
  2083. #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
  2084. #define GPIO_LCKR_LCK4_Pos (4U)
  2085. #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
  2086. #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
  2087. #define GPIO_LCKR_LCK5_Pos (5U)
  2088. #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
  2089. #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
  2090. #define GPIO_LCKR_LCK6_Pos (6U)
  2091. #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
  2092. #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
  2093. #define GPIO_LCKR_LCK7_Pos (7U)
  2094. #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
  2095. #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
  2096. #define GPIO_LCKR_LCK8_Pos (8U)
  2097. #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
  2098. #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
  2099. #define GPIO_LCKR_LCK9_Pos (9U)
  2100. #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
  2101. #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
  2102. #define GPIO_LCKR_LCK10_Pos (10U)
  2103. #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
  2104. #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
  2105. #define GPIO_LCKR_LCK11_Pos (11U)
  2106. #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
  2107. #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
  2108. #define GPIO_LCKR_LCK12_Pos (12U)
  2109. #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
  2110. #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
  2111. #define GPIO_LCKR_LCK13_Pos (13U)
  2112. #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
  2113. #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
  2114. #define GPIO_LCKR_LCK14_Pos (14U)
  2115. #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
  2116. #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
  2117. #define GPIO_LCKR_LCK15_Pos (15U)
  2118. #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
  2119. #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
  2120. #define GPIO_LCKR_LCKK_Pos (16U)
  2121. #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
  2122. #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
  2123. /****************** Bit definition for GPIO_AFRL register ********************/
  2124. #define GPIO_AFRL_AFRL0_Pos (0U)
  2125. #define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
  2126. #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
  2127. #define GPIO_AFRL_AFRL1_Pos (4U)
  2128. #define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
  2129. #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
  2130. #define GPIO_AFRL_AFRL2_Pos (8U)
  2131. #define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
  2132. #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
  2133. #define GPIO_AFRL_AFRL3_Pos (12U)
  2134. #define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
  2135. #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
  2136. #define GPIO_AFRL_AFRL4_Pos (16U)
  2137. #define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
  2138. #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
  2139. #define GPIO_AFRL_AFRL5_Pos (20U)
  2140. #define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
  2141. #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
  2142. #define GPIO_AFRL_AFRL6_Pos (24U)
  2143. #define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
  2144. #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
  2145. #define GPIO_AFRL_AFRL7_Pos (28U)
  2146. #define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
  2147. #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
  2148. /****************** Bit definition for GPIO_AFRH register ********************/
  2149. #define GPIO_AFRH_AFRH0_Pos (0U)
  2150. #define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
  2151. #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
  2152. #define GPIO_AFRH_AFRH1_Pos (4U)
  2153. #define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
  2154. #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
  2155. #define GPIO_AFRH_AFRH2_Pos (8U)
  2156. #define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
  2157. #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
  2158. #define GPIO_AFRH_AFRH3_Pos (12U)
  2159. #define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
  2160. #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
  2161. #define GPIO_AFRH_AFRH4_Pos (16U)
  2162. #define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
  2163. #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
  2164. #define GPIO_AFRH_AFRH5_Pos (20U)
  2165. #define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
  2166. #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
  2167. #define GPIO_AFRH_AFRH6_Pos (24U)
  2168. #define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
  2169. #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
  2170. #define GPIO_AFRH_AFRH7_Pos (28U)
  2171. #define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
  2172. #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
  2173. /****************** Bit definition for GPIO_BRR register *********************/
  2174. #define GPIO_BRR_BR_0 (0x00000001U)
  2175. #define GPIO_BRR_BR_1 (0x00000002U)
  2176. #define GPIO_BRR_BR_2 (0x00000004U)
  2177. #define GPIO_BRR_BR_3 (0x00000008U)
  2178. #define GPIO_BRR_BR_4 (0x00000010U)
  2179. #define GPIO_BRR_BR_5 (0x00000020U)
  2180. #define GPIO_BRR_BR_6 (0x00000040U)
  2181. #define GPIO_BRR_BR_7 (0x00000080U)
  2182. #define GPIO_BRR_BR_8 (0x00000100U)
  2183. #define GPIO_BRR_BR_9 (0x00000200U)
  2184. #define GPIO_BRR_BR_10 (0x00000400U)
  2185. #define GPIO_BRR_BR_11 (0x00000800U)
  2186. #define GPIO_BRR_BR_12 (0x00001000U)
  2187. #define GPIO_BRR_BR_13 (0x00002000U)
  2188. #define GPIO_BRR_BR_14 (0x00004000U)
  2189. #define GPIO_BRR_BR_15 (0x00008000U)
  2190. /******************************************************************************/
  2191. /* */
  2192. /* Inter-integrated Circuit Interface (I2C) */
  2193. /* */
  2194. /******************************************************************************/
  2195. /******************* Bit definition for I2C_CR1 register *******************/
  2196. #define I2C_CR1_PE_Pos (0U)
  2197. #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
  2198. #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
  2199. #define I2C_CR1_TXIE_Pos (1U)
  2200. #define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
  2201. #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
  2202. #define I2C_CR1_RXIE_Pos (2U)
  2203. #define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
  2204. #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
  2205. #define I2C_CR1_ADDRIE_Pos (3U)
  2206. #define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
  2207. #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
  2208. #define I2C_CR1_NACKIE_Pos (4U)
  2209. #define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
  2210. #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
  2211. #define I2C_CR1_STOPIE_Pos (5U)
  2212. #define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
  2213. #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
  2214. #define I2C_CR1_TCIE_Pos (6U)
  2215. #define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
  2216. #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
  2217. #define I2C_CR1_ERRIE_Pos (7U)
  2218. #define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
  2219. #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
  2220. #define I2C_CR1_DNF_Pos (8U)
  2221. #define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
  2222. #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
  2223. #define I2C_CR1_ANFOFF_Pos (12U)
  2224. #define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
  2225. #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
  2226. #define I2C_CR1_SWRST_Pos (13U)
  2227. #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
  2228. #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
  2229. #define I2C_CR1_TXDMAEN_Pos (14U)
  2230. #define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
  2231. #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
  2232. #define I2C_CR1_RXDMAEN_Pos (15U)
  2233. #define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
  2234. #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
  2235. #define I2C_CR1_SBC_Pos (16U)
  2236. #define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
  2237. #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
  2238. #define I2C_CR1_NOSTRETCH_Pos (17U)
  2239. #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
  2240. #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
  2241. #define I2C_CR1_GCEN_Pos (19U)
  2242. #define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
  2243. #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
  2244. #define I2C_CR1_SMBHEN_Pos (20U)
  2245. #define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
  2246. #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
  2247. #define I2C_CR1_SMBDEN_Pos (21U)
  2248. #define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
  2249. #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
  2250. #define I2C_CR1_ALERTEN_Pos (22U)
  2251. #define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
  2252. #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
  2253. #define I2C_CR1_PECEN_Pos (23U)
  2254. #define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
  2255. #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
  2256. /****************** Bit definition for I2C_CR2 register ********************/
  2257. #define I2C_CR2_SADD_Pos (0U)
  2258. #define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
  2259. #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
  2260. #define I2C_CR2_RD_WRN_Pos (10U)
  2261. #define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
  2262. #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
  2263. #define I2C_CR2_ADD10_Pos (11U)
  2264. #define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
  2265. #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
  2266. #define I2C_CR2_HEAD10R_Pos (12U)
  2267. #define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
  2268. #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
  2269. #define I2C_CR2_START_Pos (13U)
  2270. #define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
  2271. #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
  2272. #define I2C_CR2_STOP_Pos (14U)
  2273. #define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
  2274. #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
  2275. #define I2C_CR2_NACK_Pos (15U)
  2276. #define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
  2277. #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
  2278. #define I2C_CR2_NBYTES_Pos (16U)
  2279. #define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
  2280. #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
  2281. #define I2C_CR2_RELOAD_Pos (24U)
  2282. #define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
  2283. #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
  2284. #define I2C_CR2_AUTOEND_Pos (25U)
  2285. #define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
  2286. #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
  2287. #define I2C_CR2_PECBYTE_Pos (26U)
  2288. #define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
  2289. #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
  2290. /******************* Bit definition for I2C_OAR1 register ******************/
  2291. #define I2C_OAR1_OA1_Pos (0U)
  2292. #define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
  2293. #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
  2294. #define I2C_OAR1_OA1MODE_Pos (10U)
  2295. #define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
  2296. #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
  2297. #define I2C_OAR1_OA1EN_Pos (15U)
  2298. #define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
  2299. #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
  2300. /******************* Bit definition for I2C_OAR2 register ******************/
  2301. #define I2C_OAR2_OA2_Pos (1U)
  2302. #define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
  2303. #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
  2304. #define I2C_OAR2_OA2MSK_Pos (8U)
  2305. #define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
  2306. #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
  2307. #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
  2308. #define I2C_OAR2_OA2MASK01_Pos (8U)
  2309. #define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
  2310. #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
  2311. #define I2C_OAR2_OA2MASK02_Pos (9U)
  2312. #define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
  2313. #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
  2314. #define I2C_OAR2_OA2MASK03_Pos (8U)
  2315. #define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
  2316. #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
  2317. #define I2C_OAR2_OA2MASK04_Pos (10U)
  2318. #define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
  2319. #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
  2320. #define I2C_OAR2_OA2MASK05_Pos (8U)
  2321. #define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
  2322. #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
  2323. #define I2C_OAR2_OA2MASK06_Pos (9U)
  2324. #define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
  2325. #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
  2326. #define I2C_OAR2_OA2MASK07_Pos (8U)
  2327. #define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
  2328. #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
  2329. #define I2C_OAR2_OA2EN_Pos (15U)
  2330. #define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
  2331. #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
  2332. /******************* Bit definition for I2C_TIMINGR register ****************/
  2333. #define I2C_TIMINGR_SCLL_Pos (0U)
  2334. #define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
  2335. #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
  2336. #define I2C_TIMINGR_SCLH_Pos (8U)
  2337. #define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
  2338. #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
  2339. #define I2C_TIMINGR_SDADEL_Pos (16U)
  2340. #define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
  2341. #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
  2342. #define I2C_TIMINGR_SCLDEL_Pos (20U)
  2343. #define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
  2344. #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
  2345. #define I2C_TIMINGR_PRESC_Pos (28U)
  2346. #define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
  2347. #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
  2348. /******************* Bit definition for I2C_TIMEOUTR register ****************/
  2349. #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
  2350. #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
  2351. #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
  2352. #define I2C_TIMEOUTR_TIDLE_Pos (12U)
  2353. #define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
  2354. #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
  2355. #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
  2356. #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
  2357. #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
  2358. #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
  2359. #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
  2360. #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
  2361. #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
  2362. #define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
  2363. #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
  2364. /****************** Bit definition for I2C_ISR register ********************/
  2365. #define I2C_ISR_TXE_Pos (0U)
  2366. #define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
  2367. #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
  2368. #define I2C_ISR_TXIS_Pos (1U)
  2369. #define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
  2370. #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
  2371. #define I2C_ISR_RXNE_Pos (2U)
  2372. #define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
  2373. #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
  2374. #define I2C_ISR_ADDR_Pos (3U)
  2375. #define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
  2376. #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
  2377. #define I2C_ISR_NACKF_Pos (4U)
  2378. #define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
  2379. #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
  2380. #define I2C_ISR_STOPF_Pos (5U)
  2381. #define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
  2382. #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
  2383. #define I2C_ISR_TC_Pos (6U)
  2384. #define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
  2385. #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
  2386. #define I2C_ISR_TCR_Pos (7U)
  2387. #define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
  2388. #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
  2389. #define I2C_ISR_BERR_Pos (8U)
  2390. #define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
  2391. #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
  2392. #define I2C_ISR_ARLO_Pos (9U)
  2393. #define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
  2394. #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
  2395. #define I2C_ISR_OVR_Pos (10U)
  2396. #define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
  2397. #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
  2398. #define I2C_ISR_PECERR_Pos (11U)
  2399. #define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
  2400. #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
  2401. #define I2C_ISR_TIMEOUT_Pos (12U)
  2402. #define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
  2403. #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
  2404. #define I2C_ISR_ALERT_Pos (13U)
  2405. #define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
  2406. #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
  2407. #define I2C_ISR_BUSY_Pos (15U)
  2408. #define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
  2409. #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
  2410. #define I2C_ISR_DIR_Pos (16U)
  2411. #define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
  2412. #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
  2413. #define I2C_ISR_ADDCODE_Pos (17U)
  2414. #define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
  2415. #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
  2416. /****************** Bit definition for I2C_ICR register ********************/
  2417. #define I2C_ICR_ADDRCF_Pos (3U)
  2418. #define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
  2419. #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
  2420. #define I2C_ICR_NACKCF_Pos (4U)
  2421. #define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
  2422. #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
  2423. #define I2C_ICR_STOPCF_Pos (5U)
  2424. #define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
  2425. #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
  2426. #define I2C_ICR_BERRCF_Pos (8U)
  2427. #define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
  2428. #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
  2429. #define I2C_ICR_ARLOCF_Pos (9U)
  2430. #define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
  2431. #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
  2432. #define I2C_ICR_OVRCF_Pos (10U)
  2433. #define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
  2434. #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
  2435. #define I2C_ICR_PECCF_Pos (11U)
  2436. #define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
  2437. #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
  2438. #define I2C_ICR_TIMOUTCF_Pos (12U)
  2439. #define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
  2440. #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
  2441. #define I2C_ICR_ALERTCF_Pos (13U)
  2442. #define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
  2443. #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
  2444. /****************** Bit definition for I2C_PECR register *******************/
  2445. #define I2C_PECR_PEC_Pos (0U)
  2446. #define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
  2447. #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
  2448. /****************** Bit definition for I2C_RXDR register *********************/
  2449. #define I2C_RXDR_RXDATA_Pos (0U)
  2450. #define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
  2451. #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
  2452. /****************** Bit definition for I2C_TXDR register *******************/
  2453. #define I2C_TXDR_TXDATA_Pos (0U)
  2454. #define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
  2455. #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
  2456. /*****************************************************************************/
  2457. /* */
  2458. /* Independent WATCHDOG (IWDG) */
  2459. /* */
  2460. /*****************************************************************************/
  2461. /******************* Bit definition for IWDG_KR register *******************/
  2462. #define IWDG_KR_KEY_Pos (0U)
  2463. #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
  2464. #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
  2465. /******************* Bit definition for IWDG_PR register *******************/
  2466. #define IWDG_PR_PR_Pos (0U)
  2467. #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
  2468. #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
  2469. #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
  2470. #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
  2471. #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
  2472. /******************* Bit definition for IWDG_RLR register ******************/
  2473. #define IWDG_RLR_RL_Pos (0U)
  2474. #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
  2475. #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
  2476. /******************* Bit definition for IWDG_SR register *******************/
  2477. #define IWDG_SR_PVU_Pos (0U)
  2478. #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
  2479. #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
  2480. #define IWDG_SR_RVU_Pos (1U)
  2481. #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
  2482. #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
  2483. #define IWDG_SR_WVU_Pos (2U)
  2484. #define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
  2485. #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
  2486. /******************* Bit definition for IWDG_KR register *******************/
  2487. #define IWDG_WINR_WIN_Pos (0U)
  2488. #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
  2489. #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
  2490. /*****************************************************************************/
  2491. /* */
  2492. /* Power Control (PWR) */
  2493. /* */
  2494. /*****************************************************************************/
  2495. /* Note: No specific macro feature on this device */
  2496. /******************** Bit definition for PWR_CR register *******************/
  2497. #define PWR_CR_LPDS_Pos (0U)
  2498. #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
  2499. #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-power Deepsleep */
  2500. #define PWR_CR_PDDS_Pos (1U)
  2501. #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
  2502. #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
  2503. #define PWR_CR_CWUF_Pos (2U)
  2504. #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
  2505. #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
  2506. #define PWR_CR_CSBF_Pos (3U)
  2507. #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
  2508. #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
  2509. #define PWR_CR_DBP_Pos (8U)
  2510. #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
  2511. #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
  2512. /******************* Bit definition for PWR_CSR register *******************/
  2513. #define PWR_CSR_WUF_Pos (0U)
  2514. #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
  2515. #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
  2516. #define PWR_CSR_SBF_Pos (1U)
  2517. #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
  2518. #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
  2519. #define PWR_CSR_EWUP1_Pos (8U)
  2520. #define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
  2521. #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
  2522. #define PWR_CSR_EWUP2_Pos (9U)
  2523. #define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
  2524. #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
  2525. /*****************************************************************************/
  2526. /* */
  2527. /* Reset and Clock Control */
  2528. /* */
  2529. /*****************************************************************************/
  2530. /*
  2531. * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
  2532. */
  2533. /******************** Bit definition for RCC_CR register *******************/
  2534. #define RCC_CR_HSION_Pos (0U)
  2535. #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
  2536. #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
  2537. #define RCC_CR_HSIRDY_Pos (1U)
  2538. #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
  2539. #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
  2540. #define RCC_CR_HSITRIM_Pos (3U)
  2541. #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
  2542. #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
  2543. #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
  2544. #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
  2545. #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
  2546. #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
  2547. #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
  2548. #define RCC_CR_HSICAL_Pos (8U)
  2549. #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
  2550. #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
  2551. #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
  2552. #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
  2553. #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
  2554. #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
  2555. #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
  2556. #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
  2557. #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
  2558. #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
  2559. #define RCC_CR_HSEON_Pos (16U)
  2560. #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
  2561. #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
  2562. #define RCC_CR_HSERDY_Pos (17U)
  2563. #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
  2564. #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
  2565. #define RCC_CR_HSEBYP_Pos (18U)
  2566. #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
  2567. #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
  2568. #define RCC_CR_CSSON_Pos (19U)
  2569. #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
  2570. #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
  2571. #define RCC_CR_PLLON_Pos (24U)
  2572. #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
  2573. #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
  2574. #define RCC_CR_PLLRDY_Pos (25U)
  2575. #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
  2576. #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
  2577. /******************** Bit definition for RCC_CFGR register *****************/
  2578. /*!< SW configuration */
  2579. #define RCC_CFGR_SW_Pos (0U)
  2580. #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
  2581. #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
  2582. #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
  2583. #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
  2584. #define RCC_CFGR_SW_HSI (0x00000000U) /*!< HSI selected as system clock */
  2585. #define RCC_CFGR_SW_HSE (0x00000001U) /*!< HSE selected as system clock */
  2586. #define RCC_CFGR_SW_PLL (0x00000002U) /*!< PLL selected as system clock */
  2587. /*!< SWS configuration */
  2588. #define RCC_CFGR_SWS_Pos (2U)
  2589. #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
  2590. #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
  2591. #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
  2592. #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
  2593. #define RCC_CFGR_SWS_HSI (0x00000000U) /*!< HSI oscillator used as system clock */
  2594. #define RCC_CFGR_SWS_HSE (0x00000004U) /*!< HSE oscillator used as system clock */
  2595. #define RCC_CFGR_SWS_PLL (0x00000008U) /*!< PLL used as system clock */
  2596. /*!< HPRE configuration */
  2597. #define RCC_CFGR_HPRE_Pos (4U)
  2598. #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
  2599. #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
  2600. #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
  2601. #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
  2602. #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
  2603. #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
  2604. #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
  2605. #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
  2606. #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
  2607. #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
  2608. #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
  2609. #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
  2610. #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
  2611. #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
  2612. #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
  2613. /*!< PPRE configuration */
  2614. #define RCC_CFGR_PPRE_Pos (8U)
  2615. #define RCC_CFGR_PPRE_Msk (0x7U << RCC_CFGR_PPRE_Pos) /*!< 0x00000700 */
  2616. #define RCC_CFGR_PPRE RCC_CFGR_PPRE_Msk /*!< PRE[2:0] bits (APB prescaler) */
  2617. #define RCC_CFGR_PPRE_0 (0x1U << RCC_CFGR_PPRE_Pos) /*!< 0x00000100 */
  2618. #define RCC_CFGR_PPRE_1 (0x2U << RCC_CFGR_PPRE_Pos) /*!< 0x00000200 */
  2619. #define RCC_CFGR_PPRE_2 (0x4U << RCC_CFGR_PPRE_Pos) /*!< 0x00000400 */
  2620. #define RCC_CFGR_PPRE_DIV1 (0x00000000U) /*!< HCLK not divided */
  2621. #define RCC_CFGR_PPRE_DIV2_Pos (10U)
  2622. #define RCC_CFGR_PPRE_DIV2_Msk (0x1U << RCC_CFGR_PPRE_DIV2_Pos) /*!< 0x00000400 */
  2623. #define RCC_CFGR_PPRE_DIV2 RCC_CFGR_PPRE_DIV2_Msk /*!< HCLK divided by 2 */
  2624. #define RCC_CFGR_PPRE_DIV4_Pos (8U)
  2625. #define RCC_CFGR_PPRE_DIV4_Msk (0x5U << RCC_CFGR_PPRE_DIV4_Pos) /*!< 0x00000500 */
  2626. #define RCC_CFGR_PPRE_DIV4 RCC_CFGR_PPRE_DIV4_Msk /*!< HCLK divided by 4 */
  2627. #define RCC_CFGR_PPRE_DIV8_Pos (9U)
  2628. #define RCC_CFGR_PPRE_DIV8_Msk (0x3U << RCC_CFGR_PPRE_DIV8_Pos) /*!< 0x00000600 */
  2629. #define RCC_CFGR_PPRE_DIV8 RCC_CFGR_PPRE_DIV8_Msk /*!< HCLK divided by 8 */
  2630. #define RCC_CFGR_PPRE_DIV16_Pos (8U)
  2631. #define RCC_CFGR_PPRE_DIV16_Msk (0x7U << RCC_CFGR_PPRE_DIV16_Pos) /*!< 0x00000700 */
  2632. #define RCC_CFGR_PPRE_DIV16 RCC_CFGR_PPRE_DIV16_Msk /*!< HCLK divided by 16 */
  2633. /*!< ADCPPRE configuration */
  2634. #define RCC_CFGR_ADCPRE_Pos (14U)
  2635. #define RCC_CFGR_ADCPRE_Msk (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
  2636. #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE bit (ADC prescaler) */
  2637. #define RCC_CFGR_ADCPRE_DIV2 (0x00000000U) /*!< PCLK divided by 2 */
  2638. #define RCC_CFGR_ADCPRE_DIV4 (0x00004000U) /*!< PCLK divided by 4 */
  2639. #define RCC_CFGR_PLLSRC_Pos (16U)
  2640. #define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
  2641. #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
  2642. #define RCC_CFGR_PLLSRC_HSI_DIV2 (0x00000000U) /*!< HSI clock divided by 2 selected as PLL entry clock source */
  2643. #define RCC_CFGR_PLLSRC_HSE_PREDIV (0x00010000U) /*!< HSE/PREDIV clock selected as PLL entry clock source */
  2644. #define RCC_CFGR_PLLXTPRE_Pos (17U)
  2645. #define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
  2646. #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
  2647. #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 (0x00000000U) /*!< HSE/PREDIV clock not divided for PLL entry */
  2648. #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 (0x00020000U) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
  2649. /*!< PLLMUL configuration */
  2650. #define RCC_CFGR_PLLMUL_Pos (18U)
  2651. #define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
  2652. #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
  2653. #define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
  2654. #define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
  2655. #define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
  2656. #define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
  2657. #define RCC_CFGR_PLLMUL2 (0x00000000U) /*!< PLL input clock*2 */
  2658. #define RCC_CFGR_PLLMUL3 (0x00040000U) /*!< PLL input clock*3 */
  2659. #define RCC_CFGR_PLLMUL4 (0x00080000U) /*!< PLL input clock*4 */
  2660. #define RCC_CFGR_PLLMUL5 (0x000C0000U) /*!< PLL input clock*5 */
  2661. #define RCC_CFGR_PLLMUL6 (0x00100000U) /*!< PLL input clock*6 */
  2662. #define RCC_CFGR_PLLMUL7 (0x00140000U) /*!< PLL input clock*7 */
  2663. #define RCC_CFGR_PLLMUL8 (0x00180000U) /*!< PLL input clock*8 */
  2664. #define RCC_CFGR_PLLMUL9 (0x001C0000U) /*!< PLL input clock*9 */
  2665. #define RCC_CFGR_PLLMUL10 (0x00200000U) /*!< PLL input clock10 */
  2666. #define RCC_CFGR_PLLMUL11 (0x00240000U) /*!< PLL input clock*11 */
  2667. #define RCC_CFGR_PLLMUL12 (0x00280000U) /*!< PLL input clock*12 */
  2668. #define RCC_CFGR_PLLMUL13 (0x002C0000U) /*!< PLL input clock*13 */
  2669. #define RCC_CFGR_PLLMUL14 (0x00300000U) /*!< PLL input clock*14 */
  2670. #define RCC_CFGR_PLLMUL15 (0x00340000U) /*!< PLL input clock*15 */
  2671. #define RCC_CFGR_PLLMUL16 (0x00380000U) /*!< PLL input clock*16 */
  2672. /*!< MCO configuration */
  2673. #define RCC_CFGR_MCO_Pos (24U)
  2674. #define RCC_CFGR_MCO_Msk (0xFU << RCC_CFGR_MCO_Pos) /*!< 0x0F000000 */
  2675. #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
  2676. #define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
  2677. #define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
  2678. #define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
  2679. #define RCC_CFGR_MCO_NOCLOCK (0x00000000U) /*!< No clock */
  2680. #define RCC_CFGR_MCO_HSI14 (0x01000000U) /*!< HSI14 clock selected as MCO source */
  2681. #define RCC_CFGR_MCO_LSI (0x02000000U) /*!< LSI clock selected as MCO source */
  2682. #define RCC_CFGR_MCO_LSE (0x03000000U) /*!< LSE clock selected as MCO source */
  2683. #define RCC_CFGR_MCO_SYSCLK (0x04000000U) /*!< System clock selected as MCO source */
  2684. #define RCC_CFGR_MCO_HSI (0x05000000U) /*!< HSI clock selected as MCO source */
  2685. #define RCC_CFGR_MCO_HSE (0x06000000U) /*!< HSE clock selected as MCO source */
  2686. #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divided by 2 selected as MCO source */
  2687. #define RCC_CFGR_MCOPRE_Pos (28U)
  2688. #define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
  2689. #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
  2690. #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
  2691. #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
  2692. #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
  2693. #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
  2694. #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
  2695. #define RCC_CFGR_MCOPRE_DIV32 (0x50000000U) /*!< MCO is divided by 32 */
  2696. #define RCC_CFGR_MCOPRE_DIV64 (0x60000000U) /*!< MCO is divided by 64 */
  2697. #define RCC_CFGR_MCOPRE_DIV128 (0x70000000U) /*!< MCO is divided by 128 */
  2698. #define RCC_CFGR_PLLNODIV_Pos (31U)
  2699. #define RCC_CFGR_PLLNODIV_Msk (0x1U << RCC_CFGR_PLLNODIV_Pos) /*!< 0x80000000 */
  2700. #define RCC_CFGR_PLLNODIV RCC_CFGR_PLLNODIV_Msk /*!< PLL is not divided to MCO */
  2701. /* Reference defines */
  2702. #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
  2703. #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
  2704. #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
  2705. #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
  2706. #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
  2707. #define RCC_CFGR_MCOSEL_HSI14 RCC_CFGR_MCO_HSI14
  2708. #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCO_LSI
  2709. #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCO_LSE
  2710. #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
  2711. #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
  2712. #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
  2713. #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
  2714. /*!<****************** Bit definition for RCC_CIR register *****************/
  2715. #define RCC_CIR_LSIRDYF_Pos (0U)
  2716. #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
  2717. #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
  2718. #define RCC_CIR_LSERDYF_Pos (1U)
  2719. #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
  2720. #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
  2721. #define RCC_CIR_HSIRDYF_Pos (2U)
  2722. #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
  2723. #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
  2724. #define RCC_CIR_HSERDYF_Pos (3U)
  2725. #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
  2726. #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
  2727. #define RCC_CIR_PLLRDYF_Pos (4U)
  2728. #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
  2729. #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
  2730. #define RCC_CIR_HSI14RDYF_Pos (5U)
  2731. #define RCC_CIR_HSI14RDYF_Msk (0x1U << RCC_CIR_HSI14RDYF_Pos) /*!< 0x00000020 */
  2732. #define RCC_CIR_HSI14RDYF RCC_CIR_HSI14RDYF_Msk /*!< HSI14 Ready Interrupt flag */
  2733. #define RCC_CIR_CSSF_Pos (7U)
  2734. #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
  2735. #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
  2736. #define RCC_CIR_LSIRDYIE_Pos (8U)
  2737. #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
  2738. #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
  2739. #define RCC_CIR_LSERDYIE_Pos (9U)
  2740. #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
  2741. #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
  2742. #define RCC_CIR_HSIRDYIE_Pos (10U)
  2743. #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
  2744. #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
  2745. #define RCC_CIR_HSERDYIE_Pos (11U)
  2746. #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
  2747. #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
  2748. #define RCC_CIR_PLLRDYIE_Pos (12U)
  2749. #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
  2750. #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
  2751. #define RCC_CIR_HSI14RDYIE_Pos (13U)
  2752. #define RCC_CIR_HSI14RDYIE_Msk (0x1U << RCC_CIR_HSI14RDYIE_Pos) /*!< 0x00002000 */
  2753. #define RCC_CIR_HSI14RDYIE RCC_CIR_HSI14RDYIE_Msk /*!< HSI14 Ready Interrupt Enable */
  2754. #define RCC_CIR_LSIRDYC_Pos (16U)
  2755. #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
  2756. #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
  2757. #define RCC_CIR_LSERDYC_Pos (17U)
  2758. #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
  2759. #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
  2760. #define RCC_CIR_HSIRDYC_Pos (18U)
  2761. #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
  2762. #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
  2763. #define RCC_CIR_HSERDYC_Pos (19U)
  2764. #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
  2765. #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
  2766. #define RCC_CIR_PLLRDYC_Pos (20U)
  2767. #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
  2768. #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
  2769. #define RCC_CIR_HSI14RDYC_Pos (21U)
  2770. #define RCC_CIR_HSI14RDYC_Msk (0x1U << RCC_CIR_HSI14RDYC_Pos) /*!< 0x00200000 */
  2771. #define RCC_CIR_HSI14RDYC RCC_CIR_HSI14RDYC_Msk /*!< HSI14 Ready Interrupt Clear */
  2772. #define RCC_CIR_CSSC_Pos (23U)
  2773. #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
  2774. #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
  2775. /***************** Bit definition for RCC_APB2RSTR register ****************/
  2776. #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
  2777. #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
  2778. #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */
  2779. #define RCC_APB2RSTR_ADCRST_Pos (9U)
  2780. #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
  2781. #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC clock reset */
  2782. #define RCC_APB2RSTR_TIM1RST_Pos (11U)
  2783. #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
  2784. #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 clock reset */
  2785. #define RCC_APB2RSTR_SPI1RST_Pos (12U)
  2786. #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
  2787. #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */
  2788. #define RCC_APB2RSTR_USART1RST_Pos (14U)
  2789. #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
  2790. #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */
  2791. #define RCC_APB2RSTR_TIM16RST_Pos (17U)
  2792. #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
  2793. #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 clock reset */
  2794. #define RCC_APB2RSTR_TIM17RST_Pos (18U)
  2795. #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
  2796. #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 clock reset */
  2797. #define RCC_APB2RSTR_DBGMCURST_Pos (22U)
  2798. #define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */
  2799. #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU clock reset */
  2800. /*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
  2801. #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
  2802. /***************** Bit definition for RCC_APB1RSTR register ****************/
  2803. #define RCC_APB1RSTR_TIM3RST_Pos (1U)
  2804. #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
  2805. #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */
  2806. #define RCC_APB1RSTR_TIM14RST_Pos (8U)
  2807. #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
  2808. #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 clock reset */
  2809. #define RCC_APB1RSTR_WWDGRST_Pos (11U)
  2810. #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
  2811. #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */
  2812. #define RCC_APB1RSTR_I2C1RST_Pos (21U)
  2813. #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
  2814. #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */
  2815. #define RCC_APB1RSTR_PWRRST_Pos (28U)
  2816. #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
  2817. #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */
  2818. /****************** Bit definition for RCC_AHBENR register *****************/
  2819. #define RCC_AHBENR_DMAEN_Pos (0U)
  2820. #define RCC_AHBENR_DMAEN_Msk (0x1U << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
  2821. #define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */
  2822. #define RCC_AHBENR_SRAMEN_Pos (2U)
  2823. #define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
  2824. #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
  2825. #define RCC_AHBENR_FLITFEN_Pos (4U)
  2826. #define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
  2827. #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
  2828. #define RCC_AHBENR_CRCEN_Pos (6U)
  2829. #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
  2830. #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
  2831. #define RCC_AHBENR_GPIOAEN_Pos (17U)
  2832. #define RCC_AHBENR_GPIOAEN_Msk (0x1U << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00020000 */
  2833. #define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /*!< GPIOA clock enable */
  2834. #define RCC_AHBENR_GPIOBEN_Pos (18U)
  2835. #define RCC_AHBENR_GPIOBEN_Msk (0x1U << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00040000 */
  2836. #define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /*!< GPIOB clock enable */
  2837. #define RCC_AHBENR_GPIOCEN_Pos (19U)
  2838. #define RCC_AHBENR_GPIOCEN_Msk (0x1U << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00080000 */
  2839. #define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /*!< GPIOC clock enable */
  2840. #define RCC_AHBENR_GPIODEN_Pos (20U)
  2841. #define RCC_AHBENR_GPIODEN_Msk (0x1U << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00100000 */
  2842. #define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /*!< GPIOD clock enable */
  2843. #define RCC_AHBENR_GPIOFEN_Pos (22U)
  2844. #define RCC_AHBENR_GPIOFEN_Msk (0x1U << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00400000 */
  2845. #define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk /*!< GPIOF clock enable */
  2846. /* Old Bit definition maintained for legacy purpose */
  2847. #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
  2848. #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
  2849. /***************** Bit definition for RCC_APB2ENR register *****************/
  2850. #define RCC_APB2ENR_SYSCFGCOMPEN_Pos (0U)
  2851. #define RCC_APB2ENR_SYSCFGCOMPEN_Msk (0x1U << RCC_APB2ENR_SYSCFGCOMPEN_Pos) /*!< 0x00000001 */
  2852. #define RCC_APB2ENR_SYSCFGCOMPEN RCC_APB2ENR_SYSCFGCOMPEN_Msk /*!< SYSCFG and comparator clock enable */
  2853. #define RCC_APB2ENR_ADCEN_Pos (9U)
  2854. #define RCC_APB2ENR_ADCEN_Msk (0x1U << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
  2855. #define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */
  2856. #define RCC_APB2ENR_TIM1EN_Pos (11U)
  2857. #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
  2858. #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 clock enable */
  2859. #define RCC_APB2ENR_SPI1EN_Pos (12U)
  2860. #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
  2861. #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
  2862. #define RCC_APB2ENR_USART1EN_Pos (14U)
  2863. #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
  2864. #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
  2865. #define RCC_APB2ENR_TIM16EN_Pos (17U)
  2866. #define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
  2867. #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 clock enable */
  2868. #define RCC_APB2ENR_TIM17EN_Pos (18U)
  2869. #define RCC_APB2ENR_TIM17EN_Msk (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
  2870. #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 clock enable */
  2871. #define RCC_APB2ENR_DBGMCUEN_Pos (22U)
  2872. #define RCC_APB2ENR_DBGMCUEN_Msk (0x1U << RCC_APB2ENR_DBGMCUEN_Pos) /*!< 0x00400000 */
  2873. #define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGMCUEN_Msk /*!< DBGMCU clock enable */
  2874. /* Old Bit definition maintained for legacy purpose */
  2875. #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
  2876. #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
  2877. /***************** Bit definition for RCC_APB1ENR register *****************/
  2878. #define RCC_APB1ENR_TIM3EN_Pos (1U)
  2879. #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
  2880. #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
  2881. #define RCC_APB1ENR_TIM14EN_Pos (8U)
  2882. #define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
  2883. #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk /*!< Timer 14 clock enable */
  2884. #define RCC_APB1ENR_WWDGEN_Pos (11U)
  2885. #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
  2886. #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
  2887. #define RCC_APB1ENR_I2C1EN_Pos (21U)
  2888. #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
  2889. #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */
  2890. #define RCC_APB1ENR_PWREN_Pos (28U)
  2891. #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
  2892. #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
  2893. /******************* Bit definition for RCC_BDCR register ******************/
  2894. #define RCC_BDCR_LSEON_Pos (0U)
  2895. #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
  2896. #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
  2897. #define RCC_BDCR_LSERDY_Pos (1U)
  2898. #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
  2899. #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
  2900. #define RCC_BDCR_LSEBYP_Pos (2U)
  2901. #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
  2902. #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
  2903. #define RCC_BDCR_LSEDRV_Pos (3U)
  2904. #define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
  2905. #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
  2906. #define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
  2907. #define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
  2908. #define RCC_BDCR_RTCSEL_Pos (8U)
  2909. #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
  2910. #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
  2911. #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
  2912. #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
  2913. /*!< RTC configuration */
  2914. #define RCC_BDCR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
  2915. #define RCC_BDCR_RTCSEL_LSE (0x00000100U) /*!< LSE oscillator clock used as RTC clock */
  2916. #define RCC_BDCR_RTCSEL_LSI (0x00000200U) /*!< LSI oscillator clock used as RTC clock */
  2917. #define RCC_BDCR_RTCSEL_HSE (0x00000300U) /*!< HSE oscillator clock divided by 128 used as RTC clock */
  2918. #define RCC_BDCR_RTCEN_Pos (15U)
  2919. #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
  2920. #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
  2921. #define RCC_BDCR_BDRST_Pos (16U)
  2922. #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
  2923. #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
  2924. /******************* Bit definition for RCC_CSR register *******************/
  2925. #define RCC_CSR_LSION_Pos (0U)
  2926. #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
  2927. #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
  2928. #define RCC_CSR_LSIRDY_Pos (1U)
  2929. #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
  2930. #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
  2931. #define RCC_CSR_V18PWRRSTF_Pos (23U)
  2932. #define RCC_CSR_V18PWRRSTF_Msk (0x1U << RCC_CSR_V18PWRRSTF_Pos) /*!< 0x00800000 */
  2933. #define RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF_Msk /*!< V1.8 power domain reset flag */
  2934. #define RCC_CSR_RMVF_Pos (24U)
  2935. #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
  2936. #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
  2937. #define RCC_CSR_OBLRSTF_Pos (25U)
  2938. #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
  2939. #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
  2940. #define RCC_CSR_PINRSTF_Pos (26U)
  2941. #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
  2942. #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
  2943. #define RCC_CSR_PORRSTF_Pos (27U)
  2944. #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
  2945. #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
  2946. #define RCC_CSR_SFTRSTF_Pos (28U)
  2947. #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
  2948. #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
  2949. #define RCC_CSR_IWDGRSTF_Pos (29U)
  2950. #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
  2951. #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
  2952. #define RCC_CSR_WWDGRSTF_Pos (30U)
  2953. #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
  2954. #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
  2955. #define RCC_CSR_LPWRRSTF_Pos (31U)
  2956. #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
  2957. #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
  2958. /* Old Bit definition maintained for legacy purpose */
  2959. #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
  2960. /******************* Bit definition for RCC_AHBRSTR register ***************/
  2961. #define RCC_AHBRSTR_GPIOARST_Pos (17U)
  2962. #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
  2963. #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA clock reset */
  2964. #define RCC_AHBRSTR_GPIOBRST_Pos (18U)
  2965. #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
  2966. #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB clock reset */
  2967. #define RCC_AHBRSTR_GPIOCRST_Pos (19U)
  2968. #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
  2969. #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC clock reset */
  2970. #define RCC_AHBRSTR_GPIODRST_Pos (20U)
  2971. #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */
  2972. #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD clock reset */
  2973. #define RCC_AHBRSTR_GPIOFRST_Pos (22U)
  2974. #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
  2975. #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF clock reset */
  2976. /******************* Bit definition for RCC_CFGR2 register *****************/
  2977. /*!< PREDIV configuration */
  2978. #define RCC_CFGR2_PREDIV_Pos (0U)
  2979. #define RCC_CFGR2_PREDIV_Msk (0xFU << RCC_CFGR2_PREDIV_Pos) /*!< 0x0000000F */
  2980. #define RCC_CFGR2_PREDIV RCC_CFGR2_PREDIV_Msk /*!< PREDIV[3:0] bits */
  2981. #define RCC_CFGR2_PREDIV_0 (0x1U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000001 */
  2982. #define RCC_CFGR2_PREDIV_1 (0x2U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000002 */
  2983. #define RCC_CFGR2_PREDIV_2 (0x4U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000004 */
  2984. #define RCC_CFGR2_PREDIV_3 (0x8U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000008 */
  2985. #define RCC_CFGR2_PREDIV_DIV1 (0x00000000U) /*!< PREDIV input clock not divided */
  2986. #define RCC_CFGR2_PREDIV_DIV2 (0x00000001U) /*!< PREDIV input clock divided by 2 */
  2987. #define RCC_CFGR2_PREDIV_DIV3 (0x00000002U) /*!< PREDIV input clock divided by 3 */
  2988. #define RCC_CFGR2_PREDIV_DIV4 (0x00000003U) /*!< PREDIV input clock divided by 4 */
  2989. #define RCC_CFGR2_PREDIV_DIV5 (0x00000004U) /*!< PREDIV input clock divided by 5 */
  2990. #define RCC_CFGR2_PREDIV_DIV6 (0x00000005U) /*!< PREDIV input clock divided by 6 */
  2991. #define RCC_CFGR2_PREDIV_DIV7 (0x00000006U) /*!< PREDIV input clock divided by 7 */
  2992. #define RCC_CFGR2_PREDIV_DIV8 (0x00000007U) /*!< PREDIV input clock divided by 8 */
  2993. #define RCC_CFGR2_PREDIV_DIV9 (0x00000008U) /*!< PREDIV input clock divided by 9 */
  2994. #define RCC_CFGR2_PREDIV_DIV10 (0x00000009U) /*!< PREDIV input clock divided by 10 */
  2995. #define RCC_CFGR2_PREDIV_DIV11 (0x0000000AU) /*!< PREDIV input clock divided by 11 */
  2996. #define RCC_CFGR2_PREDIV_DIV12 (0x0000000BU) /*!< PREDIV input clock divided by 12 */
  2997. #define RCC_CFGR2_PREDIV_DIV13 (0x0000000CU) /*!< PREDIV input clock divided by 13 */
  2998. #define RCC_CFGR2_PREDIV_DIV14 (0x0000000DU) /*!< PREDIV input clock divided by 14 */
  2999. #define RCC_CFGR2_PREDIV_DIV15 (0x0000000EU) /*!< PREDIV input clock divided by 15 */
  3000. #define RCC_CFGR2_PREDIV_DIV16 (0x0000000FU) /*!< PREDIV input clock divided by 16 */
  3001. /******************* Bit definition for RCC_CFGR3 register *****************/
  3002. /*!< USART1 Clock source selection */
  3003. #define RCC_CFGR3_USART1SW_Pos (0U)
  3004. #define RCC_CFGR3_USART1SW_Msk (0x3U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000003 */
  3005. #define RCC_CFGR3_USART1SW RCC_CFGR3_USART1SW_Msk /*!< USART1SW[1:0] bits */
  3006. #define RCC_CFGR3_USART1SW_0 (0x1U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000001 */
  3007. #define RCC_CFGR3_USART1SW_1 (0x2U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000002 */
  3008. #define RCC_CFGR3_USART1SW_PCLK (0x00000000U) /*!< PCLK clock used as USART1 clock source */
  3009. #define RCC_CFGR3_USART1SW_SYSCLK (0x00000001U) /*!< System clock selected as USART1 clock source */
  3010. #define RCC_CFGR3_USART1SW_LSE (0x00000002U) /*!< LSE oscillator clock used as USART1 clock source */
  3011. #define RCC_CFGR3_USART1SW_HSI (0x00000003U) /*!< HSI oscillator clock used as USART1 clock source */
  3012. /*!< I2C1 Clock source selection */
  3013. #define RCC_CFGR3_I2C1SW_Pos (4U)
  3014. #define RCC_CFGR3_I2C1SW_Msk (0x1U << RCC_CFGR3_I2C1SW_Pos) /*!< 0x00000010 */
  3015. #define RCC_CFGR3_I2C1SW RCC_CFGR3_I2C1SW_Msk /*!< I2C1SW bits */
  3016. #define RCC_CFGR3_I2C1SW_HSI (0x00000000U) /*!< HSI oscillator clock used as I2C1 clock source */
  3017. #define RCC_CFGR3_I2C1SW_SYSCLK_Pos (4U)
  3018. #define RCC_CFGR3_I2C1SW_SYSCLK_Msk (0x1U << RCC_CFGR3_I2C1SW_SYSCLK_Pos) /*!< 0x00000010 */
  3019. #define RCC_CFGR3_I2C1SW_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK_Msk /*!< System clock selected as I2C1 clock source */
  3020. /******************* Bit definition for RCC_CR2 register *******************/
  3021. #define RCC_CR2_HSI14ON_Pos (0U)
  3022. #define RCC_CR2_HSI14ON_Msk (0x1U << RCC_CR2_HSI14ON_Pos) /*!< 0x00000001 */
  3023. #define RCC_CR2_HSI14ON RCC_CR2_HSI14ON_Msk /*!< Internal High Speed 14MHz clock enable */
  3024. #define RCC_CR2_HSI14RDY_Pos (1U)
  3025. #define RCC_CR2_HSI14RDY_Msk (0x1U << RCC_CR2_HSI14RDY_Pos) /*!< 0x00000002 */
  3026. #define RCC_CR2_HSI14RDY RCC_CR2_HSI14RDY_Msk /*!< Internal High Speed 14MHz clock ready flag */
  3027. #define RCC_CR2_HSI14DIS_Pos (2U)
  3028. #define RCC_CR2_HSI14DIS_Msk (0x1U << RCC_CR2_HSI14DIS_Pos) /*!< 0x00000004 */
  3029. #define RCC_CR2_HSI14DIS RCC_CR2_HSI14DIS_Msk /*!< Internal High Speed 14MHz clock disable */
  3030. #define RCC_CR2_HSI14TRIM_Pos (3U)
  3031. #define RCC_CR2_HSI14TRIM_Msk (0x1FU << RCC_CR2_HSI14TRIM_Pos) /*!< 0x000000F8 */
  3032. #define RCC_CR2_HSI14TRIM RCC_CR2_HSI14TRIM_Msk /*!< Internal High Speed 14MHz clock trimming */
  3033. #define RCC_CR2_HSI14CAL_Pos (8U)
  3034. #define RCC_CR2_HSI14CAL_Msk (0xFFU << RCC_CR2_HSI14CAL_Pos) /*!< 0x0000FF00 */
  3035. #define RCC_CR2_HSI14CAL RCC_CR2_HSI14CAL_Msk /*!< Internal High Speed 14MHz clock Calibration */
  3036. /*****************************************************************************/
  3037. /* */
  3038. /* Real-Time Clock (RTC) */
  3039. /* */
  3040. /*****************************************************************************/
  3041. /*
  3042. * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
  3043. */
  3044. #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
  3045. #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
  3046. /******************** Bits definition for RTC_TR register ******************/
  3047. #define RTC_TR_PM_Pos (22U)
  3048. #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
  3049. #define RTC_TR_PM RTC_TR_PM_Msk
  3050. #define RTC_TR_HT_Pos (20U)
  3051. #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
  3052. #define RTC_TR_HT RTC_TR_HT_Msk
  3053. #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
  3054. #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
  3055. #define RTC_TR_HU_Pos (16U)
  3056. #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
  3057. #define RTC_TR_HU RTC_TR_HU_Msk
  3058. #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
  3059. #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
  3060. #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
  3061. #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
  3062. #define RTC_TR_MNT_Pos (12U)
  3063. #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
  3064. #define RTC_TR_MNT RTC_TR_MNT_Msk
  3065. #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
  3066. #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
  3067. #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
  3068. #define RTC_TR_MNU_Pos (8U)
  3069. #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
  3070. #define RTC_TR_MNU RTC_TR_MNU_Msk
  3071. #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
  3072. #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
  3073. #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
  3074. #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
  3075. #define RTC_TR_ST_Pos (4U)
  3076. #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
  3077. #define RTC_TR_ST RTC_TR_ST_Msk
  3078. #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
  3079. #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
  3080. #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
  3081. #define RTC_TR_SU_Pos (0U)
  3082. #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
  3083. #define RTC_TR_SU RTC_TR_SU_Msk
  3084. #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
  3085. #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
  3086. #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
  3087. #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
  3088. /******************** Bits definition for RTC_DR register ******************/
  3089. #define RTC_DR_YT_Pos (20U)
  3090. #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
  3091. #define RTC_DR_YT RTC_DR_YT_Msk
  3092. #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
  3093. #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
  3094. #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
  3095. #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
  3096. #define RTC_DR_YU_Pos (16U)
  3097. #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
  3098. #define RTC_DR_YU RTC_DR_YU_Msk
  3099. #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
  3100. #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
  3101. #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
  3102. #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
  3103. #define RTC_DR_WDU_Pos (13U)
  3104. #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
  3105. #define RTC_DR_WDU RTC_DR_WDU_Msk
  3106. #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
  3107. #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
  3108. #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
  3109. #define RTC_DR_MT_Pos (12U)
  3110. #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
  3111. #define RTC_DR_MT RTC_DR_MT_Msk
  3112. #define RTC_DR_MU_Pos (8U)
  3113. #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
  3114. #define RTC_DR_MU RTC_DR_MU_Msk
  3115. #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
  3116. #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
  3117. #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
  3118. #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
  3119. #define RTC_DR_DT_Pos (4U)
  3120. #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
  3121. #define RTC_DR_DT RTC_DR_DT_Msk
  3122. #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
  3123. #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
  3124. #define RTC_DR_DU_Pos (0U)
  3125. #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
  3126. #define RTC_DR_DU RTC_DR_DU_Msk
  3127. #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
  3128. #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
  3129. #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
  3130. #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
  3131. /******************** Bits definition for RTC_CR register ******************/
  3132. #define RTC_CR_COE_Pos (23U)
  3133. #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
  3134. #define RTC_CR_COE RTC_CR_COE_Msk
  3135. #define RTC_CR_OSEL_Pos (21U)
  3136. #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
  3137. #define RTC_CR_OSEL RTC_CR_OSEL_Msk
  3138. #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
  3139. #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
  3140. #define RTC_CR_POL_Pos (20U)
  3141. #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
  3142. #define RTC_CR_POL RTC_CR_POL_Msk
  3143. #define RTC_CR_COSEL_Pos (19U)
  3144. #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
  3145. #define RTC_CR_COSEL RTC_CR_COSEL_Msk
  3146. #define RTC_CR_BCK_Pos (18U)
  3147. #define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
  3148. #define RTC_CR_BCK RTC_CR_BCK_Msk
  3149. #define RTC_CR_SUB1H_Pos (17U)
  3150. #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
  3151. #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
  3152. #define RTC_CR_ADD1H_Pos (16U)
  3153. #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
  3154. #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
  3155. #define RTC_CR_TSIE_Pos (15U)
  3156. #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
  3157. #define RTC_CR_TSIE RTC_CR_TSIE_Msk
  3158. #define RTC_CR_ALRAIE_Pos (12U)
  3159. #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
  3160. #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
  3161. #define RTC_CR_TSE_Pos (11U)
  3162. #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
  3163. #define RTC_CR_TSE RTC_CR_TSE_Msk
  3164. #define RTC_CR_ALRAE_Pos (8U)
  3165. #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
  3166. #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
  3167. #define RTC_CR_FMT_Pos (6U)
  3168. #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
  3169. #define RTC_CR_FMT RTC_CR_FMT_Msk
  3170. #define RTC_CR_BYPSHAD_Pos (5U)
  3171. #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
  3172. #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
  3173. #define RTC_CR_REFCKON_Pos (4U)
  3174. #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
  3175. #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
  3176. #define RTC_CR_TSEDGE_Pos (3U)
  3177. #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
  3178. #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
  3179. /******************** Bits definition for RTC_ISR register *****************/
  3180. #define RTC_ISR_RECALPF_Pos (16U)
  3181. #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
  3182. #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
  3183. #define RTC_ISR_TAMP2F_Pos (14U)
  3184. #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
  3185. #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
  3186. #define RTC_ISR_TAMP1F_Pos (13U)
  3187. #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
  3188. #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
  3189. #define RTC_ISR_TSOVF_Pos (12U)
  3190. #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
  3191. #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
  3192. #define RTC_ISR_TSF_Pos (11U)
  3193. #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
  3194. #define RTC_ISR_TSF RTC_ISR_TSF_Msk
  3195. #define RTC_ISR_ALRAF_Pos (8U)
  3196. #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
  3197. #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
  3198. #define RTC_ISR_INIT_Pos (7U)
  3199. #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
  3200. #define RTC_ISR_INIT RTC_ISR_INIT_Msk
  3201. #define RTC_ISR_INITF_Pos (6U)
  3202. #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
  3203. #define RTC_ISR_INITF RTC_ISR_INITF_Msk
  3204. #define RTC_ISR_RSF_Pos (5U)
  3205. #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
  3206. #define RTC_ISR_RSF RTC_ISR_RSF_Msk
  3207. #define RTC_ISR_INITS_Pos (4U)
  3208. #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
  3209. #define RTC_ISR_INITS RTC_ISR_INITS_Msk
  3210. #define RTC_ISR_SHPF_Pos (3U)
  3211. #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
  3212. #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
  3213. #define RTC_ISR_ALRAWF_Pos (0U)
  3214. #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
  3215. #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
  3216. /******************** Bits definition for RTC_PRER register ****************/
  3217. #define RTC_PRER_PREDIV_A_Pos (16U)
  3218. #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
  3219. #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
  3220. #define RTC_PRER_PREDIV_S_Pos (0U)
  3221. #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
  3222. #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
  3223. /******************** Bits definition for RTC_ALRMAR register **************/
  3224. #define RTC_ALRMAR_MSK4_Pos (31U)
  3225. #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
  3226. #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
  3227. #define RTC_ALRMAR_WDSEL_Pos (30U)
  3228. #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
  3229. #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
  3230. #define RTC_ALRMAR_DT_Pos (28U)
  3231. #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
  3232. #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
  3233. #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
  3234. #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
  3235. #define RTC_ALRMAR_DU_Pos (24U)
  3236. #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
  3237. #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
  3238. #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
  3239. #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
  3240. #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
  3241. #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
  3242. #define RTC_ALRMAR_MSK3_Pos (23U)
  3243. #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
  3244. #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
  3245. #define RTC_ALRMAR_PM_Pos (22U)
  3246. #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
  3247. #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
  3248. #define RTC_ALRMAR_HT_Pos (20U)
  3249. #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
  3250. #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
  3251. #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
  3252. #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
  3253. #define RTC_ALRMAR_HU_Pos (16U)
  3254. #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
  3255. #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
  3256. #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
  3257. #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
  3258. #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
  3259. #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
  3260. #define RTC_ALRMAR_MSK2_Pos (15U)
  3261. #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
  3262. #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
  3263. #define RTC_ALRMAR_MNT_Pos (12U)
  3264. #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
  3265. #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
  3266. #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
  3267. #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
  3268. #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
  3269. #define RTC_ALRMAR_MNU_Pos (8U)
  3270. #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
  3271. #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
  3272. #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
  3273. #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
  3274. #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
  3275. #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
  3276. #define RTC_ALRMAR_MSK1_Pos (7U)
  3277. #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
  3278. #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
  3279. #define RTC_ALRMAR_ST_Pos (4U)
  3280. #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
  3281. #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
  3282. #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
  3283. #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
  3284. #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
  3285. #define RTC_ALRMAR_SU_Pos (0U)
  3286. #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
  3287. #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
  3288. #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
  3289. #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
  3290. #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
  3291. #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
  3292. /******************** Bits definition for RTC_WPR register *****************/
  3293. #define RTC_WPR_KEY_Pos (0U)
  3294. #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
  3295. #define RTC_WPR_KEY RTC_WPR_KEY_Msk
  3296. /******************** Bits definition for RTC_SSR register *****************/
  3297. #define RTC_SSR_SS_Pos (0U)
  3298. #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
  3299. #define RTC_SSR_SS RTC_SSR_SS_Msk
  3300. /******************** Bits definition for RTC_SHIFTR register **************/
  3301. #define RTC_SHIFTR_SUBFS_Pos (0U)
  3302. #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
  3303. #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
  3304. #define RTC_SHIFTR_ADD1S_Pos (31U)
  3305. #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
  3306. #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
  3307. /******************** Bits definition for RTC_TSTR register ****************/
  3308. #define RTC_TSTR_PM_Pos (22U)
  3309. #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
  3310. #define RTC_TSTR_PM RTC_TSTR_PM_Msk
  3311. #define RTC_TSTR_HT_Pos (20U)
  3312. #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
  3313. #define RTC_TSTR_HT RTC_TSTR_HT_Msk
  3314. #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
  3315. #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
  3316. #define RTC_TSTR_HU_Pos (16U)
  3317. #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
  3318. #define RTC_TSTR_HU RTC_TSTR_HU_Msk
  3319. #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
  3320. #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
  3321. #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
  3322. #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
  3323. #define RTC_TSTR_MNT_Pos (12U)
  3324. #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
  3325. #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
  3326. #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
  3327. #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
  3328. #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
  3329. #define RTC_TSTR_MNU_Pos (8U)
  3330. #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
  3331. #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
  3332. #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
  3333. #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
  3334. #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
  3335. #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
  3336. #define RTC_TSTR_ST_Pos (4U)
  3337. #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
  3338. #define RTC_TSTR_ST RTC_TSTR_ST_Msk
  3339. #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
  3340. #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
  3341. #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
  3342. #define RTC_TSTR_SU_Pos (0U)
  3343. #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
  3344. #define RTC_TSTR_SU RTC_TSTR_SU_Msk
  3345. #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
  3346. #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
  3347. #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
  3348. #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
  3349. /******************** Bits definition for RTC_TSDR register ****************/
  3350. #define RTC_TSDR_WDU_Pos (13U)
  3351. #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
  3352. #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
  3353. #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
  3354. #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
  3355. #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
  3356. #define RTC_TSDR_MT_Pos (12U)
  3357. #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
  3358. #define RTC_TSDR_MT RTC_TSDR_MT_Msk
  3359. #define RTC_TSDR_MU_Pos (8U)
  3360. #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
  3361. #define RTC_TSDR_MU RTC_TSDR_MU_Msk
  3362. #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
  3363. #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
  3364. #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
  3365. #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
  3366. #define RTC_TSDR_DT_Pos (4U)
  3367. #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
  3368. #define RTC_TSDR_DT RTC_TSDR_DT_Msk
  3369. #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
  3370. #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
  3371. #define RTC_TSDR_DU_Pos (0U)
  3372. #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
  3373. #define RTC_TSDR_DU RTC_TSDR_DU_Msk
  3374. #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
  3375. #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
  3376. #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
  3377. #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
  3378. /******************** Bits definition for RTC_TSSSR register ***************/
  3379. #define RTC_TSSSR_SS_Pos (0U)
  3380. #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
  3381. #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
  3382. /******************** Bits definition for RTC_CALR register ****************/
  3383. #define RTC_CALR_CALP_Pos (15U)
  3384. #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
  3385. #define RTC_CALR_CALP RTC_CALR_CALP_Msk
  3386. #define RTC_CALR_CALW8_Pos (14U)
  3387. #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
  3388. #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
  3389. #define RTC_CALR_CALW16_Pos (13U)
  3390. #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
  3391. #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
  3392. #define RTC_CALR_CALM_Pos (0U)
  3393. #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
  3394. #define RTC_CALR_CALM RTC_CALR_CALM_Msk
  3395. #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
  3396. #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
  3397. #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
  3398. #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
  3399. #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
  3400. #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
  3401. #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
  3402. #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
  3403. #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
  3404. /******************** Bits definition for RTC_TAFCR register ***************/
  3405. #define RTC_TAFCR_PC15MODE_Pos (23U)
  3406. #define RTC_TAFCR_PC15MODE_Msk (0x1U << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */
  3407. #define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk
  3408. #define RTC_TAFCR_PC15VALUE_Pos (22U)
  3409. #define RTC_TAFCR_PC15VALUE_Msk (0x1U << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */
  3410. #define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk
  3411. #define RTC_TAFCR_PC14MODE_Pos (21U)
  3412. #define RTC_TAFCR_PC14MODE_Msk (0x1U << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */
  3413. #define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk
  3414. #define RTC_TAFCR_PC14VALUE_Pos (20U)
  3415. #define RTC_TAFCR_PC14VALUE_Msk (0x1U << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */
  3416. #define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk
  3417. #define RTC_TAFCR_PC13MODE_Pos (19U)
  3418. #define RTC_TAFCR_PC13MODE_Msk (0x1U << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */
  3419. #define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk
  3420. #define RTC_TAFCR_PC13VALUE_Pos (18U)
  3421. #define RTC_TAFCR_PC13VALUE_Msk (0x1U << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */
  3422. #define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk
  3423. #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
  3424. #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
  3425. #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
  3426. #define RTC_TAFCR_TAMPPRCH_Pos (13U)
  3427. #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
  3428. #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
  3429. #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
  3430. #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
  3431. #define RTC_TAFCR_TAMPFLT_Pos (11U)
  3432. #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
  3433. #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
  3434. #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
  3435. #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
  3436. #define RTC_TAFCR_TAMPFREQ_Pos (8U)
  3437. #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
  3438. #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
  3439. #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
  3440. #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
  3441. #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
  3442. #define RTC_TAFCR_TAMPTS_Pos (7U)
  3443. #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
  3444. #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
  3445. #define RTC_TAFCR_TAMP2TRG_Pos (4U)
  3446. #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
  3447. #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
  3448. #define RTC_TAFCR_TAMP2E_Pos (3U)
  3449. #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
  3450. #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
  3451. #define RTC_TAFCR_TAMPIE_Pos (2U)
  3452. #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
  3453. #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
  3454. #define RTC_TAFCR_TAMP1TRG_Pos (1U)
  3455. #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
  3456. #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
  3457. #define RTC_TAFCR_TAMP1E_Pos (0U)
  3458. #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
  3459. #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
  3460. /* Reference defines */
  3461. #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE
  3462. /******************** Bits definition for RTC_ALRMASSR register ************/
  3463. #define RTC_ALRMASSR_MASKSS_Pos (24U)
  3464. #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
  3465. #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
  3466. #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
  3467. #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
  3468. #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
  3469. #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
  3470. #define RTC_ALRMASSR_SS_Pos (0U)
  3471. #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
  3472. #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
  3473. /*****************************************************************************/
  3474. /* */
  3475. /* Serial Peripheral Interface (SPI) */
  3476. /* */
  3477. /*****************************************************************************/
  3478. /*
  3479. * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
  3480. */
  3481. /* Note: No specific macro feature on this device */
  3482. /******************* Bit definition for SPI_CR1 register *******************/
  3483. #define SPI_CR1_CPHA_Pos (0U)
  3484. #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
  3485. #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
  3486. #define SPI_CR1_CPOL_Pos (1U)
  3487. #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
  3488. #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
  3489. #define SPI_CR1_MSTR_Pos (2U)
  3490. #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
  3491. #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
  3492. #define SPI_CR1_BR_Pos (3U)
  3493. #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
  3494. #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
  3495. #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
  3496. #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
  3497. #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
  3498. #define SPI_CR1_SPE_Pos (6U)
  3499. #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
  3500. #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
  3501. #define SPI_CR1_LSBFIRST_Pos (7U)
  3502. #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
  3503. #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
  3504. #define SPI_CR1_SSI_Pos (8U)
  3505. #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
  3506. #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
  3507. #define SPI_CR1_SSM_Pos (9U)
  3508. #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
  3509. #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
  3510. #define SPI_CR1_RXONLY_Pos (10U)
  3511. #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
  3512. #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
  3513. #define SPI_CR1_CRCL_Pos (11U)
  3514. #define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
  3515. #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
  3516. #define SPI_CR1_CRCNEXT_Pos (12U)
  3517. #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
  3518. #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
  3519. #define SPI_CR1_CRCEN_Pos (13U)
  3520. #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
  3521. #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
  3522. #define SPI_CR1_BIDIOE_Pos (14U)
  3523. #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
  3524. #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
  3525. #define SPI_CR1_BIDIMODE_Pos (15U)
  3526. #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
  3527. #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
  3528. /******************* Bit definition for SPI_CR2 register *******************/
  3529. #define SPI_CR2_RXDMAEN_Pos (0U)
  3530. #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
  3531. #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
  3532. #define SPI_CR2_TXDMAEN_Pos (1U)
  3533. #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
  3534. #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
  3535. #define SPI_CR2_SSOE_Pos (2U)
  3536. #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
  3537. #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
  3538. #define SPI_CR2_NSSP_Pos (3U)
  3539. #define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
  3540. #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
  3541. #define SPI_CR2_FRF_Pos (4U)
  3542. #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
  3543. #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
  3544. #define SPI_CR2_ERRIE_Pos (5U)
  3545. #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
  3546. #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
  3547. #define SPI_CR2_RXNEIE_Pos (6U)
  3548. #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
  3549. #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
  3550. #define SPI_CR2_TXEIE_Pos (7U)
  3551. #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
  3552. #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
  3553. #define SPI_CR2_DS_Pos (8U)
  3554. #define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
  3555. #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
  3556. #define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */
  3557. #define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */
  3558. #define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */
  3559. #define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */
  3560. #define SPI_CR2_FRXTH_Pos (12U)
  3561. #define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
  3562. #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
  3563. #define SPI_CR2_LDMARX_Pos (13U)
  3564. #define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
  3565. #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
  3566. #define SPI_CR2_LDMATX_Pos (14U)
  3567. #define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
  3568. #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
  3569. /******************** Bit definition for SPI_SR register *******************/
  3570. #define SPI_SR_RXNE_Pos (0U)
  3571. #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
  3572. #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
  3573. #define SPI_SR_TXE_Pos (1U)
  3574. #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
  3575. #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
  3576. #define SPI_SR_CRCERR_Pos (4U)
  3577. #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
  3578. #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
  3579. #define SPI_SR_MODF_Pos (5U)
  3580. #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
  3581. #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
  3582. #define SPI_SR_OVR_Pos (6U)
  3583. #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
  3584. #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
  3585. #define SPI_SR_BSY_Pos (7U)
  3586. #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
  3587. #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
  3588. #define SPI_SR_FRE_Pos (8U)
  3589. #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
  3590. #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
  3591. #define SPI_SR_FRLVL_Pos (9U)
  3592. #define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
  3593. #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
  3594. #define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
  3595. #define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
  3596. #define SPI_SR_FTLVL_Pos (11U)
  3597. #define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
  3598. #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
  3599. #define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
  3600. #define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
  3601. /******************** Bit definition for SPI_DR register *******************/
  3602. #define SPI_DR_DR_Pos (0U)
  3603. #define SPI_DR_DR_Msk (0xFFFFFFFFU << SPI_DR_DR_Pos) /*!< 0xFFFFFFFF */
  3604. #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
  3605. /******************* Bit definition for SPI_CRCPR register *****************/
  3606. #define SPI_CRCPR_CRCPOLY_Pos (0U)
  3607. #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
  3608. #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
  3609. /****************** Bit definition for SPI_RXCRCR register *****************/
  3610. #define SPI_RXCRCR_RXCRC_Pos (0U)
  3611. #define SPI_RXCRCR_RXCRC_Msk (0xFFFFFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0xFFFFFFFF */
  3612. #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
  3613. /****************** Bit definition for SPI_TXCRCR register *****************/
  3614. #define SPI_TXCRCR_TXCRC_Pos (0U)
  3615. #define SPI_TXCRCR_TXCRC_Msk (0xFFFFFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0xFFFFFFFF */
  3616. #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
  3617. /****************** Bit definition for SPI_I2SCFGR register ****************/
  3618. #define SPI_I2SCFGR_I2SMOD_Pos (11U)
  3619. #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
  3620. #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< Keep for compatibility */
  3621. /*****************************************************************************/
  3622. /* */
  3623. /* System Configuration (SYSCFG) */
  3624. /* */
  3625. /*****************************************************************************/
  3626. /***************** Bit definition for SYSCFG_CFGR1 register ****************/
  3627. #define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
  3628. #define SYSCFG_CFGR1_MEM_MODE_Msk (0x3U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
  3629. #define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
  3630. #define SYSCFG_CFGR1_MEM_MODE_0 (0x1U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
  3631. #define SYSCFG_CFGR1_MEM_MODE_1 (0x2U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
  3632. #define SYSCFG_CFGR1_DMA_RMP_Pos (8U)
  3633. #define SYSCFG_CFGR1_DMA_RMP_Msk (0x1FU << SYSCFG_CFGR1_DMA_RMP_Pos) /*!< 0x00001F00 */
  3634. #define SYSCFG_CFGR1_DMA_RMP SYSCFG_CFGR1_DMA_RMP_Msk /*!< DMA remap mask */
  3635. #define SYSCFG_CFGR1_ADC_DMA_RMP_Pos (8U)
  3636. #define SYSCFG_CFGR1_ADC_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_ADC_DMA_RMP_Pos) /*!< 0x00000100 */
  3637. #define SYSCFG_CFGR1_ADC_DMA_RMP SYSCFG_CFGR1_ADC_DMA_RMP_Msk /*!< ADC DMA remap */
  3638. #define SYSCFG_CFGR1_USART1TX_DMA_RMP_Pos (9U)
  3639. #define SYSCFG_CFGR1_USART1TX_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_USART1TX_DMA_RMP_Pos) /*!< 0x00000200 */
  3640. #define SYSCFG_CFGR1_USART1TX_DMA_RMP SYSCFG_CFGR1_USART1TX_DMA_RMP_Msk /*!< USART1 TX DMA remap */
  3641. #define SYSCFG_CFGR1_USART1RX_DMA_RMP_Pos (10U)
  3642. #define SYSCFG_CFGR1_USART1RX_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_USART1RX_DMA_RMP_Pos) /*!< 0x00000400 */
  3643. #define SYSCFG_CFGR1_USART1RX_DMA_RMP SYSCFG_CFGR1_USART1RX_DMA_RMP_Msk /*!< USART1 RX DMA remap */
  3644. #define SYSCFG_CFGR1_TIM16_DMA_RMP_Pos (11U)
  3645. #define SYSCFG_CFGR1_TIM16_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM16_DMA_RMP_Pos) /*!< 0x00000800 */
  3646. #define SYSCFG_CFGR1_TIM16_DMA_RMP SYSCFG_CFGR1_TIM16_DMA_RMP_Msk /*!< Timer 16 DMA remap */
  3647. #define SYSCFG_CFGR1_TIM17_DMA_RMP_Pos (12U)
  3648. #define SYSCFG_CFGR1_TIM17_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM17_DMA_RMP_Pos) /*!< 0x00001000 */
  3649. #define SYSCFG_CFGR1_TIM17_DMA_RMP SYSCFG_CFGR1_TIM17_DMA_RMP_Msk /*!< Timer 17 DMA remap */
  3650. #define SYSCFG_CFGR1_I2C_FMP_PB6_Pos (16U)
  3651. #define SYSCFG_CFGR1_I2C_FMP_PB6_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB6_Pos) /*!< 0x00010000 */
  3652. #define SYSCFG_CFGR1_I2C_FMP_PB6 SYSCFG_CFGR1_I2C_FMP_PB6_Msk /*!< I2C PB6 Fast mode plus */
  3653. #define SYSCFG_CFGR1_I2C_FMP_PB7_Pos (17U)
  3654. #define SYSCFG_CFGR1_I2C_FMP_PB7_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB7_Pos) /*!< 0x00020000 */
  3655. #define SYSCFG_CFGR1_I2C_FMP_PB7 SYSCFG_CFGR1_I2C_FMP_PB7_Msk /*!< I2C PB7 Fast mode plus */
  3656. #define SYSCFG_CFGR1_I2C_FMP_PB8_Pos (18U)
  3657. #define SYSCFG_CFGR1_I2C_FMP_PB8_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB8_Pos) /*!< 0x00040000 */
  3658. #define SYSCFG_CFGR1_I2C_FMP_PB8 SYSCFG_CFGR1_I2C_FMP_PB8_Msk /*!< I2C PB8 Fast mode plus */
  3659. #define SYSCFG_CFGR1_I2C_FMP_PB9_Pos (19U)
  3660. #define SYSCFG_CFGR1_I2C_FMP_PB9_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB9_Pos) /*!< 0x00080000 */
  3661. #define SYSCFG_CFGR1_I2C_FMP_PB9 SYSCFG_CFGR1_I2C_FMP_PB9_Msk /*!< I2C PB9 Fast mode plus */
  3662. #define SYSCFG_CFGR1_I2C_FMP_I2C1_Pos (20U)
  3663. #define SYSCFG_CFGR1_I2C_FMP_I2C1_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_I2C1_Pos) /*!< 0x00100000 */
  3664. #define SYSCFG_CFGR1_I2C_FMP_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1_Msk /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
  3665. #define SYSCFG_CFGR1_I2C_FMP_PA9_Pos (22U)
  3666. #define SYSCFG_CFGR1_I2C_FMP_PA9_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PA9_Pos) /*!< 0x00400000 */
  3667. #define SYSCFG_CFGR1_I2C_FMP_PA9 SYSCFG_CFGR1_I2C_FMP_PA9_Msk /*!< Enable Fast Mode Plus on PA9 */
  3668. #define SYSCFG_CFGR1_I2C_FMP_PA10_Pos (23U)
  3669. #define SYSCFG_CFGR1_I2C_FMP_PA10_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PA10_Pos) /*!< 0x00800000 */
  3670. #define SYSCFG_CFGR1_I2C_FMP_PA10 SYSCFG_CFGR1_I2C_FMP_PA10_Msk /*!< Enable Fast Mode Plus on PA10 */
  3671. /***************** Bit definition for SYSCFG_EXTICR1 register **************/
  3672. #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
  3673. #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
  3674. #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
  3675. #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
  3676. #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
  3677. #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
  3678. #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
  3679. #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
  3680. #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
  3681. #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
  3682. #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
  3683. #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
  3684. /**
  3685. * @brief EXTI0 configuration
  3686. */
  3687. #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
  3688. #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
  3689. #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
  3690. #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */
  3691. #define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!< PF[0] pin */
  3692. /**
  3693. * @brief EXTI1 configuration
  3694. */
  3695. #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
  3696. #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
  3697. #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
  3698. #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */
  3699. #define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!< PF[1] pin */
  3700. /**
  3701. * @brief EXTI2 configuration
  3702. */
  3703. #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
  3704. #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
  3705. #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
  3706. #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
  3707. #define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!< PF[2] pin */
  3708. /**
  3709. * @brief EXTI3 configuration
  3710. */
  3711. #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
  3712. #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
  3713. #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
  3714. #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
  3715. #define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!< PF[3] pin */
  3716. /***************** Bit definition for SYSCFG_EXTICR2 register **************/
  3717. #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
  3718. #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
  3719. #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
  3720. #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
  3721. #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
  3722. #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
  3723. #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
  3724. #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
  3725. #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
  3726. #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
  3727. #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
  3728. #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
  3729. /**
  3730. * @brief EXTI4 configuration
  3731. */
  3732. #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
  3733. #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
  3734. #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
  3735. #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */
  3736. #define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!< PF[4] pin */
  3737. /**
  3738. * @brief EXTI5 configuration
  3739. */
  3740. #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
  3741. #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
  3742. #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
  3743. #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */
  3744. #define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!< PF[5] pin */
  3745. /**
  3746. * @brief EXTI6 configuration
  3747. */
  3748. #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
  3749. #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
  3750. #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
  3751. #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */
  3752. #define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!< PF[6] pin */
  3753. /**
  3754. * @brief EXTI7 configuration
  3755. */
  3756. #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
  3757. #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
  3758. #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
  3759. #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */
  3760. #define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!< PF[7] pin */
  3761. /***************** Bit definition for SYSCFG_EXTICR3 register **************/
  3762. #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
  3763. #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
  3764. #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
  3765. #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
  3766. #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
  3767. #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
  3768. #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
  3769. #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
  3770. #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
  3771. #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
  3772. #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
  3773. #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
  3774. /**
  3775. * @brief EXTI8 configuration
  3776. */
  3777. #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
  3778. #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
  3779. #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
  3780. #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */
  3781. #define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!< PF[8] pin */
  3782. /**
  3783. * @brief EXTI9 configuration
  3784. */
  3785. #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
  3786. #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
  3787. #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
  3788. #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */
  3789. #define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!< PF[9] pin */
  3790. /**
  3791. * @brief EXTI10 configuration
  3792. */
  3793. #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
  3794. #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
  3795. #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
  3796. #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */
  3797. #define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!< PF[10] pin */
  3798. /**
  3799. * @brief EXTI11 configuration
  3800. */
  3801. #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
  3802. #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
  3803. #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
  3804. #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */
  3805. #define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!< PF[11] pin */
  3806. /***************** Bit definition for SYSCFG_EXTICR4 register **************/
  3807. #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
  3808. #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
  3809. #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
  3810. #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
  3811. #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
  3812. #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
  3813. #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
  3814. #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
  3815. #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
  3816. #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
  3817. #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
  3818. #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
  3819. /**
  3820. * @brief EXTI12 configuration
  3821. */
  3822. #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
  3823. #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
  3824. #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
  3825. #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */
  3826. #define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!< PF[12] pin */
  3827. /**
  3828. * @brief EXTI13 configuration
  3829. */
  3830. #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
  3831. #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
  3832. #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
  3833. #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */
  3834. #define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!< PF[13] pin */
  3835. /**
  3836. * @brief EXTI14 configuration
  3837. */
  3838. #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
  3839. #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
  3840. #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
  3841. #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */
  3842. #define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!< PF[14] pin */
  3843. /**
  3844. * @brief EXTI15 configuration
  3845. */
  3846. #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
  3847. #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
  3848. #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
  3849. #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */
  3850. #define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!< PF[15] pin */
  3851. /***************** Bit definition for SYSCFG_CFGR2 register ****************/
  3852. #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U)
  3853. #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1U << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */
  3854. #define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
  3855. #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos (1U)
  3856. #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk (0x1U << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos) /*!< 0x00000002 */
  3857. #define SYSCFG_CFGR2_SRAM_PARITY_LOCK SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
  3858. #define SYSCFG_CFGR2_SRAM_PEF_Pos (8U)
  3859. #define SYSCFG_CFGR2_SRAM_PEF_Msk (0x1U << SYSCFG_CFGR2_SRAM_PEF_Pos) /*!< 0x00000100 */
  3860. #define SYSCFG_CFGR2_SRAM_PEF SYSCFG_CFGR2_SRAM_PEF_Msk /*!< SRAM Parity error flag */
  3861. #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
  3862. /*****************************************************************************/
  3863. /* */
  3864. /* Timers (TIM) */
  3865. /* */
  3866. /*****************************************************************************/
  3867. /******************* Bit definition for TIM_CR1 register *******************/
  3868. #define TIM_CR1_CEN_Pos (0U)
  3869. #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
  3870. #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
  3871. #define TIM_CR1_UDIS_Pos (1U)
  3872. #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
  3873. #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
  3874. #define TIM_CR1_URS_Pos (2U)
  3875. #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
  3876. #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
  3877. #define TIM_CR1_OPM_Pos (3U)
  3878. #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
  3879. #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
  3880. #define TIM_CR1_DIR_Pos (4U)
  3881. #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
  3882. #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
  3883. #define TIM_CR1_CMS_Pos (5U)
  3884. #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
  3885. #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
  3886. #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
  3887. #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
  3888. #define TIM_CR1_ARPE_Pos (7U)
  3889. #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
  3890. #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
  3891. #define TIM_CR1_CKD_Pos (8U)
  3892. #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
  3893. #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
  3894. #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
  3895. #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
  3896. /******************* Bit definition for TIM_CR2 register *******************/
  3897. #define TIM_CR2_CCPC_Pos (0U)
  3898. #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
  3899. #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
  3900. #define TIM_CR2_CCUS_Pos (2U)
  3901. #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
  3902. #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
  3903. #define TIM_CR2_CCDS_Pos (3U)
  3904. #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
  3905. #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
  3906. #define TIM_CR2_MMS_Pos (4U)
  3907. #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
  3908. #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
  3909. #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
  3910. #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
  3911. #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
  3912. #define TIM_CR2_TI1S_Pos (7U)
  3913. #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
  3914. #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
  3915. #define TIM_CR2_OIS1_Pos (8U)
  3916. #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
  3917. #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
  3918. #define TIM_CR2_OIS1N_Pos (9U)
  3919. #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
  3920. #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
  3921. #define TIM_CR2_OIS2_Pos (10U)
  3922. #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
  3923. #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
  3924. #define TIM_CR2_OIS2N_Pos (11U)
  3925. #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
  3926. #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
  3927. #define TIM_CR2_OIS3_Pos (12U)
  3928. #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
  3929. #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
  3930. #define TIM_CR2_OIS3N_Pos (13U)
  3931. #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
  3932. #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
  3933. #define TIM_CR2_OIS4_Pos (14U)
  3934. #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
  3935. #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
  3936. /******************* Bit definition for TIM_SMCR register ******************/
  3937. #define TIM_SMCR_SMS_Pos (0U)
  3938. #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
  3939. #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
  3940. #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
  3941. #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
  3942. #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
  3943. #define TIM_SMCR_OCCS_Pos (3U)
  3944. #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
  3945. #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
  3946. #define TIM_SMCR_TS_Pos (4U)
  3947. #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
  3948. #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
  3949. #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
  3950. #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
  3951. #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
  3952. #define TIM_SMCR_MSM_Pos (7U)
  3953. #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
  3954. #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
  3955. #define TIM_SMCR_ETF_Pos (8U)
  3956. #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
  3957. #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
  3958. #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
  3959. #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
  3960. #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
  3961. #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
  3962. #define TIM_SMCR_ETPS_Pos (12U)
  3963. #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
  3964. #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
  3965. #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
  3966. #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
  3967. #define TIM_SMCR_ECE_Pos (14U)
  3968. #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
  3969. #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
  3970. #define TIM_SMCR_ETP_Pos (15U)
  3971. #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
  3972. #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
  3973. /******************* Bit definition for TIM_DIER register ******************/
  3974. #define TIM_DIER_UIE_Pos (0U)
  3975. #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
  3976. #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
  3977. #define TIM_DIER_CC1IE_Pos (1U)
  3978. #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
  3979. #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
  3980. #define TIM_DIER_CC2IE_Pos (2U)
  3981. #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
  3982. #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
  3983. #define TIM_DIER_CC3IE_Pos (3U)
  3984. #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
  3985. #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
  3986. #define TIM_DIER_CC4IE_Pos (4U)
  3987. #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
  3988. #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
  3989. #define TIM_DIER_COMIE_Pos (5U)
  3990. #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
  3991. #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
  3992. #define TIM_DIER_TIE_Pos (6U)
  3993. #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
  3994. #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
  3995. #define TIM_DIER_BIE_Pos (7U)
  3996. #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
  3997. #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
  3998. #define TIM_DIER_UDE_Pos (8U)
  3999. #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
  4000. #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
  4001. #define TIM_DIER_CC1DE_Pos (9U)
  4002. #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
  4003. #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
  4004. #define TIM_DIER_CC2DE_Pos (10U)
  4005. #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
  4006. #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
  4007. #define TIM_DIER_CC3DE_Pos (11U)
  4008. #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
  4009. #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
  4010. #define TIM_DIER_CC4DE_Pos (12U)
  4011. #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
  4012. #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
  4013. #define TIM_DIER_COMDE_Pos (13U)
  4014. #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
  4015. #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
  4016. #define TIM_DIER_TDE_Pos (14U)
  4017. #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
  4018. #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
  4019. /******************** Bit definition for TIM_SR register *******************/
  4020. #define TIM_SR_UIF_Pos (0U)
  4021. #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
  4022. #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
  4023. #define TIM_SR_CC1IF_Pos (1U)
  4024. #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
  4025. #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
  4026. #define TIM_SR_CC2IF_Pos (2U)
  4027. #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
  4028. #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
  4029. #define TIM_SR_CC3IF_Pos (3U)
  4030. #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
  4031. #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
  4032. #define TIM_SR_CC4IF_Pos (4U)
  4033. #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
  4034. #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
  4035. #define TIM_SR_COMIF_Pos (5U)
  4036. #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
  4037. #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
  4038. #define TIM_SR_TIF_Pos (6U)
  4039. #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
  4040. #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
  4041. #define TIM_SR_BIF_Pos (7U)
  4042. #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
  4043. #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
  4044. #define TIM_SR_CC1OF_Pos (9U)
  4045. #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
  4046. #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
  4047. #define TIM_SR_CC2OF_Pos (10U)
  4048. #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
  4049. #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
  4050. #define TIM_SR_CC3OF_Pos (11U)
  4051. #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
  4052. #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
  4053. #define TIM_SR_CC4OF_Pos (12U)
  4054. #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
  4055. #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
  4056. /******************* Bit definition for TIM_EGR register *******************/
  4057. #define TIM_EGR_UG_Pos (0U)
  4058. #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
  4059. #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
  4060. #define TIM_EGR_CC1G_Pos (1U)
  4061. #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
  4062. #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
  4063. #define TIM_EGR_CC2G_Pos (2U)
  4064. #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
  4065. #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
  4066. #define TIM_EGR_CC3G_Pos (3U)
  4067. #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
  4068. #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
  4069. #define TIM_EGR_CC4G_Pos (4U)
  4070. #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
  4071. #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
  4072. #define TIM_EGR_COMG_Pos (5U)
  4073. #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
  4074. #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
  4075. #define TIM_EGR_TG_Pos (6U)
  4076. #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
  4077. #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
  4078. #define TIM_EGR_BG_Pos (7U)
  4079. #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
  4080. #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
  4081. /****************** Bit definition for TIM_CCMR1 register ******************/
  4082. #define TIM_CCMR1_CC1S_Pos (0U)
  4083. #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
  4084. #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
  4085. #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
  4086. #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
  4087. #define TIM_CCMR1_OC1FE_Pos (2U)
  4088. #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
  4089. #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
  4090. #define TIM_CCMR1_OC1PE_Pos (3U)
  4091. #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
  4092. #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
  4093. #define TIM_CCMR1_OC1M_Pos (4U)
  4094. #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
  4095. #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
  4096. #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
  4097. #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
  4098. #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
  4099. #define TIM_CCMR1_OC1CE_Pos (7U)
  4100. #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
  4101. #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
  4102. #define TIM_CCMR1_CC2S_Pos (8U)
  4103. #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
  4104. #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
  4105. #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
  4106. #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
  4107. #define TIM_CCMR1_OC2FE_Pos (10U)
  4108. #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
  4109. #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
  4110. #define TIM_CCMR1_OC2PE_Pos (11U)
  4111. #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
  4112. #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
  4113. #define TIM_CCMR1_OC2M_Pos (12U)
  4114. #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
  4115. #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
  4116. #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
  4117. #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
  4118. #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
  4119. #define TIM_CCMR1_OC2CE_Pos (15U)
  4120. #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
  4121. #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
  4122. /*---------------------------------------------------------------------------*/
  4123. #define TIM_CCMR1_IC1PSC_Pos (2U)
  4124. #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
  4125. #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
  4126. #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
  4127. #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
  4128. #define TIM_CCMR1_IC1F_Pos (4U)
  4129. #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
  4130. #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
  4131. #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
  4132. #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
  4133. #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
  4134. #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
  4135. #define TIM_CCMR1_IC2PSC_Pos (10U)
  4136. #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
  4137. #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
  4138. #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
  4139. #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
  4140. #define TIM_CCMR1_IC2F_Pos (12U)
  4141. #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
  4142. #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
  4143. #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
  4144. #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
  4145. #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
  4146. #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
  4147. /****************** Bit definition for TIM_CCMR2 register ******************/
  4148. #define TIM_CCMR2_CC3S_Pos (0U)
  4149. #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
  4150. #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
  4151. #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
  4152. #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
  4153. #define TIM_CCMR2_OC3FE_Pos (2U)
  4154. #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
  4155. #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
  4156. #define TIM_CCMR2_OC3PE_Pos (3U)
  4157. #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
  4158. #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
  4159. #define TIM_CCMR2_OC3M_Pos (4U)
  4160. #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
  4161. #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
  4162. #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
  4163. #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
  4164. #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
  4165. #define TIM_CCMR2_OC3CE_Pos (7U)
  4166. #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
  4167. #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
  4168. #define TIM_CCMR2_CC4S_Pos (8U)
  4169. #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
  4170. #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
  4171. #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
  4172. #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
  4173. #define TIM_CCMR2_OC4FE_Pos (10U)
  4174. #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
  4175. #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
  4176. #define TIM_CCMR2_OC4PE_Pos (11U)
  4177. #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
  4178. #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
  4179. #define TIM_CCMR2_OC4M_Pos (12U)
  4180. #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
  4181. #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
  4182. #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
  4183. #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
  4184. #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
  4185. #define TIM_CCMR2_OC4CE_Pos (15U)
  4186. #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
  4187. #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
  4188. /*---------------------------------------------------------------------------*/
  4189. #define TIM_CCMR2_IC3PSC_Pos (2U)
  4190. #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
  4191. #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
  4192. #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
  4193. #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
  4194. #define TIM_CCMR2_IC3F_Pos (4U)
  4195. #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
  4196. #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
  4197. #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
  4198. #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
  4199. #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
  4200. #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
  4201. #define TIM_CCMR2_IC4PSC_Pos (10U)
  4202. #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
  4203. #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
  4204. #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
  4205. #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
  4206. #define TIM_CCMR2_IC4F_Pos (12U)
  4207. #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
  4208. #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
  4209. #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
  4210. #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
  4211. #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
  4212. #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
  4213. /******************* Bit definition for TIM_CCER register ******************/
  4214. #define TIM_CCER_CC1E_Pos (0U)
  4215. #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
  4216. #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
  4217. #define TIM_CCER_CC1P_Pos (1U)
  4218. #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
  4219. #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
  4220. #define TIM_CCER_CC1NE_Pos (2U)
  4221. #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
  4222. #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
  4223. #define TIM_CCER_CC1NP_Pos (3U)
  4224. #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
  4225. #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
  4226. #define TIM_CCER_CC2E_Pos (4U)
  4227. #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
  4228. #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
  4229. #define TIM_CCER_CC2P_Pos (5U)
  4230. #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
  4231. #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
  4232. #define TIM_CCER_CC2NE_Pos (6U)
  4233. #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
  4234. #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
  4235. #define TIM_CCER_CC2NP_Pos (7U)
  4236. #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
  4237. #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
  4238. #define TIM_CCER_CC3E_Pos (8U)
  4239. #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
  4240. #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
  4241. #define TIM_CCER_CC3P_Pos (9U)
  4242. #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
  4243. #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
  4244. #define TIM_CCER_CC3NE_Pos (10U)
  4245. #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
  4246. #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
  4247. #define TIM_CCER_CC3NP_Pos (11U)
  4248. #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
  4249. #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
  4250. #define TIM_CCER_CC4E_Pos (12U)
  4251. #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
  4252. #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
  4253. #define TIM_CCER_CC4P_Pos (13U)
  4254. #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
  4255. #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
  4256. #define TIM_CCER_CC4NP_Pos (15U)
  4257. #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
  4258. #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
  4259. /******************* Bit definition for TIM_CNT register *******************/
  4260. #define TIM_CNT_CNT_Pos (0U)
  4261. #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
  4262. #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
  4263. /******************* Bit definition for TIM_PSC register *******************/
  4264. #define TIM_PSC_PSC_Pos (0U)
  4265. #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
  4266. #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
  4267. /******************* Bit definition for TIM_ARR register *******************/
  4268. #define TIM_ARR_ARR_Pos (0U)
  4269. #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
  4270. #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
  4271. /******************* Bit definition for TIM_RCR register *******************/
  4272. #define TIM_RCR_REP_Pos (0U)
  4273. #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
  4274. #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
  4275. /******************* Bit definition for TIM_CCR1 register ******************/
  4276. #define TIM_CCR1_CCR1_Pos (0U)
  4277. #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
  4278. #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
  4279. /******************* Bit definition for TIM_CCR2 register ******************/
  4280. #define TIM_CCR2_CCR2_Pos (0U)
  4281. #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
  4282. #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
  4283. /******************* Bit definition for TIM_CCR3 register ******************/
  4284. #define TIM_CCR3_CCR3_Pos (0U)
  4285. #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
  4286. #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
  4287. /******************* Bit definition for TIM_CCR4 register ******************/
  4288. #define TIM_CCR4_CCR4_Pos (0U)
  4289. #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
  4290. #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
  4291. /******************* Bit definition for TIM_BDTR register ******************/
  4292. #define TIM_BDTR_DTG_Pos (0U)
  4293. #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
  4294. #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
  4295. #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
  4296. #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
  4297. #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
  4298. #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
  4299. #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
  4300. #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
  4301. #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
  4302. #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
  4303. #define TIM_BDTR_LOCK_Pos (8U)
  4304. #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
  4305. #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
  4306. #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
  4307. #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
  4308. #define TIM_BDTR_OSSI_Pos (10U)
  4309. #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
  4310. #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
  4311. #define TIM_BDTR_OSSR_Pos (11U)
  4312. #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
  4313. #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
  4314. #define TIM_BDTR_BKE_Pos (12U)
  4315. #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
  4316. #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
  4317. #define TIM_BDTR_BKP_Pos (13U)
  4318. #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
  4319. #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
  4320. #define TIM_BDTR_AOE_Pos (14U)
  4321. #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
  4322. #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
  4323. #define TIM_BDTR_MOE_Pos (15U)
  4324. #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
  4325. #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
  4326. /******************* Bit definition for TIM_DCR register *******************/
  4327. #define TIM_DCR_DBA_Pos (0U)
  4328. #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
  4329. #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
  4330. #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
  4331. #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
  4332. #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
  4333. #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
  4334. #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
  4335. #define TIM_DCR_DBL_Pos (8U)
  4336. #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
  4337. #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
  4338. #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
  4339. #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
  4340. #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
  4341. #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
  4342. #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
  4343. /******************* Bit definition for TIM_DMAR register ******************/
  4344. #define TIM_DMAR_DMAB_Pos (0U)
  4345. #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
  4346. #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
  4347. /******************* Bit definition for TIM14_OR register ********************/
  4348. #define TIM14_OR_TI1_RMP_Pos (0U)
  4349. #define TIM14_OR_TI1_RMP_Msk (0x3U << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000003 */
  4350. #define TIM14_OR_TI1_RMP TIM14_OR_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
  4351. #define TIM14_OR_TI1_RMP_0 (0x1U << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000001 */
  4352. #define TIM14_OR_TI1_RMP_1 (0x2U << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000002 */
  4353. /******************************************************************************/
  4354. /* */
  4355. /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
  4356. /* */
  4357. /******************************************************************************/
  4358. /****************** Bit definition for USART_CR1 register *******************/
  4359. #define USART_CR1_UE_Pos (0U)
  4360. #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
  4361. #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
  4362. #define USART_CR1_RE_Pos (2U)
  4363. #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
  4364. #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
  4365. #define USART_CR1_TE_Pos (3U)
  4366. #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
  4367. #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
  4368. #define USART_CR1_IDLEIE_Pos (4U)
  4369. #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
  4370. #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
  4371. #define USART_CR1_RXNEIE_Pos (5U)
  4372. #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
  4373. #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
  4374. #define USART_CR1_TCIE_Pos (6U)
  4375. #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
  4376. #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
  4377. #define USART_CR1_TXEIE_Pos (7U)
  4378. #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
  4379. #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
  4380. #define USART_CR1_PEIE_Pos (8U)
  4381. #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
  4382. #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
  4383. #define USART_CR1_PS_Pos (9U)
  4384. #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
  4385. #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
  4386. #define USART_CR1_PCE_Pos (10U)
  4387. #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
  4388. #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
  4389. #define USART_CR1_WAKE_Pos (11U)
  4390. #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
  4391. #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
  4392. #define USART_CR1_M_Pos (12U)
  4393. #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
  4394. #define USART_CR1_M USART_CR1_M_Msk /*!< Word Length */
  4395. #define USART_CR1_MME_Pos (13U)
  4396. #define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
  4397. #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
  4398. #define USART_CR1_CMIE_Pos (14U)
  4399. #define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
  4400. #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
  4401. #define USART_CR1_OVER8_Pos (15U)
  4402. #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
  4403. #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
  4404. #define USART_CR1_DEDT_Pos (16U)
  4405. #define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
  4406. #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
  4407. #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
  4408. #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
  4409. #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
  4410. #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
  4411. #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
  4412. #define USART_CR1_DEAT_Pos (21U)
  4413. #define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
  4414. #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
  4415. #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
  4416. #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
  4417. #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
  4418. #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
  4419. #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
  4420. #define USART_CR1_RTOIE_Pos (26U)
  4421. #define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
  4422. #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
  4423. #define USART_CR1_EOBIE_Pos (27U)
  4424. #define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
  4425. #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
  4426. /****************** Bit definition for USART_CR2 register *******************/
  4427. #define USART_CR2_ADDM7_Pos (4U)
  4428. #define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
  4429. #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
  4430. #define USART_CR2_LBCL_Pos (8U)
  4431. #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
  4432. #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
  4433. #define USART_CR2_CPHA_Pos (9U)
  4434. #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
  4435. #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
  4436. #define USART_CR2_CPOL_Pos (10U)
  4437. #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
  4438. #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
  4439. #define USART_CR2_CLKEN_Pos (11U)
  4440. #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
  4441. #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
  4442. #define USART_CR2_STOP_Pos (12U)
  4443. #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
  4444. #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
  4445. #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
  4446. #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
  4447. #define USART_CR2_SWAP_Pos (15U)
  4448. #define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
  4449. #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
  4450. #define USART_CR2_RXINV_Pos (16U)
  4451. #define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
  4452. #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
  4453. #define USART_CR2_TXINV_Pos (17U)
  4454. #define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
  4455. #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
  4456. #define USART_CR2_DATAINV_Pos (18U)
  4457. #define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
  4458. #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
  4459. #define USART_CR2_MSBFIRST_Pos (19U)
  4460. #define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
  4461. #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
  4462. #define USART_CR2_ABREN_Pos (20U)
  4463. #define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
  4464. #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
  4465. #define USART_CR2_ABRMODE_Pos (21U)
  4466. #define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
  4467. #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
  4468. #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
  4469. #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
  4470. #define USART_CR2_RTOEN_Pos (23U)
  4471. #define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
  4472. #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
  4473. #define USART_CR2_ADD_Pos (24U)
  4474. #define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
  4475. #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
  4476. /****************** Bit definition for USART_CR3 register *******************/
  4477. #define USART_CR3_EIE_Pos (0U)
  4478. #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
  4479. #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
  4480. #define USART_CR3_HDSEL_Pos (3U)
  4481. #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
  4482. #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
  4483. #define USART_CR3_DMAR_Pos (6U)
  4484. #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
  4485. #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
  4486. #define USART_CR3_DMAT_Pos (7U)
  4487. #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
  4488. #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
  4489. #define USART_CR3_RTSE_Pos (8U)
  4490. #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
  4491. #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
  4492. #define USART_CR3_CTSE_Pos (9U)
  4493. #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
  4494. #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
  4495. #define USART_CR3_CTSIE_Pos (10U)
  4496. #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
  4497. #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
  4498. #define USART_CR3_ONEBIT_Pos (11U)
  4499. #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
  4500. #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
  4501. #define USART_CR3_OVRDIS_Pos (12U)
  4502. #define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
  4503. #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
  4504. #define USART_CR3_DDRE_Pos (13U)
  4505. #define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
  4506. #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
  4507. #define USART_CR3_DEM_Pos (14U)
  4508. #define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
  4509. #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
  4510. #define USART_CR3_DEP_Pos (15U)
  4511. #define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
  4512. #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
  4513. /****************** Bit definition for USART_BRR register *******************/
  4514. #define USART_BRR_DIV_FRACTION_Pos (0U)
  4515. #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
  4516. #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
  4517. #define USART_BRR_DIV_MANTISSA_Pos (4U)
  4518. #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
  4519. #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
  4520. /****************** Bit definition for USART_GTPR register ******************/
  4521. #define USART_GTPR_PSC_Pos (0U)
  4522. #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
  4523. #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
  4524. #define USART_GTPR_GT_Pos (8U)
  4525. #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
  4526. #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
  4527. /******************* Bit definition for USART_RTOR register *****************/
  4528. #define USART_RTOR_RTO_Pos (0U)
  4529. #define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
  4530. #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
  4531. #define USART_RTOR_BLEN_Pos (24U)
  4532. #define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
  4533. #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
  4534. /******************* Bit definition for USART_RQR register ******************/
  4535. #define USART_RQR_ABRRQ_Pos (0U)
  4536. #define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
  4537. #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
  4538. #define USART_RQR_SBKRQ_Pos (1U)
  4539. #define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
  4540. #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
  4541. #define USART_RQR_MMRQ_Pos (2U)
  4542. #define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
  4543. #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
  4544. #define USART_RQR_RXFRQ_Pos (3U)
  4545. #define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
  4546. #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
  4547. /******************* Bit definition for USART_ISR register ******************/
  4548. #define USART_ISR_PE_Pos (0U)
  4549. #define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
  4550. #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
  4551. #define USART_ISR_FE_Pos (1U)
  4552. #define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
  4553. #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
  4554. #define USART_ISR_NE_Pos (2U)
  4555. #define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
  4556. #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
  4557. #define USART_ISR_ORE_Pos (3U)
  4558. #define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
  4559. #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
  4560. #define USART_ISR_IDLE_Pos (4U)
  4561. #define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
  4562. #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
  4563. #define USART_ISR_RXNE_Pos (5U)
  4564. #define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
  4565. #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
  4566. #define USART_ISR_TC_Pos (6U)
  4567. #define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
  4568. #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
  4569. #define USART_ISR_TXE_Pos (7U)
  4570. #define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
  4571. #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
  4572. #define USART_ISR_CTSIF_Pos (9U)
  4573. #define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
  4574. #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
  4575. #define USART_ISR_CTS_Pos (10U)
  4576. #define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
  4577. #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
  4578. #define USART_ISR_RTOF_Pos (11U)
  4579. #define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
  4580. #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
  4581. #define USART_ISR_ABRE_Pos (14U)
  4582. #define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
  4583. #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
  4584. #define USART_ISR_ABRF_Pos (15U)
  4585. #define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
  4586. #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
  4587. #define USART_ISR_BUSY_Pos (16U)
  4588. #define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
  4589. #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
  4590. #define USART_ISR_CMF_Pos (17U)
  4591. #define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
  4592. #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
  4593. #define USART_ISR_SBKF_Pos (18U)
  4594. #define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
  4595. #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
  4596. #define USART_ISR_RWU_Pos (19U)
  4597. #define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
  4598. #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
  4599. #define USART_ISR_TEACK_Pos (21U)
  4600. #define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
  4601. #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
  4602. #define USART_ISR_REACK_Pos (22U)
  4603. #define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
  4604. #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
  4605. /******************* Bit definition for USART_ICR register ******************/
  4606. #define USART_ICR_PECF_Pos (0U)
  4607. #define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
  4608. #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
  4609. #define USART_ICR_FECF_Pos (1U)
  4610. #define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
  4611. #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
  4612. #define USART_ICR_NCF_Pos (2U)
  4613. #define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
  4614. #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
  4615. #define USART_ICR_ORECF_Pos (3U)
  4616. #define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
  4617. #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
  4618. #define USART_ICR_IDLECF_Pos (4U)
  4619. #define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
  4620. #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
  4621. #define USART_ICR_TCCF_Pos (6U)
  4622. #define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
  4623. #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
  4624. #define USART_ICR_CTSCF_Pos (9U)
  4625. #define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
  4626. #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
  4627. #define USART_ICR_RTOCF_Pos (11U)
  4628. #define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
  4629. #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
  4630. #define USART_ICR_CMCF_Pos (17U)
  4631. #define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
  4632. #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
  4633. /******************* Bit definition for USART_RDR register ******************/
  4634. #define USART_RDR_RDR ((uint16_t)0x01FFU) /*!< RDR[8:0] bits (Receive Data value) */
  4635. /******************* Bit definition for USART_TDR register ******************/
  4636. #define USART_TDR_TDR ((uint16_t)0x01FFU) /*!< TDR[8:0] bits (Transmit Data value) */
  4637. /******************************************************************************/
  4638. /* */
  4639. /* Window WATCHDOG (WWDG) */
  4640. /* */
  4641. /******************************************************************************/
  4642. /******************* Bit definition for WWDG_CR register ********************/
  4643. #define WWDG_CR_T_Pos (0U)
  4644. #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
  4645. #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
  4646. #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
  4647. #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
  4648. #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
  4649. #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
  4650. #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
  4651. #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
  4652. #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
  4653. /* Legacy defines */
  4654. #define WWDG_CR_T0 WWDG_CR_T_0
  4655. #define WWDG_CR_T1 WWDG_CR_T_1
  4656. #define WWDG_CR_T2 WWDG_CR_T_2
  4657. #define WWDG_CR_T3 WWDG_CR_T_3
  4658. #define WWDG_CR_T4 WWDG_CR_T_4
  4659. #define WWDG_CR_T5 WWDG_CR_T_5
  4660. #define WWDG_CR_T6 WWDG_CR_T_6
  4661. #define WWDG_CR_WDGA_Pos (7U)
  4662. #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
  4663. #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
  4664. /******************* Bit definition for WWDG_CFR register *******************/
  4665. #define WWDG_CFR_W_Pos (0U)
  4666. #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
  4667. #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
  4668. #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
  4669. #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
  4670. #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
  4671. #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
  4672. #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
  4673. #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
  4674. #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
  4675. /* Legacy defines */
  4676. #define WWDG_CFR_W0 WWDG_CFR_W_0
  4677. #define WWDG_CFR_W1 WWDG_CFR_W_1
  4678. #define WWDG_CFR_W2 WWDG_CFR_W_2
  4679. #define WWDG_CFR_W3 WWDG_CFR_W_3
  4680. #define WWDG_CFR_W4 WWDG_CFR_W_4
  4681. #define WWDG_CFR_W5 WWDG_CFR_W_5
  4682. #define WWDG_CFR_W6 WWDG_CFR_W_6
  4683. #define WWDG_CFR_WDGTB_Pos (7U)
  4684. #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
  4685. #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
  4686. #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
  4687. #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
  4688. /* Legacy defines */
  4689. #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
  4690. #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
  4691. #define WWDG_CFR_EWI_Pos (9U)
  4692. #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
  4693. #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
  4694. /******************* Bit definition for WWDG_SR register ********************/
  4695. #define WWDG_SR_EWIF_Pos (0U)
  4696. #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
  4697. #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
  4698. /**
  4699. * @}
  4700. */
  4701. /**
  4702. * @}
  4703. */
  4704. /** @addtogroup Exported_macro
  4705. * @{
  4706. */
  4707. /****************************** ADC Instances *********************************/
  4708. #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
  4709. #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
  4710. /****************************** CRC Instances *********************************/
  4711. #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
  4712. /******************************* DMA Instances ********************************/
  4713. #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
  4714. ((INSTANCE) == DMA1_Channel2) || \
  4715. ((INSTANCE) == DMA1_Channel3) || \
  4716. ((INSTANCE) == DMA1_Channel4) || \
  4717. ((INSTANCE) == DMA1_Channel5))
  4718. /****************************** GPIO Instances ********************************/
  4719. #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
  4720. ((INSTANCE) == GPIOB) || \
  4721. ((INSTANCE) == GPIOC) || \
  4722. ((INSTANCE) == GPIOD) || \
  4723. ((INSTANCE) == GPIOF))
  4724. /**************************** GPIO Alternate Function Instances ***************/
  4725. #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
  4726. ((INSTANCE) == GPIOB))
  4727. /****************************** GPIO Lock Instances ***************************/
  4728. #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
  4729. ((INSTANCE) == GPIOB))
  4730. /****************************** I2C Instances *********************************/
  4731. #define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
  4732. /****************************** IWDG Instances ********************************/
  4733. #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
  4734. /****************************** RTC Instances *********************************/
  4735. #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
  4736. /****************************** SMBUS Instances *********************************/
  4737. #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
  4738. /****************************** SPI Instances *********************************/
  4739. #define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
  4740. /****************************** TIM Instances *********************************/
  4741. #define IS_TIM_INSTANCE(INSTANCE)\
  4742. (((INSTANCE) == TIM1) || \
  4743. ((INSTANCE) == TIM3) || \
  4744. ((INSTANCE) == TIM14) || \
  4745. ((INSTANCE) == TIM16) || \
  4746. ((INSTANCE) == TIM17))
  4747. #define IS_TIM_CC1_INSTANCE(INSTANCE)\
  4748. (((INSTANCE) == TIM1) || \
  4749. ((INSTANCE) == TIM3) || \
  4750. ((INSTANCE) == TIM14) || \
  4751. ((INSTANCE) == TIM16) || \
  4752. ((INSTANCE) == TIM17))
  4753. #define IS_TIM_CC2_INSTANCE(INSTANCE)\
  4754. (((INSTANCE) == TIM1) || \
  4755. ((INSTANCE) == TIM3))
  4756. #define IS_TIM_CC3_INSTANCE(INSTANCE)\
  4757. (((INSTANCE) == TIM1) || \
  4758. ((INSTANCE) == TIM3))
  4759. #define IS_TIM_CC4_INSTANCE(INSTANCE)\
  4760. (((INSTANCE) == TIM1) || \
  4761. ((INSTANCE) == TIM3))
  4762. #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
  4763. (((INSTANCE) == TIM1) || \
  4764. ((INSTANCE) == TIM3))
  4765. #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
  4766. (((INSTANCE) == TIM1) || \
  4767. ((INSTANCE) == TIM3))
  4768. #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
  4769. (((INSTANCE) == TIM1) || \
  4770. ((INSTANCE) == TIM3))
  4771. #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
  4772. (((INSTANCE) == TIM1) || \
  4773. ((INSTANCE) == TIM3))
  4774. #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
  4775. (((INSTANCE) == TIM1) || \
  4776. ((INSTANCE) == TIM3))
  4777. #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
  4778. (((INSTANCE) == TIM1) || \
  4779. ((INSTANCE) == TIM3))
  4780. #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
  4781. (((INSTANCE) == TIM1))
  4782. #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\
  4783. (((INSTANCE) == TIM1))
  4784. #define IS_TIM_XOR_INSTANCE(INSTANCE)\
  4785. (((INSTANCE) == TIM1) || \
  4786. ((INSTANCE) == TIM3))
  4787. #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
  4788. (((INSTANCE) == TIM1) || \
  4789. ((INSTANCE) == TIM3))
  4790. #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
  4791. (((INSTANCE) == TIM1) || \
  4792. ((INSTANCE) == TIM3))
  4793. #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (0)
  4794. #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
  4795. (((INSTANCE) == TIM1) || \
  4796. ((INSTANCE) == TIM3) || \
  4797. ((INSTANCE) == TIM16) || \
  4798. ((INSTANCE) == TIM17))
  4799. #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
  4800. (((INSTANCE) == TIM1) || \
  4801. ((INSTANCE) == TIM16) || \
  4802. ((INSTANCE) == TIM17))
  4803. #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
  4804. ((((INSTANCE) == TIM1) && \
  4805. (((CHANNEL) == TIM_CHANNEL_1) || \
  4806. ((CHANNEL) == TIM_CHANNEL_2) || \
  4807. ((CHANNEL) == TIM_CHANNEL_3) || \
  4808. ((CHANNEL) == TIM_CHANNEL_4))) \
  4809. || \
  4810. (((INSTANCE) == TIM3) && \
  4811. (((CHANNEL) == TIM_CHANNEL_1) || \
  4812. ((CHANNEL) == TIM_CHANNEL_2) || \
  4813. ((CHANNEL) == TIM_CHANNEL_3) || \
  4814. ((CHANNEL) == TIM_CHANNEL_4))) \
  4815. || \
  4816. (((INSTANCE) == TIM14) && \
  4817. (((CHANNEL) == TIM_CHANNEL_1))) \
  4818. || \
  4819. (((INSTANCE) == TIM16) && \
  4820. (((CHANNEL) == TIM_CHANNEL_1))) \
  4821. || \
  4822. (((INSTANCE) == TIM17) && \
  4823. (((CHANNEL) == TIM_CHANNEL_1))))
  4824. #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
  4825. ((((INSTANCE) == TIM1) && \
  4826. (((CHANNEL) == TIM_CHANNEL_1) || \
  4827. ((CHANNEL) == TIM_CHANNEL_2) || \
  4828. ((CHANNEL) == TIM_CHANNEL_3))) \
  4829. || \
  4830. (((INSTANCE) == TIM16) && \
  4831. ((CHANNEL) == TIM_CHANNEL_1)) \
  4832. || \
  4833. (((INSTANCE) == TIM17) && \
  4834. ((CHANNEL) == TIM_CHANNEL_1)))
  4835. #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
  4836. (((INSTANCE) == TIM1) || \
  4837. ((INSTANCE) == TIM3))
  4838. #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
  4839. (((INSTANCE) == TIM1) || \
  4840. ((INSTANCE) == TIM16) || \
  4841. ((INSTANCE) == TIM17))
  4842. #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
  4843. (((INSTANCE) == TIM1) || \
  4844. ((INSTANCE) == TIM3) || \
  4845. ((INSTANCE) == TIM14) || \
  4846. ((INSTANCE) == TIM16) || \
  4847. ((INSTANCE) == TIM17))
  4848. #define IS_TIM_DMA_INSTANCE(INSTANCE)\
  4849. (((INSTANCE) == TIM1) || \
  4850. ((INSTANCE) == TIM3) || \
  4851. ((INSTANCE) == TIM16) || \
  4852. ((INSTANCE) == TIM17))
  4853. #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
  4854. (((INSTANCE) == TIM1) || \
  4855. ((INSTANCE) == TIM3) || \
  4856. ((INSTANCE) == TIM16) || \
  4857. ((INSTANCE) == TIM17))
  4858. #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
  4859. (((INSTANCE) == TIM1) || \
  4860. ((INSTANCE) == TIM16) || \
  4861. ((INSTANCE) == TIM17))
  4862. #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
  4863. ((INSTANCE) == TIM14)
  4864. /******************** USART Instances : Synchronous mode **********************/
  4865. #define IS_USART_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
  4866. /******************** USART Instances : auto Baud rate detection **************/
  4867. #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
  4868. /******************** UART Instances : Asynchronous mode **********************/
  4869. #define IS_UART_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
  4870. /******************** UART Instances : Half-Duplex mode **********************/
  4871. #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
  4872. /****************** UART Instances : Hardware Flow control ********************/
  4873. #define IS_UART_HWFLOW_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
  4874. /****************** UART Instances : Driver enable detection ********************/
  4875. #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
  4876. /****************************** WWDG Instances ********************************/
  4877. #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
  4878. /**
  4879. * @}
  4880. */
  4881. /******************************************************************************/
  4882. /* For a painless codes migration between the STM32F0xx device product */
  4883. /* lines, the aliases defined below are put in place to overcome the */
  4884. /* differences in the interrupt handlers and IRQn definitions. */
  4885. /* No need to update developed interrupt code when moving across */
  4886. /* product lines within the same STM32F0 Family */
  4887. /******************************************************************************/
  4888. /* Aliases for __IRQn */
  4889. #define ADC1_COMP_IRQn ADC1_IRQn
  4890. #define DMA1_Ch1_IRQn DMA1_Channel1_IRQn
  4891. #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn
  4892. #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
  4893. #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
  4894. #define RCC_CRS_IRQn RCC_IRQn
  4895. /* Aliases for __IRQHandler */
  4896. #define ADC1_COMP_IRQHandler ADC1_IRQHandler
  4897. #define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler
  4898. #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler
  4899. #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
  4900. #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler
  4901. #define RCC_CRS_IRQHandler RCC_IRQHandler
  4902. #ifdef __cplusplus
  4903. }
  4904. #endif /* __cplusplus */
  4905. #endif /* __STM32F030x6_H */
  4906. /**
  4907. * @}
  4908. */
  4909. /**
  4910. * @}
  4911. */
  4912. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/