startup_stm32f030x6.s 10.0 KB

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  1. /**
  2. ******************************************************************************
  3. * @file startup_stm32f030x6.s
  4. * @author MCD Application Team
  5. * @version V2.3.1
  6. * @date 04-November-2016
  7. * @brief STM32F030x4/STM32F030x6 devices vector table for Atollic TrueSTUDIO toolchain.
  8. * This module performs:
  9. * - Set the initial SP
  10. * - Set the initial PC == Reset_Handler,
  11. * - Set the vector table entries with the exceptions ISR address
  12. * - Branches to main in the C library (which eventually
  13. * calls main()).
  14. * After Reset the Cortex-M0 processor is in Thread mode,
  15. * priority is Privileged, and the Stack is set to Main.
  16. ******************************************************************************
  17. *
  18. * Redistribution and use in source and binary forms, with or without modification,
  19. * are permitted provided that the following conditions are met:
  20. * 1. Redistributions of source code must retain the above copyright notice,
  21. * this list of conditions and the following disclaimer.
  22. * 2. Redistributions in binary form must reproduce the above copyright notice,
  23. * this list of conditions and the following disclaimer in the documentation
  24. * and/or other materials provided with the distribution.
  25. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  26. * may be used to endorse or promote products derived from this software
  27. * without specific prior written permission.
  28. *
  29. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  30. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  31. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  32. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  33. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  34. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  35. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  36. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  37. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39. *
  40. ******************************************************************************
  41. */
  42. .syntax unified
  43. .cpu cortex-m0
  44. .fpu softvfp
  45. .thumb
  46. .global g_pfnVectors
  47. .global Default_Handler
  48. /* start address for the initialization values of the .data section.
  49. defined in linker script */
  50. .word _sidata
  51. /* start address for the .data section. defined in linker script */
  52. .word _sdata
  53. /* end address for the .data section. defined in linker script */
  54. .word _edata
  55. /* start address for the .bss section. defined in linker script */
  56. .word _sbss
  57. /* end address for the .bss section. defined in linker script */
  58. .word _ebss
  59. .section .text.Reset_Handler
  60. .weak Reset_Handler
  61. .type Reset_Handler, %function
  62. Reset_Handler:
  63. ldr r0, =_estack
  64. mov sp, r0 /* set stack pointer */
  65. /* Copy the data segment initializers from flash to SRAM */
  66. movs r1, #0
  67. b LoopCopyDataInit
  68. CopyDataInit:
  69. ldr r3, =_sidata
  70. ldr r3, [r3, r1]
  71. str r3, [r0, r1]
  72. adds r1, r1, #4
  73. LoopCopyDataInit:
  74. ldr r0, =_sdata
  75. ldr r3, =_edata
  76. adds r2, r0, r1
  77. cmp r2, r3
  78. bcc CopyDataInit
  79. ldr r2, =_sbss
  80. b LoopFillZerobss
  81. /* Zero fill the bss segment. */
  82. FillZerobss:
  83. movs r3, #0
  84. str r3, [r2]
  85. adds r2, r2, #4
  86. LoopFillZerobss:
  87. ldr r3, = _ebss
  88. cmp r2, r3
  89. bcc FillZerobss
  90. /* Call the clock system intitialization function.*/
  91. bl SystemInit
  92. /* Call static constructors */
  93. bl __libc_init_array
  94. /* Call the application's entry point.*/
  95. bl main
  96. LoopForever:
  97. b LoopForever
  98. .size Reset_Handler, .-Reset_Handler
  99. /**
  100. * @brief This is the code that gets called when the processor receives an
  101. * unexpected interrupt. This simply enters an infinite loop, preserving
  102. * the system state for examination by a debugger.
  103. *
  104. * @param None
  105. * @retval : None
  106. */
  107. .section .text.Default_Handler,"ax",%progbits
  108. Default_Handler:
  109. Infinite_Loop:
  110. b Infinite_Loop
  111. .size Default_Handler, .-Default_Handler
  112. /******************************************************************************
  113. *
  114. * The minimal vector table for a Cortex M0. Note that the proper constructs
  115. * must be placed on this to ensure that it ends up at physical address
  116. * 0x0000.0000.
  117. *
  118. ******************************************************************************/
  119. .section .isr_vector,"a",%progbits
  120. .type g_pfnVectors, %object
  121. .size g_pfnVectors, .-g_pfnVectors
  122. g_pfnVectors:
  123. .word _estack
  124. .word Reset_Handler
  125. .word NMI_Handler
  126. .word HardFault_Handler
  127. .word 0
  128. .word 0
  129. .word 0
  130. .word 0
  131. .word 0
  132. .word 0
  133. .word 0
  134. .word SVC_Handler
  135. .word 0
  136. .word 0
  137. .word PendSV_Handler
  138. .word SysTick_Handler
  139. .word WWDG_IRQHandler /* Window WatchDog */
  140. .word 0 /* Reserved */
  141. .word RTC_IRQHandler /* RTC through the EXTI line */
  142. .word FLASH_IRQHandler /* FLASH */
  143. .word RCC_IRQHandler /* RCC */
  144. .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
  145. .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
  146. .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
  147. .word 0 /* Reserved */
  148. .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
  149. .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
  150. .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */
  151. .word ADC1_IRQHandler /* ADC1 */
  152. .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
  153. .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
  154. .word 0 /* Reserved */
  155. .word TIM3_IRQHandler /* TIM3 */
  156. .word 0 /* Reserved */
  157. .word 0 /* Reserved */
  158. .word TIM14_IRQHandler /* TIM14 */
  159. .word 0 /* Reserved */
  160. .word TIM16_IRQHandler /* TIM16 */
  161. .word TIM17_IRQHandler /* TIM17 */
  162. .word I2C1_IRQHandler /* I2C1 */
  163. .word 0 /* Reserved */
  164. .word SPI1_IRQHandler /* SPI1 */
  165. .word 0 /* Reserved */
  166. .word USART1_IRQHandler /* USART1 */
  167. .word 0 /* Reserved */
  168. .word 0 /* Reserved */
  169. .word 0 /* Reserved */
  170. .word 0 /* Reserved */
  171. /*******************************************************************************
  172. *
  173. * Provide weak aliases for each Exception handler to the Default_Handler.
  174. * As they are weak aliases, any function with the same name will override
  175. * this definition.
  176. *
  177. *******************************************************************************/
  178. .weak NMI_Handler
  179. .thumb_set NMI_Handler,Default_Handler
  180. .weak HardFault_Handler
  181. .thumb_set HardFault_Handler,Default_Handler
  182. .weak SVC_Handler
  183. .thumb_set SVC_Handler,Default_Handler
  184. .weak PendSV_Handler
  185. .thumb_set PendSV_Handler,Default_Handler
  186. .weak SysTick_Handler
  187. .thumb_set SysTick_Handler,Default_Handler
  188. .weak WWDG_IRQHandler
  189. .thumb_set WWDG_IRQHandler,Default_Handler
  190. .weak RTC_IRQHandler
  191. .thumb_set RTC_IRQHandler,Default_Handler
  192. .weak FLASH_IRQHandler
  193. .thumb_set FLASH_IRQHandler,Default_Handler
  194. .weak RCC_IRQHandler
  195. .thumb_set RCC_IRQHandler,Default_Handler
  196. .weak EXTI0_1_IRQHandler
  197. .thumb_set EXTI0_1_IRQHandler,Default_Handler
  198. .weak EXTI2_3_IRQHandler
  199. .thumb_set EXTI2_3_IRQHandler,Default_Handler
  200. .weak EXTI4_15_IRQHandler
  201. .thumb_set EXTI4_15_IRQHandler,Default_Handler
  202. .weak DMA1_Channel1_IRQHandler
  203. .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
  204. .weak DMA1_Channel2_3_IRQHandler
  205. .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
  206. .weak DMA1_Channel4_5_IRQHandler
  207. .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
  208. .weak ADC1_IRQHandler
  209. .thumb_set ADC1_IRQHandler,Default_Handler
  210. .weak TIM1_BRK_UP_TRG_COM_IRQHandler
  211. .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
  212. .weak TIM1_CC_IRQHandler
  213. .thumb_set TIM1_CC_IRQHandler,Default_Handler
  214. .weak TIM3_IRQHandler
  215. .thumb_set TIM3_IRQHandler,Default_Handler
  216. .weak TIM14_IRQHandler
  217. .thumb_set TIM14_IRQHandler,Default_Handler
  218. .weak TIM16_IRQHandler
  219. .thumb_set TIM16_IRQHandler,Default_Handler
  220. .weak TIM17_IRQHandler
  221. .thumb_set TIM17_IRQHandler,Default_Handler
  222. .weak I2C1_IRQHandler
  223. .thumb_set I2C1_IRQHandler,Default_Handler
  224. .weak SPI1_IRQHandler
  225. .thumb_set SPI1_IRQHandler,Default_Handler
  226. .weak USART1_IRQHandler
  227. .thumb_set USART1_IRQHandler,Default_Handler
  228. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/