cmsis_armcc.h 24 KB

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  1. /**************************************************************************//**
  2. * @file cmsis_armcc.h
  3. * @brief CMSIS Cortex-M Core Function/Instruction Header File
  4. * @version V4.30
  5. * @date 20. October 2015
  6. ******************************************************************************/
  7. /* Copyright (c) 2009 - 2015 ARM LIMITED
  8. All rights reserved.
  9. Redistribution and use in source and binary forms, with or without
  10. modification, are permitted provided that the following conditions are met:
  11. - Redistributions of source code must retain the above copyright
  12. notice, this list of conditions and the following disclaimer.
  13. - Redistributions in binary form must reproduce the above copyright
  14. notice, this list of conditions and the following disclaimer in the
  15. documentation and/or other materials provided with the distribution.
  16. - Neither the name of ARM nor the names of its contributors may be used
  17. to endorse or promote products derived from this software without
  18. specific prior written permission.
  19. *
  20. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21. AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22. IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23. ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
  24. LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25. CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26. SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27. INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28. CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29. ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30. POSSIBILITY OF SUCH DAMAGE.
  31. ---------------------------------------------------------------------------*/
  32. #ifndef __CMSIS_ARMCC_H
  33. #define __CMSIS_ARMCC_H
  34. #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
  35. #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
  36. #endif
  37. /* ########################### Core Function Access ########################### */
  38. /** \ingroup CMSIS_Core_FunctionInterface
  39. \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
  40. @{
  41. */
  42. /* intrinsic void __enable_irq(); */
  43. /* intrinsic void __disable_irq(); */
  44. /**
  45. \brief Get Control Register
  46. \details Returns the content of the Control Register.
  47. \return Control Register value
  48. */
  49. __STATIC_INLINE uint32_t __get_CONTROL(void)
  50. {
  51. register uint32_t __regControl __ASM("control");
  52. return(__regControl);
  53. }
  54. /**
  55. \brief Set Control Register
  56. \details Writes the given value to the Control Register.
  57. \param [in] control Control Register value to set
  58. */
  59. __STATIC_INLINE void __set_CONTROL(uint32_t control)
  60. {
  61. register uint32_t __regControl __ASM("control");
  62. __regControl = control;
  63. }
  64. /**
  65. \brief Get IPSR Register
  66. \details Returns the content of the IPSR Register.
  67. \return IPSR Register value
  68. */
  69. __STATIC_INLINE uint32_t __get_IPSR(void)
  70. {
  71. register uint32_t __regIPSR __ASM("ipsr");
  72. return(__regIPSR);
  73. }
  74. /**
  75. \brief Get APSR Register
  76. \details Returns the content of the APSR Register.
  77. \return APSR Register value
  78. */
  79. __STATIC_INLINE uint32_t __get_APSR(void)
  80. {
  81. register uint32_t __regAPSR __ASM("apsr");
  82. return(__regAPSR);
  83. }
  84. /**
  85. \brief Get xPSR Register
  86. \details Returns the content of the xPSR Register.
  87. \return xPSR Register value
  88. */
  89. __STATIC_INLINE uint32_t __get_xPSR(void)
  90. {
  91. register uint32_t __regXPSR __ASM("xpsr");
  92. return(__regXPSR);
  93. }
  94. /**
  95. \brief Get Process Stack Pointer
  96. \details Returns the current value of the Process Stack Pointer (PSP).
  97. \return PSP Register value
  98. */
  99. __STATIC_INLINE uint32_t __get_PSP(void)
  100. {
  101. register uint32_t __regProcessStackPointer __ASM("psp");
  102. return(__regProcessStackPointer);
  103. }
  104. /**
  105. \brief Set Process Stack Pointer
  106. \details Assigns the given value to the Process Stack Pointer (PSP).
  107. \param [in] topOfProcStack Process Stack Pointer value to set
  108. */
  109. __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
  110. {
  111. register uint32_t __regProcessStackPointer __ASM("psp");
  112. __regProcessStackPointer = topOfProcStack;
  113. }
  114. /**
  115. \brief Get Main Stack Pointer
  116. \details Returns the current value of the Main Stack Pointer (MSP).
  117. \return MSP Register value
  118. */
  119. __STATIC_INLINE uint32_t __get_MSP(void)
  120. {
  121. register uint32_t __regMainStackPointer __ASM("msp");
  122. return(__regMainStackPointer);
  123. }
  124. /**
  125. \brief Set Main Stack Pointer
  126. \details Assigns the given value to the Main Stack Pointer (MSP).
  127. \param [in] topOfMainStack Main Stack Pointer value to set
  128. */
  129. __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
  130. {
  131. register uint32_t __regMainStackPointer __ASM("msp");
  132. __regMainStackPointer = topOfMainStack;
  133. }
  134. /**
  135. \brief Get Priority Mask
  136. \details Returns the current state of the priority mask bit from the Priority Mask Register.
  137. \return Priority Mask value
  138. */
  139. __STATIC_INLINE uint32_t __get_PRIMASK(void)
  140. {
  141. register uint32_t __regPriMask __ASM("primask");
  142. return(__regPriMask);
  143. }
  144. /**
  145. \brief Set Priority Mask
  146. \details Assigns the given value to the Priority Mask Register.
  147. \param [in] priMask Priority Mask
  148. */
  149. __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
  150. {
  151. register uint32_t __regPriMask __ASM("primask");
  152. __regPriMask = (priMask);
  153. }
  154. #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
  155. /**
  156. \brief Enable FIQ
  157. \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
  158. Can only be executed in Privileged modes.
  159. */
  160. #define __enable_fault_irq __enable_fiq
  161. /**
  162. \brief Disable FIQ
  163. \details Disables FIQ interrupts by setting the F-bit in the CPSR.
  164. Can only be executed in Privileged modes.
  165. */
  166. #define __disable_fault_irq __disable_fiq
  167. /**
  168. \brief Get Base Priority
  169. \details Returns the current value of the Base Priority register.
  170. \return Base Priority register value
  171. */
  172. __STATIC_INLINE uint32_t __get_BASEPRI(void)
  173. {
  174. register uint32_t __regBasePri __ASM("basepri");
  175. return(__regBasePri);
  176. }
  177. /**
  178. \brief Set Base Priority
  179. \details Assigns the given value to the Base Priority register.
  180. \param [in] basePri Base Priority value to set
  181. */
  182. __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
  183. {
  184. register uint32_t __regBasePri __ASM("basepri");
  185. __regBasePri = (basePri & 0xFFU);
  186. }
  187. /**
  188. \brief Set Base Priority with condition
  189. \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
  190. or the new value increases the BASEPRI priority level.
  191. \param [in] basePri Base Priority value to set
  192. */
  193. __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
  194. {
  195. register uint32_t __regBasePriMax __ASM("basepri_max");
  196. __regBasePriMax = (basePri & 0xFFU);
  197. }
  198. /**
  199. \brief Get Fault Mask
  200. \details Returns the current value of the Fault Mask register.
  201. \return Fault Mask register value
  202. */
  203. __STATIC_INLINE uint32_t __get_FAULTMASK(void)
  204. {
  205. register uint32_t __regFaultMask __ASM("faultmask");
  206. return(__regFaultMask);
  207. }
  208. /**
  209. \brief Set Fault Mask
  210. \details Assigns the given value to the Fault Mask register.
  211. \param [in] faultMask Fault Mask value to set
  212. */
  213. __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
  214. {
  215. register uint32_t __regFaultMask __ASM("faultmask");
  216. __regFaultMask = (faultMask & (uint32_t)1);
  217. }
  218. #endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
  219. #if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
  220. /**
  221. \brief Get FPSCR
  222. \details Returns the current value of the Floating Point Status/Control register.
  223. \return Floating Point Status/Control register value
  224. */
  225. __STATIC_INLINE uint32_t __get_FPSCR(void)
  226. {
  227. #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
  228. register uint32_t __regfpscr __ASM("fpscr");
  229. return(__regfpscr);
  230. #else
  231. return(0U);
  232. #endif
  233. }
  234. /**
  235. \brief Set FPSCR
  236. \details Assigns the given value to the Floating Point Status/Control register.
  237. \param [in] fpscr Floating Point Status/Control value to set
  238. */
  239. __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
  240. {
  241. #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
  242. register uint32_t __regfpscr __ASM("fpscr");
  243. __regfpscr = (fpscr);
  244. #endif
  245. }
  246. #endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
  247. /*@} end of CMSIS_Core_RegAccFunctions */
  248. /* ########################## Core Instruction Access ######################### */
  249. /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
  250. Access to dedicated instructions
  251. @{
  252. */
  253. /**
  254. \brief No Operation
  255. \details No Operation does nothing. This instruction can be used for code alignment purposes.
  256. */
  257. #define __NOP __nop
  258. /**
  259. \brief Wait For Interrupt
  260. \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
  261. */
  262. #define __WFI __wfi
  263. /**
  264. \brief Wait For Event
  265. \details Wait For Event is a hint instruction that permits the processor to enter
  266. a low-power state until one of a number of events occurs.
  267. */
  268. #define __WFE __wfe
  269. /**
  270. \brief Send Event
  271. \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
  272. */
  273. #define __SEV __sev
  274. /**
  275. \brief Instruction Synchronization Barrier
  276. \details Instruction Synchronization Barrier flushes the pipeline in the processor,
  277. so that all instructions following the ISB are fetched from cache or memory,
  278. after the instruction has been completed.
  279. */
  280. #define __ISB() do {\
  281. __schedule_barrier();\
  282. __isb(0xF);\
  283. __schedule_barrier();\
  284. } while (0U)
  285. /**
  286. \brief Data Synchronization Barrier
  287. \details Acts as a special kind of Data Memory Barrier.
  288. It completes when all explicit memory accesses before this instruction complete.
  289. */
  290. #define __DSB() do {\
  291. __schedule_barrier();\
  292. __dsb(0xF);\
  293. __schedule_barrier();\
  294. } while (0U)
  295. /**
  296. \brief Data Memory Barrier
  297. \details Ensures the apparent order of the explicit memory operations before
  298. and after the instruction, without ensuring their completion.
  299. */
  300. #define __DMB() do {\
  301. __schedule_barrier();\
  302. __dmb(0xF);\
  303. __schedule_barrier();\
  304. } while (0U)
  305. /**
  306. \brief Reverse byte order (32 bit)
  307. \details Reverses the byte order in integer value.
  308. \param [in] value Value to reverse
  309. \return Reversed value
  310. */
  311. #define __REV __rev
  312. /**
  313. \brief Reverse byte order (16 bit)
  314. \details Reverses the byte order in two unsigned short values.
  315. \param [in] value Value to reverse
  316. \return Reversed value
  317. */
  318. #ifndef __NO_EMBEDDED_ASM
  319. __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
  320. {
  321. rev16 r0, r0
  322. bx lr
  323. }
  324. #endif
  325. /**
  326. \brief Reverse byte order in signed short value
  327. \details Reverses the byte order in a signed short value with sign extension to integer.
  328. \param [in] value Value to reverse
  329. \return Reversed value
  330. */
  331. #ifndef __NO_EMBEDDED_ASM
  332. __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
  333. {
  334. revsh r0, r0
  335. bx lr
  336. }
  337. #endif
  338. /**
  339. \brief Rotate Right in unsigned value (32 bit)
  340. \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
  341. \param [in] value Value to rotate
  342. \param [in] value Number of Bits to rotate
  343. \return Rotated value
  344. */
  345. #define __ROR __ror
  346. /**
  347. \brief Breakpoint
  348. \details Causes the processor to enter Debug state.
  349. Debug tools can use this to investigate system state when the instruction at a particular address is reached.
  350. \param [in] value is ignored by the processor.
  351. If required, a debugger can use it to store additional information about the breakpoint.
  352. */
  353. #define __BKPT(value) __breakpoint(value)
  354. /**
  355. \brief Reverse bit order of value
  356. \details Reverses the bit order of the given value.
  357. \param [in] value Value to reverse
  358. \return Reversed value
  359. */
  360. #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
  361. #define __RBIT __rbit
  362. #else
  363. __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
  364. {
  365. uint32_t result;
  366. int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
  367. result = value; /* r will be reversed bits of v; first get LSB of v */
  368. for (value >>= 1U; value; value >>= 1U)
  369. {
  370. result <<= 1U;
  371. result |= value & 1U;
  372. s--;
  373. }
  374. result <<= s; /* shift when v's highest bits are zero */
  375. return(result);
  376. }
  377. #endif
  378. /**
  379. \brief Count leading zeros
  380. \details Counts the number of leading zeros of a data value.
  381. \param [in] value Value to count the leading zeros
  382. \return number of leading zeros in value
  383. */
  384. #define __CLZ __clz
  385. #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
  386. /**
  387. \brief LDR Exclusive (8 bit)
  388. \details Executes a exclusive LDR instruction for 8 bit value.
  389. \param [in] ptr Pointer to data
  390. \return value of type uint8_t at (*ptr)
  391. */
  392. #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
  393. #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
  394. #else
  395. #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
  396. #endif
  397. /**
  398. \brief LDR Exclusive (16 bit)
  399. \details Executes a exclusive LDR instruction for 16 bit values.
  400. \param [in] ptr Pointer to data
  401. \return value of type uint16_t at (*ptr)
  402. */
  403. #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
  404. #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
  405. #else
  406. #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
  407. #endif
  408. /**
  409. \brief LDR Exclusive (32 bit)
  410. \details Executes a exclusive LDR instruction for 32 bit values.
  411. \param [in] ptr Pointer to data
  412. \return value of type uint32_t at (*ptr)
  413. */
  414. #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
  415. #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
  416. #else
  417. #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
  418. #endif
  419. /**
  420. \brief STR Exclusive (8 bit)
  421. \details Executes a exclusive STR instruction for 8 bit values.
  422. \param [in] value Value to store
  423. \param [in] ptr Pointer to location
  424. \return 0 Function succeeded
  425. \return 1 Function failed
  426. */
  427. #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
  428. #define __STREXB(value, ptr) __strex(value, ptr)
  429. #else
  430. #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
  431. #endif
  432. /**
  433. \brief STR Exclusive (16 bit)
  434. \details Executes a exclusive STR instruction for 16 bit values.
  435. \param [in] value Value to store
  436. \param [in] ptr Pointer to location
  437. \return 0 Function succeeded
  438. \return 1 Function failed
  439. */
  440. #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
  441. #define __STREXH(value, ptr) __strex(value, ptr)
  442. #else
  443. #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
  444. #endif
  445. /**
  446. \brief STR Exclusive (32 bit)
  447. \details Executes a exclusive STR instruction for 32 bit values.
  448. \param [in] value Value to store
  449. \param [in] ptr Pointer to location
  450. \return 0 Function succeeded
  451. \return 1 Function failed
  452. */
  453. #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
  454. #define __STREXW(value, ptr) __strex(value, ptr)
  455. #else
  456. #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
  457. #endif
  458. /**
  459. \brief Remove the exclusive lock
  460. \details Removes the exclusive lock which is created by LDREX.
  461. */
  462. #define __CLREX __clrex
  463. /**
  464. \brief Signed Saturate
  465. \details Saturates a signed value.
  466. \param [in] value Value to be saturated
  467. \param [in] sat Bit position to saturate to (1..32)
  468. \return Saturated value
  469. */
  470. #define __SSAT __ssat
  471. /**
  472. \brief Unsigned Saturate
  473. \details Saturates an unsigned value.
  474. \param [in] value Value to be saturated
  475. \param [in] sat Bit position to saturate to (0..31)
  476. \return Saturated value
  477. */
  478. #define __USAT __usat
  479. /**
  480. \brief Rotate Right with Extend (32 bit)
  481. \details Moves each bit of a bitstring right by one bit.
  482. The carry input is shifted in at the left end of the bitstring.
  483. \param [in] value Value to rotate
  484. \return Rotated value
  485. */
  486. #ifndef __NO_EMBEDDED_ASM
  487. __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
  488. {
  489. rrx r0, r0
  490. bx lr
  491. }
  492. #endif
  493. /**
  494. \brief LDRT Unprivileged (8 bit)
  495. \details Executes a Unprivileged LDRT instruction for 8 bit value.
  496. \param [in] ptr Pointer to data
  497. \return value of type uint8_t at (*ptr)
  498. */
  499. #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
  500. /**
  501. \brief LDRT Unprivileged (16 bit)
  502. \details Executes a Unprivileged LDRT instruction for 16 bit values.
  503. \param [in] ptr Pointer to data
  504. \return value of type uint16_t at (*ptr)
  505. */
  506. #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
  507. /**
  508. \brief LDRT Unprivileged (32 bit)
  509. \details Executes a Unprivileged LDRT instruction for 32 bit values.
  510. \param [in] ptr Pointer to data
  511. \return value of type uint32_t at (*ptr)
  512. */
  513. #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
  514. /**
  515. \brief STRT Unprivileged (8 bit)
  516. \details Executes a Unprivileged STRT instruction for 8 bit values.
  517. \param [in] value Value to store
  518. \param [in] ptr Pointer to location
  519. */
  520. #define __STRBT(value, ptr) __strt(value, ptr)
  521. /**
  522. \brief STRT Unprivileged (16 bit)
  523. \details Executes a Unprivileged STRT instruction for 16 bit values.
  524. \param [in] value Value to store
  525. \param [in] ptr Pointer to location
  526. */
  527. #define __STRHT(value, ptr) __strt(value, ptr)
  528. /**
  529. \brief STRT Unprivileged (32 bit)
  530. \details Executes a Unprivileged STRT instruction for 32 bit values.
  531. \param [in] value Value to store
  532. \param [in] ptr Pointer to location
  533. */
  534. #define __STRT(value, ptr) __strt(value, ptr)
  535. #endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
  536. /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
  537. /* ################### Compiler specific Intrinsics ########################### */
  538. /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
  539. Access to dedicated SIMD instructions
  540. @{
  541. */
  542. #if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
  543. #define __SADD8 __sadd8
  544. #define __QADD8 __qadd8
  545. #define __SHADD8 __shadd8
  546. #define __UADD8 __uadd8
  547. #define __UQADD8 __uqadd8
  548. #define __UHADD8 __uhadd8
  549. #define __SSUB8 __ssub8
  550. #define __QSUB8 __qsub8
  551. #define __SHSUB8 __shsub8
  552. #define __USUB8 __usub8
  553. #define __UQSUB8 __uqsub8
  554. #define __UHSUB8 __uhsub8
  555. #define __SADD16 __sadd16
  556. #define __QADD16 __qadd16
  557. #define __SHADD16 __shadd16
  558. #define __UADD16 __uadd16
  559. #define __UQADD16 __uqadd16
  560. #define __UHADD16 __uhadd16
  561. #define __SSUB16 __ssub16
  562. #define __QSUB16 __qsub16
  563. #define __SHSUB16 __shsub16
  564. #define __USUB16 __usub16
  565. #define __UQSUB16 __uqsub16
  566. #define __UHSUB16 __uhsub16
  567. #define __SASX __sasx
  568. #define __QASX __qasx
  569. #define __SHASX __shasx
  570. #define __UASX __uasx
  571. #define __UQASX __uqasx
  572. #define __UHASX __uhasx
  573. #define __SSAX __ssax
  574. #define __QSAX __qsax
  575. #define __SHSAX __shsax
  576. #define __USAX __usax
  577. #define __UQSAX __uqsax
  578. #define __UHSAX __uhsax
  579. #define __USAD8 __usad8
  580. #define __USADA8 __usada8
  581. #define __SSAT16 __ssat16
  582. #define __USAT16 __usat16
  583. #define __UXTB16 __uxtb16
  584. #define __UXTAB16 __uxtab16
  585. #define __SXTB16 __sxtb16
  586. #define __SXTAB16 __sxtab16
  587. #define __SMUAD __smuad
  588. #define __SMUADX __smuadx
  589. #define __SMLAD __smlad
  590. #define __SMLADX __smladx
  591. #define __SMLALD __smlald
  592. #define __SMLALDX __smlaldx
  593. #define __SMUSD __smusd
  594. #define __SMUSDX __smusdx
  595. #define __SMLSD __smlsd
  596. #define __SMLSDX __smlsdx
  597. #define __SMLSLD __smlsld
  598. #define __SMLSLDX __smlsldx
  599. #define __SEL __sel
  600. #define __QADD __qadd
  601. #define __QSUB __qsub
  602. #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
  603. ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
  604. #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
  605. ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
  606. #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
  607. ((int64_t)(ARG3) << 32U) ) >> 32U))
  608. #endif /* (__CORTEX_M >= 0x04) */
  609. /*@} end of group CMSIS_SIMD_intrinsics */
  610. #endif /* __CMSIS_ARMCC_H */