core_cm0.h 36 KB

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  1. /**************************************************************************//**
  2. * @file core_cm0.h
  3. * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
  4. * @version V4.30
  5. * @date 20. October 2015
  6. ******************************************************************************/
  7. /* Copyright (c) 2009 - 2015 ARM LIMITED
  8. All rights reserved.
  9. Redistribution and use in source and binary forms, with or without
  10. modification, are permitted provided that the following conditions are met:
  11. - Redistributions of source code must retain the above copyright
  12. notice, this list of conditions and the following disclaimer.
  13. - Redistributions in binary form must reproduce the above copyright
  14. notice, this list of conditions and the following disclaimer in the
  15. documentation and/or other materials provided with the distribution.
  16. - Neither the name of ARM nor the names of its contributors may be used
  17. to endorse or promote products derived from this software without
  18. specific prior written permission.
  19. *
  20. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21. AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22. IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23. ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
  24. LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25. CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26. SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27. INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28. CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29. ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30. POSSIBILITY OF SUCH DAMAGE.
  31. ---------------------------------------------------------------------------*/
  32. #if defined ( __ICCARM__ )
  33. #pragma system_include /* treat file as system include file for MISRA check */
  34. #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  35. #pragma clang system_header /* treat file as system include file */
  36. #endif
  37. #ifndef __CORE_CM0_H_GENERIC
  38. #define __CORE_CM0_H_GENERIC
  39. #include <stdint.h>
  40. #ifdef __cplusplus
  41. extern "C" {
  42. #endif
  43. /**
  44. \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
  45. CMSIS violates the following MISRA-C:2004 rules:
  46. \li Required Rule 8.5, object/function definition in header file.<br>
  47. Function definitions in header files are used to allow 'inlining'.
  48. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
  49. Unions are used for effective representation of core registers.
  50. \li Advisory Rule 19.7, Function-like macro defined.<br>
  51. Function-like macros are used to allow more efficient code.
  52. */
  53. /*******************************************************************************
  54. * CMSIS definitions
  55. ******************************************************************************/
  56. /**
  57. \ingroup Cortex_M0
  58. @{
  59. */
  60. /* CMSIS CM0 definitions */
  61. #define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
  62. #define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
  63. #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
  64. __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
  65. #define __CORTEX_M (0x00U) /*!< Cortex-M Core */
  66. #if defined ( __CC_ARM )
  67. #define __ASM __asm /*!< asm keyword for ARM Compiler */
  68. #define __INLINE __inline /*!< inline keyword for ARM Compiler */
  69. #define __STATIC_INLINE static __inline
  70. #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  71. #define __ASM __asm /*!< asm keyword for ARM Compiler */
  72. #define __INLINE __inline /*!< inline keyword for ARM Compiler */
  73. #define __STATIC_INLINE static __inline
  74. #elif defined ( __GNUC__ )
  75. #define __ASM __asm /*!< asm keyword for GNU Compiler */
  76. #define __INLINE inline /*!< inline keyword for GNU Compiler */
  77. #define __STATIC_INLINE static inline
  78. #elif defined ( __ICCARM__ )
  79. #define __ASM __asm /*!< asm keyword for IAR Compiler */
  80. #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
  81. #define __STATIC_INLINE static inline
  82. #elif defined ( __TMS470__ )
  83. #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
  84. #define __STATIC_INLINE static inline
  85. #elif defined ( __TASKING__ )
  86. #define __ASM __asm /*!< asm keyword for TASKING Compiler */
  87. #define __INLINE inline /*!< inline keyword for TASKING Compiler */
  88. #define __STATIC_INLINE static inline
  89. #elif defined ( __CSMC__ )
  90. #define __packed
  91. #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
  92. #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
  93. #define __STATIC_INLINE static inline
  94. #else
  95. #error Unknown compiler
  96. #endif
  97. /** __FPU_USED indicates whether an FPU is used or not.
  98. This core does not support an FPU at all
  99. */
  100. #define __FPU_USED 0U
  101. #if defined ( __CC_ARM )
  102. #if defined __TARGET_FPU_VFP
  103. #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  104. #endif
  105. #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  106. #if defined __ARM_PCS_VFP
  107. #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  108. #endif
  109. #elif defined ( __GNUC__ )
  110. #if defined (__VFP_FP__) && !defined(__SOFTFP__)
  111. #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  112. #endif
  113. #elif defined ( __ICCARM__ )
  114. #if defined __ARMVFP__
  115. #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  116. #endif
  117. #elif defined ( __TMS470__ )
  118. #if defined __TI_VFP_SUPPORT__
  119. #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  120. #endif
  121. #elif defined ( __TASKING__ )
  122. #if defined __FPU_VFP__
  123. #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  124. #endif
  125. #elif defined ( __CSMC__ )
  126. #if ( __CSMC__ & 0x400U)
  127. #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  128. #endif
  129. #endif
  130. #include "core_cmInstr.h" /* Core Instruction Access */
  131. #include "core_cmFunc.h" /* Core Function Access */
  132. #ifdef __cplusplus
  133. }
  134. #endif
  135. #endif /* __CORE_CM0_H_GENERIC */
  136. #ifndef __CMSIS_GENERIC
  137. #ifndef __CORE_CM0_H_DEPENDANT
  138. #define __CORE_CM0_H_DEPENDANT
  139. #ifdef __cplusplus
  140. extern "C" {
  141. #endif
  142. /* check device defines and use defaults */
  143. #if defined __CHECK_DEVICE_DEFINES
  144. #ifndef __CM0_REV
  145. #define __CM0_REV 0x0000U
  146. #warning "__CM0_REV not defined in device header file; using default!"
  147. #endif
  148. #ifndef __NVIC_PRIO_BITS
  149. #define __NVIC_PRIO_BITS 2U
  150. #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
  151. #endif
  152. #ifndef __Vendor_SysTickConfig
  153. #define __Vendor_SysTickConfig 0U
  154. #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
  155. #endif
  156. #endif
  157. /* IO definitions (access restrictions to peripheral registers) */
  158. /**
  159. \defgroup CMSIS_glob_defs CMSIS Global Defines
  160. <strong>IO Type Qualifiers</strong> are used
  161. \li to specify the access to peripheral variables.
  162. \li for automatic generation of peripheral register debug information.
  163. */
  164. #ifdef __cplusplus
  165. #define __I volatile /*!< Defines 'read only' permissions */
  166. #else
  167. #define __I volatile const /*!< Defines 'read only' permissions */
  168. #endif
  169. #define __O volatile /*!< Defines 'write only' permissions */
  170. #define __IO volatile /*!< Defines 'read / write' permissions */
  171. /* following defines should be used for structure members */
  172. #define __IM volatile const /*! Defines 'read only' structure member permissions */
  173. #define __OM volatile /*! Defines 'write only' structure member permissions */
  174. #define __IOM volatile /*! Defines 'read / write' structure member permissions */
  175. /*@} end of group Cortex_M0 */
  176. /*******************************************************************************
  177. * Register Abstraction
  178. Core Register contain:
  179. - Core Register
  180. - Core NVIC Register
  181. - Core SCB Register
  182. - Core SysTick Register
  183. ******************************************************************************/
  184. /**
  185. \defgroup CMSIS_core_register Defines and Type Definitions
  186. \brief Type definitions and defines for Cortex-M processor based devices.
  187. */
  188. /**
  189. \ingroup CMSIS_core_register
  190. \defgroup CMSIS_CORE Status and Control Registers
  191. \brief Core Register type definitions.
  192. @{
  193. */
  194. /**
  195. \brief Union type to access the Application Program Status Register (APSR).
  196. */
  197. typedef union
  198. {
  199. struct
  200. {
  201. uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
  202. uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
  203. uint32_t C:1; /*!< bit: 29 Carry condition code flag */
  204. uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
  205. uint32_t N:1; /*!< bit: 31 Negative condition code flag */
  206. } b; /*!< Structure used for bit access */
  207. uint32_t w; /*!< Type used for word access */
  208. } APSR_Type;
  209. /* APSR Register Definitions */
  210. #define APSR_N_Pos 31U /*!< APSR: N Position */
  211. #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
  212. #define APSR_Z_Pos 30U /*!< APSR: Z Position */
  213. #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
  214. #define APSR_C_Pos 29U /*!< APSR: C Position */
  215. #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
  216. #define APSR_V_Pos 28U /*!< APSR: V Position */
  217. #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
  218. /**
  219. \brief Union type to access the Interrupt Program Status Register (IPSR).
  220. */
  221. typedef union
  222. {
  223. struct
  224. {
  225. uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
  226. uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
  227. } b; /*!< Structure used for bit access */
  228. uint32_t w; /*!< Type used for word access */
  229. } IPSR_Type;
  230. /* IPSR Register Definitions */
  231. #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
  232. #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
  233. /**
  234. \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
  235. */
  236. typedef union
  237. {
  238. struct
  239. {
  240. uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
  241. uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
  242. uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
  243. uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
  244. uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
  245. uint32_t C:1; /*!< bit: 29 Carry condition code flag */
  246. uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
  247. uint32_t N:1; /*!< bit: 31 Negative condition code flag */
  248. } b; /*!< Structure used for bit access */
  249. uint32_t w; /*!< Type used for word access */
  250. } xPSR_Type;
  251. /* xPSR Register Definitions */
  252. #define xPSR_N_Pos 31U /*!< xPSR: N Position */
  253. #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
  254. #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
  255. #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
  256. #define xPSR_C_Pos 29U /*!< xPSR: C Position */
  257. #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
  258. #define xPSR_V_Pos 28U /*!< xPSR: V Position */
  259. #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
  260. #define xPSR_T_Pos 24U /*!< xPSR: T Position */
  261. #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
  262. #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
  263. #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
  264. /**
  265. \brief Union type to access the Control Registers (CONTROL).
  266. */
  267. typedef union
  268. {
  269. struct
  270. {
  271. uint32_t _reserved0:1; /*!< bit: 0 Reserved */
  272. uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
  273. uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
  274. } b; /*!< Structure used for bit access */
  275. uint32_t w; /*!< Type used for word access */
  276. } CONTROL_Type;
  277. /* CONTROL Register Definitions */
  278. #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
  279. #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
  280. /*@} end of group CMSIS_CORE */
  281. /**
  282. \ingroup CMSIS_core_register
  283. \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
  284. \brief Type definitions for the NVIC Registers
  285. @{
  286. */
  287. /**
  288. \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
  289. */
  290. typedef struct
  291. {
  292. __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
  293. uint32_t RESERVED0[31U];
  294. __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
  295. uint32_t RSERVED1[31U];
  296. __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
  297. uint32_t RESERVED2[31U];
  298. __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
  299. uint32_t RESERVED3[31U];
  300. uint32_t RESERVED4[64U];
  301. __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
  302. } NVIC_Type;
  303. /*@} end of group CMSIS_NVIC */
  304. /**
  305. \ingroup CMSIS_core_register
  306. \defgroup CMSIS_SCB System Control Block (SCB)
  307. \brief Type definitions for the System Control Block Registers
  308. @{
  309. */
  310. /**
  311. \brief Structure type to access the System Control Block (SCB).
  312. */
  313. typedef struct
  314. {
  315. __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
  316. __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
  317. uint32_t RESERVED0;
  318. __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
  319. __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
  320. __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
  321. uint32_t RESERVED1;
  322. __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
  323. __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
  324. } SCB_Type;
  325. /* SCB CPUID Register Definitions */
  326. #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
  327. #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
  328. #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
  329. #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
  330. #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
  331. #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
  332. #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
  333. #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
  334. #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
  335. #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
  336. /* SCB Interrupt Control State Register Definitions */
  337. #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
  338. #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
  339. #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
  340. #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
  341. #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
  342. #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
  343. #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
  344. #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
  345. #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
  346. #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
  347. #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
  348. #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
  349. #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
  350. #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
  351. #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
  352. #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
  353. #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
  354. #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
  355. /* SCB Application Interrupt and Reset Control Register Definitions */
  356. #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
  357. #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
  358. #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
  359. #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
  360. #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
  361. #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
  362. #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
  363. #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
  364. #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
  365. #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
  366. /* SCB System Control Register Definitions */
  367. #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
  368. #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
  369. #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
  370. #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
  371. #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
  372. #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
  373. /* SCB Configuration Control Register Definitions */
  374. #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
  375. #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
  376. #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
  377. #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
  378. /* SCB System Handler Control and State Register Definitions */
  379. #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
  380. #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
  381. /*@} end of group CMSIS_SCB */
  382. /**
  383. \ingroup CMSIS_core_register
  384. \defgroup CMSIS_SysTick System Tick Timer (SysTick)
  385. \brief Type definitions for the System Timer Registers.
  386. @{
  387. */
  388. /**
  389. \brief Structure type to access the System Timer (SysTick).
  390. */
  391. typedef struct
  392. {
  393. __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
  394. __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
  395. __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
  396. __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
  397. } SysTick_Type;
  398. /* SysTick Control / Status Register Definitions */
  399. #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
  400. #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
  401. #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
  402. #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
  403. #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
  404. #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
  405. #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
  406. #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
  407. /* SysTick Reload Register Definitions */
  408. #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
  409. #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
  410. /* SysTick Current Register Definitions */
  411. #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
  412. #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
  413. /* SysTick Calibration Register Definitions */
  414. #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
  415. #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
  416. #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
  417. #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
  418. #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
  419. #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
  420. /*@} end of group CMSIS_SysTick */
  421. /**
  422. \ingroup CMSIS_core_register
  423. \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
  424. \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
  425. Therefore they are not covered by the Cortex-M0 header file.
  426. @{
  427. */
  428. /*@} end of group CMSIS_CoreDebug */
  429. /**
  430. \ingroup CMSIS_core_register
  431. \defgroup CMSIS_core_bitfield Core register bit field macros
  432. \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
  433. @{
  434. */
  435. /**
  436. \brief Mask and shift a bit field value for use in a register bit range.
  437. \param[in] field Name of the register bit field.
  438. \param[in] value Value of the bit field.
  439. \return Masked and shifted value.
  440. */
  441. #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
  442. /**
  443. \brief Mask and shift a register value to extract a bit filed value.
  444. \param[in] field Name of the register bit field.
  445. \param[in] value Value of register.
  446. \return Masked and shifted bit field value.
  447. */
  448. #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
  449. /*@} end of group CMSIS_core_bitfield */
  450. /**
  451. \ingroup CMSIS_core_register
  452. \defgroup CMSIS_core_base Core Definitions
  453. \brief Definitions for base addresses, unions, and structures.
  454. @{
  455. */
  456. /* Memory mapping of Cortex-M0 Hardware */
  457. #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
  458. #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
  459. #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
  460. #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
  461. #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
  462. #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
  463. #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
  464. /*@} */
  465. /*******************************************************************************
  466. * Hardware Abstraction Layer
  467. Core Function Interface contains:
  468. - Core NVIC Functions
  469. - Core SysTick Functions
  470. - Core Register Access Functions
  471. ******************************************************************************/
  472. /**
  473. \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
  474. */
  475. /* ########################## NVIC functions #################################### */
  476. /**
  477. \ingroup CMSIS_Core_FunctionInterface
  478. \defgroup CMSIS_Core_NVICFunctions NVIC Functions
  479. \brief Functions that manage interrupts and exceptions via the NVIC.
  480. @{
  481. */
  482. /* Interrupt Priorities are WORD accessible only under ARMv6M */
  483. /* The following MACROS handle generation of the register offset and byte masks */
  484. #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
  485. #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
  486. #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
  487. /**
  488. \brief Enable External Interrupt
  489. \details Enables a device-specific interrupt in the NVIC interrupt controller.
  490. \param [in] IRQn External interrupt number. Value cannot be negative.
  491. */
  492. __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
  493. {
  494. NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
  495. }
  496. /**
  497. \brief Disable External Interrupt
  498. \details Disables a device-specific interrupt in the NVIC interrupt controller.
  499. \param [in] IRQn External interrupt number. Value cannot be negative.
  500. */
  501. __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
  502. {
  503. NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
  504. }
  505. /**
  506. \brief Get Pending Interrupt
  507. \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
  508. \param [in] IRQn Interrupt number.
  509. \return 0 Interrupt status is not pending.
  510. \return 1 Interrupt status is pending.
  511. */
  512. __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
  513. {
  514. return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
  515. }
  516. /**
  517. \brief Set Pending Interrupt
  518. \details Sets the pending bit of an external interrupt.
  519. \param [in] IRQn Interrupt number. Value cannot be negative.
  520. */
  521. __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
  522. {
  523. NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
  524. }
  525. /**
  526. \brief Clear Pending Interrupt
  527. \details Clears the pending bit of an external interrupt.
  528. \param [in] IRQn External interrupt number. Value cannot be negative.
  529. */
  530. __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
  531. {
  532. NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
  533. }
  534. /**
  535. \brief Set Interrupt Priority
  536. \details Sets the priority of an interrupt.
  537. \note The priority cannot be set for every core interrupt.
  538. \param [in] IRQn Interrupt number.
  539. \param [in] priority Priority to set.
  540. */
  541. __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
  542. {
  543. if ((int32_t)(IRQn) < 0)
  544. {
  545. SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
  546. (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  547. }
  548. else
  549. {
  550. NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
  551. (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  552. }
  553. }
  554. /**
  555. \brief Get Interrupt Priority
  556. \details Reads the priority of an interrupt.
  557. The interrupt number can be positive to specify an external (device specific) interrupt,
  558. or negative to specify an internal (core) interrupt.
  559. \param [in] IRQn Interrupt number.
  560. \return Interrupt Priority.
  561. Value is aligned automatically to the implemented priority bits of the microcontroller.
  562. */
  563. __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
  564. {
  565. if ((int32_t)(IRQn) < 0)
  566. {
  567. return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
  568. }
  569. else
  570. {
  571. return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
  572. }
  573. }
  574. /**
  575. \brief System Reset
  576. \details Initiates a system reset request to reset the MCU.
  577. */
  578. __STATIC_INLINE void NVIC_SystemReset(void)
  579. {
  580. __DSB(); /* Ensure all outstanding memory accesses included
  581. buffered write are completed before reset */
  582. SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
  583. SCB_AIRCR_SYSRESETREQ_Msk);
  584. __DSB(); /* Ensure completion of memory access */
  585. for(;;) /* wait until reset */
  586. {
  587. __NOP();
  588. }
  589. }
  590. /*@} end of CMSIS_Core_NVICFunctions */
  591. /* ################################## SysTick function ############################################ */
  592. /**
  593. \ingroup CMSIS_Core_FunctionInterface
  594. \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
  595. \brief Functions that configure the System.
  596. @{
  597. */
  598. #if (__Vendor_SysTickConfig == 0U)
  599. /**
  600. \brief System Tick Configuration
  601. \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
  602. Counter is in free running mode to generate periodic interrupts.
  603. \param [in] ticks Number of ticks between two interrupts.
  604. \return 0 Function succeeded.
  605. \return 1 Function failed.
  606. \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
  607. function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
  608. must contain a vendor-specific implementation of this function.
  609. */
  610. __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
  611. {
  612. if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
  613. {
  614. return (1UL); /* Reload value impossible */
  615. }
  616. SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
  617. NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
  618. SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
  619. SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
  620. SysTick_CTRL_TICKINT_Msk |
  621. SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
  622. return (0UL); /* Function successful */
  623. }
  624. #endif
  625. /*@} end of CMSIS_Core_SysTickFunctions */
  626. #ifdef __cplusplus
  627. }
  628. #endif
  629. #endif /* __CORE_CM0_H_DEPENDANT */
  630. #endif /* __CMSIS_GENERIC */