system_stm32f0xx.c 13 KB

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  1. /**
  2. ******************************************************************************
  3. * @file system_stm32f0xx.c
  4. * @author MCD Application Team
  5. * @version V2.3.1
  6. * @date 04-November-2016
  7. * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
  8. *
  9. * 1. This file provides two functions and one global variable to be called from
  10. * user application:
  11. * - SystemInit(): This function is called at startup just after reset and
  12. * before branch to main program. This call is made inside
  13. * the "startup_stm32f0xx.s" file.
  14. *
  15. * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  16. * by the user application to setup the SysTick
  17. * timer or configure other parameters.
  18. *
  19. * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  20. * be called whenever the core clock is changed
  21. * during program execution.
  22. *
  23. * 2. After each device reset the HSI (8 MHz) is used as system clock source.
  24. * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
  25. * configure the system clock before to branch to main program.
  26. *
  27. * 3. This file configures the system clock as follows:
  28. *=============================================================================
  29. * Supported STM32F0xx device
  30. *-----------------------------------------------------------------------------
  31. * System Clock source | HSI
  32. *-----------------------------------------------------------------------------
  33. * SYSCLK(Hz) | 8000000
  34. *-----------------------------------------------------------------------------
  35. * HCLK(Hz) | 8000000
  36. *-----------------------------------------------------------------------------
  37. * AHB Prescaler | 1
  38. *-----------------------------------------------------------------------------
  39. * APB1 Prescaler | 1
  40. *-----------------------------------------------------------------------------
  41. *=============================================================================
  42. ******************************************************************************
  43. * @attention
  44. *
  45. * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  46. *
  47. * Redistribution and use in source and binary forms, with or without modification,
  48. * are permitted provided that the following conditions are met:
  49. * 1. Redistributions of source code must retain the above copyright notice,
  50. * this list of conditions and the following disclaimer.
  51. * 2. Redistributions in binary form must reproduce the above copyright notice,
  52. * this list of conditions and the following disclaimer in the documentation
  53. * and/or other materials provided with the distribution.
  54. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  55. * may be used to endorse or promote products derived from this software
  56. * without specific prior written permission.
  57. *
  58. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  59. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  60. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  61. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  62. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  63. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  64. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  65. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  66. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  67. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  68. *
  69. ******************************************************************************
  70. */
  71. /** @addtogroup CMSIS
  72. * @{
  73. */
  74. /** @addtogroup stm32f0xx_system
  75. * @{
  76. */
  77. /** @addtogroup STM32F0xx_System_Private_Includes
  78. * @{
  79. */
  80. #include "stm32f0xx.h"
  81. /**
  82. * @}
  83. */
  84. /** @addtogroup STM32F0xx_System_Private_TypesDefinitions
  85. * @{
  86. */
  87. /**
  88. * @}
  89. */
  90. /** @addtogroup STM32F0xx_System_Private_Defines
  91. * @{
  92. */
  93. #if !defined (HSE_VALUE)
  94. #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
  95. This value can be provided and adapted by the user application. */
  96. #endif /* HSE_VALUE */
  97. #if !defined (HSI_VALUE)
  98. #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
  99. This value can be provided and adapted by the user application. */
  100. #endif /* HSI_VALUE */
  101. #if !defined (HSI48_VALUE)
  102. #define HSI48_VALUE ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz.
  103. This value can be provided and adapted by the user application. */
  104. #endif /* HSI48_VALUE */
  105. /**
  106. * @}
  107. */
  108. /** @addtogroup STM32F0xx_System_Private_Macros
  109. * @{
  110. */
  111. /**
  112. * @}
  113. */
  114. /** @addtogroup STM32F0xx_System_Private_Variables
  115. * @{
  116. */
  117. /* This variable is updated in three ways:
  118. 1) by calling CMSIS function SystemCoreClockUpdate()
  119. 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
  120. 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
  121. Note: If you use this function to configure the system clock there is no need to
  122. call the 2 first functions listed above, since SystemCoreClock variable is
  123. updated automatically.
  124. */
  125. uint32_t SystemCoreClock = 8000000;
  126. const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
  127. const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
  128. /**
  129. * @}
  130. */
  131. /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
  132. * @{
  133. */
  134. /**
  135. * @}
  136. */
  137. /** @addtogroup STM32F0xx_System_Private_Functions
  138. * @{
  139. */
  140. /**
  141. * @brief Setup the microcontroller system.
  142. * Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
  143. * @param None
  144. * @retval None
  145. */
  146. void SystemInit(void)
  147. {
  148. /* Reset the RCC clock configuration to the default reset state ------------*/
  149. /* Set HSION bit */
  150. RCC->CR |= (uint32_t)0x00000001U;
  151. #if defined (STM32F051x8) || defined (STM32F058x8)
  152. /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
  153. RCC->CFGR &= (uint32_t)0xF8FFB80CU;
  154. #else
  155. /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
  156. RCC->CFGR &= (uint32_t)0x08FFB80CU;
  157. #endif /* STM32F051x8 or STM32F058x8 */
  158. /* Reset HSEON, CSSON and PLLON bits */
  159. RCC->CR &= (uint32_t)0xFEF6FFFFU;
  160. /* Reset HSEBYP bit */
  161. RCC->CR &= (uint32_t)0xFFFBFFFFU;
  162. /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
  163. RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
  164. /* Reset PREDIV[3:0] bits */
  165. RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
  166. #if defined (STM32F072xB) || defined (STM32F078xx)
  167. /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
  168. RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
  169. #elif defined (STM32F071xB)
  170. /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
  171. RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
  172. #elif defined (STM32F091xC) || defined (STM32F098xx)
  173. /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
  174. RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
  175. #elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
  176. /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
  177. RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
  178. #elif defined (STM32F051x8) || defined (STM32F058xx)
  179. /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
  180. RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
  181. #elif defined (STM32F042x6) || defined (STM32F048xx)
  182. /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
  183. RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
  184. #elif defined (STM32F070x6) || defined (STM32F070xB)
  185. /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
  186. RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
  187. /* Set default USB clock to PLLCLK, since there is no HSI48 */
  188. RCC->CFGR3 |= (uint32_t)0x00000080U;
  189. #else
  190. #warning "No target selected"
  191. #endif
  192. /* Reset HSI14 bit */
  193. RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
  194. /* Disable all interrupts */
  195. RCC->CIR = 0x00000000U;
  196. }
  197. /**
  198. * @brief Update SystemCoreClock variable according to Clock Register Values.
  199. * The SystemCoreClock variable contains the core clock (HCLK), it can
  200. * be used by the user application to setup the SysTick timer or configure
  201. * other parameters.
  202. *
  203. * @note Each time the core clock (HCLK) changes, this function must be called
  204. * to update SystemCoreClock variable value. Otherwise, any configuration
  205. * based on this variable will be incorrect.
  206. *
  207. * @note - The system frequency computed by this function is not the real
  208. * frequency in the chip. It is calculated based on the predefined
  209. * constant and the selected clock source:
  210. *
  211. * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
  212. *
  213. * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
  214. *
  215. * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
  216. * or HSI_VALUE(*) multiplied/divided by the PLL factors.
  217. *
  218. * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
  219. * 8 MHz) but the real value may vary depending on the variations
  220. * in voltage and temperature.
  221. *
  222. * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
  223. * 8 MHz), user has to ensure that HSE_VALUE is same as the real
  224. * frequency of the crystal used. Otherwise, this function may
  225. * have wrong result.
  226. *
  227. * - The result of this function could be not correct when using fractional
  228. * value for HSE crystal.
  229. *
  230. * @param None
  231. * @retval None
  232. */
  233. void SystemCoreClockUpdate (void)
  234. {
  235. uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
  236. /* Get SYSCLK source -------------------------------------------------------*/
  237. tmp = RCC->CFGR & RCC_CFGR_SWS;
  238. switch (tmp)
  239. {
  240. case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
  241. SystemCoreClock = HSI_VALUE;
  242. break;
  243. case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
  244. SystemCoreClock = HSE_VALUE;
  245. break;
  246. case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
  247. /* Get PLL clock source and multiplication factor ----------------------*/
  248. pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
  249. pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
  250. pllmull = ( pllmull >> 18) + 2;
  251. predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
  252. if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
  253. {
  254. /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
  255. SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
  256. }
  257. #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
  258. else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
  259. {
  260. /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
  261. SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
  262. }
  263. #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
  264. else
  265. {
  266. #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
  267. || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
  268. || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
  269. /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
  270. SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
  271. #else
  272. /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
  273. SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
  274. #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
  275. STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
  276. STM32F091xC || STM32F098xx || STM32F030xC */
  277. }
  278. break;
  279. default: /* HSI used as system clock */
  280. SystemCoreClock = HSI_VALUE;
  281. break;
  282. }
  283. /* Compute HCLK clock frequency ----------------*/
  284. /* Get HCLK prescaler */
  285. tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
  286. /* HCLK clock frequency */
  287. SystemCoreClock >>= tmp;
  288. }
  289. /**
  290. * @}
  291. */
  292. /**
  293. * @}
  294. */
  295. /**
  296. * @}
  297. */
  298. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/