stm32f0xx_hal_pwr.c 18 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f0xx_hal_pwr.c
  4. * @author MCD Application Team
  5. * @version V1.5.0
  6. * @date 04-November-2016
  7. * @brief PWR HAL module driver.
  8. * This file provides firmware functions to manage the following
  9. * functionalities of the Power Controller (PWR) peripheral:
  10. * + Initialization/de-initialization function
  11. * + Peripheral Control function
  12. *
  13. @verbatim
  14. ******************************************************************************
  15. * @attention
  16. *
  17. * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  18. *
  19. * Redistribution and use in source and binary forms, with or without modification,
  20. * are permitted provided that the following conditions are met:
  21. * 1. Redistributions of source code must retain the above copyright notice,
  22. * this list of conditions and the following disclaimer.
  23. * 2. Redistributions in binary form must reproduce the above copyright notice,
  24. * this list of conditions and the following disclaimer in the documentation
  25. * and/or other materials provided with the distribution.
  26. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  27. * may be used to endorse or promote products derived from this software
  28. * without specific prior written permission.
  29. *
  30. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  31. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  32. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  33. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  34. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  35. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  36. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  37. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  38. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40. *
  41. ******************************************************************************
  42. */
  43. /* Includes ------------------------------------------------------------------*/
  44. #include "stm32f0xx_hal.h"
  45. /** @addtogroup STM32F0xx_HAL_Driver
  46. * @{
  47. */
  48. /** @defgroup PWR PWR
  49. * @brief PWR HAL module driver
  50. * @{
  51. */
  52. #ifdef HAL_PWR_MODULE_ENABLED
  53. /* Private typedef -----------------------------------------------------------*/
  54. /* Private define ------------------------------------------------------------*/
  55. /* Private macro -------------------------------------------------------------*/
  56. /* Private variables ---------------------------------------------------------*/
  57. /* Private function prototypes -----------------------------------------------*/
  58. /* Private functions ---------------------------------------------------------*/
  59. /** @defgroup PWR_Exported_Functions PWR Exported Functions
  60. * @{
  61. */
  62. /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
  63. * @brief Initialization and de-initialization functions
  64. *
  65. @verbatim
  66. ===============================================================================
  67. ##### Initialization and de-initialization functions #####
  68. ===============================================================================
  69. [..]
  70. After reset, the backup domain (RTC registers, RTC backup data
  71. registers) is protected against possible unwanted
  72. write accesses.
  73. To enable access to the RTC Domain and RTC registers, proceed as follows:
  74. (+) Enable the Power Controller (PWR) APB1 interface clock using the
  75. __HAL_RCC_PWR_CLK_ENABLE() macro.
  76. (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
  77. @endverbatim
  78. * @{
  79. */
  80. /**
  81. * @brief Deinitializes the PWR peripheral registers to their default reset values.
  82. * @retval None
  83. */
  84. void HAL_PWR_DeInit(void)
  85. {
  86. __HAL_RCC_PWR_FORCE_RESET();
  87. __HAL_RCC_PWR_RELEASE_RESET();
  88. }
  89. /**
  90. * @brief Enables access to the backup domain (RTC registers, RTC
  91. * backup data registers when present).
  92. * @note If the HSE divided by 32 is used as the RTC clock, the
  93. * Backup Domain Access should be kept enabled.
  94. * @retval None
  95. */
  96. void HAL_PWR_EnableBkUpAccess(void)
  97. {
  98. PWR->CR |= (uint32_t)PWR_CR_DBP;
  99. }
  100. /**
  101. * @brief Disables access to the backup domain (RTC registers, RTC
  102. * backup data registers when present).
  103. * @note If the HSE divided by 32 is used as the RTC clock, the
  104. * Backup Domain Access should be kept enabled.
  105. * @retval None
  106. */
  107. void HAL_PWR_DisableBkUpAccess(void)
  108. {
  109. PWR->CR &= ~((uint32_t)PWR_CR_DBP);
  110. }
  111. /**
  112. * @}
  113. */
  114. /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
  115. * @brief Low Power modes configuration functions
  116. *
  117. @verbatim
  118. ===============================================================================
  119. ##### Peripheral Control functions #####
  120. ===============================================================================
  121. *** WakeUp pin configuration ***
  122. ================================
  123. [..]
  124. (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
  125. forced in input pull down configuration and is active on rising edges.
  126. (+) There are two WakeUp pins, and up to eight Wakeup pins on STM32F07x & STM32F09x devices.
  127. (++)WakeUp Pin 1 on PA.00.
  128. (++)WakeUp Pin 2 on PC.13.
  129. (++)WakeUp Pin 3 on PE.06.(STM32F07x/STM32F09x)
  130. (++)WakeUp Pin 4 on PA.02.(STM32F07x/STM32F09x)
  131. (++)WakeUp Pin 5 on PC.05.(STM32F07x/STM32F09x)
  132. (++)WakeUp Pin 6 on PB.05.(STM32F07x/STM32F09x)
  133. (++)WakeUp Pin 7 on PB.15.(STM32F07x/STM32F09x)
  134. (++)WakeUp Pin 8 on PF.02.(STM32F07x/STM32F09x)
  135. *** Low Power modes configuration ***
  136. =====================================
  137. [..]
  138. The devices feature 3 low-power modes:
  139. (+) Sleep mode: Cortex-M0 core stopped, peripherals kept running.
  140. (+) Stop mode: all clocks are stopped, regulator running, regulator
  141. in low power mode
  142. (+) Standby mode: 1.2V domain powered off (mode not available on STM32F0x8 devices).
  143. *** Sleep mode ***
  144. ==================
  145. [..]
  146. (+) Entry:
  147. The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
  148. functions with
  149. (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
  150. (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
  151. (+) Exit:
  152. (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
  153. controller (NVIC) can wake up the device from Sleep mode.
  154. *** Stop mode ***
  155. =================
  156. [..]
  157. In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI,
  158. and the HSE RC oscillators are disabled. Internal SRAM and register contents
  159. are preserved.
  160. The voltage regulator can be configured either in normal or low-power mode.
  161. To minimize the consumption.
  162. (+) Entry:
  163. The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI )
  164. function with:
  165. (++) Main regulator ON.
  166. (++) Low Power regulator ON.
  167. (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction
  168. (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
  169. (+) Exit:
  170. (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
  171. (++) Some specific communication peripherals (CEC, USART, I2C) interrupts,
  172. when programmed in wakeup mode (the peripheral must be
  173. programmed in wakeup mode and the corresponding interrupt vector
  174. must be enabled in the NVIC)
  175. *** Standby mode ***
  176. ====================
  177. [..]
  178. The Standby mode allows to achieve the lowest power consumption. It is based
  179. on the Cortex-M0 deep sleep mode, with the voltage regulator disabled.
  180. The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and
  181. the HSE oscillator are also switched off. SRAM and register contents are lost
  182. except for the RTC registers, RTC backup registers and Standby circuitry.
  183. The voltage regulator is OFF.
  184. (+) Entry:
  185. (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
  186. (+) Exit:
  187. (++) WKUP pin rising edge, RTC alarm (Alarm A), RTC wakeup,
  188. tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
  189. *** Auto-wakeup (AWU) from low-power mode ***
  190. =============================================
  191. [..]
  192. The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
  193. Wakeup event, a tamper event, a time-stamp event, or a comparator event,
  194. without depending on an external interrupt (Auto-wakeup mode).
  195. (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
  196. (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
  197. configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
  198. (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
  199. is necessary to configure the RTC to detect the tamper or time stamp event using the
  200. HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions.
  201. (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
  202. configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() function.
  203. (+) Comparator auto-wakeup (AWU) from the Stop mode
  204. (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
  205. (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2)
  206. to be sensitive to to the selected edges (falling, rising or falling
  207. and rising) (Interrupt or Event modes) using the EXTI_Init() function.
  208. (+++) Configure the comparator to generate the event.
  209. @endverbatim
  210. * @{
  211. */
  212. /**
  213. * @brief Enables the WakeUp PINx functionality.
  214. * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
  215. * This parameter can be value of :
  216. * @ref PWREx_WakeUp_Pins
  217. * @retval None
  218. */
  219. void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
  220. {
  221. /* Check the parameters */
  222. assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
  223. /* Enable the EWUPx pin */
  224. SET_BIT(PWR->CSR, WakeUpPinx);
  225. }
  226. /**
  227. * @brief Disables the WakeUp PINx functionality.
  228. * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
  229. * This parameter can be values of :
  230. * @ref PWREx_WakeUp_Pins
  231. * @retval None
  232. */
  233. void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
  234. {
  235. /* Check the parameters */
  236. assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
  237. /* Disable the EWUPx pin */
  238. CLEAR_BIT(PWR->CSR, WakeUpPinx);
  239. }
  240. /**
  241. * @brief Enters Sleep mode.
  242. * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
  243. * @param Regulator: Specifies the regulator state in SLEEP mode.
  244. * On STM32F0 devices, this parameter is a dummy value and it is ignored
  245. * as regulator can't be modified in this mode. Parameter is kept for platform
  246. * compatibility.
  247. * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
  248. * When WFI entry is used, tick interrupt have to be disabled if not desired as
  249. * the interrupt wake up source.
  250. * This parameter can be one of the following values:
  251. * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
  252. * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
  253. * @retval None
  254. */
  255. void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
  256. {
  257. /* Check the parameters */
  258. assert_param(IS_PWR_REGULATOR(Regulator));
  259. assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
  260. /* Clear SLEEPDEEP bit of Cortex System Control Register */
  261. SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
  262. /* Select SLEEP mode entry -------------------------------------------------*/
  263. if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
  264. {
  265. /* Request Wait For Interrupt */
  266. __WFI();
  267. }
  268. else
  269. {
  270. /* Request Wait For Event */
  271. __SEV();
  272. __WFE();
  273. __WFE();
  274. }
  275. }
  276. /**
  277. * @brief Enters STOP mode.
  278. * @note In Stop mode, all I/O pins keep the same state as in Run mode.
  279. * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
  280. * the HSI RC oscillator is selected as system clock.
  281. * @note When the voltage regulator operates in low power mode, an additional
  282. * startup delay is incurred when waking up from Stop mode.
  283. * By keeping the internal regulator ON during Stop mode, the consumption
  284. * is higher although the startup time is reduced.
  285. * @param Regulator: Specifies the regulator state in STOP mode.
  286. * This parameter can be one of the following values:
  287. * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON
  288. * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON
  289. * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
  290. * This parameter can be one of the following values:
  291. * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction
  292. * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction
  293. * @retval None
  294. */
  295. void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
  296. {
  297. uint32_t tmpreg = 0;
  298. /* Check the parameters */
  299. assert_param(IS_PWR_REGULATOR(Regulator));
  300. assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
  301. /* Select the regulator state in STOP mode ---------------------------------*/
  302. tmpreg = PWR->CR;
  303. /* Clear PDDS and LPDS bits */
  304. tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
  305. /* Set LPDS bit according to Regulator value */
  306. tmpreg |= Regulator;
  307. /* Store the new value */
  308. PWR->CR = tmpreg;
  309. /* Set SLEEPDEEP bit of Cortex System Control Register */
  310. SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
  311. /* Select STOP mode entry --------------------------------------------------*/
  312. if(STOPEntry == PWR_STOPENTRY_WFI)
  313. {
  314. /* Request Wait For Interrupt */
  315. __WFI();
  316. }
  317. else
  318. {
  319. /* Request Wait For Event */
  320. __SEV();
  321. __WFE();
  322. __WFE();
  323. }
  324. /* Reset SLEEPDEEP bit of Cortex System Control Register */
  325. SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
  326. }
  327. /**
  328. * @brief Enters STANDBY mode.
  329. * @note In Standby mode, all I/O pins are high impedance except for:
  330. * - Reset pad (still available)
  331. * - RTC alternate function pins if configured for tamper, time-stamp, RTC
  332. * Alarm out, or RTC clock calibration out.
  333. * - WKUP pins if enabled.
  334. * STM32F0x8 devices, the Stop mode is available, but it is
  335. * aningless to distinguish between voltage regulator in Low power
  336. * mode and voltage regulator in Run mode because the regulator
  337. * not used and the core is supplied directly from an external source.
  338. * Consequently, the Standby mode is not available on those devices.
  339. * @retval None
  340. */
  341. void HAL_PWR_EnterSTANDBYMode(void)
  342. {
  343. /* Select STANDBY mode */
  344. PWR->CR |= (uint32_t)PWR_CR_PDDS;
  345. /* Set SLEEPDEEP bit of Cortex System Control Register */
  346. SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
  347. /* This option is used to ensure that store operations are completed */
  348. #if defined ( __CC_ARM)
  349. __force_stores();
  350. #endif
  351. /* Request Wait For Interrupt */
  352. __WFI();
  353. }
  354. /**
  355. * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
  356. * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
  357. * re-enters SLEEP mode when an interruption handling is over.
  358. * Setting this bit is useful when the processor is expected to run only on
  359. * interruptions handling.
  360. * @retval None
  361. */
  362. void HAL_PWR_EnableSleepOnExit(void)
  363. {
  364. /* Set SLEEPONEXIT bit of Cortex System Control Register */
  365. SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
  366. }
  367. /**
  368. * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
  369. * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
  370. * re-enters SLEEP mode when an interruption handling is over.
  371. * @retval None
  372. */
  373. void HAL_PWR_DisableSleepOnExit(void)
  374. {
  375. /* Clear SLEEPONEXIT bit of Cortex System Control Register */
  376. CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
  377. }
  378. /**
  379. * @brief Enables CORTEX M4 SEVONPEND bit.
  380. * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
  381. * WFE to wake up when an interrupt moves from inactive to pended.
  382. * @retval None
  383. */
  384. void HAL_PWR_EnableSEVOnPend(void)
  385. {
  386. /* Set SEVONPEND bit of Cortex System Control Register */
  387. SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
  388. }
  389. /**
  390. * @brief Disables CORTEX M4 SEVONPEND bit.
  391. * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
  392. * WFE to wake up when an interrupt moves from inactive to pended.
  393. * @retval None
  394. */
  395. void HAL_PWR_DisableSEVOnPend(void)
  396. {
  397. /* Clear SEVONPEND bit of Cortex System Control Register */
  398. CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
  399. }
  400. /**
  401. * @}
  402. */
  403. /**
  404. * @}
  405. */
  406. #endif /* HAL_PWR_MODULE_ENABLED */
  407. /**
  408. * @}
  409. */
  410. /**
  411. * @}
  412. */
  413. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/