STM32_Devel/FPGA/Test/_xmsgs/pn_parser.xmsgs

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<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/lusius/Devel/STM32_Devel/FPGA/Test/Test1sym.vhd&quot; into library work</arg>
</msg>

<msg type="error" file="ProjectMgmt" num="806" >&quot;<arg fmt="%s" index="1">/home/lusius/Devel/STM32_Devel/FPGA/Test/Test1sym.vhd</arg>&quot; Line <arg fmt="%d" index="2">50</arg>. <arg fmt="%s" index="3">Syntax error near &quot;if&quot;.</arg>
</msg>

<msg type="error" file="ProjectMgmt" num="806" >&quot;<arg fmt="%s" index="1">/home/lusius/Devel/STM32_Devel/FPGA/Test/Test1sym.vhd</arg>&quot; Line <arg fmt="%d" index="2">55</arg>. <arg fmt="%s" index="3">Syntax error near &quot;&lt;=&quot;.</arg>
</msg>

<msg type="error" file="ProjectMgmt" num="806" >&quot;<arg fmt="%s" index="1">/home/lusius/Devel/STM32_Devel/FPGA/Test/Test1sym.vhd</arg>&quot; Line <arg fmt="%d" index="2">58</arg>. <arg fmt="%s" index="3">Syntax error near &quot;process&quot;.</arg>
</msg>

<msg type="error" file="ProjectMgmt" num="806" >&quot;<arg fmt="%s" index="1">/home/lusius/Devel/STM32_Devel/FPGA/Test/Test1sym.vhd</arg>&quot; Line <arg fmt="%d" index="2">60</arg>. <arg fmt="%s" index="3">Syntax error near &quot;Behavioral&quot;.</arg>
</msg>

</messages>