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STM32_Devel
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FPGA
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step_driver_control
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count_test_summary.html

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  1. <HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
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  2. <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
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  3. <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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  4. <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
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  5. <TD ALIGN=CENTER COLSPAN='4'><B>count_test Project Status (07/19/2018 - 19:41:16)</B></TD></TR>
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  6. <TR ALIGN=LEFT>
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  7. <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
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  8. <TD>step_driver_control.xise</TD>
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  9. <TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
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  10. <TD> No Errors </TD>
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  11. </TR>
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  12. <TR ALIGN=LEFT>
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  13. <TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
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  14. <TD>count_test</TD>
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  15. <TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
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  16. <TD>Placed and Routed</TD>
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  17. </TR>
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  18. <TR ALIGN=LEFT>
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  19. <TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
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  20. <TD>xc6slx9-3tqg144</TD>
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  21. <TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
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  22. <TD>&nbsp;</TD>
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  23. </TR>
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  24. <TR ALIGN=LEFT>
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  25. <TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
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  26. <TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
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  27. <TD>&nbsp;</TD>
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  28. </TR>
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  29. <TR ALIGN=LEFT>
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  30. <TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
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  31. <TD>Balanced</TD>
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  32. <TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
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  33. <TD>
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  34. &nbsp;</TD>
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  35. </TR>
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  36. <TR ALIGN=LEFT>
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  37. <TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
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  38. <TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
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  39. <TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
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  40. <TD>&nbsp;</TD>
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  41. </TR>
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  42. <TR ALIGN=LEFT>
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  43. <TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
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  44. <TD>&nbsp;</TD>
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  45. <TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
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  46. <TD>&nbsp;&nbsp;</TD>
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  47. </TR>
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  48. </TABLE>
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  59. 

  60. &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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  61. <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
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  62. <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
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  63. <TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
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  64. <TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
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  65. <TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
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  66. <TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
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  67. <TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
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  68. <TR ALIGN=LEFT><TD>CPLD Fitter Report (Text)</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
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  69. <TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
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  70. <TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
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  71. <TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
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  72. </TABLE>
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  73. &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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  74. <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
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  75. <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
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  76. <TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/trurl/STM32_Devel/FPGA/CNC/step_driver_control/isim.log'>ISIM Simulator Log</A></TD><TD>Current</TD><TD COLSPAN='2'>Чт июля 19 19:45:08 2018</TD></TR>
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  77. <TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/trurl/STM32_Devel/FPGA/CNC/step_driver_control/usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Чт июля 19 17:26:12 2018</TD></TR>
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  78. <TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/trurl/STM32_Devel/FPGA/CNC/step_driver_control/webtalk.log'>WebTalk Log File</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Чт июля 19 17:26:13 2018</TD></TR>
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  79. </TABLE>
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  82. <br><center><b>Date Generated:</b> 07/19/2018 - 19:46:08</cent
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