halfway done

Project Outputs for BIAS_TGA2237-SM/Design Rule Check - PCB1.drc

@@ -1,9 +1,12 @@
 Protel Design System Design Rule Check
 PCB File : C:\Users\Vlad\Documents\BIAS_TGA2237-SM\PCB1.PcbDoc
-Date     : 23.07.2024
-Time     : 6:43:50
+Date     : 24.07.2024
+Time     : 8:18:32
 
-Processing Rule : Clearance Constraint (Gap=10mil) (All),(All)
+WARNING: Design contains shelved or modified (but not repoured) polygons. The result of DRC is not correct. Recommended to restore/repour all polygons and proceed with DRC again
+   Polygon named: NONET_L01_P000 In net GND On Top Layer
+
+Processing Rule : Clearance Constraint (Gap=0.254mm) (All),(All)
 Rule Violations :0
 
 Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
@@ -13,120 +16,133 @@ Processing Rule : Un-Routed Net Constraint ( (All) )
 Rule Violations :0
 
 Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
-Rule Violations :0
+   Violation between Modified Polygon: Polygon Shelved  (NONET_L01_P000) on Top Layer 
+Rule Violations :1
 
-Processing Rule : Width Constraint (Min=10mil) (Max=50mil) (Preferred=20mil) (All)
+Processing Rule : Width Constraint (Min=0.254mm) (Max=1.27mm) (Preferred=0.508mm) (All)
 Rule Violations :0
 
-Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
+Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
 Rule Violations :0
 
-Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (All)
+Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
 Rule Violations :0
 
-Processing Rule : Hole To Hole Clearance (Gap=10mil) (All),(All)
+Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
 Rule Violations :0
 
-Processing Rule : Minimum Solder Mask Sliver (Gap=10mil) (All),(All)
-Rule Violations :0
+Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
+   Violation between Minimum Solder Mask Sliver Constraint: (0.25mm < 0.254mm) Between Pad DD1-1(41.295mm,11.248mm) on Top Layer And Pad DD1-2(41.295mm,10.298mm) on Top Layer [Top Solder] Mask Sliver [0.25mm]
+   Violation between Minimum Solder Mask Sliver Constraint: (0.25mm < 0.254mm) Between Pad DD1-2(41.295mm,10.298mm) on Top Layer And Pad DD1-3(41.295mm,9.348mm) on Top Layer [Top Solder] Mask Sliver [0.25mm]
+Rule Violations :2
+
+Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C10-1(37.852mm,9.319mm) on Top Layer And Track (37.09mm,9.827mm)(37.09mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C10-1(37.852mm,9.319mm) on Top Layer And Track (37.09mm,9.827mm)(37.09mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.203mm < 0.254mm) Between Pad C10-1(37.852mm,9.319mm) on Top Layer And Track (38.608mm,9.89mm)(38.608mm,10.398mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.203mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C10-1(37.852mm,9.319mm) on Top Layer And Track (38.614mm,9.827mm)(38.614mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C10-2(37.852mm,10.906mm) on Top Layer And Track (37.09mm,9.827mm)(37.09mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C10-2(37.852mm,10.906mm) on Top Layer And Track (37.09mm,9.827mm)(37.09mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.185mm < 0.254mm) Between Pad C10-2(37.852mm,10.906mm) on Top Layer And Track (38.608mm,9.89mm)(38.608mm,10.398mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.185mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C10-2(37.852mm,10.906mm) on Top Layer And Track (38.614mm,9.827mm)(38.614mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C3-1(32.512mm,3.8mm) on Top Layer And Track (31.496mm,3.038mm)(32.004mm,3.038mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C3-1(32.512mm,3.8mm) on Top Layer And Track (31.496mm,4.562mm)(32.004mm,4.562mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C3-2(30.924mm,3.8mm) on Top Layer And Track (31.496mm,3.038mm)(32.004mm,3.038mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C3-2(30.924mm,3.8mm) on Top Layer And Track (31.496mm,4.562mm)(32.004mm,4.562mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C4-1(16.51mm,10.404mm) on Top Layer And Track (15.748mm,9.388mm)(15.748mm,9.896mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C4-1(16.51mm,10.404mm) on Top Layer And Track (17.272mm,9.388mm)(17.272mm,9.896mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C4-2(16.51mm,8.816mm) on Top Layer And Track (15.748mm,9.388mm)(15.748mm,9.896mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C4-2(16.51mm,8.816mm) on Top Layer And Track (17.272mm,9.388mm)(17.272mm,9.896mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C7-1(19.558mm,5.07mm) on Top Layer And Track (18.796mm,4.054mm)(18.796mm,4.562mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C7-1(19.558mm,5.07mm) on Top Layer And Track (20.32mm,4.054mm)(20.32mm,4.562mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C7-2(19.558mm,3.482mm) on Top Layer And Track (18.796mm,4.054mm)(18.796mm,4.562mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C7-2(19.558mm,3.482mm) on Top Layer And Track (20.32mm,4.054mm)(20.32mm,4.562mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C8-1(34.804mm,9.319mm) on Top Layer And Track (34.042mm,9.827mm)(34.042mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C8-1(34.804mm,9.319mm) on Top Layer And Track (35.566mm,9.827mm)(35.566mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C8-1(34.804mm,9.319mm) on Top Layer And Track (35.566mm,9.827mm)(35.566mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C8-2(34.804mm,10.906mm) on Top Layer And Track (34.042mm,9.827mm)(34.042mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C8-2(34.804mm,10.906mm) on Top Layer And Track (35.566mm,9.827mm)(35.566mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C8-2(34.804mm,10.906mm) on Top Layer And Track (35.566mm,9.827mm)(35.566mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C9-1(36.328mm,9.319mm) on Top Layer And Track (35.566mm,9.827mm)(35.566mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C9-1(36.328mm,9.319mm) on Top Layer And Track (35.566mm,9.827mm)(35.566mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C9-1(36.328mm,9.319mm) on Top Layer And Track (37.09mm,9.827mm)(37.09mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad C9-1(36.328mm,9.319mm) on Top Layer And Track (37.09mm,9.827mm)(37.09mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C9-2(36.328mm,10.906mm) on Top Layer And Track (35.566mm,9.827mm)(35.566mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C9-2(36.328mm,10.906mm) on Top Layer And Track (35.566mm,9.827mm)(35.566mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C9-2(36.328mm,10.906mm) on Top Layer And Track (37.09mm,9.827mm)(37.09mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad C9-2(36.328mm,10.906mm) on Top Layer And Track (37.09mm,9.827mm)(37.09mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-1(9.226mm,7.229mm) on Top Layer And Track (10.338mm,2.874mm)(10.338mm,7.774mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-1(9.226mm,7.229mm) on Top Layer And Track (8.463mm,7.904mm)(9.988mm,7.904mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-2(9.226mm,5.959mm) on Top Layer And Track (10.338mm,2.874mm)(10.338mm,7.774mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-3(9.226mm,4.689mm) on Top Layer And Track (10.338mm,2.874mm)(10.338mm,7.774mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-4(9.226mm,3.419mm) on Top Layer And Track (10.338mm,2.874mm)(10.338mm,7.774mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-5(14.65mm,3.419mm) on Top Layer And Track (13.538mm,2.874mm)(13.538mm,7.774mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-6(14.65mm,4.689mm) on Top Layer And Track (13.538mm,2.874mm)(13.538mm,7.774mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-7(14.65mm,5.959mm) on Top Layer And Track (13.538mm,2.874mm)(13.538mm,7.774mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA1-8(14.65mm,7.229mm) on Top Layer And Track (13.538mm,2.874mm)(13.538mm,7.774mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.229mm < 0.254mm) Between Pad DA2-1(23.45mm,7.483mm) on Top Layer And Track (22.352mm,6.53mm)(22.352mm,7.038mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.229mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA2-1(23.45mm,7.483mm) on Top Layer And Track (22.687mm,8.158mm)(24.212mm,8.158mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA2-1(23.45mm,7.483mm) on Top Layer And Track (24.562mm,3.128mm)(24.562mm,8.028mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad DA2-2(23.45mm,6.213mm) on Top Layer And Track (22.352mm,6.53mm)(22.352mm,7.038mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA2-2(23.45mm,6.213mm) on Top Layer And Track (24.562mm,3.128mm)(24.562mm,8.028mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA2-3(23.45mm,4.943mm) on Top Layer And Track (24.562mm,3.128mm)(24.562mm,8.028mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA2-4(23.45mm,3.673mm) on Top Layer And Track (24.562mm,3.128mm)(24.562mm,8.028mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA2-5(28.874mm,3.673mm) on Top Layer And Track (27.762mm,3.128mm)(27.762mm,8.028mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA2-6(28.874mm,4.943mm) on Top Layer And Track (27.762mm,3.128mm)(27.762mm,8.028mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA2-7(28.874mm,6.213mm) on Top Layer And Track (27.762mm,3.128mm)(27.762mm,8.028mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad DA2-8(28.874mm,7.483mm) on Top Layer And Track (27.762mm,3.128mm)(27.762mm,8.028mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R1-1(39.37mm,9.382mm) on Top Layer And Track (38.608mm,9.89mm)(38.608mm,10.398mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.179mm < 0.254mm) Between Pad R1-1(39.37mm,9.382mm) on Top Layer And Track (38.614mm,9.827mm)(38.614mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.179mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R1-1(39.37mm,9.382mm) on Top Layer And Track (40.132mm,9.89mm)(40.132mm,10.398mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R1-2(39.37mm,10.97mm) on Top Layer And Track (38.608mm,9.89mm)(38.608mm,10.398mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.231mm < 0.254mm) Between Pad R1-2(39.37mm,10.97mm) on Top Layer And Track (38.614mm,9.827mm)(38.614mm,10.335mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.231mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R1-2(39.37mm,10.97mm) on Top Layer And Track (40.132mm,9.89mm)(40.132mm,10.398mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R2-1(30.861mm,10.023mm) on Top Layer And Track (31.369mm,10.785mm)(31.877mm,10.785mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R2-1(30.861mm,10.023mm) on Top Layer And Track (31.369mm,9.261mm)(31.877mm,9.261mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R2-2(32.449mm,10.023mm) on Top Layer And Track (31.369mm,10.785mm)(31.877mm,10.785mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R2-2(32.449mm,10.023mm) on Top Layer And Track (31.369mm,9.261mm)(31.877mm,9.261mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R3-1(7.303mm,9.388mm) on Top Layer And Track (7.811mm,10.15mm)(8.319mm,10.15mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R3-1(7.303mm,9.388mm) on Top Layer And Track (7.811mm,8.626mm)(8.319mm,8.626mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R3-2(8.89mm,9.388mm) on Top Layer And Track (7.811mm,10.15mm)(8.319mm,10.15mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R3-2(8.89mm,9.388mm) on Top Layer And Track (7.811mm,8.626mm)(8.319mm,8.626mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R4-1(27.178mm,10.023mm) on Top Layer And Track (27.686mm,10.785mm)(28.194mm,10.785mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R4-1(27.178mm,10.023mm) on Top Layer And Track (27.686mm,9.261mm)(28.194mm,9.261mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R4-2(28.765mm,10.023mm) on Top Layer And Track (27.686mm,10.785mm)(28.194mm,10.785mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R4-2(28.765mm,10.023mm) on Top Layer And Track (27.686mm,9.261mm)(28.194mm,9.261mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R5-1(18.542mm,8.816mm) on Top Layer And Track (17.78mm,9.324mm)(17.78mm,9.832mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R5-1(18.542mm,8.816mm) on Top Layer And Track (19.304mm,9.324mm)(19.304mm,9.832mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R5-2(18.542mm,10.404mm) on Top Layer And Track (17.78mm,9.324mm)(17.78mm,9.832mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R5-2(18.542mm,10.404mm) on Top Layer And Track (19.304mm,9.324mm)(19.304mm,9.832mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R6-1(30.988mm,6.34mm) on Top Layer And Track (30.226mm,6.848mm)(30.226mm,7.356mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R6-1(30.988mm,6.34mm) on Top Layer And Track (31.75mm,6.848mm)(31.75mm,7.356mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R6-2(30.988mm,7.927mm) on Top Layer And Track (30.226mm,6.848mm)(30.226mm,7.356mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R6-2(30.988mm,7.927mm) on Top Layer And Track (31.75mm,6.848mm)(31.75mm,7.356mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R7-1(21.59mm,6.022mm) on Top Layer And Track (20.828mm,6.53mm)(20.828mm,7.038mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.19mm < 0.254mm) Between Pad R7-1(21.59mm,6.022mm) on Top Layer And Track (22.352mm,6.53mm)(22.352mm,7.038mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.19mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R7-2(21.59mm,7.61mm) on Top Layer And Track (20.828mm,6.53mm)(20.828mm,7.038mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.208mm < 0.254mm) Between Pad R7-2(21.59mm,7.61mm) on Top Layer And Track (22.352mm,6.53mm)(22.352mm,7.038mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.208mm]
+Rule Violations :84
+
+Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All)
+   Violation between Silk To Silk Clearance Constraint: (0.216mm < 0.254mm) Between Text "C10" (37.473mm,8.143mm) on Top Overlay And Track (33.528mm,7.8mm)(38.608mm,7.8mm) on Top Overlay Silk Text to Silk Clearance [0.216mm]
+   Violation between Silk To Silk Clearance Constraint: (0.158mm < 0.254mm) Between Text "C7" (20.605mm,4.57mm) on Top Overlay And Track (20.32mm,4.054mm)(20.32mm,4.562mm) on Top Overlay Silk Text to Silk Clearance [0.158mm]
+   Violation between Silk To Silk Clearance Constraint: (0.216mm < 0.254mm) Between Text "C8" (34.53mm,8.143mm) on Top Overlay And Track (33.528mm,7.8mm)(38.608mm,7.8mm) on Top Overlay Silk Text to Silk Clearance [0.216mm]
+   Violation between Silk To Silk Clearance Constraint: (0.216mm < 0.254mm) Between Text "C9" (36.06mm,8.143mm) on Top Overlay And Track (33.528mm,7.8mm)(38.608mm,7.8mm) on Top Overlay Silk Text to Silk Clearance [0.216mm]
+   Violation between Silk To Silk Clearance Constraint: (0.221mm < 0.254mm) Between Text "R1" (39.125mm,8.143mm) on Top Overlay And Track (39.37mm,2.397mm)(39.37mm,7.795mm) on Top Overlay Silk Text to Silk Clearance [0.221mm]
+   Violation between Silk To Silk Clearance Constraint: (0.221mm < 0.254mm) Between Text "R1" (39.125mm,8.143mm) on Top Overlay And Track (39.37mm,7.795mm)(44.45mm,7.795mm) on Top Overlay Silk Text to Silk Clearance [0.221mm]
+   Violation between Silk To Silk Clearance Constraint: (0.158mm < 0.254mm) Between Text "R6" (32.035mm,7.392mm) on Top Overlay And Track (31.75mm,6.848mm)(31.75mm,7.356mm) on Top Overlay Silk Text to Silk Clearance [0.158mm]
+   Violation between Silk To Silk Clearance Constraint: (0.158mm < 0.254mm) Between Text "R7" (20.543mm,6.557mm) on Top Overlay And Track (20.828mm,6.53mm)(20.828mm,7.038mm) on Top Overlay Silk Text to Silk Clearance [0.158mm]
+   Violation between Silk To Silk Clearance Constraint: (0.235mm < 0.254mm) Between Text "XP2" (25.685mm,10.64mm) on Top Overlay And Track (25.4mm,8.626mm)(25.4mm,11.166mm) on Top Overlay Silk Text to Silk Clearance [0.235mm]
+   Violation between Silk To Silk Clearance Constraint: (0.235mm < 0.254mm) Between Text "XP3" (0.539mm,10.386mm) on Top Overlay And Track (1.27mm,8.626mm)(1.27mm,11.166mm) on Top Overlay Silk Text to Silk Clearance [0.235mm]
+Rule Violations :10
 
-Processing Rule : Silk To Solder Mask (Clearance=10mil) (IsPad),(All)
-   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C10-1(1490.217mil,327.5mil) on Top Layer And Track (1460.217mil,347.5mil)(1460.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C10-1(1490.217mil,327.5mil) on Top Layer And Track (1460.217mil,347.5mil)(1460.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C10-1(1490.217mil,327.5mil) on Top Layer And Track (1520.217mil,347.5mil)(1520.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C10-2(1490.217mil,390mil) on Top Layer And Track (1460.217mil,347.5mil)(1460.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C10-2(1490.217mil,390mil) on Top Layer And Track (1460.217mil,347.5mil)(1460.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C10-2(1490.217mil,390mil) on Top Layer And Track (1520.217mil,347.5mil)(1520.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C3-1(1280mil,110.217mil) on Top Layer And Track (1240mil,140.217mil)(1260mil,140.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C3-1(1280mil,110.217mil) on Top Layer And Track (1240mil,80.217mil)(1260mil,80.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C3-2(1217.5mil,110.217mil) on Top Layer And Track (1240mil,140.217mil)(1260mil,140.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C3-2(1217.5mil,110.217mil) on Top Layer And Track (1240mil,80.217mil)(1260mil,80.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C4-1(650mil,370.217mil) on Top Layer And Track (620mil,330.217mil)(620mil,350.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C4-1(650mil,370.217mil) on Top Layer And Track (680mil,330.217mil)(680mil,350.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C4-2(650mil,307.717mil) on Top Layer And Track (620mil,330.217mil)(620mil,350.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C4-2(650mil,307.717mil) on Top Layer And Track (680mil,330.217mil)(680mil,350.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C7-1(770mil,160.217mil) on Top Layer And Track (740mil,120.217mil)(740mil,140.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C7-1(770mil,160.217mil) on Top Layer And Track (800mil,120.217mil)(800mil,140.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C7-2(770mil,97.717mil) on Top Layer And Track (740mil,120.217mil)(740mil,140.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C7-2(770mil,97.717mil) on Top Layer And Track (800mil,120.217mil)(800mil,140.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C8-1(1370.217mil,327.5mil) on Top Layer And Track (1340.217mil,347.5mil)(1340.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C8-1(1370.217mil,327.5mil) on Top Layer And Track (1400.217mil,347.5mil)(1400.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C8-1(1370.217mil,327.5mil) on Top Layer And Track (1400.217mil,347.5mil)(1400.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C8-2(1370.217mil,390mil) on Top Layer And Track (1340.217mil,347.5mil)(1340.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C8-2(1370.217mil,390mil) on Top Layer And Track (1400.217mil,347.5mil)(1400.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C8-2(1370.217mil,390mil) on Top Layer And Track (1400.217mil,347.5mil)(1400.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C9-1(1430.217mil,327.5mil) on Top Layer And Track (1400.217mil,347.5mil)(1400.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C9-1(1430.217mil,327.5mil) on Top Layer And Track (1400.217mil,347.5mil)(1400.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C9-1(1430.217mil,327.5mil) on Top Layer And Track (1460.217mil,347.5mil)(1460.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad C9-1(1430.217mil,327.5mil) on Top Layer And Track (1460.217mil,347.5mil)(1460.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C9-2(1430.217mil,390mil) on Top Layer And Track (1400.217mil,347.5mil)(1400.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C9-2(1430.217mil,390mil) on Top Layer And Track (1400.217mil,347.5mil)(1400.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C9-2(1430.217mil,390mil) on Top Layer And Track (1460.217mil,347.5mil)(1460.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad C9-2(1430.217mil,390mil) on Top Layer And Track (1460.217mil,347.5mil)(1460.217mil,367.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (9.842mil < 10mil) Between Pad DA1-1(363.228mil,245.217mil) on Top Layer And Track (333.189mil,271.791mil)(393.228mil,271.791mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.842mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA1-1(363.228mil,245.217mil) on Top Layer And Track (407.008mil,73.76mil)(407.008mil,266.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA1-2(363.228mil,195.217mil) on Top Layer And Track (407.008mil,73.76mil)(407.008mil,266.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA1-3(363.228mil,145.217mil) on Top Layer And Track (407.008mil,73.76mil)(407.008mil,266.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA1-4(363.228mil,95.217mil) on Top Layer And Track (407.008mil,73.76mil)(407.008mil,266.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA1-5(576.772mil,95.217mil) on Top Layer And Track (532.992mil,73.76mil)(532.992mil,266.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA1-6(576.772mil,145.217mil) on Top Layer And Track (532.992mil,73.76mil)(532.992mil,266.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA1-7(576.772mil,195.217mil) on Top Layer And Track (532.992mil,73.76mil)(532.992mil,266.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA1-8(576.772mil,245.217mil) on Top Layer And Track (532.992mil,73.76mil)(532.992mil,266.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (9.021mil < 10mil) Between Pad DA2-1(923.228mil,255.217mil) on Top Layer And Track (880mil,217.717mil)(880mil,237.717mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.021mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (9.842mil < 10mil) Between Pad DA2-1(923.228mil,255.217mil) on Top Layer And Track (893.189mil,281.791mil)(953.228mil,281.791mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.842mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA2-1(923.228mil,255.217mil) on Top Layer And Track (967.008mil,83.76mil)(967.008mil,276.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.209mil < 10mil) Between Pad DA2-2(923.228mil,205.217mil) on Top Layer And Track (880mil,217.717mil)(880mil,237.717mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.209mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA2-2(923.228mil,205.217mil) on Top Layer And Track (967.008mil,83.76mil)(967.008mil,276.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA2-3(923.228mil,155.217mil) on Top Layer And Track (967.008mil,83.76mil)(967.008mil,276.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA2-4(923.228mil,105.217mil) on Top Layer And Track (967.008mil,83.76mil)(967.008mil,276.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA2-5(1136.772mil,105.217mil) on Top Layer And Track (1092.992mil,83.76mil)(1092.992mil,276.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA2-6(1136.772mil,155.217mil) on Top Layer And Track (1092.992mil,83.76mil)(1092.992mil,276.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA2-7(1136.772mil,205.217mil) on Top Layer And Track (1092.992mil,83.76mil)(1092.992mil,276.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (9.823mil < 10mil) Between Pad DA2-8(1136.772mil,255.217mil) on Top Layer And Track (1092.992mil,83.76mil)(1092.992mil,276.673mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.823mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad R1-1(1215mil,355.217mil) on Top Layer And Track (1235mil,325.217mil)(1255mil,325.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad R1-1(1215mil,355.217mil) on Top Layer And Track (1235mil,385.217mil)(1255mil,385.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad R1-2(1277.5mil,355.217mil) on Top Layer And Track (1235mil,325.217mil)(1255mil,325.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad R1-2(1277.5mil,355.217mil) on Top Layer And Track (1235mil,385.217mil)(1255mil,385.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad R2-1(287.5mil,330.217mil) on Top Layer And Track (307.5mil,300.217mil)(327.5mil,300.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad R2-1(287.5mil,330.217mil) on Top Layer And Track (307.5mil,360.217mil)(327.5mil,360.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad R2-2(350mil,330.217mil) on Top Layer And Track (307.5mil,300.217mil)(327.5mil,300.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad R2-2(350mil,330.217mil) on Top Layer And Track (307.5mil,360.217mil)(327.5mil,360.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad R3-1(1070mil,355.217mil) on Top Layer And Track (1090mil,325.217mil)(1110mil,325.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad R3-1(1070mil,355.217mil) on Top Layer And Track (1090mil,385.217mil)(1110mil,385.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad R3-2(1132.5mil,355.217mil) on Top Layer And Track (1090mil,325.217mil)(1110mil,325.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad R3-2(1132.5mil,355.217mil) on Top Layer And Track (1090mil,385.217mil)(1110mil,385.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad R4-1(730mil,307.717mil) on Top Layer And Track (700mil,327.717mil)(700mil,347.717mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad R4-1(730mil,307.717mil) on Top Layer And Track (760mil,327.717mil)(760mil,347.717mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad R4-2(730mil,370.217mil) on Top Layer And Track (700mil,327.717mil)(700mil,347.717mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad R4-2(730mil,370.217mil) on Top Layer And Track (760mil,327.717mil)(760mil,347.717mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad R5-1(1220mil,210.217mil) on Top Layer And Track (1190mil,230.217mil)(1190mil,250.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad R5-1(1220mil,210.217mil) on Top Layer And Track (1250mil,230.217mil)(1250mil,250.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad R5-2(1220mil,272.717mil) on Top Layer And Track (1190mil,230.217mil)(1190mil,250.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad R5-2(1220mil,272.717mil) on Top Layer And Track (1250mil,230.217mil)(1250mil,250.217mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad R6-1(850mil,197.717mil) on Top Layer And Track (820mil,217.717mil)(820mil,237.717mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (7.494mil < 10mil) Between Pad R6-1(850mil,197.717mil) on Top Layer And Track (880mil,217.717mil)(880mil,237.717mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.494mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad R6-2(850mil,260.217mil) on Top Layer And Track (820mil,217.717mil)(820mil,237.717mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
-   Violation between Silk To Solder Mask Clearance Constraint: (8.182mil < 10mil) Between Pad R6-2(850mil,260.217mil) on Top Layer And Track (880mil,217.717mil)(880mil,237.717mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.182mil]
-Rule Violations :76
-
-Processing Rule : Silk to Silk (Clearance=10mil) (All),(All)
-   Violation between Silk To Silk Clearance Constraint: (8.502mil < 10mil) Between Text "C10" (1475.3mil,281.219mil) on Top Overlay And Track (1320mil,267.717mil)(1520mil,267.717mil) on Top Overlay Silk Text to Silk Clearance [8.502mil]
-   Violation between Silk To Silk Clearance Constraint: (6.205mil < 10mil) Between Text "C7" (811.205mil,140.567mil) on Top Overlay And Track (800mil,120.217mil)(800mil,140.217mil) on Top Overlay Silk Text to Silk Clearance [6.205mil]
-   Violation between Silk To Silk Clearance Constraint: (8.502mil < 10mil) Between Text "C8" (1359.46mil,281.219mil) on Top Overlay And Track (1320mil,267.717mil)(1520mil,267.717mil) on Top Overlay Silk Text to Silk Clearance [8.502mil]
-   Violation between Silk To Silk Clearance Constraint: (8.502mil < 10mil) Between Text "C9" (1419.677mil,281.219mil) on Top Overlay And Track (1320mil,267.717mil)(1520mil,267.717mil) on Top Overlay Silk Text to Silk Clearance [8.502mil]
-   Violation between Silk To Silk Clearance Constraint: (6.219mil < 10mil) Between Text "R5" (1261.219mil,251.643mil) on Top Overlay And Track (1250mil,230.217mil)(1250mil,250.217mil) on Top Overlay Silk Text to Silk Clearance [6.219mil]
-   Violation between Silk To Silk Clearance Constraint: (6.219mil < 10mil) Between Text "R6" (808.781mil,218.79mil) on Top Overlay And Track (820mil,217.717mil)(820mil,237.717mil) on Top Overlay Silk Text to Silk Clearance [6.219mil]
-   Violation between Silk To Silk Clearance Constraint: (9.251mil < 10mil) Between Text "XP1" (1011.219mil,377.778mil) on Top Overlay And Track (1000mil,300.217mil)(1000mil,400.217mil) on Top Overlay Silk Text to Silk Clearance [9.251mil]
-   Violation between Silk To Silk Clearance Constraint: (9.251mil < 10mil) Between Text "XP2" (21.219mil,369.537mil) on Top Overlay And Track (50mil,300.217mil)(50mil,400.217mil) on Top Overlay Silk Text to Silk Clearance [9.251mil]
-Rule Violations :8
-
-Processing Rule : Net Antennae (Tolerance=0mil) (All)
+Processing Rule : Net Antennae (Tolerance=0mm) (All)
 Rule Violations :0
 
-Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
+Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
 Rule Violations :0
 
 
-Violations Detected : 84
+Violations Detected : 97
 Waived Violations : 0
-Time Elapsed        : 00:00:02
+Time Elapsed        : 00:00:01